2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void __orr32(void __iomem *ptr, u32 val)
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
58 static inline void __bic32(void __iomem *ptr, u32 val)
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->params.g_dma;
100 * using_desc_dma - return the descriptor DMA status of the driver.
101 * @hsotg: The driver state.
103 * Return true if we're using descriptor DMA.
105 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
107 return hsotg->params.g_dma_desc;
111 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
112 * @hs_ep: The endpoint
113 * @increment: The value to increment by
115 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
116 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
118 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
120 hs_ep->target_frame += hs_ep->interval;
121 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
122 hs_ep->frame_overrun = 1;
123 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
125 hs_ep->frame_overrun = 0;
130 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
131 * @hsotg: The device state
132 * @ints: A bitmask of the interrupts to enable
134 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
136 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
139 new_gsintmsk = gsintmsk | ints;
141 if (new_gsintmsk != gsintmsk) {
142 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
143 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
148 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
149 * @hsotg: The device state
150 * @ints: A bitmask of the interrupts to enable
152 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
154 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
157 new_gsintmsk = gsintmsk & ~ints;
159 if (new_gsintmsk != gsintmsk)
160 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
164 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
165 * @hsotg: The device state
166 * @ep: The endpoint index
167 * @dir_in: True if direction is in.
168 * @en: The enable value, true to enable
170 * Set or clear the mask for an individual endpoint's interrupt
173 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
174 unsigned int ep, unsigned int dir_in,
184 local_irq_save(flags);
185 daint = dwc2_readl(hsotg->regs + DAINTMSK);
190 dwc2_writel(daint, hsotg->regs + DAINTMSK);
191 local_irq_restore(flags);
195 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
196 * @hsotg: The device instance.
198 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
204 u32 *txfsz = hsotg->params.g_tx_fifo_size;
206 /* Reset fifo map if not correctly cleared during previous session */
207 WARN_ON(hsotg->fifo_map);
210 /* set RX/NPTX FIFO sizes */
211 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
212 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
213 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
214 hsotg->regs + GNPTXFSIZ);
217 * arange all the rest of the TX FIFOs, as some versions of this
218 * block have overlapping default addresses. This also ensures
219 * that if the settings have been changed, then they are set to
223 /* start at the end of the GNPTXFSIZ, rounded up */
224 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
227 * Configure fifos sizes from provided configuration and assign
228 * them to endpoints dynamically according to maxpacket size value of
231 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
235 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
236 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
237 "insufficient fifo memory");
240 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
241 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
245 * according to p428 of the design guide, we need to ensure that
246 * all fifos are flushed before continuing
249 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
250 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
252 /* wait until the fifos are both flushed */
255 val = dwc2_readl(hsotg->regs + GRSTCTL);
257 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
260 if (--timeout == 0) {
262 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
270 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
274 * @ep: USB endpoint to allocate request for.
275 * @flags: Allocation flags
277 * Allocate a new USB request structure appropriate for the specified endpoint
279 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
282 struct dwc2_hsotg_req *req;
284 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
288 INIT_LIST_HEAD(&req->queue);
294 * is_ep_periodic - return true if the endpoint is in periodic mode.
295 * @hs_ep: The endpoint to query.
297 * Returns true if the endpoint is in periodic mode, meaning it is being
298 * used for an Interrupt or ISO transfer.
300 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
302 return hs_ep->periodic;
306 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
307 * @hsotg: The device state.
308 * @hs_ep: The endpoint for the request
309 * @hs_req: The request being processed.
311 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
312 * of a request to ensure the buffer is ready for access by the caller.
314 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
315 struct dwc2_hsotg_ep *hs_ep,
316 struct dwc2_hsotg_req *hs_req)
318 struct usb_request *req = &hs_req->req;
320 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
324 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
325 * for Control endpoint
326 * @hsotg: The device state.
328 * This function will allocate 4 descriptor chains for EP 0: 2 for
329 * Setup stage, per one for IN and OUT data/status transactions.
331 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
333 hsotg->setup_desc[0] =
334 dmam_alloc_coherent(hsotg->dev,
335 sizeof(struct dwc2_dma_desc),
336 &hsotg->setup_desc_dma[0],
338 if (!hsotg->setup_desc[0])
341 hsotg->setup_desc[1] =
342 dmam_alloc_coherent(hsotg->dev,
343 sizeof(struct dwc2_dma_desc),
344 &hsotg->setup_desc_dma[1],
346 if (!hsotg->setup_desc[1])
349 hsotg->ctrl_in_desc =
350 dmam_alloc_coherent(hsotg->dev,
351 sizeof(struct dwc2_dma_desc),
352 &hsotg->ctrl_in_desc_dma,
354 if (!hsotg->ctrl_in_desc)
357 hsotg->ctrl_out_desc =
358 dmam_alloc_coherent(hsotg->dev,
359 sizeof(struct dwc2_dma_desc),
360 &hsotg->ctrl_out_desc_dma,
362 if (!hsotg->ctrl_out_desc)
372 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
373 * @hsotg: The controller state.
374 * @hs_ep: The endpoint we're going to write for.
375 * @hs_req: The request to write data for.
377 * This is called when the TxFIFO has some space in it to hold a new
378 * transmission and we have something to give it. The actual setup of
379 * the data size is done elsewhere, so all we have to do is to actually
382 * The return value is zero if there is more space (or nothing was done)
383 * otherwise -ENOSPC is returned if the FIFO space was used up.
385 * This routine is only needed for PIO
387 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
388 struct dwc2_hsotg_ep *hs_ep,
389 struct dwc2_hsotg_req *hs_req)
391 bool periodic = is_ep_periodic(hs_ep);
392 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
393 int buf_pos = hs_req->req.actual;
394 int to_write = hs_ep->size_loaded;
400 to_write -= (buf_pos - hs_ep->last_load);
402 /* if there's nothing to write, get out early */
406 if (periodic && !hsotg->dedicated_fifos) {
407 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
412 * work out how much data was loaded so we can calculate
413 * how much data is left in the fifo.
416 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
419 * if shared fifo, we cannot write anything until the
420 * previous data has been completely sent.
422 if (hs_ep->fifo_load != 0) {
423 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
427 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
429 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
431 /* how much of the data has moved */
432 size_done = hs_ep->size_loaded - size_left;
434 /* how much data is left in the fifo */
435 can_write = hs_ep->fifo_load - size_done;
436 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
437 __func__, can_write);
439 can_write = hs_ep->fifo_size - can_write;
440 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
441 __func__, can_write);
443 if (can_write <= 0) {
444 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
447 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
448 can_write = dwc2_readl(hsotg->regs +
449 DTXFSTS(hs_ep->fifo_index));
454 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
456 "%s: no queue slots available (0x%08x)\n",
459 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
463 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
464 can_write *= 4; /* fifo size is in 32bit quantities. */
467 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
469 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
470 __func__, gnptxsts, can_write, to_write, max_transfer);
473 * limit to 512 bytes of data, it seems at least on the non-periodic
474 * FIFO, requests of >512 cause the endpoint to get stuck with a
475 * fragment of the end of the transfer in it.
477 if (can_write > 512 && !periodic)
481 * limit the write to one max-packet size worth of data, but allow
482 * the transfer to return that it did not run out of fifo space
485 if (to_write > max_transfer) {
486 to_write = max_transfer;
488 /* it's needed only when we do not use dedicated fifos */
489 if (!hsotg->dedicated_fifos)
490 dwc2_hsotg_en_gsint(hsotg,
491 periodic ? GINTSTS_PTXFEMP :
495 /* see if we can write data */
497 if (to_write > can_write) {
498 to_write = can_write;
499 pkt_round = to_write % max_transfer;
502 * Round the write down to an
503 * exact number of packets.
505 * Note, we do not currently check to see if we can ever
506 * write a full packet or not to the FIFO.
510 to_write -= pkt_round;
513 * enable correct FIFO interrupt to alert us when there
517 /* it's needed only when we do not use dedicated fifos */
518 if (!hsotg->dedicated_fifos)
519 dwc2_hsotg_en_gsint(hsotg,
520 periodic ? GINTSTS_PTXFEMP :
524 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
525 to_write, hs_req->req.length, can_write, buf_pos);
530 hs_req->req.actual = buf_pos + to_write;
531 hs_ep->total_data += to_write;
534 hs_ep->fifo_load += to_write;
536 to_write = DIV_ROUND_UP(to_write, 4);
537 data = hs_req->req.buf + buf_pos;
539 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
541 return (to_write >= can_write) ? -ENOSPC : 0;
545 * get_ep_limit - get the maximum data legnth for this endpoint
546 * @hs_ep: The endpoint
548 * Return the maximum data that can be queued in one go on a given endpoint
549 * so that transfers that are too long can be split.
551 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
553 int index = hs_ep->index;
554 unsigned int maxsize;
558 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
559 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
563 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
568 /* we made the constant loading easier above by using +1 */
573 * constrain by packet count if maxpkts*pktsize is greater
574 * than the length register size.
577 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
578 maxsize = maxpkt * hs_ep->ep.maxpacket;
584 * dwc2_hsotg_read_frameno - read current frame number
585 * @hsotg: The device instance
587 * Return the current frame number
589 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
593 dsts = dwc2_readl(hsotg->regs + DSTS);
594 dsts &= DSTS_SOFFN_MASK;
595 dsts >>= DSTS_SOFFN_SHIFT;
601 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
602 * DMA descriptor chain prepared for specific endpoint
603 * @hs_ep: The endpoint
605 * Return the maximum data that can be queued in one go on a given endpoint
606 * depending on its descriptor chain capacity so that transfers that
607 * are too long can be split.
609 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
611 int is_isoc = hs_ep->isochronous;
612 unsigned int maxsize;
615 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
616 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
618 maxsize = DEV_DMA_NBYTES_LIMIT;
620 /* Above size of one descriptor was chosen, multiple it */
621 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
627 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
628 * @hs_ep: The endpoint
629 * @mask: RX/TX bytes mask to be defined
631 * Returns maximum data payload for one descriptor after analyzing endpoint
633 * DMA descriptor transfer bytes limit depends on EP type:
635 * Isochronous - descriptor rx/tx bytes bitfield limit,
636 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
637 * have concatenations from various descriptors within one packet.
639 * Selects corresponding mask for RX/TX bytes as well.
641 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
643 u32 mps = hs_ep->ep.maxpacket;
644 int dir_in = hs_ep->dir_in;
647 if (!hs_ep->index && !dir_in) {
649 *mask = DEV_DMA_NBYTES_MASK;
650 } else if (hs_ep->isochronous) {
652 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
653 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
655 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
656 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
659 desc_size = DEV_DMA_NBYTES_LIMIT;
660 *mask = DEV_DMA_NBYTES_MASK;
662 /* Round down desc_size to be mps multiple */
663 desc_size -= desc_size % mps;
670 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
671 * @hs_ep: The endpoint
672 * @dma_buff: DMA address to use
673 * @len: Length of the transfer
675 * This function will iterate over descriptor chain and fill its entries
676 * with corresponding information based on transfer data.
678 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
682 struct dwc2_hsotg *hsotg = hs_ep->parent;
683 int dir_in = hs_ep->dir_in;
684 struct dwc2_dma_desc *desc = hs_ep->desc_list;
685 u32 mps = hs_ep->ep.maxpacket;
691 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
693 hs_ep->desc_count = (len / maxsize) +
694 ((len % maxsize) ? 1 : 0);
696 hs_ep->desc_count = 1;
698 for (i = 0; i < hs_ep->desc_count; ++i) {
700 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
701 << DEV_DMA_BUFF_STS_SHIFT);
704 if (!hs_ep->index && !dir_in)
705 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
707 desc->status |= (maxsize <<
708 DEV_DMA_NBYTES_SHIFT & mask);
709 desc->buf = dma_buff + offset;
714 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
717 desc->status |= (len % mps) ? DEV_DMA_SHORT :
718 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
720 dev_err(hsotg->dev, "wrong len %d\n", len);
723 len << DEV_DMA_NBYTES_SHIFT & mask;
724 desc->buf = dma_buff + offset;
727 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
728 desc->status |= (DEV_DMA_BUFF_STS_HREADY
729 << DEV_DMA_BUFF_STS_SHIFT);
735 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
736 * @hs_ep: The isochronous endpoint.
737 * @dma_buff: usb requests dma buffer.
738 * @len: usb request transfer length.
740 * Finds out index of first free entry either in the bottom or up half of
741 * descriptor chain depend on which is under SW control and not processed
742 * by HW. Then fills that descriptor with the data of the arrived usb request,
743 * frame info, sets Last and IOC bits increments next_desc. If filled
744 * descriptor is not the first one, removes L bit from the previous descriptor
747 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
748 dma_addr_t dma_buff, unsigned int len)
750 struct dwc2_dma_desc *desc;
751 struct dwc2_hsotg *hsotg = hs_ep->parent;
756 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
758 dev_err(hsotg->dev, "wrong len %d\n", len);
763 * If SW has already filled half of chain, then return and wait for
764 * the other chain to be processed by HW.
766 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
769 /* Increment frame number by interval for IN */
771 dwc2_gadget_incr_frame_num(hs_ep);
773 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
776 /* Sanity check of calculated index */
777 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
778 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
779 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
783 desc = &hs_ep->desc_list[index];
785 /* Clear L bit of previous desc if more than one entries in the chain */
786 if (hs_ep->next_desc)
787 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
789 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
790 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
793 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
795 desc->buf = dma_buff;
796 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
797 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
800 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
801 DEV_DMA_ISOC_PID_MASK) |
802 ((len % hs_ep->ep.maxpacket) ?
804 ((hs_ep->target_frame <<
805 DEV_DMA_ISOC_FRNUM_SHIFT) &
806 DEV_DMA_ISOC_FRNUM_MASK);
809 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
810 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
812 /* Update index of last configured entry in the chain */
819 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
820 * @hs_ep: The isochronous endpoint.
822 * Prepare first descriptor chain for isochronous endpoints. Afterwards
823 * write DMA address to HW and enable the endpoint.
825 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
826 * to prepare second descriptor chain while first one is being processed by HW.
828 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
830 struct dwc2_hsotg *hsotg = hs_ep->parent;
831 struct dwc2_hsotg_req *hs_req, *treq;
832 int index = hs_ep->index;
838 if (list_empty(&hs_ep->queue)) {
839 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
843 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
844 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
847 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
852 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
853 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
855 /* write descriptor chain address to control register */
856 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
858 ctrl = dwc2_readl(hsotg->regs + depctl);
859 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
860 dwc2_writel(ctrl, hsotg->regs + depctl);
862 /* Switch ISOC descriptor chain number being processed by SW*/
863 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
864 hs_ep->next_desc = 0;
868 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
869 * @hsotg: The controller state.
870 * @hs_ep: The endpoint to process a request for
871 * @hs_req: The request to start.
872 * @continuing: True if we are doing more for the current request.
874 * Start the given request running by setting the endpoint registers
875 * appropriately, and writing any data to the FIFOs.
877 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
878 struct dwc2_hsotg_ep *hs_ep,
879 struct dwc2_hsotg_req *hs_req,
882 struct usb_request *ureq = &hs_req->req;
883 int index = hs_ep->index;
884 int dir_in = hs_ep->dir_in;
890 unsigned int packets;
892 unsigned int dma_reg;
895 if (hs_ep->req && !continuing) {
896 dev_err(hsotg->dev, "%s: active request\n", __func__);
899 } else if (hs_ep->req != hs_req && continuing) {
901 "%s: continue different req\n", __func__);
907 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
908 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
909 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
911 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
912 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
913 hs_ep->dir_in ? "in" : "out");
915 /* If endpoint is stalled, we will restart request later */
916 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
918 if (index && ctrl & DXEPCTL_STALL) {
919 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
923 length = ureq->length - ureq->actual;
924 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
925 ureq->length, ureq->actual);
927 if (!using_desc_dma(hsotg))
928 maxreq = get_ep_limit(hs_ep);
930 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
932 if (length > maxreq) {
933 int round = maxreq % hs_ep->ep.maxpacket;
935 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
936 __func__, length, maxreq, round);
938 /* round down to multiple of packets */
946 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
948 packets = 1; /* send one packet if length is zero. */
950 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
951 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
955 if (dir_in && index != 0)
956 if (hs_ep->isochronous)
957 epsize = DXEPTSIZ_MC(packets);
959 epsize = DXEPTSIZ_MC(1);
964 * zero length packet should be programmed on its own and should not
965 * be counted in DIEPTSIZ.PktCnt with other packets.
967 if (dir_in && ureq->zero && !continuing) {
968 /* Test if zlp is actually required. */
969 if ((ureq->length >= hs_ep->ep.maxpacket) &&
970 !(ureq->length % hs_ep->ep.maxpacket))
974 epsize |= DXEPTSIZ_PKTCNT(packets);
975 epsize |= DXEPTSIZ_XFERSIZE(length);
977 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
978 __func__, packets, length, ureq->length, epsize, epsize_reg);
980 /* store the request as the current one we're doing */
983 if (using_desc_dma(hsotg)) {
985 u32 mps = hs_ep->ep.maxpacket;
987 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
991 else if (length % mps)
992 length += (mps - (length % mps));
996 * If more data to send, adjust DMA for EP0 out data stage.
997 * ureq->dma stays unchanged, hence increment it by already
998 * passed passed data count before starting new transaction.
1000 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1002 offset = ureq->actual;
1004 /* Fill DDMA chain entries */
1005 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1008 /* write descriptor chain address to control register */
1009 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1011 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1012 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1014 /* write size / packets */
1015 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1017 if (using_dma(hsotg) && !continuing && (length != 0)) {
1019 * write DMA address to control register, buffer
1020 * already synced by dwc2_hsotg_ep_queue().
1023 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1025 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1026 __func__, &ureq->dma, dma_reg);
1030 if (hs_ep->isochronous && hs_ep->interval == 1) {
1031 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1032 dwc2_gadget_incr_frame_num(hs_ep);
1034 if (hs_ep->target_frame & 0x1)
1035 ctrl |= DXEPCTL_SETODDFR;
1037 ctrl |= DXEPCTL_SETEVENFR;
1040 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1042 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1044 /* For Setup request do not clear NAK */
1045 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1046 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1048 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1049 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1052 * set these, it seems that DMA support increments past the end
1053 * of the packet buffer so we need to calculate the length from
1056 hs_ep->size_loaded = length;
1057 hs_ep->last_load = ureq->actual;
1059 if (dir_in && !using_dma(hsotg)) {
1060 /* set these anyway, we may need them for non-periodic in */
1061 hs_ep->fifo_load = 0;
1063 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1067 * Note, trying to clear the NAK here causes problems with transmit
1068 * on the S3C6400 ending up with the TXFIFO becoming full.
1071 /* check ep is enabled */
1072 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1074 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1075 index, dwc2_readl(hsotg->regs + epctrl_reg));
1077 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1078 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1080 /* enable ep interrupts */
1081 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1085 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1086 * @hsotg: The device state.
1087 * @hs_ep: The endpoint the request is on.
1088 * @req: The request being processed.
1090 * We've been asked to queue a request, so ensure that the memory buffer
1091 * is correctly setup for DMA. If we've been passed an extant DMA address
1092 * then ensure the buffer has been synced to memory. If our buffer has no
1093 * DMA memory, then we map the memory and mark our request to allow us to
1094 * cleanup on completion.
1096 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1097 struct dwc2_hsotg_ep *hs_ep,
1098 struct usb_request *req)
1102 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1109 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1110 __func__, req->buf, req->length);
1115 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1116 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
1118 void *req_buf = hs_req->req.buf;
1120 /* If dma is not being used or buffer is aligned */
1121 if (!using_dma(hsotg) || !((long)req_buf & 3))
1124 WARN_ON(hs_req->saved_req_buf);
1126 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1127 hs_ep->ep.name, req_buf, hs_req->req.length);
1129 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1130 if (!hs_req->req.buf) {
1131 hs_req->req.buf = req_buf;
1133 "%s: unable to allocate memory for bounce buffer\n",
1138 /* Save actual buffer */
1139 hs_req->saved_req_buf = req_buf;
1142 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1146 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1147 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
1149 /* If dma is not being used or buffer was aligned */
1150 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1153 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1154 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1156 /* Copy data from bounce buffer on successful out transfer */
1157 if (!hs_ep->dir_in && !hs_req->req.status)
1158 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1159 hs_req->req.actual);
1161 /* Free bounce buffer */
1162 kfree(hs_req->req.buf);
1164 hs_req->req.buf = hs_req->saved_req_buf;
1165 hs_req->saved_req_buf = NULL;
1169 * dwc2_gadget_target_frame_elapsed - Checks target frame
1170 * @hs_ep: The driver endpoint to check
1172 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1173 * corresponding transfer.
1175 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1177 struct dwc2_hsotg *hsotg = hs_ep->parent;
1178 u32 target_frame = hs_ep->target_frame;
1179 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1180 bool frame_overrun = hs_ep->frame_overrun;
1182 if (!frame_overrun && current_frame >= target_frame)
1185 if (frame_overrun && current_frame >= target_frame &&
1186 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1193 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1194 * @hsotg: The driver state
1195 * @hs_ep: the ep descriptor chain is for
1197 * Called to update EP0 structure's pointers depend on stage of
1200 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1201 struct dwc2_hsotg_ep *hs_ep)
1203 switch (hsotg->ep0_state) {
1204 case DWC2_EP0_SETUP:
1205 case DWC2_EP0_STATUS_OUT:
1206 hs_ep->desc_list = hsotg->setup_desc[0];
1207 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1209 case DWC2_EP0_DATA_IN:
1210 case DWC2_EP0_STATUS_IN:
1211 hs_ep->desc_list = hsotg->ctrl_in_desc;
1212 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1214 case DWC2_EP0_DATA_OUT:
1215 hs_ep->desc_list = hsotg->ctrl_out_desc;
1216 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1219 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1227 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1230 struct dwc2_hsotg_req *hs_req = our_req(req);
1231 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1232 struct dwc2_hsotg *hs = hs_ep->parent;
1236 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1237 ep->name, req, req->length, req->buf, req->no_interrupt,
1238 req->zero, req->short_not_ok);
1240 /* Prevent new request submission when controller is suspended */
1241 if (hs->lx_state == DWC2_L2) {
1242 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
1247 /* initialise status of the request */
1248 INIT_LIST_HEAD(&hs_req->queue);
1250 req->status = -EINPROGRESS;
1252 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1256 /* if we're using DMA, sync the buffers as necessary */
1257 if (using_dma(hs)) {
1258 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1262 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1263 if (using_desc_dma(hs) && !hs_ep->index) {
1264 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1269 first = list_empty(&hs_ep->queue);
1270 list_add_tail(&hs_req->queue, &hs_ep->queue);
1273 * Handle DDMA isochronous transfers separately - just add new entry
1274 * to the half of descriptor chain that is not processed by HW.
1275 * Transfer will be started once SW gets either one of NAK or
1276 * OutTknEpDis interrupts.
1278 if (using_desc_dma(hs) && hs_ep->isochronous &&
1279 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1280 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1281 hs_req->req.length);
1283 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1289 if (!hs_ep->isochronous) {
1290 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1294 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1295 dwc2_gadget_incr_frame_num(hs_ep);
1297 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1298 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1303 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1306 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1307 struct dwc2_hsotg *hs = hs_ep->parent;
1308 unsigned long flags = 0;
1311 spin_lock_irqsave(&hs->lock, flags);
1312 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1313 spin_unlock_irqrestore(&hs->lock, flags);
1318 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1319 struct usb_request *req)
1321 struct dwc2_hsotg_req *hs_req = our_req(req);
1327 * dwc2_hsotg_complete_oursetup - setup completion callback
1328 * @ep: The endpoint the request was on.
1329 * @req: The request completed.
1331 * Called on completion of any requests the driver itself
1332 * submitted that need cleaning up.
1334 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1335 struct usb_request *req)
1337 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1338 struct dwc2_hsotg *hsotg = hs_ep->parent;
1340 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1342 dwc2_hsotg_ep_free_request(ep, req);
1346 * ep_from_windex - convert control wIndex value to endpoint
1347 * @hsotg: The driver state.
1348 * @windex: The control request wIndex field (in host order).
1350 * Convert the given wIndex into a pointer to an driver endpoint
1351 * structure, or return NULL if it is not a valid endpoint.
1353 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1356 struct dwc2_hsotg_ep *ep;
1357 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1358 int idx = windex & 0x7F;
1360 if (windex >= 0x100)
1363 if (idx > hsotg->num_of_eps)
1366 ep = index_to_ep(hsotg, idx, dir);
1368 if (idx && ep->dir_in != dir)
1375 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1376 * @hsotg: The driver state.
1377 * @testmode: requested usb test mode
1378 * Enable usb Test Mode requested by the Host.
1380 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1382 int dctl = dwc2_readl(hsotg->regs + DCTL);
1384 dctl &= ~DCTL_TSTCTL_MASK;
1391 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1396 dwc2_writel(dctl, hsotg->regs + DCTL);
1401 * dwc2_hsotg_send_reply - send reply to control request
1402 * @hsotg: The device state
1404 * @buff: Buffer for request
1405 * @length: Length of reply.
1407 * Create a request and queue it on the given endpoint. This is useful as
1408 * an internal method of sending replies to certain control requests, etc.
1410 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1411 struct dwc2_hsotg_ep *ep,
1415 struct usb_request *req;
1418 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1420 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1421 hsotg->ep0_reply = req;
1423 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1427 req->buf = hsotg->ep0_buff;
1428 req->length = length;
1430 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1434 req->complete = dwc2_hsotg_complete_oursetup;
1437 memcpy(req->buf, buff, length);
1439 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1441 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1449 * dwc2_hsotg_process_req_status - process request GET_STATUS
1450 * @hsotg: The device state
1451 * @ctrl: USB control request
1453 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1454 struct usb_ctrlrequest *ctrl)
1456 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1457 struct dwc2_hsotg_ep *ep;
1461 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1464 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1468 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1469 case USB_RECIP_DEVICE:
1471 * bit 0 => self powered
1472 * bit 1 => remote wakeup
1474 reply = cpu_to_le16(0);
1477 case USB_RECIP_INTERFACE:
1478 /* currently, the data result should be zero */
1479 reply = cpu_to_le16(0);
1482 case USB_RECIP_ENDPOINT:
1483 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1487 reply = cpu_to_le16(ep->halted ? 1 : 0);
1494 if (le16_to_cpu(ctrl->wLength) != 2)
1497 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1499 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1506 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1509 * get_ep_head - return the first request on the endpoint
1510 * @hs_ep: The controller endpoint to get
1512 * Get the first request on the endpoint.
1514 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1516 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1521 * dwc2_gadget_start_next_request - Starts next request from ep queue
1522 * @hs_ep: Endpoint structure
1524 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1525 * in its handler. Hence we need to unmask it here to be able to do
1526 * resynchronization.
1528 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1531 struct dwc2_hsotg *hsotg = hs_ep->parent;
1532 int dir_in = hs_ep->dir_in;
1533 struct dwc2_hsotg_req *hs_req;
1534 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1536 if (!list_empty(&hs_ep->queue)) {
1537 hs_req = get_ep_head(hs_ep);
1538 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1541 if (!hs_ep->isochronous)
1545 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1548 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1550 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1551 mask |= DOEPMSK_OUTTKNEPDISMSK;
1552 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1557 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1558 * @hsotg: The device state
1559 * @ctrl: USB control request
1561 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1562 struct usb_ctrlrequest *ctrl)
1564 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1565 struct dwc2_hsotg_req *hs_req;
1566 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1567 struct dwc2_hsotg_ep *ep;
1574 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1575 __func__, set ? "SET" : "CLEAR");
1577 wValue = le16_to_cpu(ctrl->wValue);
1578 wIndex = le16_to_cpu(ctrl->wIndex);
1579 recip = ctrl->bRequestType & USB_RECIP_MASK;
1582 case USB_RECIP_DEVICE:
1584 case USB_DEVICE_TEST_MODE:
1585 if ((wIndex & 0xff) != 0)
1590 hsotg->test_mode = wIndex >> 8;
1591 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1594 "%s: failed to send reply\n", __func__);
1603 case USB_RECIP_ENDPOINT:
1604 ep = ep_from_windex(hsotg, wIndex);
1606 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1612 case USB_ENDPOINT_HALT:
1613 halted = ep->halted;
1615 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1617 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1620 "%s: failed to send reply\n", __func__);
1625 * we have to complete all requests for ep if it was
1626 * halted, and the halt was cleared by CLEAR_FEATURE
1629 if (!set && halted) {
1631 * If we have request in progress,
1637 list_del_init(&hs_req->queue);
1638 if (hs_req->req.complete) {
1639 spin_unlock(&hsotg->lock);
1640 usb_gadget_giveback_request(
1641 &ep->ep, &hs_req->req);
1642 spin_lock(&hsotg->lock);
1646 /* If we have pending request, then start it */
1648 dwc2_gadget_start_next_request(ep);
1663 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1666 * dwc2_hsotg_stall_ep0 - stall ep0
1667 * @hsotg: The device state
1669 * Set stall for ep0 as response for setup request.
1671 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1673 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1677 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1678 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1681 * DxEPCTL_Stall will be cleared by EP once it has
1682 * taken effect, so no need to clear later.
1685 ctrl = dwc2_readl(hsotg->regs + reg);
1686 ctrl |= DXEPCTL_STALL;
1687 ctrl |= DXEPCTL_CNAK;
1688 dwc2_writel(ctrl, hsotg->regs + reg);
1691 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1692 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1695 * complete won't be called, so we enqueue
1696 * setup request here
1698 dwc2_hsotg_enqueue_setup(hsotg);
1702 * dwc2_hsotg_process_control - process a control request
1703 * @hsotg: The device state
1704 * @ctrl: The control request received
1706 * The controller has received the SETUP phase of a control request, and
1707 * needs to work out what to do next (and whether to pass it on to the
1710 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1711 struct usb_ctrlrequest *ctrl)
1713 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1718 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1719 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1720 ctrl->wIndex, ctrl->wLength);
1722 if (ctrl->wLength == 0) {
1724 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1725 } else if (ctrl->bRequestType & USB_DIR_IN) {
1727 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1730 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1733 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1734 switch (ctrl->bRequest) {
1735 case USB_REQ_SET_ADDRESS:
1736 hsotg->connected = 1;
1737 dcfg = dwc2_readl(hsotg->regs + DCFG);
1738 dcfg &= ~DCFG_DEVADDR_MASK;
1739 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1740 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1741 dwc2_writel(dcfg, hsotg->regs + DCFG);
1743 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1745 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1748 case USB_REQ_GET_STATUS:
1749 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1752 case USB_REQ_CLEAR_FEATURE:
1753 case USB_REQ_SET_FEATURE:
1754 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1759 /* as a fallback, try delivering it to the driver to deal with */
1761 if (ret == 0 && hsotg->driver) {
1762 spin_unlock(&hsotg->lock);
1763 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1764 spin_lock(&hsotg->lock);
1766 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1770 * the request is either unhandlable, or is not formatted correctly
1771 * so respond with a STALL for the status stage to indicate failure.
1775 dwc2_hsotg_stall_ep0(hsotg);
1779 * dwc2_hsotg_complete_setup - completion of a setup transfer
1780 * @ep: The endpoint the request was on.
1781 * @req: The request completed.
1783 * Called on completion of any requests the driver itself submitted for
1786 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1787 struct usb_request *req)
1789 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1790 struct dwc2_hsotg *hsotg = hs_ep->parent;
1792 if (req->status < 0) {
1793 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1797 spin_lock(&hsotg->lock);
1798 if (req->actual == 0)
1799 dwc2_hsotg_enqueue_setup(hsotg);
1801 dwc2_hsotg_process_control(hsotg, req->buf);
1802 spin_unlock(&hsotg->lock);
1806 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1807 * @hsotg: The device state.
1809 * Enqueue a request on EP0 if necessary to received any SETUP packets
1810 * received from the host.
1812 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1814 struct usb_request *req = hsotg->ctrl_req;
1815 struct dwc2_hsotg_req *hs_req = our_req(req);
1818 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1822 req->buf = hsotg->ctrl_buff;
1823 req->complete = dwc2_hsotg_complete_setup;
1825 if (!list_empty(&hs_req->queue)) {
1826 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1830 hsotg->eps_out[0]->dir_in = 0;
1831 hsotg->eps_out[0]->send_zlp = 0;
1832 hsotg->ep0_state = DWC2_EP0_SETUP;
1834 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1836 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1838 * Don't think there's much we can do other than watch the
1844 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1845 struct dwc2_hsotg_ep *hs_ep)
1848 u8 index = hs_ep->index;
1849 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1850 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1853 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1856 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1858 if (using_desc_dma(hsotg)) {
1859 /* Not specific buffer needed for ep0 ZLP */
1860 dma_addr_t dma = hs_ep->desc_list_dma;
1862 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1863 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1865 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1866 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1870 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1871 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1872 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1873 ctrl |= DXEPCTL_USBACTEP;
1874 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1878 * dwc2_hsotg_complete_request - complete a request given to us
1879 * @hsotg: The device state.
1880 * @hs_ep: The endpoint the request was on.
1881 * @hs_req: The request to complete.
1882 * @result: The result code (0 => Ok, otherwise errno)
1884 * The given request has finished, so call the necessary completion
1885 * if it has one and then look to see if we can start a new request
1888 * Note, expects the ep to already be locked as appropriate.
1890 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1891 struct dwc2_hsotg_ep *hs_ep,
1892 struct dwc2_hsotg_req *hs_req,
1896 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1900 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1901 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1904 * only replace the status if we've not already set an error
1905 * from a previous transaction
1908 if (hs_req->req.status == -EINPROGRESS)
1909 hs_req->req.status = result;
1911 if (using_dma(hsotg))
1912 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1914 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1917 list_del_init(&hs_req->queue);
1920 * call the complete request with the locks off, just in case the
1921 * request tries to queue more work for this endpoint.
1924 if (hs_req->req.complete) {
1925 spin_unlock(&hsotg->lock);
1926 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1927 spin_lock(&hsotg->lock);
1930 /* In DDMA don't need to proceed to starting of next ISOC request */
1931 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1935 * Look to see if there is anything else to do. Note, the completion
1936 * of the previous request may have caused a new request to be started
1937 * so be careful when doing this.
1940 if (!hs_ep->req && result >= 0)
1941 dwc2_gadget_start_next_request(hs_ep);
1945 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
1946 * @hs_ep: The endpoint the request was on.
1948 * Get first request from the ep queue, determine descriptor on which complete
1949 * happened. SW based on isoc_chain_num discovers which half of the descriptor
1950 * chain is currently in use by HW, adjusts dma_address and calculates index
1951 * of completed descriptor based on the value of DEPDMA register. Update actual
1952 * length of request, giveback to gadget.
1954 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
1956 struct dwc2_hsotg *hsotg = hs_ep->parent;
1957 struct dwc2_hsotg_req *hs_req;
1958 struct usb_request *ureq;
1960 dma_addr_t dma_addr;
1966 hs_req = get_ep_head(hs_ep);
1968 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
1971 ureq = &hs_req->req;
1973 dma_addr = hs_ep->desc_list_dma;
1976 * If lower half of descriptor chain is currently use by SW,
1977 * that means higher half is being processed by HW, so shift
1978 * DMA address to higher half of descriptor chain.
1980 if (!hs_ep->isoc_chain_num)
1981 dma_addr += sizeof(struct dwc2_dma_desc) *
1982 (MAX_DMA_DESC_NUM_GENERIC / 2);
1984 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
1985 depdma = dwc2_readl(hsotg->regs + dma_reg);
1987 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
1988 desc_sts = hs_ep->desc_list[index].status;
1990 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
1991 DEV_DMA_ISOC_RX_NBYTES_MASK;
1992 ureq->actual = ureq->length -
1993 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
1995 /* Adjust actual length for ISOC Out if length is not align of 4 */
1996 if (!hs_ep->dir_in && ureq->length & 0x3)
1997 ureq->actual += 4 - (ureq->length & 0x3);
1999 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2003 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2004 * @hs_ep: The isochronous endpoint to be re-enabled.
2006 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2007 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2008 * was under SW control till HW was busy and restart the endpoint if needed.
2010 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2012 struct dwc2_hsotg *hsotg = hs_ep->parent;
2016 u32 dma_addr = hs_ep->desc_list_dma;
2017 unsigned char index = hs_ep->index;
2019 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2020 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2022 ctrl = dwc2_readl(hsotg->regs + depctl);
2025 * EP was disabled if HW has processed last descriptor or BNA was set.
2026 * So restart ep if SW has prepared new descriptor chain in ep_queue
2027 * routine while HW was busy.
2029 if (!(ctrl & DXEPCTL_EPENA)) {
2030 if (!hs_ep->next_desc) {
2031 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2036 dma_addr += sizeof(struct dwc2_dma_desc) *
2037 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2038 hs_ep->isoc_chain_num;
2039 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2041 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2042 dwc2_writel(ctrl, hsotg->regs + depctl);
2044 /* Switch ISOC descriptor chain number being processed by SW*/
2045 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2046 hs_ep->next_desc = 0;
2048 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2054 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2055 * @hsotg: The device state.
2056 * @ep_idx: The endpoint index for the data
2057 * @size: The size of data in the fifo, in bytes
2059 * The FIFO status shows there is data to read from the FIFO for a given
2060 * endpoint, so sort out whether we need to read the data into a request
2061 * that has been made for that endpoint.
2063 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2065 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2066 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2067 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2073 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2077 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2078 __func__, size, ep_idx, epctl);
2080 /* dump the data from the FIFO, we've nothing we can do */
2081 for (ptr = 0; ptr < size; ptr += 4)
2082 (void)dwc2_readl(fifo);
2088 read_ptr = hs_req->req.actual;
2089 max_req = hs_req->req.length - read_ptr;
2091 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2092 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2094 if (to_read > max_req) {
2096 * more data appeared than we where willing
2097 * to deal with in this request.
2100 /* currently we don't deal this */
2104 hs_ep->total_data += to_read;
2105 hs_req->req.actual += to_read;
2106 to_read = DIV_ROUND_UP(to_read, 4);
2109 * note, we might over-write the buffer end by 3 bytes depending on
2110 * alignment of the data.
2112 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2116 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2117 * @hsotg: The device instance
2118 * @dir_in: If IN zlp
2120 * Generate a zero-length IN packet request for terminating a SETUP
2123 * Note, since we don't write any data to the TxFIFO, then it is
2124 * currently believed that we do not need to wait for any space in
2127 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2129 /* eps_out[0] is used in both directions */
2130 hsotg->eps_out[0]->dir_in = dir_in;
2131 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2133 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2136 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2141 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2142 if (ctrl & DXEPCTL_EOFRNUM)
2143 ctrl |= DXEPCTL_SETEVENFR;
2145 ctrl |= DXEPCTL_SETODDFR;
2146 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2150 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2151 * @hs_ep - The endpoint on which transfer went
2153 * Iterate over endpoints descriptor chain and get info on bytes remained
2154 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2156 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2158 struct dwc2_hsotg *hsotg = hs_ep->parent;
2159 unsigned int bytes_rem = 0;
2160 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2167 for (i = 0; i < hs_ep->desc_count; ++i) {
2168 status = desc->status;
2169 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2171 if (status & DEV_DMA_STS_MASK)
2172 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2173 i, status & DEV_DMA_STS_MASK);
2180 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2181 * @hsotg: The device instance
2182 * @epnum: The endpoint received from
2184 * The RXFIFO has delivered an OutDone event, which means that the data
2185 * transfer for an OUT endpoint has been completed, either by a short
2186 * packet or by the finish of a transfer.
2188 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2190 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2191 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2192 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2193 struct usb_request *req = &hs_req->req;
2194 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2198 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2202 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2203 dev_dbg(hsotg->dev, "zlp packet received\n");
2204 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2205 dwc2_hsotg_enqueue_setup(hsotg);
2209 if (using_desc_dma(hsotg))
2210 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2212 if (using_dma(hsotg)) {
2213 unsigned int size_done;
2216 * Calculate the size of the transfer by checking how much
2217 * is left in the endpoint size register and then working it
2218 * out from the amount we loaded for the transfer.
2220 * We need to do this as DMA pointers are always 32bit aligned
2221 * so may overshoot/undershoot the transfer.
2224 size_done = hs_ep->size_loaded - size_left;
2225 size_done += hs_ep->last_load;
2227 req->actual = size_done;
2230 /* if there is more request to do, schedule new transfer */
2231 if (req->actual < req->length && size_left == 0) {
2232 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2236 if (req->actual < req->length && req->short_not_ok) {
2237 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2238 __func__, req->actual, req->length);
2241 * todo - what should we return here? there's no one else
2242 * even bothering to check the status.
2246 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2247 if (!using_desc_dma(hsotg) && epnum == 0 &&
2248 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2249 /* Move to STATUS IN */
2250 dwc2_hsotg_ep0_zlp(hsotg, true);
2255 * Slave mode OUT transfers do not go through XferComplete so
2256 * adjust the ISOC parity here.
2258 if (!using_dma(hsotg)) {
2259 if (hs_ep->isochronous && hs_ep->interval == 1)
2260 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2261 else if (hs_ep->isochronous && hs_ep->interval > 1)
2262 dwc2_gadget_incr_frame_num(hs_ep);
2265 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2269 * dwc2_hsotg_handle_rx - RX FIFO has data
2270 * @hsotg: The device instance
2272 * The IRQ handler has detected that the RX FIFO has some data in it
2273 * that requires processing, so find out what is in there and do the
2276 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2277 * chunks, so if you have x packets received on an endpoint you'll get x
2278 * FIFO events delivered, each with a packet's worth of data in it.
2280 * When using DMA, we should not be processing events from the RXFIFO
2281 * as the actual data should be sent to the memory directly and we turn
2282 * on the completion interrupts to get notifications of transfer completion.
2284 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2286 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2287 u32 epnum, status, size;
2289 WARN_ON(using_dma(hsotg));
2291 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2292 status = grxstsr & GRXSTS_PKTSTS_MASK;
2294 size = grxstsr & GRXSTS_BYTECNT_MASK;
2295 size >>= GRXSTS_BYTECNT_SHIFT;
2297 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2298 __func__, grxstsr, size, epnum);
2300 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2301 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2302 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2305 case GRXSTS_PKTSTS_OUTDONE:
2306 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2307 dwc2_hsotg_read_frameno(hsotg));
2309 if (!using_dma(hsotg))
2310 dwc2_hsotg_handle_outdone(hsotg, epnum);
2313 case GRXSTS_PKTSTS_SETUPDONE:
2315 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2316 dwc2_hsotg_read_frameno(hsotg),
2317 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2319 * Call dwc2_hsotg_handle_outdone here if it was not called from
2320 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2321 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2323 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2324 dwc2_hsotg_handle_outdone(hsotg, epnum);
2327 case GRXSTS_PKTSTS_OUTRX:
2328 dwc2_hsotg_rx_data(hsotg, epnum, size);
2331 case GRXSTS_PKTSTS_SETUPRX:
2333 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2334 dwc2_hsotg_read_frameno(hsotg),
2335 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2337 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2339 dwc2_hsotg_rx_data(hsotg, epnum, size);
2343 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2346 dwc2_hsotg_dump(hsotg);
2352 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2353 * @mps: The maximum packet size in bytes.
2355 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2359 return D0EPCTL_MPS_64;
2361 return D0EPCTL_MPS_32;
2363 return D0EPCTL_MPS_16;
2365 return D0EPCTL_MPS_8;
2368 /* bad max packet size, warn and return invalid result */
2374 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2375 * @hsotg: The driver state.
2376 * @ep: The index number of the endpoint
2377 * @mps: The maximum packet size in bytes
2378 * @mc: The multicount value
2380 * Configure the maximum packet size for the given endpoint, updating
2381 * the hardware control registers to reflect this.
2383 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2384 unsigned int ep, unsigned int mps,
2385 unsigned int mc, unsigned int dir_in)
2387 struct dwc2_hsotg_ep *hs_ep;
2388 void __iomem *regs = hsotg->regs;
2391 hs_ep = index_to_ep(hsotg, ep, dir_in);
2396 u32 mps_bytes = mps;
2398 /* EP0 is a special case */
2399 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2402 hs_ep->ep.maxpacket = mps_bytes;
2410 hs_ep->ep.maxpacket = mps;
2414 reg = dwc2_readl(regs + DIEPCTL(ep));
2415 reg &= ~DXEPCTL_MPS_MASK;
2417 dwc2_writel(reg, regs + DIEPCTL(ep));
2419 reg = dwc2_readl(regs + DOEPCTL(ep));
2420 reg &= ~DXEPCTL_MPS_MASK;
2422 dwc2_writel(reg, regs + DOEPCTL(ep));
2428 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2432 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2433 * @hsotg: The driver state
2434 * @idx: The index for the endpoint (0..15)
2436 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2441 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2442 hsotg->regs + GRSTCTL);
2444 /* wait until the fifo is flushed */
2448 val = dwc2_readl(hsotg->regs + GRSTCTL);
2450 if ((val & (GRSTCTL_TXFFLSH)) == 0)
2453 if (--timeout == 0) {
2455 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2465 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2466 * @hsotg: The driver state
2467 * @hs_ep: The driver endpoint to check.
2469 * Check to see if there is a request that has data to send, and if so
2470 * make an attempt to write data into the FIFO.
2472 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2473 struct dwc2_hsotg_ep *hs_ep)
2475 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2477 if (!hs_ep->dir_in || !hs_req) {
2479 * if request is not enqueued, we disable interrupts
2480 * for endpoints, excepting ep0
2482 if (hs_ep->index != 0)
2483 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2488 if (hs_req->req.actual < hs_req->req.length) {
2489 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2491 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2498 * dwc2_hsotg_complete_in - complete IN transfer
2499 * @hsotg: The device state.
2500 * @hs_ep: The endpoint that has just completed.
2502 * An IN transfer has been completed, update the transfer's state and then
2503 * call the relevant completion routines.
2505 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2506 struct dwc2_hsotg_ep *hs_ep)
2508 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2509 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2510 int size_left, size_done;
2513 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2517 /* Finish ZLP handling for IN EP0 transactions */
2518 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2519 dev_dbg(hsotg->dev, "zlp packet sent\n");
2522 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2523 * changed to IN. Change back to complete OUT transfer request
2527 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2528 if (hsotg->test_mode) {
2531 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2533 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2535 dwc2_hsotg_stall_ep0(hsotg);
2539 dwc2_hsotg_enqueue_setup(hsotg);
2544 * Calculate the size of the transfer by checking how much is left
2545 * in the endpoint size register and then working it out from
2546 * the amount we loaded for the transfer.
2548 * We do this even for DMA, as the transfer may have incremented
2549 * past the end of the buffer (DMA transfers are always 32bit
2552 if (using_desc_dma(hsotg)) {
2553 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2555 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2558 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2561 size_done = hs_ep->size_loaded - size_left;
2562 size_done += hs_ep->last_load;
2564 if (hs_req->req.actual != size_done)
2565 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2566 __func__, hs_req->req.actual, size_done);
2568 hs_req->req.actual = size_done;
2569 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2570 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2572 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2573 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2574 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2578 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2579 if (hs_ep->send_zlp) {
2580 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2581 hs_ep->send_zlp = 0;
2582 /* transfer will be completed on next complete interrupt */
2586 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2587 /* Move to STATUS OUT */
2588 dwc2_hsotg_ep0_zlp(hsotg, false);
2592 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2596 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2597 * @hsotg: The device state.
2598 * @idx: Index of ep.
2599 * @dir_in: Endpoint direction 1-in 0-out.
2601 * Reads for endpoint with given index and direction, by masking
2602 * epint_reg with coresponding mask.
2604 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2605 unsigned int idx, int dir_in)
2607 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2608 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2613 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2614 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2615 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2616 mask |= DXEPINT_SETUP_RCVD;
2618 ints = dwc2_readl(hsotg->regs + epint_reg);
2624 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2625 * @hs_ep: The endpoint on which interrupt is asserted.
2627 * This interrupt indicates that the endpoint has been disabled per the
2628 * application's request.
2630 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2631 * in case of ISOC completes current request.
2633 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2634 * request starts it.
2636 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2638 struct dwc2_hsotg *hsotg = hs_ep->parent;
2639 struct dwc2_hsotg_req *hs_req;
2640 unsigned char idx = hs_ep->index;
2641 int dir_in = hs_ep->dir_in;
2642 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2643 int dctl = dwc2_readl(hsotg->regs + DCTL);
2645 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2648 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2650 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2652 if (hs_ep->isochronous) {
2653 dwc2_hsotg_complete_in(hsotg, hs_ep);
2657 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2658 int dctl = dwc2_readl(hsotg->regs + DCTL);
2660 dctl |= DCTL_CGNPINNAK;
2661 dwc2_writel(dctl, hsotg->regs + DCTL);
2666 if (dctl & DCTL_GOUTNAKSTS) {
2667 dctl |= DCTL_CGOUTNAK;
2668 dwc2_writel(dctl, hsotg->regs + DCTL);
2671 if (!hs_ep->isochronous)
2674 if (list_empty(&hs_ep->queue)) {
2675 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2681 hs_req = get_ep_head(hs_ep);
2683 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2685 dwc2_gadget_incr_frame_num(hs_ep);
2686 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2688 dwc2_gadget_start_next_request(hs_ep);
2692 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2693 * @hs_ep: The endpoint on which interrupt is asserted.
2695 * This is starting point for ISOC-OUT transfer, synchronization done with
2696 * first out token received from host while corresponding EP is disabled.
2698 * Device does not know initial frame in which out token will come. For this
2699 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2700 * getting this interrupt SW starts calculation for next transfer frame.
2702 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2704 struct dwc2_hsotg *hsotg = ep->parent;
2705 int dir_in = ep->dir_in;
2709 if (dir_in || !ep->isochronous)
2713 * Store frame in which irq was asserted here, as
2714 * it can change while completing request below.
2716 tmp = dwc2_hsotg_read_frameno(hsotg);
2718 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2720 if (using_desc_dma(hsotg)) {
2721 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2722 /* Start first ISO Out */
2723 ep->target_frame = tmp;
2724 dwc2_gadget_start_isoc_ddma(ep);
2729 if (ep->interval > 1 &&
2730 ep->target_frame == TARGET_FRAME_INITIAL) {
2734 dsts = dwc2_readl(hsotg->regs + DSTS);
2735 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2736 dwc2_gadget_incr_frame_num(ep);
2738 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2739 if (ep->target_frame & 0x1)
2740 ctrl |= DXEPCTL_SETODDFR;
2742 ctrl |= DXEPCTL_SETEVENFR;
2744 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2747 dwc2_gadget_start_next_request(ep);
2748 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2749 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2750 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2754 * dwc2_gadget_handle_nak - handle NAK interrupt
2755 * @hs_ep: The endpoint on which interrupt is asserted.
2757 * This is starting point for ISOC-IN transfer, synchronization done with
2758 * first IN token received from host while corresponding EP is disabled.
2760 * Device does not know when first one token will arrive from host. On first
2761 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2762 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2763 * sent in response to that as there was no data in FIFO. SW is basing on this
2764 * interrupt to obtain frame in which token has come and then based on the
2765 * interval calculates next frame for transfer.
2767 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2769 struct dwc2_hsotg *hsotg = hs_ep->parent;
2770 int dir_in = hs_ep->dir_in;
2772 if (!dir_in || !hs_ep->isochronous)
2775 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2776 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2778 if (using_desc_dma(hsotg)) {
2779 dwc2_gadget_start_isoc_ddma(hs_ep);
2783 if (hs_ep->interval > 1) {
2784 u32 ctrl = dwc2_readl(hsotg->regs +
2785 DIEPCTL(hs_ep->index));
2786 if (hs_ep->target_frame & 0x1)
2787 ctrl |= DXEPCTL_SETODDFR;
2789 ctrl |= DXEPCTL_SETEVENFR;
2791 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2794 dwc2_hsotg_complete_request(hsotg, hs_ep,
2795 get_ep_head(hs_ep), 0);
2798 dwc2_gadget_incr_frame_num(hs_ep);
2802 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2803 * @hsotg: The driver state
2804 * @idx: The index for the endpoint (0..15)
2805 * @dir_in: Set if this is an IN endpoint
2807 * Process and clear any interrupt pending for an individual endpoint
2809 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2812 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2813 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2814 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2815 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2819 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2820 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2822 /* Clear endpoint interrupts */
2823 dwc2_writel(ints, hsotg->regs + epint_reg);
2826 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2827 __func__, idx, dir_in ? "in" : "out");
2831 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2832 __func__, idx, dir_in ? "in" : "out", ints);
2834 /* Don't process XferCompl interrupt if it is a setup packet */
2835 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2836 ints &= ~DXEPINT_XFERCOMPL;
2839 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2840 * stage and xfercomplete was generated without SETUP phase done
2841 * interrupt. SW should parse received setup packet only after host's
2842 * exit from setup phase of control transfer.
2844 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2845 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2846 ints &= ~DXEPINT_XFERCOMPL;
2848 if (ints & DXEPINT_XFERCOMPL) {
2850 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2851 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2852 dwc2_readl(hsotg->regs + epsiz_reg));
2854 /* In DDMA handle isochronous requests separately */
2855 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2856 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2857 /* Try to start next isoc request */
2858 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2859 } else if (dir_in) {
2861 * We get OutDone from the FIFO, so we only
2862 * need to look at completing IN requests here
2863 * if operating slave mode
2865 if (hs_ep->isochronous && hs_ep->interval > 1)
2866 dwc2_gadget_incr_frame_num(hs_ep);
2868 dwc2_hsotg_complete_in(hsotg, hs_ep);
2869 if (ints & DXEPINT_NAKINTRPT)
2870 ints &= ~DXEPINT_NAKINTRPT;
2872 if (idx == 0 && !hs_ep->req)
2873 dwc2_hsotg_enqueue_setup(hsotg);
2874 } else if (using_dma(hsotg)) {
2876 * We're using DMA, we need to fire an OutDone here
2877 * as we ignore the RXFIFO.
2879 if (hs_ep->isochronous && hs_ep->interval > 1)
2880 dwc2_gadget_incr_frame_num(hs_ep);
2882 dwc2_hsotg_handle_outdone(hsotg, idx);
2886 if (ints & DXEPINT_EPDISBLD)
2887 dwc2_gadget_handle_ep_disabled(hs_ep);
2889 if (ints & DXEPINT_OUTTKNEPDIS)
2890 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2892 if (ints & DXEPINT_NAKINTRPT)
2893 dwc2_gadget_handle_nak(hs_ep);
2895 if (ints & DXEPINT_AHBERR)
2896 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2898 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2899 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2901 if (using_dma(hsotg) && idx == 0) {
2903 * this is the notification we've received a
2904 * setup packet. In non-DMA mode we'd get this
2905 * from the RXFIFO, instead we need to process
2912 dwc2_hsotg_handle_outdone(hsotg, 0);
2916 if (ints & DXEPINT_STSPHSERCVD) {
2917 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2919 /* Move to STATUS IN for DDMA */
2920 if (using_desc_dma(hsotg))
2921 dwc2_hsotg_ep0_zlp(hsotg, true);
2924 if (ints & DXEPINT_BACK2BACKSETUP)
2925 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2927 if (ints & DXEPINT_BNAINTR) {
2928 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2931 * Try to start next isoc request, if any.
2932 * Sometimes the endpoint remains enabled after BNA interrupt
2933 * assertion, which is not expected, hence we can enter here
2936 if (hs_ep->isochronous)
2937 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2940 if (dir_in && !hs_ep->isochronous) {
2941 /* not sure if this is important, but we'll clear it anyway */
2942 if (ints & DXEPINT_INTKNTXFEMP) {
2943 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2947 /* this probably means something bad is happening */
2948 if (ints & DXEPINT_INTKNEPMIS) {
2949 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2953 /* FIFO has space or is empty (see GAHBCFG) */
2954 if (hsotg->dedicated_fifos &&
2955 ints & DXEPINT_TXFEMP) {
2956 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2958 if (!using_dma(hsotg))
2959 dwc2_hsotg_trytx(hsotg, hs_ep);
2965 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2966 * @hsotg: The device state.
2968 * Handle updating the device settings after the enumeration phase has
2971 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2973 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2974 int ep0_mps = 0, ep_mps = 8;
2977 * This should signal the finish of the enumeration phase
2978 * of the USB handshaking, so we should now know what rate
2982 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2985 * note, since we're limited by the size of transfer on EP0, and
2986 * it seems IN transfers must be a even number of packets we do
2987 * not advertise a 64byte MPS on EP0.
2990 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2991 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2992 case DSTS_ENUMSPD_FS:
2993 case DSTS_ENUMSPD_FS48:
2994 hsotg->gadget.speed = USB_SPEED_FULL;
2995 ep0_mps = EP0_MPS_LIMIT;
2999 case DSTS_ENUMSPD_HS:
3000 hsotg->gadget.speed = USB_SPEED_HIGH;
3001 ep0_mps = EP0_MPS_LIMIT;
3005 case DSTS_ENUMSPD_LS:
3006 hsotg->gadget.speed = USB_SPEED_LOW;
3010 * note, we don't actually support LS in this driver at the
3011 * moment, and the documentation seems to imply that it isn't
3012 * supported by the PHYs on some of the devices.
3016 dev_info(hsotg->dev, "new device is %s\n",
3017 usb_speed_string(hsotg->gadget.speed));
3020 * we should now know the maximum packet size for an
3021 * endpoint, so set the endpoints to a default value.
3026 /* Initialize ep0 for both in and out directions */
3027 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3028 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3029 for (i = 1; i < hsotg->num_of_eps; i++) {
3030 if (hsotg->eps_in[i])
3031 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3033 if (hsotg->eps_out[i])
3034 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3039 /* ensure after enumeration our EP0 is active */
3041 dwc2_hsotg_enqueue_setup(hsotg);
3043 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3044 dwc2_readl(hsotg->regs + DIEPCTL0),
3045 dwc2_readl(hsotg->regs + DOEPCTL0));
3049 * kill_all_requests - remove all requests from the endpoint's queue
3050 * @hsotg: The device state.
3051 * @ep: The endpoint the requests may be on.
3052 * @result: The result code to use.
3054 * Go through the requests on the given endpoint and mark them
3055 * completed with the given result code.
3057 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3058 struct dwc2_hsotg_ep *ep,
3061 struct dwc2_hsotg_req *req, *treq;
3066 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3067 dwc2_hsotg_complete_request(hsotg, ep, req,
3070 if (!hsotg->dedicated_fifos)
3072 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3073 if (size < ep->fifo_size)
3074 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3078 * dwc2_hsotg_disconnect - disconnect service
3079 * @hsotg: The device state.
3081 * The device has been disconnected. Remove all current
3082 * transactions and signal the gadget driver that this
3085 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3089 if (!hsotg->connected)
3092 hsotg->connected = 0;
3093 hsotg->test_mode = 0;
3095 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3096 if (hsotg->eps_in[ep])
3097 kill_all_requests(hsotg, hsotg->eps_in[ep],
3099 if (hsotg->eps_out[ep])
3100 kill_all_requests(hsotg, hsotg->eps_out[ep],
3104 call_gadget(hsotg, disconnect);
3105 hsotg->lx_state = DWC2_L3;
3109 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3110 * @hsotg: The device state:
3111 * @periodic: True if this is a periodic FIFO interrupt
3113 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3115 struct dwc2_hsotg_ep *ep;
3118 /* look through for any more data to transmit */
3119 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3120 ep = index_to_ep(hsotg, epno, 1);
3128 if ((periodic && !ep->periodic) ||
3129 (!periodic && ep->periodic))
3132 ret = dwc2_hsotg_trytx(hsotg, ep);
3138 /* IRQ flags which will trigger a retry around the IRQ loop */
3139 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3144 * dwc2_hsotg_core_init - issue softreset to the core
3145 * @hsotg: The device state
3147 * Issue a soft reset to the core, and await the core finishing it.
3149 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3157 /* Kill any ep0 requests as controller will be reinitialized */
3158 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3161 if (dwc2_core_reset(hsotg))
3165 * we must now enable ep0 ready for host detection and then
3166 * set configuration.
3169 /* keep other bits untouched (so e.g. forced modes are not lost) */
3170 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3171 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3174 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3175 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3176 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3177 /* FS/LS Dedicated Transceiver Interface */
3178 usbcfg |= GUSBCFG_PHYSEL;
3180 /* set the PLL on, remove the HNP/SRP and set the PHY */
3181 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3182 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3183 (val << GUSBCFG_USBTRDTIM_SHIFT);
3185 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3187 dwc2_hsotg_init_fifo(hsotg);
3190 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3192 dcfg |= DCFG_EPMISCNT(1);
3194 switch (hsotg->params.speed) {
3195 case DWC2_SPEED_PARAM_LOW:
3196 dcfg |= DCFG_DEVSPD_LS;
3198 case DWC2_SPEED_PARAM_FULL:
3199 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3200 dcfg |= DCFG_DEVSPD_FS48;
3202 dcfg |= DCFG_DEVSPD_FS;
3205 dcfg |= DCFG_DEVSPD_HS;
3208 dwc2_writel(dcfg, hsotg->regs + DCFG);
3210 /* Clear any pending OTG interrupts */
3211 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3213 /* Clear any pending interrupts */
3214 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3215 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3216 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3217 GINTSTS_USBRST | GINTSTS_RESETDET |
3218 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3219 GINTSTS_USBSUSP | GINTSTS_WKUPINT;
3221 if (!using_desc_dma(hsotg))
3222 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3224 if (hsotg->params.external_id_pin_ctl <= 0)
3225 intmsk |= GINTSTS_CONIDSTSCHNG;
3227 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3229 if (using_dma(hsotg)) {
3230 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3231 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
3232 hsotg->regs + GAHBCFG);
3234 /* Set DDMA mode support in the core if needed */
3235 if (using_desc_dma(hsotg))
3236 __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3239 dwc2_writel(((hsotg->dedicated_fifos) ?
3240 (GAHBCFG_NP_TXF_EMP_LVL |
3241 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3242 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3246 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3247 * when we have no data to transfer. Otherwise we get being flooded by
3251 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3252 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3253 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3254 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3255 hsotg->regs + DIEPMSK);
3258 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3259 * DMA mode we may need this and StsPhseRcvd.
3261 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3262 DOEPMSK_STSPHSERCVDMSK) : 0) |
3263 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3265 hsotg->regs + DOEPMSK);
3267 /* Enable BNA interrupt for DDMA */
3268 if (using_desc_dma(hsotg))
3269 __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3271 dwc2_writel(0, hsotg->regs + DAINTMSK);
3273 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3274 dwc2_readl(hsotg->regs + DIEPCTL0),
3275 dwc2_readl(hsotg->regs + DOEPCTL0));
3277 /* enable in and out endpoint interrupts */
3278 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3281 * Enable the RXFIFO when in slave mode, as this is how we collect
3282 * the data. In DMA mode, we get events from the FIFO but also
3283 * things we cannot process, so do not use it.
3285 if (!using_dma(hsotg))
3286 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3288 /* Enable interrupts for EP0 in and out */
3289 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3290 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3292 if (!is_usb_reset) {
3293 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3294 udelay(10); /* see openiboot */
3295 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3298 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3301 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3302 * writing to the EPCTL register..
3305 /* set to read 1 8byte packet */
3306 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3307 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3309 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3310 DXEPCTL_CNAK | DXEPCTL_EPENA |
3312 hsotg->regs + DOEPCTL0);
3314 /* enable, but don't activate EP0in */
3315 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3316 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3318 dwc2_hsotg_enqueue_setup(hsotg);
3320 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3321 dwc2_readl(hsotg->regs + DIEPCTL0),
3322 dwc2_readl(hsotg->regs + DOEPCTL0));
3324 /* clear global NAKs */
3325 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3327 val |= DCTL_SFTDISCON;
3328 __orr32(hsotg->regs + DCTL, val);
3330 /* must be at-least 3ms to allow bus to see disconnect */
3333 hsotg->lx_state = DWC2_L0;
3336 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3338 /* set the soft-disconnect bit */
3339 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3342 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3344 /* remove the soft-disconnect and let's go */
3345 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3349 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3350 * @hsotg: The device state:
3352 * This interrupt indicates one of the following conditions occurred while
3353 * transmitting an ISOC transaction.
3354 * - Corrupted IN Token for ISOC EP.
3355 * - Packet not complete in FIFO.
3357 * The following actions will be taken:
3358 * - Determine the EP
3359 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3361 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3363 struct dwc2_hsotg_ep *hs_ep;
3367 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3369 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3370 hs_ep = hsotg->eps_in[idx];
3371 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3372 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3373 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3374 epctrl |= DXEPCTL_SNAK;
3375 epctrl |= DXEPCTL_EPDIS;
3376 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3380 /* Clear interrupt */
3381 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3385 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3386 * @hsotg: The device state:
3388 * This interrupt indicates one of the following conditions occurred while
3389 * transmitting an ISOC transaction.
3390 * - Corrupted OUT Token for ISOC EP.
3391 * - Packet not complete in FIFO.
3393 * The following actions will be taken:
3394 * - Determine the EP
3395 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3397 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3402 struct dwc2_hsotg_ep *hs_ep;
3405 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3407 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3408 hs_ep = hsotg->eps_out[idx];
3409 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3410 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3411 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3412 /* Unmask GOUTNAKEFF interrupt */
3413 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3414 gintmsk |= GINTSTS_GOUTNAKEFF;
3415 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3417 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3418 if (!(gintsts & GINTSTS_GOUTNAKEFF))
3419 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3423 /* Clear interrupt */
3424 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3428 * dwc2_hsotg_irq - handle device interrupt
3429 * @irq: The IRQ number triggered
3430 * @pw: The pw value when registered the handler.
3432 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3434 struct dwc2_hsotg *hsotg = pw;
3435 int retry_count = 8;
3439 if (!dwc2_is_device_mode(hsotg))
3442 spin_lock(&hsotg->lock);
3444 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3445 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3447 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3448 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3452 if (gintsts & GINTSTS_RESETDET) {
3453 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3455 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3457 /* This event must be used only if controller is suspended */
3458 if (hsotg->lx_state == DWC2_L2) {
3459 dwc2_exit_hibernation(hsotg, true);
3460 hsotg->lx_state = DWC2_L0;
3464 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3465 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3466 u32 connected = hsotg->connected;
3468 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3469 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3470 dwc2_readl(hsotg->regs + GNPTXSTS));
3472 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3474 /* Report disconnection if it is not already done. */
3475 dwc2_hsotg_disconnect(hsotg);
3477 if (usb_status & GOTGCTL_BSESVLD && connected)
3478 dwc2_hsotg_core_init_disconnected(hsotg, true);
3481 if (gintsts & GINTSTS_ENUMDONE) {
3482 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3484 dwc2_hsotg_irq_enumdone(hsotg);
3487 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3488 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3489 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3490 u32 daint_out, daint_in;
3494 daint_out = daint >> DAINT_OUTEP_SHIFT;
3495 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3497 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3499 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3500 ep++, daint_out >>= 1) {
3502 dwc2_hsotg_epint(hsotg, ep, 0);
3505 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3506 ep++, daint_in >>= 1) {
3508 dwc2_hsotg_epint(hsotg, ep, 1);
3512 /* check both FIFOs */
3514 if (gintsts & GINTSTS_NPTXFEMP) {
3515 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3518 * Disable the interrupt to stop it happening again
3519 * unless one of these endpoint routines decides that
3520 * it needs re-enabling
3523 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3524 dwc2_hsotg_irq_fifoempty(hsotg, false);
3527 if (gintsts & GINTSTS_PTXFEMP) {
3528 dev_dbg(hsotg->dev, "PTxFEmp\n");
3530 /* See note in GINTSTS_NPTxFEmp */
3532 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3533 dwc2_hsotg_irq_fifoempty(hsotg, true);
3536 if (gintsts & GINTSTS_RXFLVL) {
3538 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3539 * we need to retry dwc2_hsotg_handle_rx if this is still
3543 dwc2_hsotg_handle_rx(hsotg);
3546 if (gintsts & GINTSTS_ERLYSUSP) {
3547 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3548 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3552 * these next two seem to crop-up occasionally causing the core
3553 * to shutdown the USB transfer, so try clearing them and logging
3557 if (gintsts & GINTSTS_GOUTNAKEFF) {
3561 struct dwc2_hsotg_ep *hs_ep;
3563 /* Mask this interrupt */
3564 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3565 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3566 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3568 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3569 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3570 hs_ep = hsotg->eps_out[idx];
3571 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3573 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3574 epctrl |= DXEPCTL_SNAK;
3575 epctrl |= DXEPCTL_EPDIS;
3576 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3580 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3583 if (gintsts & GINTSTS_GINNAKEFF) {
3584 dev_info(hsotg->dev, "GINNakEff triggered\n");
3586 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3588 dwc2_hsotg_dump(hsotg);
3591 if (gintsts & GINTSTS_INCOMPL_SOIN)
3592 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3594 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3595 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3598 * if we've had fifo events, we should try and go around the
3599 * loop again to see if there's any point in returning yet.
3602 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3605 spin_unlock(&hsotg->lock);
3610 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3611 u32 bit, u32 timeout)
3615 for (i = 0; i < timeout; i++) {
3616 if (dwc2_readl(hs_otg->regs + reg) & bit)
3624 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3625 struct dwc2_hsotg_ep *hs_ep)
3630 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3631 DOEPCTL(hs_ep->index);
3632 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3633 DOEPINT(hs_ep->index);
3635 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3638 if (hs_ep->dir_in) {
3639 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3640 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3641 /* Wait for Nak effect */
3642 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3643 DXEPINT_INEPNAKEFF, 100))
3644 dev_warn(hsotg->dev,
3645 "%s: timeout DIEPINT.NAKEFF\n",
3648 __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3649 /* Wait for Nak effect */
3650 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3651 GINTSTS_GINNAKEFF, 100))
3652 dev_warn(hsotg->dev,
3653 "%s: timeout GINTSTS.GINNAKEFF\n",
3657 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3658 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3660 /* Wait for global nak to take effect */
3661 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3662 GINTSTS_GOUTNAKEFF, 100))
3663 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3668 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3670 /* Wait for ep to be disabled */
3671 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3672 dev_warn(hsotg->dev,
3673 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3675 /* Clear EPDISBLD interrupt */
3676 __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3678 if (hs_ep->dir_in) {
3679 unsigned short fifo_index;
3681 if (hsotg->dedicated_fifos || hs_ep->periodic)
3682 fifo_index = hs_ep->fifo_index;
3687 dwc2_flush_tx_fifo(hsotg, fifo_index);
3689 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3690 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3691 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3694 /* Remove global NAKs */
3695 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3700 * dwc2_hsotg_ep_enable - enable the given endpoint
3701 * @ep: The USB endpint to configure
3702 * @desc: The USB endpoint descriptor to configure with.
3704 * This is called from the USB gadget code's usb_ep_enable().
3706 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3707 const struct usb_endpoint_descriptor *desc)
3709 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3710 struct dwc2_hsotg *hsotg = hs_ep->parent;
3711 unsigned long flags;
3712 unsigned int index = hs_ep->index;
3718 unsigned int dir_in;
3719 unsigned int i, val, size;
3723 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3724 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3725 desc->wMaxPacketSize, desc->bInterval);
3727 /* not to be called for EP0 */
3729 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3733 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3734 if (dir_in != hs_ep->dir_in) {
3735 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3739 mps = usb_endpoint_maxp(desc);
3740 mc = usb_endpoint_maxp_mult(desc);
3742 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3744 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3745 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3747 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3748 __func__, epctrl, epctrl_reg);
3750 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3751 if (using_desc_dma(hsotg)) {
3752 hs_ep->desc_list = dma_alloc_coherent(hsotg->dev,
3753 MAX_DMA_DESC_NUM_GENERIC *
3754 sizeof(struct dwc2_dma_desc),
3755 &hs_ep->desc_list_dma, GFP_ATOMIC);
3756 if (!hs_ep->desc_list) {
3762 spin_lock_irqsave(&hsotg->lock, flags);
3764 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3765 epctrl |= DXEPCTL_MPS(mps);
3768 * mark the endpoint as active, otherwise the core may ignore
3769 * transactions entirely for this endpoint
3771 epctrl |= DXEPCTL_USBACTEP;
3773 /* update the endpoint state */
3774 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3776 /* default, set to non-periodic */
3777 hs_ep->isochronous = 0;
3778 hs_ep->periodic = 0;
3780 hs_ep->interval = desc->bInterval;
3782 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3783 case USB_ENDPOINT_XFER_ISOC:
3784 epctrl |= DXEPCTL_EPTYPE_ISO;
3785 epctrl |= DXEPCTL_SETEVENFR;
3786 hs_ep->isochronous = 1;
3787 hs_ep->interval = 1 << (desc->bInterval - 1);
3788 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3789 hs_ep->isoc_chain_num = 0;
3790 hs_ep->next_desc = 0;
3792 hs_ep->periodic = 1;
3793 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3794 mask |= DIEPMSK_NAKMSK;
3795 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3797 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3798 mask |= DOEPMSK_OUTTKNEPDISMSK;
3799 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3803 case USB_ENDPOINT_XFER_BULK:
3804 epctrl |= DXEPCTL_EPTYPE_BULK;
3807 case USB_ENDPOINT_XFER_INT:
3809 hs_ep->periodic = 1;
3811 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3812 hs_ep->interval = 1 << (desc->bInterval - 1);
3814 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3817 case USB_ENDPOINT_XFER_CONTROL:
3818 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3823 * if the hardware has dedicated fifos, we must give each IN EP
3824 * a unique tx-fifo even if it is non-periodic.
3826 if (dir_in && hsotg->dedicated_fifos) {
3828 u32 fifo_size = UINT_MAX;
3830 size = hs_ep->ep.maxpacket * hs_ep->mc;
3831 for (i = 1; i < hsotg->num_of_eps; ++i) {
3832 if (hsotg->fifo_map & (1 << i))
3834 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3835 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3838 /* Search for smallest acceptable fifo */
3839 if (val < fifo_size) {
3846 "%s: No suitable fifo found\n", __func__);
3850 hsotg->fifo_map |= 1 << fifo_index;
3851 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3852 hs_ep->fifo_index = fifo_index;
3853 hs_ep->fifo_size = fifo_size;
3856 /* for non control endpoints, set PID to D0 */
3857 if (index && !hs_ep->isochronous)
3858 epctrl |= DXEPCTL_SETD0PID;
3860 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3863 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3864 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3865 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3867 /* enable the endpoint interrupt */
3868 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3871 spin_unlock_irqrestore(&hsotg->lock, flags);
3874 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3875 dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3876 sizeof(struct dwc2_dma_desc),
3877 hs_ep->desc_list, hs_ep->desc_list_dma);
3878 hs_ep->desc_list = NULL;
3885 * dwc2_hsotg_ep_disable - disable given endpoint
3886 * @ep: The endpoint to disable.
3888 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
3890 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3891 struct dwc2_hsotg *hsotg = hs_ep->parent;
3892 int dir_in = hs_ep->dir_in;
3893 int index = hs_ep->index;
3894 unsigned long flags;
3898 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
3900 if (ep == &hsotg->eps_out[0]->ep) {
3901 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3905 /* Remove DMA memory allocated for non-control Endpoints */
3906 if (using_desc_dma(hsotg)) {
3907 dma_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3908 sizeof(struct dwc2_dma_desc),
3909 hs_ep->desc_list, hs_ep->desc_list_dma);
3910 hs_ep->desc_list = NULL;
3913 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3915 spin_lock_irqsave(&hsotg->lock, flags);
3917 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3919 if (ctrl & DXEPCTL_EPENA)
3920 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3922 ctrl &= ~DXEPCTL_EPENA;
3923 ctrl &= ~DXEPCTL_USBACTEP;
3924 ctrl |= DXEPCTL_SNAK;
3926 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
3927 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
3929 /* disable endpoint interrupts */
3930 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
3932 /* terminate all requests with shutdown */
3933 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
3935 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
3936 hs_ep->fifo_index = 0;
3937 hs_ep->fifo_size = 0;
3939 spin_unlock_irqrestore(&hsotg->lock, flags);
3944 * on_list - check request is on the given endpoint
3945 * @ep: The endpoint to check.
3946 * @test: The request to test if it is on the endpoint.
3948 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
3950 struct dwc2_hsotg_req *req, *treq;
3952 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
3961 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3962 * @ep: The endpoint to dequeue.
3963 * @req: The request to be removed from a queue.
3965 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
3967 struct dwc2_hsotg_req *hs_req = our_req(req);
3968 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3969 struct dwc2_hsotg *hs = hs_ep->parent;
3970 unsigned long flags;
3972 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
3974 spin_lock_irqsave(&hs->lock, flags);
3976 if (!on_list(hs_ep, hs_req)) {
3977 spin_unlock_irqrestore(&hs->lock, flags);
3981 /* Dequeue already started request */
3982 if (req == &hs_ep->req->req)
3983 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
3985 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
3986 spin_unlock_irqrestore(&hs->lock, flags);
3992 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3993 * @ep: The endpoint to set halt.
3994 * @value: Set or unset the halt.
3995 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
3996 * the endpoint is busy processing requests.
3998 * We need to stall the endpoint immediately if request comes from set_feature
3999 * protocol command handler.
4001 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4003 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4004 struct dwc2_hsotg *hs = hs_ep->parent;
4005 int index = hs_ep->index;
4010 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4014 dwc2_hsotg_stall_ep0(hs);
4017 "%s: can't clear halt on ep0\n", __func__);
4021 if (hs_ep->isochronous) {
4022 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4026 if (!now && value && !list_empty(&hs_ep->queue)) {
4027 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4032 if (hs_ep->dir_in) {
4033 epreg = DIEPCTL(index);
4034 epctl = dwc2_readl(hs->regs + epreg);
4037 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4038 if (epctl & DXEPCTL_EPENA)
4039 epctl |= DXEPCTL_EPDIS;
4041 epctl &= ~DXEPCTL_STALL;
4042 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4043 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4044 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4045 epctl |= DXEPCTL_SETD0PID;
4047 dwc2_writel(epctl, hs->regs + epreg);
4049 epreg = DOEPCTL(index);
4050 epctl = dwc2_readl(hs->regs + epreg);
4053 epctl |= DXEPCTL_STALL;
4055 epctl &= ~DXEPCTL_STALL;
4056 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4057 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4058 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4059 epctl |= DXEPCTL_SETD0PID;
4061 dwc2_writel(epctl, hs->regs + epreg);
4064 hs_ep->halted = value;
4070 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4071 * @ep: The endpoint to set halt.
4072 * @value: Set or unset the halt.
4074 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4076 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4077 struct dwc2_hsotg *hs = hs_ep->parent;
4078 unsigned long flags = 0;
4081 spin_lock_irqsave(&hs->lock, flags);
4082 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4083 spin_unlock_irqrestore(&hs->lock, flags);
4088 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
4089 .enable = dwc2_hsotg_ep_enable,
4090 .disable = dwc2_hsotg_ep_disable,
4091 .alloc_request = dwc2_hsotg_ep_alloc_request,
4092 .free_request = dwc2_hsotg_ep_free_request,
4093 .queue = dwc2_hsotg_ep_queue_lock,
4094 .dequeue = dwc2_hsotg_ep_dequeue,
4095 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4096 /* note, don't believe we have any call for the fifo routines */
4100 * dwc2_hsotg_init - initialize the usb core
4101 * @hsotg: The driver state
4103 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4107 /* unmask subset of endpoint interrupts */
4109 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4110 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4111 hsotg->regs + DIEPMSK);
4113 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4114 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4115 hsotg->regs + DOEPMSK);
4117 dwc2_writel(0, hsotg->regs + DAINTMSK);
4119 /* Be in disconnected state until gadget is registered */
4120 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
4124 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4125 dwc2_readl(hsotg->regs + GRXFSIZ),
4126 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4128 dwc2_hsotg_init_fifo(hsotg);
4130 /* keep other bits untouched (so e.g. forced modes are not lost) */
4131 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4132 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4135 /* set the PLL on, remove the HNP/SRP and set the PHY */
4136 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4137 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4138 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4139 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4141 if (using_dma(hsotg))
4142 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4146 * dwc2_hsotg_udc_start - prepare the udc for work
4147 * @gadget: The usb gadget state
4148 * @driver: The usb gadget driver
4150 * Perform initialization to prepare udc device and driver
4153 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4154 struct usb_gadget_driver *driver)
4156 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4157 unsigned long flags;
4161 pr_err("%s: called with no device\n", __func__);
4166 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4170 if (driver->max_speed < USB_SPEED_FULL)
4171 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4173 if (!driver->setup) {
4174 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4178 WARN_ON(hsotg->driver);
4180 driver->driver.bus = NULL;
4181 hsotg->driver = driver;
4182 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4183 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4185 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4186 ret = dwc2_lowlevel_hw_enable(hsotg);
4191 if (!IS_ERR_OR_NULL(hsotg->uphy))
4192 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4194 spin_lock_irqsave(&hsotg->lock, flags);
4195 if (dwc2_hw_is_device(hsotg)) {
4196 dwc2_hsotg_init(hsotg);
4197 dwc2_hsotg_core_init_disconnected(hsotg, false);
4201 spin_unlock_irqrestore(&hsotg->lock, flags);
4203 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4208 hsotg->driver = NULL;
4213 * dwc2_hsotg_udc_stop - stop the udc
4214 * @gadget: The usb gadget state
4215 * @driver: The usb gadget driver
4217 * Stop udc hw block and stay tunned for future transmissions
4219 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4221 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4222 unsigned long flags = 0;
4228 /* all endpoints should be shutdown */
4229 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4230 if (hsotg->eps_in[ep])
4231 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4232 if (hsotg->eps_out[ep])
4233 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4236 spin_lock_irqsave(&hsotg->lock, flags);
4238 hsotg->driver = NULL;
4239 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4242 spin_unlock_irqrestore(&hsotg->lock, flags);
4244 if (!IS_ERR_OR_NULL(hsotg->uphy))
4245 otg_set_peripheral(hsotg->uphy->otg, NULL);
4247 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4248 dwc2_lowlevel_hw_disable(hsotg);
4254 * dwc2_hsotg_gadget_getframe - read the frame number
4255 * @gadget: The usb gadget state
4257 * Read the {micro} frame number
4259 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4261 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4265 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4266 * @gadget: The usb gadget state
4267 * @is_on: Current state of the USB PHY
4269 * Connect/Disconnect the USB PHY pullup
4271 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4273 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4274 unsigned long flags = 0;
4276 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4279 /* Don't modify pullup state while in host mode */
4280 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4281 hsotg->enabled = is_on;
4285 spin_lock_irqsave(&hsotg->lock, flags);
4288 dwc2_hsotg_core_init_disconnected(hsotg, false);
4289 dwc2_hsotg_core_connect(hsotg);
4291 dwc2_hsotg_core_disconnect(hsotg);
4292 dwc2_hsotg_disconnect(hsotg);
4296 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4297 spin_unlock_irqrestore(&hsotg->lock, flags);
4302 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4304 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4305 unsigned long flags;
4307 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4308 spin_lock_irqsave(&hsotg->lock, flags);
4311 * If controller is hibernated, it must exit from hibernation
4312 * before being initialized / de-initialized
4314 if (hsotg->lx_state == DWC2_L2)
4315 dwc2_exit_hibernation(hsotg, false);
4318 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4320 dwc2_hsotg_core_init_disconnected(hsotg, false);
4322 dwc2_hsotg_core_connect(hsotg);
4324 dwc2_hsotg_core_disconnect(hsotg);
4325 dwc2_hsotg_disconnect(hsotg);
4328 spin_unlock_irqrestore(&hsotg->lock, flags);
4333 * dwc2_hsotg_vbus_draw - report bMaxPower field
4334 * @gadget: The usb gadget state
4335 * @mA: Amount of current
4337 * Report how much power the device may consume to the phy.
4339 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4341 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4343 if (IS_ERR_OR_NULL(hsotg->uphy))
4345 return usb_phy_set_power(hsotg->uphy, mA);
4348 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4349 .get_frame = dwc2_hsotg_gadget_getframe,
4350 .udc_start = dwc2_hsotg_udc_start,
4351 .udc_stop = dwc2_hsotg_udc_stop,
4352 .pullup = dwc2_hsotg_pullup,
4353 .vbus_session = dwc2_hsotg_vbus_session,
4354 .vbus_draw = dwc2_hsotg_vbus_draw,
4358 * dwc2_hsotg_initep - initialise a single endpoint
4359 * @hsotg: The device state.
4360 * @hs_ep: The endpoint to be initialised.
4361 * @epnum: The endpoint number
4363 * Initialise the given endpoint (as part of the probe and device state
4364 * creation) to give to the gadget driver. Setup the endpoint name, any
4365 * direction information and other state that may be required.
4367 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4368 struct dwc2_hsotg_ep *hs_ep,
4381 hs_ep->dir_in = dir_in;
4382 hs_ep->index = epnum;
4384 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4386 INIT_LIST_HEAD(&hs_ep->queue);
4387 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4389 /* add to the list of endpoints known by the gadget driver */
4391 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4393 hs_ep->parent = hsotg;
4394 hs_ep->ep.name = hs_ep->name;
4396 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4397 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4399 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4400 epnum ? 1024 : EP0_MPS_LIMIT);
4401 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4404 hs_ep->ep.caps.type_control = true;
4406 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4407 hs_ep->ep.caps.type_iso = true;
4408 hs_ep->ep.caps.type_bulk = true;
4410 hs_ep->ep.caps.type_int = true;
4414 hs_ep->ep.caps.dir_in = true;
4416 hs_ep->ep.caps.dir_out = true;
4419 * if we're using dma, we need to set the next-endpoint pointer
4420 * to be something valid.
4423 if (using_dma(hsotg)) {
4424 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4427 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4429 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4434 * dwc2_hsotg_hw_cfg - read HW configuration registers
4435 * @param: The device state
4437 * Read the USB core HW configuration registers
4439 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4445 /* check hardware configuration */
4447 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4450 hsotg->num_of_eps++;
4452 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
4454 if (!hsotg->eps_in[0])
4456 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4457 hsotg->eps_out[0] = hsotg->eps_in[0];
4459 cfg = hsotg->hw_params.dev_ep_dirs;
4460 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4462 /* Direction in or both */
4463 if (!(ep_type & 2)) {
4464 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4465 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4466 if (!hsotg->eps_in[i])
4469 /* Direction out or both */
4470 if (!(ep_type & 1)) {
4471 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4472 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4473 if (!hsotg->eps_out[i])
4478 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4479 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4481 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4483 hsotg->dedicated_fifos ? "dedicated" : "shared",
4489 * dwc2_hsotg_dump - dump state of the udc
4490 * @param: The device state
4492 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4495 struct device *dev = hsotg->dev;
4496 void __iomem *regs = hsotg->regs;
4500 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4501 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4502 dwc2_readl(regs + DIEPMSK));
4504 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4505 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4507 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4508 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4510 /* show periodic fifo settings */
4512 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4513 val = dwc2_readl(regs + DPTXFSIZN(idx));
4514 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4515 val >> FIFOSIZE_DEPTH_SHIFT,
4516 val & FIFOSIZE_STARTADDR_MASK);
4519 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4521 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4522 dwc2_readl(regs + DIEPCTL(idx)),
4523 dwc2_readl(regs + DIEPTSIZ(idx)),
4524 dwc2_readl(regs + DIEPDMA(idx)));
4526 val = dwc2_readl(regs + DOEPCTL(idx));
4528 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4529 idx, dwc2_readl(regs + DOEPCTL(idx)),
4530 dwc2_readl(regs + DOEPTSIZ(idx)),
4531 dwc2_readl(regs + DOEPDMA(idx)));
4534 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4535 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4540 * dwc2_gadget_init - init function for gadget
4541 * @dwc2: The data structure for the DWC2 driver.
4542 * @irq: The IRQ number for the controller.
4544 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4546 struct device *dev = hsotg->dev;
4550 /* Dump fifo information */
4551 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4552 hsotg->params.g_np_tx_fifo_size);
4553 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4555 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4556 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4557 hsotg->gadget.name = dev_name(dev);
4558 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4559 hsotg->gadget.is_otg = 1;
4560 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4561 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4563 ret = dwc2_hsotg_hw_cfg(hsotg);
4565 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4569 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4570 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4571 if (!hsotg->ctrl_buff)
4574 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4575 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4576 if (!hsotg->ep0_buff)
4579 if (using_desc_dma(hsotg)) {
4580 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4585 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
4586 dev_name(hsotg->dev), hsotg);
4588 dev_err(dev, "cannot claim IRQ for gadget\n");
4592 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4594 if (hsotg->num_of_eps == 0) {
4595 dev_err(dev, "wrong number of EPs (zero)\n");
4599 /* setup endpoint information */
4601 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4602 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4604 /* allocate EP0 request */
4606 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4608 if (!hsotg->ctrl_req) {
4609 dev_err(dev, "failed to allocate ctrl req\n");
4613 /* initialise the endpoints now the core has been initialised */
4614 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4615 if (hsotg->eps_in[epnum])
4616 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4618 if (hsotg->eps_out[epnum])
4619 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4623 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4627 dwc2_hsotg_dump(hsotg);
4633 * dwc2_hsotg_remove - remove function for hsotg driver
4634 * @pdev: The platform information for the driver
4636 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4638 usb_del_gadget_udc(&hsotg->gadget);
4643 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4645 unsigned long flags;
4647 if (hsotg->lx_state != DWC2_L0)
4650 if (hsotg->driver) {
4653 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4654 hsotg->driver->driver.name);
4656 spin_lock_irqsave(&hsotg->lock, flags);
4658 dwc2_hsotg_core_disconnect(hsotg);
4659 dwc2_hsotg_disconnect(hsotg);
4660 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4661 spin_unlock_irqrestore(&hsotg->lock, flags);
4663 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4664 if (hsotg->eps_in[ep])
4665 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4666 if (hsotg->eps_out[ep])
4667 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4674 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4676 unsigned long flags;
4678 if (hsotg->lx_state == DWC2_L2)
4681 if (hsotg->driver) {
4682 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4683 hsotg->driver->driver.name);
4685 spin_lock_irqsave(&hsotg->lock, flags);
4686 dwc2_hsotg_core_init_disconnected(hsotg, false);
4688 dwc2_hsotg_core_connect(hsotg);
4689 spin_unlock_irqrestore(&hsotg->lock, flags);
4696 * dwc2_backup_device_registers() - Backup controller device registers.
4697 * When suspending usb bus, registers needs to be backuped
4698 * if controller power is disabled once suspended.
4700 * @hsotg: Programming view of the DWC_otg controller
4702 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4704 struct dwc2_dregs_backup *dr;
4707 dev_dbg(hsotg->dev, "%s\n", __func__);
4709 /* Backup dev regs */
4710 dr = &hsotg->dr_backup;
4712 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4713 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4714 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4715 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4716 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4718 for (i = 0; i < hsotg->num_of_eps; i++) {
4720 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4722 /* Ensure DATA PID is correctly configured */
4723 if (dr->diepctl[i] & DXEPCTL_DPID)
4724 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4726 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4728 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4729 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4731 /* Backup OUT EPs */
4732 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4734 /* Ensure DATA PID is correctly configured */
4735 if (dr->doepctl[i] & DXEPCTL_DPID)
4736 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4738 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4740 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4741 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4748 * dwc2_restore_device_registers() - Restore controller device registers.
4749 * When resuming usb bus, device registers needs to be restored
4750 * if controller power were disabled.
4752 * @hsotg: Programming view of the DWC_otg controller
4754 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
4756 struct dwc2_dregs_backup *dr;
4760 dev_dbg(hsotg->dev, "%s\n", __func__);
4762 /* Restore dev regs */
4763 dr = &hsotg->dr_backup;
4765 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4771 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
4772 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4773 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4774 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4775 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4777 for (i = 0; i < hsotg->num_of_eps; i++) {
4778 /* Restore IN EPs */
4779 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4780 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4781 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4783 /* Restore OUT EPs */
4784 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4785 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4786 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4789 /* Set the Power-On Programming done bit */
4790 dctl = dwc2_readl(hsotg->regs + DCTL);
4791 dctl |= DCTL_PWRONPRGDONE;
4792 dwc2_writel(dctl, hsotg->regs + DCTL);