2 * core.h - DesignWare HS OTG Controller common declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
40 #include <linux/phy/phy.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/usb/gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/phy.h>
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
54 #define DWC2_TRACE_SCHEDULER no_printk
55 #define DWC2_TRACE_SCHEDULER_VB no_printk
57 /* Detailed scheduler tracing, but won't overwhelm console */
58 #define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
62 /* Verbose scheduler tracing */
63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
78 static inline u32 dwc2_readl(const void __iomem *addr)
80 u32 value = __raw_readl(addr);
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
90 static inline void dwc2_writel(u32 value, void __iomem *addr)
92 __raw_writel(value, addr);
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
100 #ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
105 /* Normal architectures just use readl/write */
106 static inline u32 dwc2_readl(const void __iomem *addr)
111 static inline void dwc2_writel(u32 value, void __iomem *addr)
115 #ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
121 /* Maximum number of Endpoints/HostChannels */
122 #define MAX_EPS_CHANNELS 16
124 /* dwc2-hsotg declarations */
125 static const char * const dwc2_hsotg_supply_names[] = {
126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
133 * Unfortunately there seems to be a limit of the amount of data that can
134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
135 * packets (which practically means 1 packet and 63 bytes of data) when the
138 * This means if we are wanting to move >127 bytes of data, we need to
139 * split the transactions up, but just doing one packet at a time does
140 * not work (this may be an implicit DATA0 PID on first packet of the
141 * transaction) and doing 2 packets is outside the controller's limits.
143 * If we try to lower the MPS size for EP0, then no transfers work properly
144 * for EP0, and the system will fail basic enumeration. As no cause for this
145 * has currently been found, we cannot support any large IN transfers for
148 #define EP0_MPS_LIMIT 64
151 struct dwc2_hsotg_req;
154 * struct dwc2_hsotg_ep - driver endpoint definition.
155 * @ep: The gadget layer representation of the endpoint.
156 * @name: The driver generated name for the endpoint.
157 * @queue: Queue of requests for this endpoint.
158 * @parent: Reference back to the parent device structure.
159 * @req: The current request that the endpoint is processing. This is
160 * used to indicate an request has been loaded onto the endpoint
161 * and has yet to be completed (maybe due to data move, or simply
162 * awaiting an ack from the core all the data has been completed).
163 * @debugfs: File entry for debugfs file for this endpoint.
164 * @lock: State lock to protect contents of endpoint.
165 * @dir_in: Set to true if this endpoint is of the IN direction, which
166 * means that it is sending data to the Host.
167 * @index: The index for the endpoint registers.
168 * @mc: Multi Count - number of transactions per microframe
169 * @interval - Interval for periodic endpoints, in frames or microframes.
170 * @name: The name array passed to the USB core.
171 * @halted: Set if the endpoint has been halted.
172 * @periodic: Set if this is a periodic ep, such as Interrupt
173 * @isochronous: Set if this is a isochronous ep
174 * @send_zlp: Set if we need to send a zero-length packet.
175 * @total_data: The total number of data bytes done.
176 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
177 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
178 * @last_load: The offset of data for the last start of request.
179 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
180 * @target_frame: Targeted frame num to setup next ISOC transfer
181 * @frame_overrun: Indicates SOF number overrun in DSTS
183 * This is the driver's state for each registered enpoint, allowing it
184 * to keep track of transactions that need doing. Each endpoint has a
185 * lock to protect the state, to try and avoid using an overall lock
186 * for the host controller as much as possible.
188 * For periodic IN endpoints, we have fifo_size and fifo_load to try
189 * and keep track of the amount of data in the periodic FIFO for each
190 * of these as we don't have a status register that tells us how much
191 * is in each of them. (note, this may actually be useless information
192 * as in shared-fifo mode periodic in acts like a single-frame packet
193 * buffer than a fifo)
195 struct dwc2_hsotg_ep {
197 struct list_head queue;
198 struct dwc2_hsotg *parent;
199 struct dwc2_hsotg_req *req;
200 struct dentry *debugfs;
202 unsigned long total_data;
203 unsigned int size_loaded;
204 unsigned int last_load;
205 unsigned int fifo_load;
206 unsigned short fifo_size;
207 unsigned short fifo_index;
209 unsigned char dir_in;
212 unsigned char interval;
214 unsigned int halted:1;
215 unsigned int periodic:1;
216 unsigned int isochronous:1;
217 unsigned int send_zlp:1;
218 unsigned int target_frame;
219 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
226 * struct dwc2_hsotg_req - data transfer request
227 * @req: The USB gadget request
228 * @queue: The list of requests for the endpoint this is queued for.
229 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
231 struct dwc2_hsotg_req {
232 struct usb_request req;
233 struct list_head queue;
237 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
238 #define call_gadget(_hs, _entry) \
240 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
241 (_hs)->driver && (_hs)->driver->_entry) { \
242 spin_unlock(&_hs->lock); \
243 (_hs)->driver->_entry(&(_hs)->gadget); \
244 spin_lock(&_hs->lock); \
248 #define call_gadget(_hs, _entry) do {} while (0)
252 struct dwc2_host_chan;
256 DWC2_L0, /* On state */
257 DWC2_L1, /* LPM sleep state */
258 DWC2_L2, /* USB suspend state */
259 DWC2_L3, /* Off state */
263 * Gadget periodic tx fifo sizes as used by legacy driver
264 * EP0 is not included
266 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
267 768, 0, 0, 0, 0, 0, 0, 0}
269 /* Gadget ep0 states */
270 enum dwc2_ep0_state {
279 * struct dwc2_core_params - Parameters for configuring the core
281 * @otg_cap: Specifies the OTG capabilities.
282 * 0 - HNP and SRP capable
283 * 1 - SRP Only capable
284 * 2 - No HNP/SRP capable (always available)
285 * Defaults to best available option (0, 1, then 2)
286 * @otg_ver: OTG version supported
289 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
290 * the data FIFOs. The driver will automatically detect the
291 * value for this parameter if none is specified.
292 * 0 - Slave (always available)
293 * 1 - DMA (default, if available)
294 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
295 * address DMA mode or descriptor DMA mode for accessing
296 * the data FIFOs. The driver will automatically detect the
297 * value for this if none is specified.
299 * 1 - Descriptor DMA (default, if available)
300 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
301 * address DMA mode or descriptor DMA mode for accessing
302 * the data FIFOs in Full Speed mode only. The driver
303 * will automatically detect the value for this if none is
306 * 1 - Descriptor DMA in FS (default, if available)
307 * @speed: Specifies the maximum speed of operation in host and
308 * device mode. The actual speed depends on the speed of
309 * the attached device and the value of phy_type.
311 * (default when phy_type is UTMI+ or ULPI)
313 * (default when phy_type is Full Speed)
314 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
315 * 1 - Allow dynamic FIFO sizing (default, if available)
316 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
317 * are enabled for non-periodic IN endpoints in device
319 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
320 * dynamic FIFO sizing is enabled
322 * Actual maximum value is autodetected and also
324 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
325 * in host mode when dynamic FIFO sizing is enabled
327 * Actual maximum value is autodetected and also
329 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
330 * host mode when dynamic FIFO sizing is enabled
332 * Actual maximum value is autodetected and also
334 * @max_transfer_size: The maximum transfer size supported, in bytes
336 * Actual maximum value is autodetected and also
338 * @max_packet_count: The maximum number of packets in a transfer
340 * Actual maximum value is autodetected and also
342 * @host_channels: The number of host channel registers to use
344 * Actual maximum value is autodetected and also
346 * @phy_type: Specifies the type of PHY interface to use. By default,
347 * the driver will automatically detect the phy_type.
351 * Defaults to best available option (2, 1, then 0)
352 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
353 * is applicable for a phy_type of UTMI+ or ULPI. (For a
354 * ULPI phy_type, this parameter indicates the data width
355 * between the MAC and the ULPI Wrapper.) Also, this
356 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
357 * parameter was set to "8 and 16 bits", meaning that the
358 * core has been configured to work at either data path
360 * 8 or 16 (default 16 if available)
361 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
362 * data rate. This parameter is only applicable if phy_type
364 * 0 - single data rate ULPI interface with 8 bit wide
366 * 1 - double data rate ULPI interface with 4 bit wide
368 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
369 * external supply to drive the VBus
370 * 0 - Internal supply (default)
371 * 1 - External supply
372 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
373 * speed PHY. This parameter is only applicable if phy_type
377 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
380 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
381 * when attached to a Full Speed or Low Speed device in
383 * 0 - Don't support low power mode (default)
384 * 1 - Support low power mode
385 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
386 * when connected to a Low Speed device in host
387 * mode. This parameter is applicable only if
388 * host_support_fs_ls_low_power is enabled.
390 * (default when phy_type is UTMI+ or ULPI)
392 * (default when phy_type is Full Speed)
393 * @ts_dline: Enable Term Select Dline pulsing
396 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
397 * 0 - No (default for core < 2.92a)
398 * 1 - Yes (default for core >= 2.92a)
399 * @ahbcfg: This field allows the default value of the GAHBCFG
400 * register to be overridden
401 * -1 - GAHBCFG value will be set to 0x06
403 * all others - GAHBCFG value will be overridden with
405 * Not all bits can be controlled like this, the
406 * bits defined by GAHBCFG_CTRL_MASK are controlled
407 * by the driver and are ignored in this
408 * configuration value.
409 * @uframe_sched: True to enable the microframe scheduler
410 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
411 * Disable CONIDSTSCHNG controller interrupt in such
415 * @hibernation: Specifies whether the controller support hibernation.
416 * If hibernation is enabled, the controller will enter
417 * hibernation in both peripheral and host mode when
422 * The following parameters may be specified when starting the module. These
423 * parameters define how the DWC_otg controller should be configured. A
424 * value of -1 (or any other out of range value) for any parameter means
425 * to read the value from hardware (if possible) or use the builtin
426 * default described above.
428 struct dwc2_core_params {
430 * Don't add any non-int members here, this will break
431 * dwc2_set_all_params!
434 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
435 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
436 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
441 int dma_desc_fs_enable;
443 #define DWC2_SPEED_PARAM_HIGH 0
444 #define DWC2_SPEED_PARAM_FULL 1
446 int enable_dynamic_fifo;
447 int en_multiple_tx_fifo;
448 int host_rx_fifo_size;
449 int host_nperio_tx_fifo_size;
450 int host_perio_tx_fifo_size;
451 int max_transfer_size;
452 int max_packet_count;
455 #define DWC2_PHY_TYPE_PARAM_FS 0
456 #define DWC2_PHY_TYPE_PARAM_UTMI 1
457 #define DWC2_PHY_TYPE_PARAM_ULPI 2
461 int phy_ulpi_ext_vbus;
462 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0
463 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
467 int host_support_fs_ls_low_power;
468 int host_ls_low_power_phy_clk;
469 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
470 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
476 int external_id_pin_ctl;
481 * struct dwc2_hw_params - Autodetected parameters.
483 * These parameters are the various parameters read from hardware
484 * registers during initialization. They typically contain the best
485 * supported or maximum value that can be configured in the
486 * corresponding dwc2_core_params value.
488 * The values that are not in dwc2_core_params are documented below.
490 * @op_mode Mode of Operation
491 * 0 - HNP- and SRP-Capable OTG (Host & Device)
492 * 1 - SRP-Capable OTG (Host & Device)
493 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
494 * 3 - SRP-Capable Device
496 * 5 - SRP-Capable Host
502 * @power_optimized Are power optimizations enabled?
503 * @num_dev_ep Number of device endpoints available
504 * @num_dev_perio_in_ep Number of device periodic IN endpoints
506 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
509 * @host_perio_tx_q_depth
510 * Host Mode Periodic Request Queue Depth
513 * Non-Periodic Request Queue Depth
515 * @hs_phy_type High-speed PHY interface type
516 * 0 - High-speed interface not supported
520 * @fs_phy_type Full-speed PHY interface type
521 * 0 - Full speed interface not supported
522 * 1 - Dedicated full speed interface
523 * 2 - FS pins shared with UTMI+ pins
524 * 3 - FS pins shared with ULPI pins
525 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
526 * @utmi_phy_data_width UTMI+ PHY data width
530 * @snpsid: Value from SNPSID register
531 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
533 struct dwc2_hw_params {
536 unsigned dma_desc_enable:1;
537 unsigned enable_dynamic_fifo:1;
538 unsigned en_multiple_tx_fifo:1;
539 unsigned host_rx_fifo_size:16;
540 unsigned host_nperio_tx_fifo_size:16;
541 unsigned dev_nperio_tx_fifo_size:16;
542 unsigned host_perio_tx_fifo_size:16;
543 unsigned nperio_tx_q_depth:3;
544 unsigned host_perio_tx_q_depth:3;
545 unsigned dev_token_q_depth:5;
546 unsigned max_transfer_size:26;
547 unsigned max_packet_count:11;
548 unsigned host_channels:5;
549 unsigned hs_phy_type:2;
550 unsigned fs_phy_type:2;
551 unsigned i2c_enable:1;
552 unsigned num_dev_ep:4;
553 unsigned num_dev_perio_in_ep:4;
554 unsigned total_fifo_size:16;
555 unsigned power_optimized:1;
556 unsigned utmi_phy_data_width:2;
561 /* Size of control and EP0 buffers */
562 #define DWC2_CTRL_BUFF_SIZE 8
565 * struct dwc2_gregs_backup - Holds global registers state before entering partial
567 * @gotgctl: Backup of GOTGCTL register
568 * @gintmsk: Backup of GINTMSK register
569 * @gahbcfg: Backup of GAHBCFG register
570 * @gusbcfg: Backup of GUSBCFG register
571 * @grxfsiz: Backup of GRXFSIZ register
572 * @gnptxfsiz: Backup of GNPTXFSIZ register
573 * @gi2cctl: Backup of GI2CCTL register
574 * @hptxfsiz: Backup of HPTXFSIZ register
575 * @gdfifocfg: Backup of GDFIFOCFG register
576 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
577 * @gpwrdn: Backup of GPWRDN register
579 struct dwc2_gregs_backup {
590 u32 dtxfsiz[MAX_EPS_CHANNELS];
596 * struct dwc2_dregs_backup - Holds device registers state before entering partial
598 * @dcfg: Backup of DCFG register
599 * @dctl: Backup of DCTL register
600 * @daintmsk: Backup of DAINTMSK register
601 * @diepmsk: Backup of DIEPMSK register
602 * @doepmsk: Backup of DOEPMSK register
603 * @diepctl: Backup of DIEPCTL register
604 * @dieptsiz: Backup of DIEPTSIZ register
605 * @diepdma: Backup of DIEPDMA register
606 * @doepctl: Backup of DOEPCTL register
607 * @doeptsiz: Backup of DOEPTSIZ register
608 * @doepdma: Backup of DOEPDMA register
610 struct dwc2_dregs_backup {
616 u32 diepctl[MAX_EPS_CHANNELS];
617 u32 dieptsiz[MAX_EPS_CHANNELS];
618 u32 diepdma[MAX_EPS_CHANNELS];
619 u32 doepctl[MAX_EPS_CHANNELS];
620 u32 doeptsiz[MAX_EPS_CHANNELS];
621 u32 doepdma[MAX_EPS_CHANNELS];
626 * struct dwc2_hregs_backup - Holds host registers state before entering partial
628 * @hcfg: Backup of HCFG register
629 * @haintmsk: Backup of HAINTMSK register
630 * @hcintmsk: Backup of HCINTMSK register
631 * @hptr0: Backup of HPTR0 register
632 * @hfir: Backup of HFIR register
634 struct dwc2_hregs_backup {
637 u32 hcintmsk[MAX_EPS_CHANNELS];
644 * Constants related to high speed periodic scheduling
646 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
647 * reservation point of view it's assumed that the schedule goes right back to
648 * the beginning after the end of the schedule.
650 * What does that mean for scheduling things with a long interval? It means
651 * we'll reserve time for them in every possible microframe that they could
652 * ever be scheduled in. ...but we'll still only actually schedule them as
653 * often as they were requested.
655 * We keep our schedule in a "bitmap" structure. This simplifies having
656 * to keep track of and merge intervals: we just let the bitmap code do most
657 * of the heavy lifting. In a way scheduling is much like memory allocation.
659 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
660 * supposed to schedule for periodic transfers). That's according to spec.
662 * Note that though we only schedule 80% of each microframe, the bitmap that we
663 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
664 * space for each uFrame).
667 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
668 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
669 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
670 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
672 #define DWC2_US_PER_UFRAME 125
673 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
675 #define DWC2_HS_SCHEDULE_UFRAMES 8
676 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
677 DWC2_HS_PERIODIC_US_PER_UFRAME)
680 * Constants related to low speed scheduling
682 * For high speed we schedule every 1us. For low speed that's a bit overkill,
683 * so we make up a unit called a "slice" that's worth 25us. There are 40
684 * slices in a full frame and we can schedule 36 of those (90%) for periodic
687 * Our low speed schedule can be as short as 1 frame or could be longer. When
688 * we only schedule 1 frame it means that we'll need to reserve a time every
689 * frame even for things that only transfer very rarely, so something that runs
690 * every 2048 frames will get time reserved in every frame. Our low speed
691 * schedule can be longer and we'll be able to handle more overlap, but that
692 * will come at increased memory cost and increased time to schedule.
694 * Note: one other advantage of a short low speed schedule is that if we mess
695 * up and miss scheduling we can jump in and use any of the slots that we
696 * happened to reserve.
698 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
699 * the schedule. There will be one schedule per TT.
702 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
704 #define DWC2_US_PER_SLICE 25
705 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
707 #define DWC2_ROUND_US_TO_SLICE(us) \
708 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
711 #define DWC2_LS_PERIODIC_US_PER_FRAME \
713 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
714 (DWC2_LS_PERIODIC_US_PER_FRAME / \
717 #define DWC2_LS_SCHEDULE_FRAMES 1
718 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
719 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
722 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
723 * and periodic schedules
725 * These are common for both host and peripheral modes:
727 * @dev: The struct device pointer
728 * @regs: Pointer to controller regs
729 * @hw_params: Parameters that were autodetected from the
731 * @core_params: Parameters that define how the core should be configured
732 * @op_state: The operational State, during transitions (a_host=>
733 * a_peripheral and b_device=>b_host) this may not match
734 * the core, but allows the software to determine
736 * @dr_mode: Requested mode of operation, one of following:
737 * - USB_DR_MODE_PERIPHERAL
740 * @hcd_enabled Host mode sub-driver initialization indicator.
741 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
742 * @ll_hw_enabled Status of low-level hardware resources.
743 * @phy: The otg phy transceiver structure for phy control.
744 * @uphy: The otg phy transceiver structure for old USB phy control.
745 * @plat: The platform specific configuration data. This can be removed once
746 * all SoCs support usb transceiver.
747 * @supplies: Definition of USB power supplies
748 * @phyif: PHY interface width
749 * @lock: Spinlock that protects all the driver data structures
750 * @priv: Stores a pointer to the struct usb_hcd
751 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
752 * transfer are in process of being queued
753 * @srp_success: Stores status of SRP request in the case of a FS PHY
754 * with an I2C interface
755 * @wq_otg: Workqueue object used for handling of some interrupts
756 * @wf_otg: Work object for handling Connector ID Status Change
758 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
759 * @lx_state: Lx state of connected device
760 * @gregs_backup: Backup of global registers during suspend
761 * @dregs_backup: Backup of device registers during suspend
762 * @hregs_backup: Backup of host registers during suspend
764 * These are for host mode:
766 * @flags: Flags for handling root port state changes
767 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
768 * Transfers associated with these QHs are not currently
769 * assigned to a host channel.
770 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
771 * Transfers associated with these QHs are currently
772 * assigned to a host channel.
773 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
774 * non-periodic schedule
775 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
776 * list of QHs for periodic transfers that are _not_
777 * scheduled for the next frame. Each QH in the list has an
778 * interval counter that determines when it needs to be
779 * scheduled for execution. This scheduling mechanism
780 * allows only a simple calculation for periodic bandwidth
781 * used (i.e. must assume that all periodic transfers may
782 * need to execute in the same frame). However, it greatly
783 * simplifies scheduling and should be sufficient for the
784 * vast majority of OTG hosts, which need to connect to a
785 * small number of peripherals at one time. Items move from
786 * this list to periodic_sched_ready when the QH interval
787 * counter is 0 at SOF.
788 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
789 * the next frame, but have not yet been assigned to host
790 * channels. Items move from this list to
791 * periodic_sched_assigned as host channels become
792 * available during the current frame.
793 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
794 * frame that are assigned to host channels. Items move
795 * from this list to periodic_sched_queued as the
796 * transactions for the QH are queued to the DWC_otg
798 * @periodic_sched_queued: List of periodic QHs that have been queued for
799 * execution. Items move from this list to either
800 * periodic_sched_inactive or periodic_sched_ready when the
801 * channel associated with the transfer is released. If the
802 * interval for the QH is 1, the item moves to
803 * periodic_sched_ready because it must be rescheduled for
804 * the next frame. Otherwise, the item moves to
805 * periodic_sched_inactive.
806 * @split_order: List keeping track of channels doing splits, in order.
807 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
808 * This value is in microseconds per (micro)frame. The
809 * assumption is that all periodic transfers may occur in
810 * the same (micro)frame.
811 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
812 * host is in high speed mode; low speed schedules are
813 * stored elsewhere since we need one per TT.
814 * @frame_number: Frame number read from the core at SOF. The value ranges
815 * from 0 to HFNUM_MAX_FRNUM.
816 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
817 * SOF enable/disable.
818 * @free_hc_list: Free host channels in the controller. This is a list of
819 * struct dwc2_host_chan items.
820 * @periodic_channels: Number of host channels assigned to periodic transfers.
821 * Currently assuming that there is a dedicated host
822 * channel for each periodic transaction and at least one
823 * host channel is available for non-periodic transactions.
824 * @non_periodic_channels: Number of host channels assigned to non-periodic
826 * @available_host_channels Number of host channels available for the microframe
828 * @hc_ptr_array: Array of pointers to the host channel descriptors.
829 * Allows accessing a host channel descriptor given the
830 * host channel number. This is useful in interrupt
832 * @status_buf: Buffer used for data received during the status phase of
833 * a control transfer.
834 * @status_buf_dma: DMA address for status_buf
835 * @start_work: Delayed work for handling host A-cable connection
836 * @reset_work: Delayed work for handling a port reset
837 * @otg_port: OTG port number
838 * @frame_list: Frame list
839 * @frame_list_dma: Frame list DMA address
840 * @frame_list_sz: Frame list size
841 * @desc_gen_cache: Kmem cache for generic descriptors
842 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
844 * These are for peripheral mode:
846 * @driver: USB gadget driver
847 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
848 * @num_of_eps: Number of available EPs (excluding EP0)
849 * @debug_root: Root directrory for debugfs.
850 * @debug_file: Main status file for debugfs.
851 * @debug_testmode: Testmode status file for debugfs.
852 * @debug_fifo: FIFO status file for debugfs.
853 * @ep0_reply: Request used for ep0 reply.
854 * @ep0_buff: Buffer for EP0 reply data, if needed.
855 * @ctrl_buff: Buffer for EP0 control requests.
856 * @ctrl_req: Request for EP0 control packets.
857 * @ep0_state: EP0 control transfers state
858 * @test_mode: USB test mode requested by the host
859 * @eps: The endpoints being supplied to the gadget framework
860 * @g_using_dma: Indicate if dma usage is enabled
861 * @g_rx_fifo_sz: Contains rx fifo size value
862 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
863 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
868 /** Params detected from hardware */
869 struct dwc2_hw_params hw_params;
870 /** Params to actually use */
871 struct dwc2_core_params params;
872 enum usb_otg_state op_state;
873 enum usb_dr_mode dr_mode;
874 unsigned int hcd_enabled:1;
875 unsigned int gadget_enabled:1;
876 unsigned int ll_hw_enabled:1;
879 struct usb_phy *uphy;
880 struct dwc2_hsotg_plat *plat;
881 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
888 struct reset_control *reset;
890 unsigned int queuing_high_bandwidth:1;
891 unsigned int srp_success:1;
893 struct workqueue_struct *wq_otg;
894 struct work_struct wf_otg;
895 struct timer_list wkp_timer;
896 enum dwc2_lx_state lx_state;
897 struct dwc2_gregs_backup gr_backup;
898 struct dwc2_dregs_backup dr_backup;
899 struct dwc2_hregs_backup hr_backup;
901 struct dentry *debug_root;
902 struct debugfs_regset32 *regset;
904 /* DWC OTG HW Release versions */
905 #define DWC2_CORE_REV_2_71a 0x4f54271a
906 #define DWC2_CORE_REV_2_90a 0x4f54290a
907 #define DWC2_CORE_REV_2_92a 0x4f54292a
908 #define DWC2_CORE_REV_2_94a 0x4f54294a
909 #define DWC2_CORE_REV_3_00a 0x4f54300a
910 #define DWC2_CORE_REV_3_10a 0x4f54310a
912 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
913 union dwc2_hcd_internal_flags {
916 unsigned port_connect_status_change:1;
917 unsigned port_connect_status:1;
918 unsigned port_reset_change:1;
919 unsigned port_enable_change:1;
920 unsigned port_suspend_change:1;
921 unsigned port_over_current_change:1;
922 unsigned port_l1_change:1;
923 unsigned reserved:25;
927 struct list_head non_periodic_sched_inactive;
928 struct list_head non_periodic_sched_active;
929 struct list_head *non_periodic_qh_ptr;
930 struct list_head periodic_sched_inactive;
931 struct list_head periodic_sched_ready;
932 struct list_head periodic_sched_assigned;
933 struct list_head periodic_sched_queued;
934 struct list_head split_order;
936 unsigned long hs_periodic_bitmap[
937 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
939 u16 periodic_qh_count;
945 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
946 #define FRAME_NUM_ARRAY_SIZE 1000
947 u16 *frame_num_array;
948 u16 *last_frame_num_array;
950 int dumped_frame_num_array;
953 struct list_head free_hc_list;
954 int periodic_channels;
955 int non_periodic_channels;
956 int available_host_channels;
957 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
959 dma_addr_t status_buf_dma;
960 #define DWC2_HCD_STATUS_BUF_SIZE 64
962 struct delayed_work start_work;
963 struct delayed_work reset_work;
966 dma_addr_t frame_list_dma;
968 struct kmem_cache *desc_gen_cache;
969 struct kmem_cache *desc_hsisoc_cache;
975 u32 hfnum_7_samples_a;
976 u64 hfnum_7_frrem_accum_a;
977 u32 hfnum_0_samples_a;
978 u64 hfnum_0_frrem_accum_a;
979 u32 hfnum_other_samples_a;
980 u64 hfnum_other_frrem_accum_a;
982 u32 hfnum_7_samples_b;
983 u64 hfnum_7_frrem_accum_b;
984 u32 hfnum_0_samples_b;
985 u64 hfnum_0_frrem_accum_b;
986 u32 hfnum_other_samples_b;
987 u64 hfnum_other_frrem_accum_b;
989 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
991 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
992 /* Gadget structures */
993 struct usb_gadget_driver *driver;
995 unsigned int dedicated_fifos:1;
996 unsigned char num_of_eps;
999 struct usb_request *ep0_reply;
1000 struct usb_request *ctrl_req;
1003 enum dwc2_ep0_state ep0_state;
1006 struct usb_gadget gadget;
1007 unsigned int enabled:1;
1008 unsigned int connected:1;
1009 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1010 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1013 u32 g_np_g_tx_fifo_sz;
1014 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
1015 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1018 /* Reasons for halting a host channel */
1019 enum dwc2_halt_status {
1020 DWC2_HC_XFER_NO_HALT_STATUS,
1021 DWC2_HC_XFER_COMPLETE,
1022 DWC2_HC_XFER_URB_COMPLETE,
1027 DWC2_HC_XFER_XACT_ERR,
1028 DWC2_HC_XFER_FRAME_OVERRUN,
1029 DWC2_HC_XFER_BABBLE_ERR,
1030 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1031 DWC2_HC_XFER_AHB_ERR,
1032 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1033 DWC2_HC_XFER_URB_DEQUEUE,
1037 * The following functions support initialization of the core driver component
1038 * and the DWC_otg controller
1040 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
1041 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1042 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1043 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
1045 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1046 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
1047 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1049 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1052 * Common core Functions.
1053 * The following functions support managing the DWC_otg controller in either
1054 * device or host mode.
1056 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1057 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1058 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1060 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1061 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1063 /* This function should be called on every hardware interrupt. */
1064 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1066 /* The device ID match table */
1067 extern const struct of_device_id dwc2_of_match_table[];
1069 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1070 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1073 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1074 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1077 * The following functions check the controller's OTG operation mode
1078 * capability (GHWCFG2.OTG_MODE).
1080 * These functions can be used before the internal hsotg->hw_params
1081 * are read in and cached so they always read directly from the
1084 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1085 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1086 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1087 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1090 * Returns the mode of operation, host or device
1092 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1094 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1096 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1098 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1102 * Dump core registers and SPRAM
1104 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1105 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1106 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1109 * Return OTG version - either 1.3 or 2.0
1111 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1113 /* Gadget defines */
1114 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1115 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1116 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1117 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1118 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1119 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1121 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1122 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1123 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1124 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1125 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1126 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
1128 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1130 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1132 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1134 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1136 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1138 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1139 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1140 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1143 #define dwc2_is_device_connected(hsotg) (0)
1144 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1146 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1150 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1151 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1152 extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1153 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1154 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1155 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1156 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1157 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1159 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1161 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1164 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1165 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1166 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1167 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1168 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
1170 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1172 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1177 #endif /* __DWC2_CORE_H__ */