drivers/ufs/host/ufshcd-pltfrm.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller Platform bus based glue driver
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  *
   6  * Authors:
   7  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   8  *      Vinayak Holikatti <h.vinayak@samsung.com>
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/of.h>
  15
  16 #include <ufs/ufshcd.h>
  17 #include "ufshcd-pltfrm.h"
  18 #include <ufs/unipro.h>
  19
  20 #define UFSHCD_DEFAULT_LANES_PER_DIRECTION              2
  21
  22 static int ufshcd_parse_clock_info(struct ufs_hba *hba)
  23 {
  24         int ret = 0;
  25         int cnt;
  26         int i;
  27         struct device *dev = hba->dev;
  28         struct device_node *np = dev->of_node;
  29         const char *name;
  30         u32 *clkfreq = NULL;
  31         struct ufs_clk_info *clki;
  32         int len = 0;
  33         size_t sz = 0;
  34
  35         if (!np)
  36                 goto out;
  37
  38         cnt = of_property_count_strings(np, "clock-names");
  39         if (!cnt || (cnt == -EINVAL)) {
  40                 dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
  41                                 __func__);
  42         } else if (cnt < 0) {
  43                 dev_err(dev, "%s: count clock strings failed, err %d\n",
  44                                 __func__, cnt);
  45                 ret = cnt;
  46         }
  47
  48         if (cnt <= 0)
  49                 goto out;
  50
  51         if (!of_get_property(np, "freq-table-hz", &len)) {
  52                 dev_info(dev, "freq-table-hz property not specified\n");
  53                 goto out;
  54         }
  55
  56         if (len <= 0)
  57                 goto out;
  58
  59         sz = len / sizeof(*clkfreq);
  60         if (sz != 2 * cnt) {
  61                 dev_err(dev, "%s len mismatch\n", "freq-table-hz");
  62                 ret = -EINVAL;
  63                 goto out;
  64         }
  65
  66         clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
  67                                GFP_KERNEL);
  68         if (!clkfreq) {
  69                 ret = -ENOMEM;
  70                 goto out;
  71         }
  72
  73         ret = of_property_read_u32_array(np, "freq-table-hz",
  74                         clkfreq, sz);
  75         if (ret && (ret != -EINVAL)) {
  76                 dev_err(dev, "%s: error reading array %d\n",
  77                                 "freq-table-hz", ret);
  78                 return ret;
  79         }
  80
  81         for (i = 0; i < sz; i += 2) {
  82                 ret = of_property_read_string_index(np, "clock-names", i/2,
  83                                                     &name);
  84                 if (ret)
  85                         goto out;
  86
  87                 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
  88                 if (!clki) {
  89                         ret = -ENOMEM;
  90                         goto out;
  91                 }
  92
  93                 clki->min_freq = clkfreq[i];
  94                 clki->max_freq = clkfreq[i+1];
  95                 clki->name = devm_kstrdup(dev, name, GFP_KERNEL);
  96                 if (!clki->name) {
  97                         ret = -ENOMEM;
  98                         goto out;
  99                 }
 100
 101                 if (!strcmp(name, "ref_clk"))
 102                         clki->keep_link_active = true;
 103                 dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
 104                                 clki->min_freq, clki->max_freq, clki->name);
 105                 list_add_tail(&clki->list, &hba->clk_list_head);
 106         }
 107 out:
 108         return ret;
 109 }
 110
 111 static bool phandle_exists(const struct device_node *np,
 112                            const char *phandle_name, int index)
 113 {
 114         struct device_node *parse_np = of_parse_phandle(np, phandle_name, index);
 115
 116         if (parse_np)
 117                 of_node_put(parse_np);
 118
 119         return parse_np != NULL;
 120 }
 121
 122 #define MAX_PROP_SIZE 32
 123 int ufshcd_populate_vreg(struct device *dev, const char *name,
 124                          struct ufs_vreg **out_vreg, bool skip_current)
 125 {
 126         char prop_name[MAX_PROP_SIZE];
 127         struct ufs_vreg *vreg = NULL;
 128         struct device_node *np = dev->of_node;
 129
 130         if (!np) {
 131                 dev_err(dev, "%s: non DT initialization\n", __func__);
 132                 goto out;
 133         }
 134
 135         snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
 136         if (!phandle_exists(np, prop_name, 0)) {
 137                 dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
 138                                 __func__, prop_name);
 139                 goto out;
 140         }
 141
 142         vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
 143         if (!vreg)
 144                 return -ENOMEM;
 145
 146         vreg->name = devm_kstrdup(dev, name, GFP_KERNEL);
 147         if (!vreg->name)
 148                 return -ENOMEM;
 149
 150         if (skip_current) {
 151                 vreg->max_uA = 0;
 152                 goto out;
 153         }
 154
 155         snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
 156         if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
 157                 dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
 158                 vreg->max_uA = 0;
 159         }
 160 out:
 161         *out_vreg = vreg;
 162         return 0;
 163 }
 164 EXPORT_SYMBOL_GPL(ufshcd_populate_vreg);
 165
 166 /**
 167  * ufshcd_parse_regulator_info - get regulator info from device tree
 168  * @hba: per adapter instance
 169  *
 170  * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
 171  * If any of the supplies are not defined it is assumed that they are always-on
 172  * and hence return zero. If the property is defined but parsing is failed
 173  * then return corresponding error.
 174  *
 175  * Return: 0 upon success; < 0 upon failure.
 176  */
 177 static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
 178 {
 179         int err;
 180         struct device *dev = hba->dev;
 181         struct ufs_vreg_info *info = &hba->vreg_info;
 182
 183         err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba, true);
 184         if (err)
 185                 goto out;
 186
 187         err = ufshcd_populate_vreg(dev, "vcc", &info->vcc, false);
 188         if (err)
 189                 goto out;
 190
 191         err = ufshcd_populate_vreg(dev, "vccq", &info->vccq, false);
 192         if (err)
 193                 goto out;
 194
 195         err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2, false);
 196 out:
 197         return err;
 198 }
 199
 200 static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
 201 {
 202         struct device *dev = hba->dev;
 203         int ret;
 204
 205         ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
 206                 &hba->lanes_per_direction);
 207         if (ret) {
 208                 dev_dbg(hba->dev,
 209                         "%s: failed to read lanes-per-direction, ret=%d\n",
 210                         __func__, ret);
 211                 hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
 212         }
 213 }
 214
 215 /**
 216  * ufshcd_get_pwr_dev_param - get finally agreed attributes for
 217  *                            power mode change
 218  * @pltfrm_param: pointer to platform parameters
 219  * @dev_max: pointer to device attributes
 220  * @agreed_pwr: returned agreed attributes
 221  *
 222  * Return: 0 on success, non-zero value on failure.
 223  */
 224 int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
 225                              const struct ufs_pa_layer_attr *dev_max,
 226                              struct ufs_pa_layer_attr *agreed_pwr)
 227 {
 228         int min_pltfrm_gear;
 229         int min_dev_gear;
 230         bool is_dev_sup_hs = false;
 231         bool is_pltfrm_max_hs = false;
 232
 233         if (dev_max->pwr_rx == FAST_MODE)
 234                 is_dev_sup_hs = true;
 235
 236         if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
 237                 is_pltfrm_max_hs = true;
 238                 min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
 239                                         pltfrm_param->hs_tx_gear);
 240         } else {
 241                 min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
 242                                         pltfrm_param->pwm_tx_gear);
 243         }
 244
 245         /*
 246          * device doesn't support HS but
 247          * pltfrm_param->desired_working_mode is HS,
 248          * thus device and pltfrm_param don't agree
 249          */
 250         if (!is_dev_sup_hs && is_pltfrm_max_hs) {
 251                 pr_info("%s: device doesn't support HS\n",
 252                         __func__);
 253                 return -ENOTSUPP;
 254         } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
 255                 /*
 256                  * since device supports HS, it supports FAST_MODE.
 257                  * since pltfrm_param->desired_working_mode is also HS
 258                  * then final decision (FAST/FASTAUTO) is done according
 259                  * to pltfrm_params as it is the restricting factor
 260                  */
 261                 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
 262                 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
 263         } else {
 264                 /*
 265                  * here pltfrm_param->desired_working_mode is PWM.
 266                  * it doesn't matter whether device supports HS or PWM,
 267                  * in both cases pltfrm_param->desired_working_mode will
 268                  * determine the mode
 269                  */
 270                 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
 271                 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
 272         }
 273
 274         /*
 275          * we would like tx to work in the minimum number of lanes
 276          * between device capability and vendor preferences.
 277          * the same decision will be made for rx
 278          */
 279         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 280                                     pltfrm_param->tx_lanes);
 281         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 282                                     pltfrm_param->rx_lanes);
 283
 284         /* device maximum gear is the minimum between device rx and tx gears */
 285         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 286
 287         /*
 288          * if both device capabilities and vendor pre-defined preferences are
 289          * both HS or both PWM then set the minimum gear to be the chosen
 290          * working gear.
 291          * if one is PWM and one is HS then the one that is PWM get to decide
 292          * what is the gear, as it is the one that also decided previously what
 293          * pwr the device will be configured to.
 294          */
 295         if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
 296             (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
 297                 agreed_pwr->gear_rx =
 298                         min_t(u32, min_dev_gear, min_pltfrm_gear);
 299         } else if (!is_dev_sup_hs) {
 300                 agreed_pwr->gear_rx = min_dev_gear;
 301         } else {
 302                 agreed_pwr->gear_rx = min_pltfrm_gear;
 303         }
 304         agreed_pwr->gear_tx = agreed_pwr->gear_rx;
 305
 306         agreed_pwr->hs_rate = pltfrm_param->hs_rate;
 307
 308         return 0;
 309 }
 310 EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
 311
 312 void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
 313 {
 314         *dev_param = (struct ufs_dev_params){
 315                 .tx_lanes = UFS_LANE_2,
 316                 .rx_lanes = UFS_LANE_2,
 317                 .hs_rx_gear = UFS_HS_G3,
 318                 .hs_tx_gear = UFS_HS_G3,
 319                 .pwm_rx_gear = UFS_PWM_G4,
 320                 .pwm_tx_gear = UFS_PWM_G4,
 321                 .rx_pwr_pwm = SLOW_MODE,
 322                 .tx_pwr_pwm = SLOW_MODE,
 323                 .rx_pwr_hs = FAST_MODE,
 324                 .tx_pwr_hs = FAST_MODE,
 325                 .hs_rate = PA_HS_MODE_B,
 326                 .desired_working_mode = UFS_HS_MODE,
 327         };
 328 }
 329 EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
 330
 331 /**
 332  * ufshcd_pltfrm_init - probe routine of the driver
 333  * @pdev: pointer to Platform device handle
 334  * @vops: pointer to variant ops
 335  *
 336  * Return: 0 on success, non-zero value on failure.
 337  */
 338 int ufshcd_pltfrm_init(struct platform_device *pdev,
 339                        const struct ufs_hba_variant_ops *vops)
 340 {
 341         struct ufs_hba *hba;
 342         void __iomem *mmio_base;
 343         int irq, err;
 344         struct device *dev = &pdev->dev;
 345
 346         mmio_base = devm_platform_ioremap_resource(pdev, 0);
 347         if (IS_ERR(mmio_base)) {
 348                 err = PTR_ERR(mmio_base);
 349                 goto out;
 350         }
 351
 352         irq = platform_get_irq(pdev, 0);
 353         if (irq < 0) {
 354                 err = irq;
 355                 goto out;
 356         }
 357
 358         err = ufshcd_alloc_host(dev, &hba);
 359         if (err) {
 360                 dev_err(dev, "Allocation failed\n");
 361                 goto out;
 362         }
 363
 364         hba->vops = vops;
 365
 366         err = ufshcd_parse_clock_info(hba);
 367         if (err) {
 368                 dev_err(dev, "%s: clock parse failed %d\n",
 369                                 __func__, err);
 370                 goto dealloc_host;
 371         }
 372         err = ufshcd_parse_regulator_info(hba);
 373         if (err) {
 374                 dev_err(dev, "%s: regulator init failed %d\n",
 375                                 __func__, err);
 376                 goto dealloc_host;
 377         }
 378
 379         ufshcd_init_lanes_per_dir(hba);
 380
 381         err = ufshcd_init(hba, mmio_base, irq);
 382         if (err) {
 383                 dev_err_probe(dev, err, "Initialization failed with error %d\n",
 384                               err);
 385                 goto dealloc_host;
 386         }
 387
 388         pm_runtime_set_active(dev);
 389         pm_runtime_enable(dev);
 390
 391         return 0;
 392
 393 dealloc_host:
 394         ufshcd_dealloc_host(hba);
 395 out:
 396         return err;
 397 }
 398 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
 399
 400 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
 401 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
 402 MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
 403 MODULE_LICENSE("GPL");