1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
6 #include <linux/acpi.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
19 #include <soc/qcom/ice.h>
21 #include <ufs/ufshcd.h>
22 #include <ufs/ufshci.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/unipro.h>
25 #include "ufshcd-pltfrm.h"
28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
29 #define MCQ_QCFGPTR_UNIT 0x200
30 #define MCQ_SQATTR_OFFSET(c) \
31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
32 #define MCQ_QCFG_SIZE 0x40
50 #define QCOM_UFS_MAX_GEAR 4
51 #define QCOM_UFS_MAX_LANE 2
61 static const struct __ufs_qcom_bw_table {
64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
70 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
71 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
72 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
73 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
74 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
75 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
76 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
77 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
78 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
79 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
80 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
81 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
82 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
83 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
84 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
85 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
90 [MODE_MAX][0][0] = { 7643136, 307200 },
93 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
94 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
96 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
98 return container_of(rcd, struct ufs_qcom_host, rcdev);
101 #ifdef CONFIG_SCSI_UFS_CRYPTO
103 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
105 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
106 qcom_ice_enable(host->ice);
109 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
111 struct ufs_hba *hba = host->hba;
112 struct device *dev = hba->dev;
113 struct qcom_ice *ice;
115 ice = of_qcom_ice_get(dev);
116 if (ice == ERR_PTR(-EOPNOTSUPP)) {
117 dev_warn(dev, "Disabling inline encryption support\n");
121 if (IS_ERR_OR_NULL(ice))
122 return PTR_ERR_OR_ZERO(ice);
125 hba->caps |= UFSHCD_CAP_CRYPTO;
130 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
132 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
133 return qcom_ice_resume(host->ice);
138 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
140 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
141 return qcom_ice_suspend(host->ice);
146 static int ufs_qcom_ice_program_key(struct ufs_hba *hba,
147 const union ufs_crypto_cfg_entry *cfg,
150 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
151 union ufs_crypto_cap_entry cap;
153 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE;
155 /* Only AES-256-XTS has been tested so far. */
156 cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
157 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
158 cap.key_size != UFS_CRYPTO_KEY_SIZE_256)
162 return qcom_ice_program_key(host->ice,
163 QCOM_ICE_CRYPTO_ALG_AES_XTS,
164 QCOM_ICE_CRYPTO_KEY_SIZE_256,
166 cfg->data_unit_size, slot);
168 return qcom_ice_evict_key(host->ice, slot);
173 #define ufs_qcom_ice_program_key NULL
175 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
179 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
184 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
189 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
195 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
197 if (!host->is_lane_clks_enabled)
200 clk_bulk_disable_unprepare(host->num_clks, host->clks);
202 host->is_lane_clks_enabled = false;
205 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
209 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
213 host->is_lane_clks_enabled = true;
218 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
221 struct device *dev = host->hba->dev;
223 if (has_acpi_companion(dev))
226 err = devm_clk_bulk_get_all(dev, &host->clks);
230 host->num_clks = err;
235 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
239 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
242 err = ufshcd_dme_get(hba,
243 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
244 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
246 if (err || tx_fsm_val == TX_FSM_HIBERN8)
249 /* sleep for max. 200us */
250 usleep_range(100, 200);
251 } while (time_before(jiffies, timeout));
254 * we might have scheduled out for long during polling so
255 * check the state again.
257 if (time_after(jiffies, timeout))
258 err = ufshcd_dme_get(hba,
259 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
260 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
264 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
266 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
268 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
275 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
277 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
279 if (host->hw_ver.major >= 0x05)
280 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
282 /* make sure above configuration is applied before we return */
287 * ufs_qcom_host_reset - reset host controller and PHY
289 static int ufs_qcom_host_reset(struct ufs_hba *hba)
292 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
295 if (!host->core_reset)
298 reenable_intr = hba->is_irq_enabled;
299 ufshcd_disable_irq(hba);
301 ret = reset_control_assert(host->core_reset);
303 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
309 * The hardware requirement for delay between assert/deassert
310 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
311 * ~125us (4/32768). To be on the safe side add 200us delay.
313 usleep_range(200, 210);
315 ret = reset_control_deassert(host->core_reset);
317 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
322 usleep_range(1000, 1100);
325 ufshcd_enable_irq(hba);
330 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
332 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
334 if (host->hw_ver.major >= 0x4)
335 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
337 /* Default is HS-G3 */
341 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
343 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
344 struct ufs_host_params *host_params = &host->host_params;
345 struct phy *phy = host->generic_phy;
350 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
351 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
352 * so that the subsequent power mode change shall stick to Rate-A.
354 if (host->hw_ver.major == 0x5) {
355 if (host->phy_gear == UFS_HS_G5)
356 host_params->hs_rate = PA_HS_MODE_A;
358 host_params->hs_rate = PA_HS_MODE_B;
361 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
363 /* Reset UFS Host Controller and PHY */
364 ret = ufs_qcom_host_reset(hba);
368 /* phy initialization - calibrate the phy */
371 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
376 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
378 goto out_disable_phy;
380 /* power on phy - start serdes and phy's power and clocks */
381 ret = phy_power_on(phy);
383 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
385 goto out_disable_phy;
388 ufs_qcom_select_unipro_mode(host);
399 * The UTP controller has a number of internal clock gating cells (CGCs).
400 * Internal hardware sub-modules within the UTP controller control the CGCs.
401 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
402 * in a specific operation, UTP controller CGCs are by default disabled and
403 * this function enables them (after every UFS link startup) to save some power
406 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
408 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
411 /* Ensure that HW clock gating is enabled before next operations */
415 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
416 enum ufs_notify_change_status status)
418 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
423 err = ufs_qcom_power_up_sequence(hba);
428 * The PHY PLL output is the source of tx/rx lane symbol
429 * clocks, hence, enable the lane clocks only after PHY
432 err = ufs_qcom_enable_lane_clks(host);
435 /* check if UFS PHY moved from DISABLED to HIBERN8 */
436 err = ufs_qcom_check_hibern8(hba);
437 ufs_qcom_enable_hw_clk_gating(hba);
438 ufs_qcom_ice_enable(host);
441 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
449 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
451 * @hba: host controller instance
452 * @gear: Current operating gear
453 * @hs: current power mode
454 * @rate: current operating rate (A or B)
455 * @update_link_startup_timer: indicate if link_start ongoing
456 * @is_pre_scale_up: flag to check if pre scale up condition.
457 * Return: zero for success and non-zero in case of a failure.
459 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
460 u32 hs, u32 rate, bool update_link_startup_timer,
461 bool is_pre_scale_up)
463 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
464 struct ufs_clk_info *clki;
465 unsigned long core_clk_rate = 0;
466 u32 core_clk_cycles_per_us;
469 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
471 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
472 * controller V4.0.0 onwards.
474 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
478 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
482 list_for_each_entry(clki, &hba->clk_list_head, list) {
483 if (!strcmp(clki->name, "core_clk")) {
485 core_clk_rate = clki->max_freq;
487 core_clk_rate = clk_get_rate(clki->clk);
493 /* If frequency is smaller than 1MHz, set to 1MHz */
494 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
495 core_clk_rate = DEFAULT_CLK_RATE_HZ;
497 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
498 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
499 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
501 * make sure above write gets applied before we return from
510 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
511 enum ufs_notify_change_status status)
517 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
519 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
524 err = ufs_qcom_set_core_clk_ctrl(hba, true);
526 dev_err(hba->dev, "cfg core clk ctrl failed\n");
528 * Some UFS devices (and may be host) have issues if LCC is
529 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
530 * before link startup which will make sure that both host
531 * and device TX LCC are disabled once link startup is
534 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
535 err = ufshcd_disable_host_tx_lcc(hba);
545 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
547 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
549 /* reset gpio is optional */
550 if (!host->device_reset)
553 gpiod_set_value_cansleep(host->device_reset, asserted);
556 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
557 enum ufs_notify_change_status status)
559 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
560 struct phy *phy = host->generic_phy;
562 if (status == PRE_CHANGE)
565 if (ufs_qcom_is_link_off(hba)) {
567 * Disable the tx/rx lane symbol clocks before PHY is
568 * powered down as the PLL source should be disabled
569 * after downstream clocks are disabled.
571 ufs_qcom_disable_lane_clks(host);
574 /* reset the connected UFS device during power down */
575 ufs_qcom_device_reset_ctrl(hba, true);
577 } else if (!ufs_qcom_is_link_active(hba)) {
578 ufs_qcom_disable_lane_clks(host);
581 return ufs_qcom_ice_suspend(host);
584 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
586 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
587 struct phy *phy = host->generic_phy;
590 if (ufs_qcom_is_link_off(hba)) {
591 err = phy_power_on(phy);
593 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
598 err = ufs_qcom_enable_lane_clks(host);
602 } else if (!ufs_qcom_is_link_active(hba)) {
603 err = ufs_qcom_enable_lane_clks(host);
608 return ufs_qcom_ice_resume(host);
611 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
613 if (host->dev_ref_clk_ctrl_mmio &&
614 (enable ^ host->is_dev_ref_clk_enabled)) {
615 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
618 temp |= host->dev_ref_clk_en_mask;
620 temp &= ~host->dev_ref_clk_en_mask;
623 * If we are here to disable this clock it might be immediately
624 * after entering into hibern8 in which case we need to make
625 * sure that device ref_clk is active for specific time after
629 unsigned long gating_wait;
631 gating_wait = host->hba->dev_info.clk_gating_wait_us;
636 * bRefClkGatingWaitTime defines the minimum
637 * time for which the reference clock is
638 * required by device during transition from
639 * HS-MODE to LS-MODE or HIBERN8 state. Give it
640 * more delay to be on the safe side.
643 usleep_range(gating_wait, gating_wait + 10);
647 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
650 * Make sure the write to ref_clk reaches the destination and
651 * not stored in a Write Buffer (WB).
653 readl(host->dev_ref_clk_ctrl_mmio);
656 * If we call hibern8 exit after this, we need to make sure that
657 * device ref_clk is stable for at least 1us before the hibern8
663 host->is_dev_ref_clk_enabled = enable;
667 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
669 struct device *dev = host->hba->dev;
672 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
674 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
678 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
680 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
687 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
689 struct ufs_pa_layer_attr *p = &host->dev_req_params;
690 int gear = max_t(u32, p->gear_rx, p->gear_tx);
691 int lane = max_t(u32, p->lane_rx, p->lane_tx);
693 if (ufshcd_is_hs_mode(p)) {
694 if (p->hs_rate == PA_HS_MODE_B)
695 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
697 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
699 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
703 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
705 struct __ufs_qcom_bw_table bw_table;
707 bw_table = ufs_qcom_get_bw_table(host);
709 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
712 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
713 enum ufs_notify_change_status status,
714 struct ufs_pa_layer_attr *dev_max_params,
715 struct ufs_pa_layer_attr *dev_req_params)
717 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
718 struct ufs_host_params *host_params = &host->host_params;
721 if (!dev_req_params) {
722 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
728 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
730 dev_err(hba->dev, "%s: failed to determine capabilities\n",
736 * During UFS driver probe, always update the PHY gear to match the negotiated
737 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
738 * the second init can program the optimal PHY settings. This allows one to start
739 * the first init with either the minimum or the maximum support gear.
741 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
743 * Skip REINIT if the negotiated gear matches with the
744 * initial phy_gear. Otherwise, update the phy_gear to
745 * program the optimal gear setting during REINIT.
747 if (host->phy_gear == dev_req_params->gear_tx)
748 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
750 host->phy_gear = dev_req_params->gear_tx;
753 /* enable the device ref clock before changing to HS mode */
754 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
755 ufshcd_is_hs_mode(dev_req_params))
756 ufs_qcom_dev_ref_clk_ctrl(host, true);
758 if (host->hw_ver.major >= 0x4) {
759 ufshcd_dme_configure_adapt(hba,
760 dev_req_params->gear_tx,
765 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
766 dev_req_params->pwr_rx,
767 dev_req_params->hs_rate, false, false)) {
768 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
771 * we return error code at the end of the routine,
772 * but continue to configure UFS_PHY_TX_LANE_ENABLE
773 * and bus voting as usual
778 /* cache the power mode parameters to use internally */
779 memcpy(&host->dev_req_params,
780 dev_req_params, sizeof(*dev_req_params));
782 ufs_qcom_icc_update_bw(host);
784 /* disable the device ref clock if entered PWM mode */
785 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
786 !ufshcd_is_hs_mode(dev_req_params))
787 ufs_qcom_dev_ref_clk_ctrl(host, false);
797 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
800 u32 pa_vs_config_reg1;
802 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
807 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
808 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
809 (pa_vs_config_reg1 | (1 << 12)));
812 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
816 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
817 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
819 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
820 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
825 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
827 return ufshci_version(2, 0);
831 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
832 * @hba: host controller instance
834 * QCOM UFS host controller might have some non standard behaviours (quirks)
835 * than what is specified by UFSHCI specification. Advertise all such
836 * quirks to standard UFS host controller driver so standard takes them into
839 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
841 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
843 if (host->hw_ver.major == 0x2)
844 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
846 if (host->hw_ver.major > 0x3)
847 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
850 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
852 struct ufs_host_params *host_params = &host->host_params;
856 * Default to powering up the PHY to the max gear possible, which is
857 * backwards compatible with lower gears but not optimal from
858 * a power usage point of view. After device negotiation, if the
859 * gear is lower a reinit will be performed to program the PHY
860 * to the ideal gear for this combo of controller and device.
862 host->phy_gear = host_params->hs_tx_gear;
864 if (host->hw_ver.major < 0x4) {
866 * These controllers only have one PHY init sequence,
867 * let's power up the PHY using that (the minimum supported
870 host->phy_gear = UFS_HS_G2;
871 } else if (host->hw_ver.major >= 0x5) {
872 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
873 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
876 * Since the UFS device version is populated, let's remove the
877 * REINIT quirk as the negotiated gear won't change during boot.
878 * So there is no need to do reinit.
880 if (dev_major != 0x0)
881 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
884 * For UFS 3.1 device and older, power up the PHY using HS-G4
885 * PHY gear to save power.
887 if (dev_major > 0x0 && dev_major < 0x4)
888 host->phy_gear = UFS_HS_G4;
892 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
894 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
895 struct ufs_host_params *host_params = &host->host_params;
897 ufshcd_init_host_params(host_params);
899 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
900 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
903 static void ufs_qcom_set_caps(struct ufs_hba *hba)
905 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
906 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
907 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
908 hba->caps |= UFSHCD_CAP_WB_EN;
909 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
910 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
914 * ufs_qcom_setup_clocks - enables/disable clocks
915 * @hba: host controller instance
916 * @on: If true, enable clocks else disable them.
917 * @status: PRE_CHANGE or POST_CHANGE notify
919 * Return: 0 on success, non-zero on failure.
921 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
922 enum ufs_notify_change_status status)
924 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
927 * In case ufs_qcom_init() is not yet done, simply ignore.
928 * This ufs_qcom_setup_clocks() shall be called from
929 * ufs_qcom_init() after init is done.
937 ufs_qcom_icc_update_bw(host);
939 if (!ufs_qcom_is_link_active(hba)) {
940 /* disable device ref_clk */
941 ufs_qcom_dev_ref_clk_ctrl(host, false);
947 /* enable the device ref clock for HS mode*/
948 if (ufshcd_is_hs_mode(&hba->pwr_info))
949 ufs_qcom_dev_ref_clk_ctrl(host, true);
951 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
952 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
961 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
963 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
965 ufs_qcom_assert_reset(host->hba);
966 /* provide 1ms delay to let the reset pulse propagate. */
967 usleep_range(1000, 1100);
972 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
974 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
976 ufs_qcom_deassert_reset(host->hba);
979 * after reset deassertion, phy will need all ref clocks,
980 * voltage, current to settle down before starting serdes.
982 usleep_range(1000, 1100);
986 static const struct reset_control_ops ufs_qcom_reset_ops = {
987 .assert = ufs_qcom_reset_assert,
988 .deassert = ufs_qcom_reset_deassert,
991 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
993 struct device *dev = host->hba->dev;
996 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
997 if (IS_ERR(host->icc_ddr))
998 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
999 "failed to acquire interconnect path\n");
1001 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1002 if (IS_ERR(host->icc_cpu))
1003 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1004 "failed to acquire interconnect path\n");
1007 * Set Maximum bandwidth vote before initializing the UFS controller and
1008 * device. Ideally, a minimal interconnect vote would suffice for the
1009 * initialization, but a max vote would allow faster initialization.
1011 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1012 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1014 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1020 * ufs_qcom_init - bind phy with controller
1021 * @hba: host controller instance
1023 * Binds PHY with controller and powers up PHY enabling clocks
1026 * Return: -EPROBE_DEFER if binding fails, returns negative error
1027 * on phy power up failure and returns zero on success.
1029 static int ufs_qcom_init(struct ufs_hba *hba)
1032 struct device *dev = hba->dev;
1033 struct ufs_qcom_host *host;
1034 struct ufs_clk_info *clki;
1036 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1040 /* Make a two way bind between the qcom host and the hba */
1042 ufshcd_set_variant(hba, host);
1044 /* Setup the optional reset control of HCI */
1045 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1046 if (IS_ERR(host->core_reset)) {
1047 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1048 "Failed to get reset control\n");
1049 goto out_variant_clear;
1052 /* Fire up the reset controller. Failure here is non-fatal. */
1053 host->rcdev.of_node = dev->of_node;
1054 host->rcdev.ops = &ufs_qcom_reset_ops;
1055 host->rcdev.owner = dev->driver->owner;
1056 host->rcdev.nr_resets = 1;
1057 err = devm_reset_controller_register(dev, &host->rcdev);
1059 dev_warn(dev, "Failed to register reset controller\n");
1061 if (!has_acpi_companion(dev)) {
1062 host->generic_phy = devm_phy_get(dev, "ufsphy");
1063 if (IS_ERR(host->generic_phy)) {
1064 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1065 goto out_variant_clear;
1069 err = ufs_qcom_icc_init(host);
1071 goto out_variant_clear;
1073 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1075 if (IS_ERR(host->device_reset)) {
1076 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1077 "Failed to acquire device reset gpio\n");
1078 goto out_variant_clear;
1081 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1082 &host->hw_ver.minor, &host->hw_ver.step);
1084 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1085 host->dev_ref_clk_en_mask = BIT(26);
1087 list_for_each_entry(clki, &hba->clk_list_head, list) {
1088 if (!strcmp(clki->name, "core_clk_unipro"))
1089 clki->keep_link_active = true;
1092 err = ufs_qcom_init_lane_clks(host);
1094 goto out_variant_clear;
1096 ufs_qcom_set_caps(hba);
1097 ufs_qcom_advertise_quirks(hba);
1098 ufs_qcom_set_host_params(hba);
1099 ufs_qcom_set_phy_gear(host);
1101 err = ufs_qcom_ice_init(host);
1103 goto out_variant_clear;
1105 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1107 ufs_qcom_get_default_testbus_cfg(host);
1108 err = ufs_qcom_testbus_config(host);
1110 /* Failure is non-fatal */
1111 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1117 ufshcd_set_variant(hba, NULL);
1122 static void ufs_qcom_exit(struct ufs_hba *hba)
1124 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1126 ufs_qcom_disable_lane_clks(host);
1127 phy_power_off(host->generic_phy);
1128 phy_exit(host->generic_phy);
1132 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1134 * @hba: host controller instance
1135 * @cycles_in_1us: No of cycles in 1us to be configured
1137 * Returns error if dme get/set configuration for 40ns fails
1138 * and returns zero on success.
1140 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1143 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1149 * UFS host controller V4.0.0 onwards needs to program
1150 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1151 * frequency of unipro core clk of UFS host controller.
1153 if (host->hw_ver.major < 4)
1157 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1158 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1159 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1160 * specification expect to be 16. Hence use exact hardware spec
1161 * mandated value for cycles_in_40ns instead of calculating using
1164 switch (cycles_in_1us) {
1165 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1166 cycles_in_40ns = 16;
1168 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1169 cycles_in_40ns = 12;
1171 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1174 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1177 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1180 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1183 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1187 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1192 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1196 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1197 reg |= cycles_in_40ns;
1199 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1202 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
1204 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1205 struct list_head *head = &hba->clk_list_head;
1206 struct ufs_clk_info *clki;
1207 u32 cycles_in_1us = 0;
1208 u32 core_clk_ctrl_reg;
1211 list_for_each_entry(clki, head, list) {
1212 if (!IS_ERR_OR_NULL(clki->clk) &&
1213 !strcmp(clki->name, "core_clk_unipro")) {
1215 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000));
1217 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));
1222 err = ufshcd_dme_get(hba,
1223 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1224 &core_clk_ctrl_reg);
1228 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1229 if (host->hw_ver.major >= 4) {
1230 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1232 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1233 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1235 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1237 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1238 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1241 /* Clear CORE_CLK_DIV_EN */
1242 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1244 err = ufshcd_dme_set(hba,
1245 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1250 /* Configure unipro core clk 40ns attribute */
1251 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1254 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1256 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1257 struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1260 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
1261 attr->hs_rate, false, true);
1263 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1266 /* set unipro core clock attributes and clear clock divider */
1267 return ufs_qcom_set_core_clk_ctrl(hba, true);
1270 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1275 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1278 u32 core_clk_ctrl_reg;
1280 err = ufshcd_dme_get(hba,
1281 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1282 &core_clk_ctrl_reg);
1284 /* make sure CORE_CLK_DIV_EN is cleared */
1286 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1287 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1288 err = ufshcd_dme_set(hba,
1289 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1296 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1298 /* set unipro core clock attributes and clear clock divider */
1299 return ufs_qcom_set_core_clk_ctrl(hba, false);
1302 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1303 bool scale_up, enum ufs_notify_change_status status)
1305 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1308 /* check the host controller state before sending hibern8 cmd */
1309 if (!ufshcd_is_hba_active(hba))
1312 if (status == PRE_CHANGE) {
1313 err = ufshcd_uic_hibern8_enter(hba);
1317 err = ufs_qcom_clk_scale_up_pre_change(hba);
1319 err = ufs_qcom_clk_scale_down_pre_change(hba);
1322 ufshcd_uic_hibern8_exit(hba);
1327 err = ufs_qcom_clk_scale_up_post_change(hba);
1329 err = ufs_qcom_clk_scale_down_post_change(hba);
1333 ufshcd_uic_hibern8_exit(hba);
1337 ufs_qcom_icc_update_bw(host);
1338 ufshcd_uic_hibern8_exit(hba);
1344 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1346 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1347 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1348 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1351 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1353 /* provide a legal default configuration */
1354 host->testbus.select_major = TSTBUS_UNIPRO;
1355 host->testbus.select_minor = 37;
1358 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1360 if (host->testbus.select_major >= TSTBUS_MAX) {
1361 dev_err(host->hba->dev,
1362 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1363 __func__, host->testbus.select_major);
1370 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1374 u32 mask = TEST_BUS_SUB_SEL_MASK;
1379 if (!ufs_qcom_testbus_cfg_is_ok(host))
1382 switch (host->testbus.select_major) {
1384 reg = UFS_TEST_BUS_CTRL_0;
1388 reg = UFS_TEST_BUS_CTRL_0;
1392 reg = UFS_TEST_BUS_CTRL_0;
1396 reg = UFS_TEST_BUS_CTRL_0;
1400 reg = UFS_TEST_BUS_CTRL_1;
1404 reg = UFS_TEST_BUS_CTRL_1;
1408 reg = UFS_TEST_BUS_CTRL_1;
1412 reg = UFS_TEST_BUS_CTRL_1;
1415 case TSTBUS_WRAPPER:
1416 reg = UFS_TEST_BUS_CTRL_2;
1419 case TSTBUS_COMBINED:
1420 reg = UFS_TEST_BUS_CTRL_2;
1423 case TSTBUS_UTP_HCI:
1424 reg = UFS_TEST_BUS_CTRL_2;
1428 reg = UFS_UNIPRO_CFG;
1433 * No need for a default case, since
1434 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1439 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1440 (u32)host->testbus.select_major << 19,
1442 ufshcd_rmwl(host->hba, mask,
1443 (u32)host->testbus.select_minor << offset,
1445 ufs_qcom_enable_test_bus(host);
1447 * Make sure the test bus configuration is
1448 * committed before returning.
1455 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1458 struct ufs_qcom_host *host;
1460 host = ufshcd_get_variant(hba);
1462 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1463 "HCI Vendor Specific Registers ");
1465 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1466 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1468 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1469 reg |= UTP_DBG_RAMS_EN;
1470 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1472 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1473 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1475 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1476 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1478 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1479 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1481 /* clear bit 17 - UTP_DBG_RAMS_EN */
1482 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1484 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1485 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1487 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1488 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1490 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1491 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1493 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1494 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1496 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1497 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1499 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1500 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1502 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1503 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1507 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1508 * @hba: per-adapter instance
1510 * Toggles the (optional) reset line to reset the attached device.
1512 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1514 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1516 /* reset gpio is optional */
1517 if (!host->device_reset)
1521 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1522 * be on the safe side.
1524 ufs_qcom_device_reset_ctrl(hba, true);
1525 usleep_range(10, 15);
1527 ufs_qcom_device_reset_ctrl(hba, false);
1528 usleep_range(10, 15);
1533 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1534 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1535 struct devfreq_dev_profile *p,
1536 struct devfreq_simple_ondemand_data *d)
1539 p->timer = DEVFREQ_TIMER_DELAYED;
1540 d->upthreshold = 70;
1541 d->downdifferential = 5;
1544 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1545 struct devfreq_dev_profile *p,
1546 struct devfreq_simple_ondemand_data *data)
1551 static void ufs_qcom_reinit_notify(struct ufs_hba *hba)
1553 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1555 phy_power_off(host->generic_phy);
1559 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1560 {.name = "ufs_mem",},
1562 /* Submission Queue DAO */
1563 {.name = "mcq_sqd",},
1564 /* Submission Queue Interrupt Status */
1565 {.name = "mcq_sqis",},
1566 /* Completion Queue DAO */
1567 {.name = "mcq_cqd",},
1568 /* Completion Queue Interrupt Status */
1569 {.name = "mcq_cqis",},
1570 /* MCQ vendor specific */
1571 {.name = "mcq_vs",},
1574 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1576 struct platform_device *pdev = to_platform_device(hba->dev);
1577 struct ufshcd_res_info *res;
1578 struct resource *res_mem, *res_mcq;
1581 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1583 for (i = 0; i < RES_MAX; i++) {
1585 res->resource = platform_get_resource_byname(pdev,
1588 if (!res->resource) {
1589 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1593 } else if (i == RES_UFS) {
1594 res_mem = res->resource;
1595 res->base = hba->mmio_base;
1599 res->base = devm_ioremap_resource(hba->dev, res->resource);
1600 if (IS_ERR(res->base)) {
1601 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1602 res->name, (int)PTR_ERR(res->base));
1603 ret = PTR_ERR(res->base);
1609 /* MCQ resource provided in DT */
1610 res = &hba->res[RES_MCQ];
1611 /* Bail if MCQ resource is provided */
1615 /* Explicitly allocate MCQ resource from ufs_mem */
1616 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1620 res_mcq->start = res_mem->start +
1621 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1622 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1623 res_mcq->flags = res_mem->flags;
1624 res_mcq->name = "mcq";
1626 ret = insert_resource(&iomem_resource, res_mcq);
1628 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1633 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1634 if (IS_ERR(res->base)) {
1635 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1636 (int)PTR_ERR(res->base));
1637 ret = PTR_ERR(res->base);
1642 hba->mcq_base = res->base;
1646 remove_resource(res_mcq);
1650 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1652 struct ufshcd_res_info *mem_res, *sqdao_res;
1653 struct ufshcd_mcq_opr_info_t *opr;
1656 mem_res = &hba->res[RES_UFS];
1657 sqdao_res = &hba->res[RES_MCQ_SQD];
1659 if (!mem_res->base || !sqdao_res->base)
1662 for (i = 0; i < OPR_MAX; i++) {
1663 opr = &hba->mcq_opr[i];
1664 opr->offset = sqdao_res->resource->start -
1665 mem_res->resource->start + 0x40 * i;
1666 opr->stride = 0x100;
1667 opr->base = sqdao_res->base + 0x40 * i;
1673 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1675 /* Qualcomm HC supports up to 64 */
1676 return MAX_SUPP_MAC;
1679 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1680 unsigned long *ocqs)
1682 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1684 if (!mcq_vs_res->base)
1687 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1692 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1694 struct device *dev = msi_desc_to_dev(desc);
1695 struct ufs_hba *hba = dev_get_drvdata(dev);
1697 ufshcd_mcq_config_esi(hba, msg);
1700 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1702 struct msi_desc *desc = data;
1703 struct device *dev = msi_desc_to_dev(desc);
1704 struct ufs_hba *hba = dev_get_drvdata(dev);
1705 u32 id = desc->msi_index;
1706 struct ufs_hw_queue *hwq = &hba->uhq[id];
1708 ufshcd_mcq_write_cqis(hba, 0x1, id);
1709 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1714 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1716 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1717 struct msi_desc *desc;
1718 struct msi_desc *failed_desc = NULL;
1721 if (host->esi_enabled)
1725 * 1. We only handle CQs as of now.
1726 * 2. Poll queues do not need ESI.
1728 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1729 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1730 ufs_qcom_write_msi_msg);
1732 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1736 msi_lock_descs(hba->dev);
1737 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1738 ret = devm_request_irq(hba->dev, desc->irq,
1739 ufs_qcom_mcq_esi_handler,
1740 IRQF_SHARED, "qcom-mcq-esi", desc);
1742 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1743 __func__, desc->irq, ret);
1748 msi_unlock_descs(hba->dev);
1752 msi_lock_descs(hba->dev);
1753 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1754 if (desc == failed_desc)
1756 devm_free_irq(hba->dev, desc->irq, hba);
1758 msi_unlock_descs(hba->dev);
1759 platform_device_msi_free_irqs_all(hba->dev);
1761 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1762 host->hw_ver.step == 0)
1763 ufshcd_rmwl(hba, ESI_VEC_MASK,
1764 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1766 ufshcd_mcq_enable_esi(hba);
1767 host->esi_enabled = true;
1774 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1776 * The variant operations configure the necessary controller and PHY
1777 * handshake during initialization.
1779 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1781 .init = ufs_qcom_init,
1782 .exit = ufs_qcom_exit,
1783 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1784 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1785 .setup_clocks = ufs_qcom_setup_clocks,
1786 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1787 .link_startup_notify = ufs_qcom_link_startup_notify,
1788 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1789 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1790 .suspend = ufs_qcom_suspend,
1791 .resume = ufs_qcom_resume,
1792 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1793 .device_reset = ufs_qcom_device_reset,
1794 .config_scaling_param = ufs_qcom_config_scaling_param,
1795 .program_key = ufs_qcom_ice_program_key,
1796 .reinit_notify = ufs_qcom_reinit_notify,
1797 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1798 .get_hba_mac = ufs_qcom_get_hba_mac,
1799 .op_runtime_config = ufs_qcom_op_runtime_config,
1800 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1801 .config_esi = ufs_qcom_config_esi,
1805 * ufs_qcom_probe - probe routine of the driver
1806 * @pdev: pointer to Platform device handle
1808 * Return: zero for success and non-zero for failure.
1810 static int ufs_qcom_probe(struct platform_device *pdev)
1813 struct device *dev = &pdev->dev;
1815 /* Perform generic probe */
1816 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1818 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1824 * ufs_qcom_remove - set driver_data of the device to NULL
1825 * @pdev: pointer to platform device handle
1829 static void ufs_qcom_remove(struct platform_device *pdev)
1831 struct ufs_hba *hba = platform_get_drvdata(pdev);
1833 pm_runtime_get_sync(&(pdev)->dev);
1835 platform_device_msi_free_irqs_all(hba->dev);
1838 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1839 { .compatible = "qcom,ufshc"},
1842 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1845 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1849 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1852 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1853 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1854 .prepare = ufshcd_suspend_prepare,
1855 .complete = ufshcd_resume_complete,
1856 #ifdef CONFIG_PM_SLEEP
1857 .suspend = ufshcd_system_suspend,
1858 .resume = ufshcd_system_resume,
1859 .freeze = ufshcd_system_freeze,
1860 .restore = ufshcd_system_restore,
1861 .thaw = ufshcd_system_thaw,
1865 static struct platform_driver ufs_qcom_pltform = {
1866 .probe = ufs_qcom_probe,
1867 .remove_new = ufs_qcom_remove,
1869 .name = "ufshcd-qcom",
1870 .pm = &ufs_qcom_pm_ops,
1871 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1872 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1875 module_platform_driver(ufs_qcom_pltform);
1877 MODULE_LICENSE("GPL v2");