1 // SPDX-License-Identifier: GPL-1.0+
3 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
5 * Device driver for Microgate SyncLink Multiport
6 * high speed multiprotocol serial adapter.
8 * written by Paul Fulghum for Microgate Corporation
11 * Microgate and SyncLink are trademarks of Microgate Corporation
13 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <linux/uaccess.h>
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
120 } SCADESC, *PSCADESC;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events {
149 * Device instance data structure
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 struct tty_port port;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
159 struct mgsl_icount icount;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
181 u32 max_frame_size; /* as set by device config */
185 bool bh_running; /* Protection from multiple */
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
223 char device_name[25]; /* device instance name */
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
237 MGSL_PARAMS params; /* communications parameters */
239 unsigned char serial_signals; /* current serial signal states */
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
252 bool sca_base_requested;
254 unsigned char* lcr_base; /* local config registers (PCI only) */
257 int lcr_mem_requested;
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
262 bool sca_statctrl_requested;
266 bool drop_rts_on_tx_done;
268 struct _input_signal_events input_signal_events;
270 /* SPPP/Cisco HDLC device parts */
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
280 #define MGSL_MAGIC 0x5401
283 * define serial signal status change macros
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
290 /* Common Register macros */
309 /* MSCI Register macros */
339 /* Timer Register Macros */
349 /* DMA Controller Register macros */
380 /* combine with timer or DMA register address */
388 /* SCA Command Codes */
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
398 #define TXBUFCLR 0x09
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
410 /* DMA command codes */
412 #define FEICLEAR 0x02
446 * Global linked list of SyncLink devices
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
457 static bool break_on_load = 0;
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
463 static int ttymajor = 0;
466 * Array of user specified options for ISA adapters.
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
482 static const struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488 MODULE_LICENSE("GPL");
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
498 static struct tty_driver *serial_driver;
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
552 static int add_device(SLMP_INFO *info);
553 static int device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(struct timer_list *t);
619 static void status_timeout(struct timer_list *t);
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
636 static u32 read_ahead_count = 8;
638 /* DPCR, DMA Priority Control
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
649 static unsigned char dma_priority = 0x04;
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
674 printk(badinfo, name, routine);
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
689 * line discipline callback wrappers
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
694 * ldisc_receive_buf - pass receive data to line discipline
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
700 struct tty_ldisc *ld;
703 ld = tty_ldisc_ref(tty);
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
716 int line = tty->index;
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
736 tty->driver_data = info;
738 return tty_port_install(&info->port, driver, tty);
741 /* Called when a port is opened. Init and enable port.
743 static int open(struct tty_struct *tty, struct file *filp)
745 SLMP_INFO *info = tty->driver_data;
749 info->port.tty = tty;
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
760 spin_unlock_irqrestore(&info->netlock, flags);
764 spin_unlock_irqrestore(&info->netlock, flags);
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
773 retval = block_til_ready(tty, filp, info);
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
789 info->port.tty = NULL; /* tty layer will release tty struct */
797 /* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
800 static void close(struct tty_struct *tty, struct file *filp)
802 SLMP_INFO * info = tty->driver_data;
804 if (sanity_check(info, tty->name, "close"))
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
814 mutex_lock(&info->port.mutex);
815 if (tty_port_initialized(&info->port))
816 wait_until_sent(tty, info->timeout);
819 tty_ldisc_flush(tty);
821 mutex_unlock(&info->port.mutex);
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
834 static void hangup(struct tty_struct *tty)
836 SLMP_INFO *info = tty->driver_data;
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
843 if (sanity_check(info, tty->name, "hangup"))
846 mutex_lock(&info->port.mutex);
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.tty = NULL;
853 spin_unlock_irqrestore(&info->port.lock, flags);
854 tty_port_set_active(&info->port, 1);
855 mutex_unlock(&info->port.mutex);
857 wake_up_interruptible(&info->port.open_wait);
860 /* Set new termios settings
862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
864 SLMP_INFO *info = tty->driver_data;
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
878 spin_unlock_irqrestore(&info->lock,flags);
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
888 spin_unlock_irqrestore(&info->lock,flags);
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
898 /* Send a block of data
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
906 * Return Value: number of characters written
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
912 SLMP_INFO *info = tty->driver_data;
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
919 if (sanity_check(info, tty->name, "write"))
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
950 memcpy(info->tx_buf + info->tx_put, buf, c);
952 spin_lock_irqsave(&info->lock,flags);
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
957 spin_unlock_irqrestore(&info->lock,flags);
964 if (info->params.mode == MGSL_MODE_HDLC) {
966 ret = info->tx_count = 0;
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
976 spin_unlock_irqrestore(&info->lock,flags);
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
986 /* Add a character to the transmit buffer.
988 static int put_char(struct tty_struct *tty, unsigned char ch)
990 SLMP_INFO *info = tty->driver_data;
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
999 if (sanity_check(info, tty->name, "put_char"))
1005 spin_lock_irqsave(&info->lock,flags);
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1019 spin_unlock_irqrestore(&info->lock,flags);
1023 /* Send a high-priority XON/XOFF character
1025 static void send_xchar(struct tty_struct *tty, char ch)
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1034 if (sanity_check(info, tty->name, "send_xchar"))
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1043 spin_unlock_irqrestore(&info->lock,flags);
1047 /* Wait until the transmitter is empty.
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1064 if (!tty_port_initialized(&info->port))
1067 orig_jiffies = jiffies;
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1083 char_time = min_t(unsigned long, char_time, timeout);
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1113 /* Return the count of free bytes in transmit buffer
1115 static int write_room(struct tty_struct *tty)
1117 SLMP_INFO *info = tty->driver_data;
1120 if (sanity_check(info, tty->name, "write_room"))
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1126 ret = info->max_frame_size - info->tx_count - 1;
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1138 /* enable transmitter and send remaining buffered characters
1140 static void flush_chars(struct tty_struct *tty)
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1149 if (sanity_check(info, tty->name, "flush_chars"))
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1160 spin_lock_irqsave(&info->lock,flags);
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1174 spin_unlock_irqrestore(&info->lock,flags);
1177 /* Discard all data in the send buffer
1179 static void flush_buffer(struct tty_struct *tty)
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1199 /* throttle (stop) transmitter
1201 static void tx_hold(struct tty_struct *tty)
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1206 if (sanity_check(info, tty->name, "tx_hold"))
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1216 spin_unlock_irqrestore(&info->lock,flags);
1219 /* release (start) transmitter
1221 static void tx_release(struct tty_struct *tty)
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1226 if (sanity_check(info, tty->name, "tx_release"))
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1236 spin_unlock_irqrestore(&info->lock,flags);
1239 /* Service an IOCTL request
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1247 * Return Value: 0 if success, otherwise error code
1249 static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1259 if (sanity_check(info, tty->name, "ioctl"))
1262 if (cmd != TIOCMIWAIT) {
1263 if (tty_io_error(tty))
1268 case MGSL_IOCGPARAMS:
1269 return get_params(info, argp);
1270 case MGSL_IOCSPARAMS:
1271 return set_params(info, argp);
1272 case MGSL_IOCGTXIDLE:
1273 return get_txidle(info, argp);
1274 case MGSL_IOCSTXIDLE:
1275 return set_txidle(info, (int)arg);
1276 case MGSL_IOCTXENABLE:
1277 return tx_enable(info, (int)arg);
1278 case MGSL_IOCRXENABLE:
1279 return rx_enable(info, (int)arg);
1280 case MGSL_IOCTXABORT:
1281 return tx_abort(info);
1282 case MGSL_IOCGSTATS:
1283 return get_stats(info, argp);
1284 case MGSL_IOCWAITEVENT:
1285 return wait_mgsl_event(info, argp);
1286 case MGSL_IOCLOOPTXDONE:
1287 return 0; // TODO: Not supported, need to document
1288 /* Wait for modem input (DCD,RI,DSR,CTS) change
1289 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1292 return modem_input_wait(info,(int)arg);
1295 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1296 * Return: write counters to the user passed counter struct
1297 * NB: both 1->0 and 0->1 transitions are counted except for
1298 * RI where only 0->1 is counted.
1301 return -ENOIOCTLCMD;
1306 static int get_icount(struct tty_struct *tty,
1307 struct serial_icounter_struct *icount)
1309 SLMP_INFO *info = tty->driver_data;
1310 struct mgsl_icount cnow; /* kernel counter temps */
1311 unsigned long flags;
1313 spin_lock_irqsave(&info->lock,flags);
1314 cnow = info->icount;
1315 spin_unlock_irqrestore(&info->lock,flags);
1317 icount->cts = cnow.cts;
1318 icount->dsr = cnow.dsr;
1319 icount->rng = cnow.rng;
1320 icount->dcd = cnow.dcd;
1321 icount->rx = cnow.rx;
1322 icount->tx = cnow.tx;
1323 icount->frame = cnow.frame;
1324 icount->overrun = cnow.overrun;
1325 icount->parity = cnow.parity;
1326 icount->brk = cnow.brk;
1327 icount->buf_overrun = cnow.buf_overrun;
1333 * /proc fs routines....
1336 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1339 unsigned long flags;
1341 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1342 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->phys_sca_base,
1345 info->phys_memory_base,
1346 info->phys_statctrl_base,
1347 info->phys_lcr_base,
1349 info->max_frame_size );
1351 /* output current serial signal states */
1352 spin_lock_irqsave(&info->lock,flags);
1354 spin_unlock_irqrestore(&info->lock,flags);
1358 if (info->serial_signals & SerialSignal_RTS)
1359 strcat(stat_buf, "|RTS");
1360 if (info->serial_signals & SerialSignal_CTS)
1361 strcat(stat_buf, "|CTS");
1362 if (info->serial_signals & SerialSignal_DTR)
1363 strcat(stat_buf, "|DTR");
1364 if (info->serial_signals & SerialSignal_DSR)
1365 strcat(stat_buf, "|DSR");
1366 if (info->serial_signals & SerialSignal_DCD)
1367 strcat(stat_buf, "|CD");
1368 if (info->serial_signals & SerialSignal_RI)
1369 strcat(stat_buf, "|RI");
1371 if (info->params.mode == MGSL_MODE_HDLC) {
1372 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1373 info->icount.txok, info->icount.rxok);
1374 if (info->icount.txunder)
1375 seq_printf(m, " txunder:%d", info->icount.txunder);
1376 if (info->icount.txabort)
1377 seq_printf(m, " txabort:%d", info->icount.txabort);
1378 if (info->icount.rxshort)
1379 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1380 if (info->icount.rxlong)
1381 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1382 if (info->icount.rxover)
1383 seq_printf(m, " rxover:%d", info->icount.rxover);
1384 if (info->icount.rxcrc)
1385 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 seq_printf(m, "\tASYNC tx:%d rx:%d",
1388 info->icount.tx, info->icount.rx);
1389 if (info->icount.frame)
1390 seq_printf(m, " fe:%d", info->icount.frame);
1391 if (info->icount.parity)
1392 seq_printf(m, " pe:%d", info->icount.parity);
1393 if (info->icount.brk)
1394 seq_printf(m, " brk:%d", info->icount.brk);
1395 if (info->icount.overrun)
1396 seq_printf(m, " oe:%d", info->icount.overrun);
1399 /* Append serial signal status to end */
1400 seq_printf(m, " %s\n", stat_buf+1);
1402 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1403 info->tx_active,info->bh_requested,info->bh_running,
1407 /* Called to print information about devices
1409 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1413 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415 info = synclinkmp_device_list;
1418 info = info->next_device;
1423 /* Return the count of bytes in transmit buffer
1425 static int chars_in_buffer(struct tty_struct *tty)
1427 SLMP_INFO *info = tty->driver_data;
1429 if (sanity_check(info, tty->name, "chars_in_buffer"))
1432 if (debug_level >= DEBUG_LEVEL_INFO)
1433 printk("%s(%d):%s chars_in_buffer()=%d\n",
1434 __FILE__, __LINE__, info->device_name, info->tx_count);
1436 return info->tx_count;
1439 /* Signal remote device to throttle send data (our receive data)
1441 static void throttle(struct tty_struct * tty)
1443 SLMP_INFO *info = tty->driver_data;
1444 unsigned long flags;
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s throttle() entry\n",
1448 __FILE__,__LINE__, info->device_name );
1450 if (sanity_check(info, tty->name, "throttle"))
1454 send_xchar(tty, STOP_CHAR(tty));
1456 if (C_CRTSCTS(tty)) {
1457 spin_lock_irqsave(&info->lock,flags);
1458 info->serial_signals &= ~SerialSignal_RTS;
1460 spin_unlock_irqrestore(&info->lock,flags);
1464 /* Signal remote device to stop throttling send data (our receive data)
1466 static void unthrottle(struct tty_struct * tty)
1468 SLMP_INFO *info = tty->driver_data;
1469 unsigned long flags;
1471 if (debug_level >= DEBUG_LEVEL_INFO)
1472 printk("%s(%d):%s unthrottle() entry\n",
1473 __FILE__,__LINE__, info->device_name );
1475 if (sanity_check(info, tty->name, "unthrottle"))
1482 send_xchar(tty, START_CHAR(tty));
1485 if (C_CRTSCTS(tty)) {
1486 spin_lock_irqsave(&info->lock,flags);
1487 info->serial_signals |= SerialSignal_RTS;
1489 spin_unlock_irqrestore(&info->lock,flags);
1493 /* set or clear transmit break condition
1494 * break_state -1=set break condition, 0=clear
1496 static int set_break(struct tty_struct *tty, int break_state)
1498 unsigned char RegValue;
1499 SLMP_INFO * info = tty->driver_data;
1500 unsigned long flags;
1502 if (debug_level >= DEBUG_LEVEL_INFO)
1503 printk("%s(%d):%s set_break(%d)\n",
1504 __FILE__,__LINE__, info->device_name, break_state);
1506 if (sanity_check(info, tty->name, "set_break"))
1509 spin_lock_irqsave(&info->lock,flags);
1510 RegValue = read_reg(info, CTL);
1511 if (break_state == -1)
1515 write_reg(info, CTL, RegValue);
1516 spin_unlock_irqrestore(&info->lock,flags);
1520 #if SYNCLINK_GENERIC_HDLC
1523 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1524 * set encoding and frame check sequence (FCS) options
1526 * dev pointer to network device structure
1527 * encoding serial encoding setting
1528 * parity FCS setting
1530 * returns 0 if success, otherwise error code
1532 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1533 unsigned short parity)
1535 SLMP_INFO *info = dev_to_port(dev);
1536 unsigned char new_encoding;
1537 unsigned short new_crctype;
1539 /* return error if TTY interface open */
1540 if (info->port.count)
1545 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1546 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1547 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1548 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1549 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1550 default: return -EINVAL;
1555 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1556 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1557 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1558 default: return -EINVAL;
1561 info->params.encoding = new_encoding;
1562 info->params.crc_type = new_crctype;
1564 /* if network interface up, reprogram hardware */
1572 * called by generic HDLC layer to send frame
1574 * skb socket buffer containing HDLC frame
1575 * dev pointer to network device structure
1577 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1578 struct net_device *dev)
1580 SLMP_INFO *info = dev_to_port(dev);
1581 unsigned long flags;
1583 if (debug_level >= DEBUG_LEVEL_INFO)
1584 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1586 /* stop sending until this frame completes */
1587 netif_stop_queue(dev);
1589 /* copy data to device buffers */
1590 info->tx_count = skb->len;
1591 tx_load_dma_buffer(info, skb->data, skb->len);
1593 /* update network statistics */
1594 dev->stats.tx_packets++;
1595 dev->stats.tx_bytes += skb->len;
1597 /* done with socket buffer, so free it */
1600 /* save start time for transmit timeout detection */
1601 netif_trans_update(dev);
1603 /* start hardware transmitter if necessary */
1604 spin_lock_irqsave(&info->lock,flags);
1605 if (!info->tx_active)
1607 spin_unlock_irqrestore(&info->lock,flags);
1609 return NETDEV_TX_OK;
1613 * called by network layer when interface enabled
1614 * claim resources and initialize hardware
1616 * dev pointer to network device structure
1618 * returns 0 if success, otherwise error code
1620 static int hdlcdev_open(struct net_device *dev)
1622 SLMP_INFO *info = dev_to_port(dev);
1624 unsigned long flags;
1626 if (debug_level >= DEBUG_LEVEL_INFO)
1627 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1629 /* generic HDLC layer open processing */
1630 rc = hdlc_open(dev);
1634 /* arbitrate between network and tty opens */
1635 spin_lock_irqsave(&info->netlock, flags);
1636 if (info->port.count != 0 || info->netcount != 0) {
1637 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1638 spin_unlock_irqrestore(&info->netlock, flags);
1642 spin_unlock_irqrestore(&info->netlock, flags);
1644 /* claim resources and init adapter */
1645 if ((rc = startup(info)) != 0) {
1646 spin_lock_irqsave(&info->netlock, flags);
1648 spin_unlock_irqrestore(&info->netlock, flags);
1652 /* assert RTS and DTR, apply hardware settings */
1653 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1656 /* enable network layer transmit */
1657 netif_trans_update(dev);
1658 netif_start_queue(dev);
1660 /* inform generic HDLC layer of current DCD status */
1661 spin_lock_irqsave(&info->lock, flags);
1663 spin_unlock_irqrestore(&info->lock, flags);
1664 if (info->serial_signals & SerialSignal_DCD)
1665 netif_carrier_on(dev);
1667 netif_carrier_off(dev);
1672 * called by network layer when interface is disabled
1673 * shutdown hardware and release resources
1675 * dev pointer to network device structure
1677 * returns 0 if success, otherwise error code
1679 static int hdlcdev_close(struct net_device *dev)
1681 SLMP_INFO *info = dev_to_port(dev);
1682 unsigned long flags;
1684 if (debug_level >= DEBUG_LEVEL_INFO)
1685 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1687 netif_stop_queue(dev);
1689 /* shutdown adapter and release resources */
1694 spin_lock_irqsave(&info->netlock, flags);
1696 spin_unlock_irqrestore(&info->netlock, flags);
1702 * called by network layer to process IOCTL call to network device
1704 * dev pointer to network device structure
1705 * ifr pointer to network interface request structure
1706 * cmd IOCTL command code
1708 * returns 0 if success, otherwise error code
1710 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1712 const size_t size = sizeof(sync_serial_settings);
1713 sync_serial_settings new_line;
1714 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1715 SLMP_INFO *info = dev_to_port(dev);
1718 if (debug_level >= DEBUG_LEVEL_INFO)
1719 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1721 /* return error if TTY interface open */
1722 if (info->port.count)
1725 if (cmd != SIOCWANDEV)
1726 return hdlc_ioctl(dev, ifr, cmd);
1728 switch(ifr->ifr_settings.type) {
1729 case IF_GET_IFACE: /* return current sync_serial_settings */
1731 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1732 if (ifr->ifr_settings.size < size) {
1733 ifr->ifr_settings.size = size; /* data size wanted */
1737 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1738 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1739 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1740 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1742 memset(&new_line, 0, sizeof(new_line));
1744 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1745 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1746 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1747 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1748 default: new_line.clock_type = CLOCK_DEFAULT;
1751 new_line.clock_rate = info->params.clock_speed;
1752 new_line.loopback = info->params.loopback ? 1:0;
1754 if (copy_to_user(line, &new_line, size))
1758 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1760 if(!capable(CAP_NET_ADMIN))
1762 if (copy_from_user(&new_line, line, size))
1765 switch (new_line.clock_type)
1767 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1768 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1769 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1770 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1771 case CLOCK_DEFAULT: flags = info->params.flags &
1772 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1773 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1774 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1775 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1776 default: return -EINVAL;
1779 if (new_line.loopback != 0 && new_line.loopback != 1)
1782 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1783 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1784 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1785 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1786 info->params.flags |= flags;
1788 info->params.loopback = new_line.loopback;
1790 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1791 info->params.clock_speed = new_line.clock_rate;
1793 info->params.clock_speed = 0;
1795 /* if network interface up, reprogram hardware */
1801 return hdlc_ioctl(dev, ifr, cmd);
1806 * called by network layer when transmit timeout is detected
1808 * dev pointer to network device structure
1810 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1812 SLMP_INFO *info = dev_to_port(dev);
1813 unsigned long flags;
1815 if (debug_level >= DEBUG_LEVEL_INFO)
1816 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1818 dev->stats.tx_errors++;
1819 dev->stats.tx_aborted_errors++;
1821 spin_lock_irqsave(&info->lock,flags);
1823 spin_unlock_irqrestore(&info->lock,flags);
1825 netif_wake_queue(dev);
1829 * called by device driver when transmit completes
1830 * reenable network layer transmit if stopped
1832 * info pointer to device instance information
1834 static void hdlcdev_tx_done(SLMP_INFO *info)
1836 if (netif_queue_stopped(info->netdev))
1837 netif_wake_queue(info->netdev);
1841 * called by device driver when frame received
1842 * pass frame to network layer
1844 * info pointer to device instance information
1845 * buf pointer to buffer contianing frame data
1846 * size count of data bytes in buf
1848 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1850 struct sk_buff *skb = dev_alloc_skb(size);
1851 struct net_device *dev = info->netdev;
1853 if (debug_level >= DEBUG_LEVEL_INFO)
1854 printk("hdlcdev_rx(%s)\n",dev->name);
1857 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1859 dev->stats.rx_dropped++;
1863 skb_put_data(skb, buf, size);
1865 skb->protocol = hdlc_type_trans(skb, dev);
1867 dev->stats.rx_packets++;
1868 dev->stats.rx_bytes += size;
1873 static const struct net_device_ops hdlcdev_ops = {
1874 .ndo_open = hdlcdev_open,
1875 .ndo_stop = hdlcdev_close,
1876 .ndo_start_xmit = hdlc_start_xmit,
1877 .ndo_do_ioctl = hdlcdev_ioctl,
1878 .ndo_tx_timeout = hdlcdev_tx_timeout,
1882 * called by device driver when adding device instance
1883 * do generic HDLC initialization
1885 * info pointer to device instance information
1887 * returns 0 if success, otherwise error code
1889 static int hdlcdev_init(SLMP_INFO *info)
1892 struct net_device *dev;
1895 /* allocate and initialize network and HDLC layer objects */
1897 dev = alloc_hdlcdev(info);
1899 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1903 /* for network layer reporting purposes only */
1904 dev->mem_start = info->phys_sca_base;
1905 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1906 dev->irq = info->irq_level;
1908 /* network layer callbacks and settings */
1909 dev->netdev_ops = &hdlcdev_ops;
1910 dev->watchdog_timeo = 10 * HZ;
1911 dev->tx_queue_len = 50;
1913 /* generic HDLC layer callbacks and settings */
1914 hdlc = dev_to_hdlc(dev);
1915 hdlc->attach = hdlcdev_attach;
1916 hdlc->xmit = hdlcdev_xmit;
1918 /* register objects with HDLC layer */
1919 rc = register_hdlc_device(dev);
1921 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1931 * called by device driver when removing device instance
1932 * do generic HDLC cleanup
1934 * info pointer to device instance information
1936 static void hdlcdev_exit(SLMP_INFO *info)
1938 unregister_hdlc_device(info->netdev);
1939 free_netdev(info->netdev);
1940 info->netdev = NULL;
1943 #endif /* CONFIG_HDLC */
1946 /* Return next bottom half action to perform.
1947 * Return Value: BH action code or 0 if nothing to do.
1949 static int bh_action(SLMP_INFO *info)
1951 unsigned long flags;
1954 spin_lock_irqsave(&info->lock,flags);
1956 if (info->pending_bh & BH_RECEIVE) {
1957 info->pending_bh &= ~BH_RECEIVE;
1959 } else if (info->pending_bh & BH_TRANSMIT) {
1960 info->pending_bh &= ~BH_TRANSMIT;
1962 } else if (info->pending_bh & BH_STATUS) {
1963 info->pending_bh &= ~BH_STATUS;
1968 /* Mark BH routine as complete */
1969 info->bh_running = false;
1970 info->bh_requested = false;
1973 spin_unlock_irqrestore(&info->lock,flags);
1978 /* Perform bottom half processing of work items queued by ISR.
1980 static void bh_handler(struct work_struct *work)
1982 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1985 if ( debug_level >= DEBUG_LEVEL_BH )
1986 printk( "%s(%d):%s bh_handler() entry\n",
1987 __FILE__,__LINE__,info->device_name);
1989 info->bh_running = true;
1991 while((action = bh_action(info)) != 0) {
1993 /* Process work item */
1994 if ( debug_level >= DEBUG_LEVEL_BH )
1995 printk( "%s(%d):%s bh_handler() work item action=%d\n",
1996 __FILE__,__LINE__,info->device_name, action);
2010 /* unknown work item ID */
2011 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2012 __FILE__,__LINE__,info->device_name,action);
2017 if ( debug_level >= DEBUG_LEVEL_BH )
2018 printk( "%s(%d):%s bh_handler() exit\n",
2019 __FILE__,__LINE__,info->device_name);
2022 static void bh_receive(SLMP_INFO *info)
2024 if ( debug_level >= DEBUG_LEVEL_BH )
2025 printk( "%s(%d):%s bh_receive()\n",
2026 __FILE__,__LINE__,info->device_name);
2028 while( rx_get_frame(info) );
2031 static void bh_transmit(SLMP_INFO *info)
2033 struct tty_struct *tty = info->port.tty;
2035 if ( debug_level >= DEBUG_LEVEL_BH )
2036 printk( "%s(%d):%s bh_transmit() entry\n",
2037 __FILE__,__LINE__,info->device_name);
2043 static void bh_status(SLMP_INFO *info)
2045 if ( debug_level >= DEBUG_LEVEL_BH )
2046 printk( "%s(%d):%s bh_status() entry\n",
2047 __FILE__,__LINE__,info->device_name);
2049 info->ri_chkcount = 0;
2050 info->dsr_chkcount = 0;
2051 info->dcd_chkcount = 0;
2052 info->cts_chkcount = 0;
2055 static void isr_timer(SLMP_INFO * info)
2057 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2059 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2060 write_reg(info, IER2, 0);
2062 /* TMCS, Timer Control/Status Register
2064 * 07 CMF, Compare match flag (read only) 1=match
2065 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2066 * 05 Reserved, must be 0
2067 * 04 TME, Timer Enable
2068 * 03..00 Reserved, must be 0
2072 write_reg(info, (unsigned char)(timer + TMCS), 0);
2074 info->irq_occurred = true;
2076 if ( debug_level >= DEBUG_LEVEL_ISR )
2077 printk("%s(%d):%s isr_timer()\n",
2078 __FILE__,__LINE__,info->device_name);
2081 static void isr_rxint(SLMP_INFO * info)
2083 struct tty_struct *tty = info->port.tty;
2084 struct mgsl_icount *icount = &info->icount;
2085 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2086 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2088 /* clear status bits */
2090 write_reg(info, SR1, status);
2093 write_reg(info, SR2, status2);
2095 if ( debug_level >= DEBUG_LEVEL_ISR )
2096 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2097 __FILE__,__LINE__,info->device_name,status,status2);
2099 if (info->params.mode == MGSL_MODE_ASYNC) {
2100 if (status & BRKD) {
2103 /* process break detection if tty control
2104 * is not set to ignore it
2106 if (!(status & info->ignore_status_mask1)) {
2107 if (info->read_status_mask1 & BRKD) {
2108 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2109 if (tty && (info->port.flags & ASYNC_SAK))
2116 if (status & (FLGD|IDLD)) {
2118 info->icount.exithunt++;
2119 else if (status & IDLD)
2120 info->icount.rxidle++;
2121 wake_up_interruptible(&info->event_wait_q);
2125 if (status & CDCD) {
2126 /* simulate a common modem status change interrupt
2129 get_signals( info );
2131 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2136 * handle async rx data interrupts
2138 static void isr_rxrdy(SLMP_INFO * info)
2141 unsigned char DataByte;
2142 struct mgsl_icount *icount = &info->icount;
2144 if ( debug_level >= DEBUG_LEVEL_ISR )
2145 printk("%s(%d):%s isr_rxrdy\n",
2146 __FILE__,__LINE__,info->device_name);
2148 while((status = read_reg(info,CST0)) & BIT0)
2152 DataByte = read_reg(info,TRB);
2156 if ( status & (PE + FRME + OVRN) ) {
2157 printk("%s(%d):%s rxerr=%04X\n",
2158 __FILE__,__LINE__,info->device_name,status);
2160 /* update error statistics */
2163 else if (status & FRME)
2165 else if (status & OVRN)
2168 /* discard char if tty control flags say so */
2169 if (status & info->ignore_status_mask2)
2172 status &= info->read_status_mask2;
2176 else if (status & FRME)
2178 if (status & OVRN) {
2179 /* Overrun is special, since it's
2180 * reported immediately, and doesn't
2181 * affect the current character
2185 } /* end of if (error) */
2187 tty_insert_flip_char(&info->port, DataByte, flag);
2189 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2192 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2193 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2194 __FILE__,__LINE__,info->device_name,
2195 icount->rx,icount->brk,icount->parity,
2196 icount->frame,icount->overrun);
2199 tty_flip_buffer_push(&info->port);
2202 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2204 if ( debug_level >= DEBUG_LEVEL_ISR )
2205 printk("%s(%d):%s isr_txeom status=%02x\n",
2206 __FILE__,__LINE__,info->device_name,status);
2208 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2209 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2210 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2212 if (status & UDRN) {
2213 write_reg(info, CMD, TXRESET);
2214 write_reg(info, CMD, TXENABLE);
2216 write_reg(info, CMD, TXBUFCLR);
2218 /* disable and clear tx interrupts */
2219 info->ie0_value &= ~TXRDYE;
2220 info->ie1_value &= ~(IDLE + UDRN);
2221 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2222 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2224 if ( info->tx_active ) {
2225 if (info->params.mode != MGSL_MODE_ASYNC) {
2227 info->icount.txunder++;
2228 else if (status & IDLE)
2229 info->icount.txok++;
2232 info->tx_active = false;
2233 info->tx_count = info->tx_put = info->tx_get = 0;
2235 del_timer(&info->tx_timer);
2237 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2238 info->serial_signals &= ~SerialSignal_RTS;
2239 info->drop_rts_on_tx_done = false;
2243 #if SYNCLINK_GENERIC_HDLC
2245 hdlcdev_tx_done(info);
2249 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2253 info->pending_bh |= BH_TRANSMIT;
2260 * handle tx status interrupts
2262 static void isr_txint(SLMP_INFO * info)
2264 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2266 /* clear status bits */
2267 write_reg(info, SR1, status);
2269 if ( debug_level >= DEBUG_LEVEL_ISR )
2270 printk("%s(%d):%s isr_txint status=%02x\n",
2271 __FILE__,__LINE__,info->device_name,status);
2273 if (status & (UDRN + IDLE))
2274 isr_txeom(info, status);
2276 if (status & CCTS) {
2277 /* simulate a common modem status change interrupt
2280 get_signals( info );
2282 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2288 * handle async tx data interrupts
2290 static void isr_txrdy(SLMP_INFO * info)
2292 if ( debug_level >= DEBUG_LEVEL_ISR )
2293 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2294 __FILE__,__LINE__,info->device_name,info->tx_count);
2296 if (info->params.mode != MGSL_MODE_ASYNC) {
2297 /* disable TXRDY IRQ, enable IDLE IRQ */
2298 info->ie0_value &= ~TXRDYE;
2299 info->ie1_value |= IDLE;
2300 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2304 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2309 if ( info->tx_count )
2310 tx_load_fifo( info );
2312 info->tx_active = false;
2313 info->ie0_value &= ~TXRDYE;
2314 write_reg(info, IE0, info->ie0_value);
2317 if (info->tx_count < WAKEUP_CHARS)
2318 info->pending_bh |= BH_TRANSMIT;
2321 static void isr_rxdmaok(SLMP_INFO * info)
2323 /* BIT7 = EOT (end of transfer)
2324 * BIT6 = EOM (end of message/frame)
2326 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2328 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2329 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2331 if ( debug_level >= DEBUG_LEVEL_ISR )
2332 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2333 __FILE__,__LINE__,info->device_name,status);
2335 info->pending_bh |= BH_RECEIVE;
2338 static void isr_rxdmaerror(SLMP_INFO * info)
2340 /* BIT5 = BOF (buffer overflow)
2341 * BIT4 = COF (counter overflow)
2343 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2345 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2346 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2348 if ( debug_level >= DEBUG_LEVEL_ISR )
2349 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2350 __FILE__,__LINE__,info->device_name,status);
2352 info->rx_overflow = true;
2353 info->pending_bh |= BH_RECEIVE;
2356 static void isr_txdmaok(SLMP_INFO * info)
2358 unsigned char status_reg1 = read_reg(info, SR1);
2360 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2361 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2362 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2364 if ( debug_level >= DEBUG_LEVEL_ISR )
2365 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2366 __FILE__,__LINE__,info->device_name,status_reg1);
2368 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2369 write_reg16(info, TRC0, 0);
2370 info->ie0_value |= TXRDYE;
2371 write_reg(info, IE0, info->ie0_value);
2374 static void isr_txdmaerror(SLMP_INFO * info)
2376 /* BIT5 = BOF (buffer overflow)
2377 * BIT4 = COF (counter overflow)
2379 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2381 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2382 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2384 if ( debug_level >= DEBUG_LEVEL_ISR )
2385 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2386 __FILE__,__LINE__,info->device_name,status);
2389 /* handle input serial signal changes
2391 static void isr_io_pin( SLMP_INFO *info, u16 status )
2393 struct mgsl_icount *icount;
2395 if ( debug_level >= DEBUG_LEVEL_ISR )
2396 printk("%s(%d):isr_io_pin status=%04X\n",
2397 __FILE__,__LINE__,status);
2399 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2400 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2401 icount = &info->icount;
2402 /* update input line counters */
2403 if (status & MISCSTATUS_RI_LATCHED) {
2405 if ( status & SerialSignal_RI )
2406 info->input_signal_events.ri_up++;
2408 info->input_signal_events.ri_down++;
2410 if (status & MISCSTATUS_DSR_LATCHED) {
2412 if ( status & SerialSignal_DSR )
2413 info->input_signal_events.dsr_up++;
2415 info->input_signal_events.dsr_down++;
2417 if (status & MISCSTATUS_DCD_LATCHED) {
2418 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2419 info->ie1_value &= ~CDCD;
2420 write_reg(info, IE1, info->ie1_value);
2423 if (status & SerialSignal_DCD) {
2424 info->input_signal_events.dcd_up++;
2426 info->input_signal_events.dcd_down++;
2427 #if SYNCLINK_GENERIC_HDLC
2428 if (info->netcount) {
2429 if (status & SerialSignal_DCD)
2430 netif_carrier_on(info->netdev);
2432 netif_carrier_off(info->netdev);
2436 if (status & MISCSTATUS_CTS_LATCHED)
2438 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2439 info->ie1_value &= ~CCTS;
2440 write_reg(info, IE1, info->ie1_value);
2443 if ( status & SerialSignal_CTS )
2444 info->input_signal_events.cts_up++;
2446 info->input_signal_events.cts_down++;
2448 wake_up_interruptible(&info->status_event_wait_q);
2449 wake_up_interruptible(&info->event_wait_q);
2451 if (tty_port_check_carrier(&info->port) &&
2452 (status & MISCSTATUS_DCD_LATCHED) ) {
2453 if ( debug_level >= DEBUG_LEVEL_ISR )
2454 printk("%s CD now %s...", info->device_name,
2455 (status & SerialSignal_DCD) ? "on" : "off");
2456 if (status & SerialSignal_DCD)
2457 wake_up_interruptible(&info->port.open_wait);
2459 if ( debug_level >= DEBUG_LEVEL_ISR )
2460 printk("doing serial hangup...");
2462 tty_hangup(info->port.tty);
2466 if (tty_port_cts_enabled(&info->port) &&
2467 (status & MISCSTATUS_CTS_LATCHED) ) {
2468 if ( info->port.tty ) {
2469 if (info->port.tty->hw_stopped) {
2470 if (status & SerialSignal_CTS) {
2471 if ( debug_level >= DEBUG_LEVEL_ISR )
2472 printk("CTS tx start...");
2473 info->port.tty->hw_stopped = 0;
2475 info->pending_bh |= BH_TRANSMIT;
2479 if (!(status & SerialSignal_CTS)) {
2480 if ( debug_level >= DEBUG_LEVEL_ISR )
2481 printk("CTS tx stop...");
2482 info->port.tty->hw_stopped = 1;
2490 info->pending_bh |= BH_STATUS;
2493 /* Interrupt service routine entry point.
2496 * irq interrupt number that caused interrupt
2497 * dev_id device ID supplied during interrupt registration
2498 * regs interrupted processor context
2500 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2502 SLMP_INFO *info = dev_id;
2503 unsigned char status, status0, status1=0;
2504 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2505 unsigned char timerstatus0, timerstatus1=0;
2506 unsigned char shift;
2510 if ( debug_level >= DEBUG_LEVEL_ISR )
2511 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2512 __FILE__, __LINE__, info->irq_level);
2514 spin_lock(&info->lock);
2518 /* get status for SCA0 (ports 0-1) */
2519 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2520 status0 = (unsigned char)tmp;
2521 dmastatus0 = (unsigned char)(tmp>>8);
2522 timerstatus0 = read_reg(info, ISR2);
2524 if ( debug_level >= DEBUG_LEVEL_ISR )
2525 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2526 __FILE__, __LINE__, info->device_name,
2527 status0, dmastatus0, timerstatus0);
2529 if (info->port_count == 4) {
2530 /* get status for SCA1 (ports 2-3) */
2531 tmp = read_reg16(info->port_array[2], ISR0);
2532 status1 = (unsigned char)tmp;
2533 dmastatus1 = (unsigned char)(tmp>>8);
2534 timerstatus1 = read_reg(info->port_array[2], ISR2);
2536 if ( debug_level >= DEBUG_LEVEL_ISR )
2537 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2538 __FILE__,__LINE__,info->device_name,
2539 status1,dmastatus1,timerstatus1);
2542 if (!status0 && !dmastatus0 && !timerstatus0 &&
2543 !status1 && !dmastatus1 && !timerstatus1)
2546 for(i=0; i < info->port_count ; i++) {
2547 if (info->port_array[i] == NULL)
2551 dmastatus = dmastatus0;
2554 dmastatus = dmastatus1;
2557 shift = i & 1 ? 4 :0;
2559 if (status & BIT0 << shift)
2560 isr_rxrdy(info->port_array[i]);
2561 if (status & BIT1 << shift)
2562 isr_txrdy(info->port_array[i]);
2563 if (status & BIT2 << shift)
2564 isr_rxint(info->port_array[i]);
2565 if (status & BIT3 << shift)
2566 isr_txint(info->port_array[i]);
2568 if (dmastatus & BIT0 << shift)
2569 isr_rxdmaerror(info->port_array[i]);
2570 if (dmastatus & BIT1 << shift)
2571 isr_rxdmaok(info->port_array[i]);
2572 if (dmastatus & BIT2 << shift)
2573 isr_txdmaerror(info->port_array[i]);
2574 if (dmastatus & BIT3 << shift)
2575 isr_txdmaok(info->port_array[i]);
2578 if (timerstatus0 & (BIT5 | BIT4))
2579 isr_timer(info->port_array[0]);
2580 if (timerstatus0 & (BIT7 | BIT6))
2581 isr_timer(info->port_array[1]);
2582 if (timerstatus1 & (BIT5 | BIT4))
2583 isr_timer(info->port_array[2]);
2584 if (timerstatus1 & (BIT7 | BIT6))
2585 isr_timer(info->port_array[3]);
2588 for(i=0; i < info->port_count ; i++) {
2589 SLMP_INFO * port = info->port_array[i];
2591 /* Request bottom half processing if there's something
2592 * for it to do and the bh is not already running.
2594 * Note: startup adapter diags require interrupts.
2595 * do not request bottom half processing if the
2596 * device is not open in a normal mode.
2598 if ( port && (port->port.count || port->netcount) &&
2599 port->pending_bh && !port->bh_running &&
2600 !port->bh_requested ) {
2601 if ( debug_level >= DEBUG_LEVEL_ISR )
2602 printk("%s(%d):%s queueing bh task.\n",
2603 __FILE__,__LINE__,port->device_name);
2604 schedule_work(&port->task);
2605 port->bh_requested = true;
2609 spin_unlock(&info->lock);
2611 if ( debug_level >= DEBUG_LEVEL_ISR )
2612 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2613 __FILE__, __LINE__, info->irq_level);
2617 /* Initialize and start device.
2619 static int startup(SLMP_INFO * info)
2621 if ( debug_level >= DEBUG_LEVEL_INFO )
2622 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2624 if (tty_port_initialized(&info->port))
2627 if (!info->tx_buf) {
2628 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2629 if (!info->tx_buf) {
2630 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2631 __FILE__,__LINE__,info->device_name);
2636 info->pending_bh = 0;
2638 memset(&info->icount, 0, sizeof(info->icount));
2640 /* program hardware for current parameters */
2643 change_params(info);
2645 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2648 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2650 tty_port_set_initialized(&info->port, 1);
2655 /* Called by close() and hangup() to shutdown hardware
2657 static void shutdown(SLMP_INFO * info)
2659 unsigned long flags;
2661 if (!tty_port_initialized(&info->port))
2664 if (debug_level >= DEBUG_LEVEL_INFO)
2665 printk("%s(%d):%s synclinkmp_shutdown()\n",
2666 __FILE__,__LINE__, info->device_name );
2668 /* clear status wait queue because status changes */
2669 /* can't happen after shutting down the hardware */
2670 wake_up_interruptible(&info->status_event_wait_q);
2671 wake_up_interruptible(&info->event_wait_q);
2673 del_timer(&info->tx_timer);
2674 del_timer(&info->status_timer);
2676 kfree(info->tx_buf);
2677 info->tx_buf = NULL;
2679 spin_lock_irqsave(&info->lock,flags);
2683 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2684 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2688 spin_unlock_irqrestore(&info->lock,flags);
2691 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2693 tty_port_set_initialized(&info->port, 0);
2696 static void program_hw(SLMP_INFO *info)
2698 unsigned long flags;
2700 spin_lock_irqsave(&info->lock,flags);
2705 info->tx_count = info->tx_put = info->tx_get = 0;
2707 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2714 info->dcd_chkcount = 0;
2715 info->cts_chkcount = 0;
2716 info->ri_chkcount = 0;
2717 info->dsr_chkcount = 0;
2719 info->ie1_value |= (CDCD|CCTS);
2720 write_reg(info, IE1, info->ie1_value);
2724 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2727 spin_unlock_irqrestore(&info->lock,flags);
2730 /* Reconfigure adapter based on new parameters
2732 static void change_params(SLMP_INFO *info)
2737 if (!info->port.tty)
2740 if (debug_level >= DEBUG_LEVEL_INFO)
2741 printk("%s(%d):%s change_params()\n",
2742 __FILE__,__LINE__, info->device_name );
2744 cflag = info->port.tty->termios.c_cflag;
2746 /* if B0 rate (hangup) specified then negate RTS and DTR */
2747 /* otherwise assert RTS and DTR */
2749 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2751 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2753 /* byte size and parity */
2755 switch (cflag & CSIZE) {
2756 case CS5: info->params.data_bits = 5; break;
2757 case CS6: info->params.data_bits = 6; break;
2758 case CS7: info->params.data_bits = 7; break;
2759 case CS8: info->params.data_bits = 8; break;
2760 /* Never happens, but GCC is too dumb to figure it out */
2761 default: info->params.data_bits = 7; break;
2765 info->params.stop_bits = 2;
2767 info->params.stop_bits = 1;
2769 info->params.parity = ASYNC_PARITY_NONE;
2770 if (cflag & PARENB) {
2772 info->params.parity = ASYNC_PARITY_ODD;
2774 info->params.parity = ASYNC_PARITY_EVEN;
2777 info->params.parity = ASYNC_PARITY_SPACE;
2781 /* calculate number of jiffies to transmit a full
2782 * FIFO (32 bytes) at specified data rate
2784 bits_per_char = info->params.data_bits +
2785 info->params.stop_bits + 1;
2787 /* if port data rate is set to 460800 or less then
2788 * allow tty settings to override, otherwise keep the
2789 * current data rate.
2791 if (info->params.data_rate <= 460800) {
2792 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2795 if ( info->params.data_rate ) {
2796 info->timeout = (32*HZ*bits_per_char) /
2797 info->params.data_rate;
2799 info->timeout += HZ/50; /* Add .02 seconds of slop */
2801 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2802 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2804 /* process tty input control flags */
2806 info->read_status_mask2 = OVRN;
2807 if (I_INPCK(info->port.tty))
2808 info->read_status_mask2 |= PE | FRME;
2809 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2810 info->read_status_mask1 |= BRKD;
2811 if (I_IGNPAR(info->port.tty))
2812 info->ignore_status_mask2 |= PE | FRME;
2813 if (I_IGNBRK(info->port.tty)) {
2814 info->ignore_status_mask1 |= BRKD;
2815 /* If ignoring parity and break indicators, ignore
2816 * overruns too. (For real raw support).
2818 if (I_IGNPAR(info->port.tty))
2819 info->ignore_status_mask2 |= OVRN;
2825 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2829 if (debug_level >= DEBUG_LEVEL_INFO)
2830 printk("%s(%d):%s get_params()\n",
2831 __FILE__,__LINE__, info->device_name);
2834 memset(&info->icount, 0, sizeof(info->icount));
2836 mutex_lock(&info->port.mutex);
2837 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2838 mutex_unlock(&info->port.mutex);
2846 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2849 if (debug_level >= DEBUG_LEVEL_INFO)
2850 printk("%s(%d):%s get_params()\n",
2851 __FILE__,__LINE__, info->device_name);
2853 mutex_lock(&info->port.mutex);
2854 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2855 mutex_unlock(&info->port.mutex);
2857 if ( debug_level >= DEBUG_LEVEL_INFO )
2858 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2859 __FILE__,__LINE__,info->device_name);
2866 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2868 unsigned long flags;
2869 MGSL_PARAMS tmp_params;
2872 if (debug_level >= DEBUG_LEVEL_INFO)
2873 printk("%s(%d):%s set_params\n",
2874 __FILE__,__LINE__,info->device_name );
2875 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2877 if ( debug_level >= DEBUG_LEVEL_INFO )
2878 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2879 __FILE__,__LINE__,info->device_name);
2883 mutex_lock(&info->port.mutex);
2884 spin_lock_irqsave(&info->lock,flags);
2885 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2886 spin_unlock_irqrestore(&info->lock,flags);
2888 change_params(info);
2889 mutex_unlock(&info->port.mutex);
2894 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2898 if (debug_level >= DEBUG_LEVEL_INFO)
2899 printk("%s(%d):%s get_txidle()=%d\n",
2900 __FILE__,__LINE__, info->device_name, info->idle_mode);
2902 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2904 if ( debug_level >= DEBUG_LEVEL_INFO )
2905 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2906 __FILE__,__LINE__,info->device_name);
2913 static int set_txidle(SLMP_INFO * info, int idle_mode)
2915 unsigned long flags;
2917 if (debug_level >= DEBUG_LEVEL_INFO)
2918 printk("%s(%d):%s set_txidle(%d)\n",
2919 __FILE__,__LINE__,info->device_name, idle_mode );
2921 spin_lock_irqsave(&info->lock,flags);
2922 info->idle_mode = idle_mode;
2923 tx_set_idle( info );
2924 spin_unlock_irqrestore(&info->lock,flags);
2928 static int tx_enable(SLMP_INFO * info, int enable)
2930 unsigned long flags;
2932 if (debug_level >= DEBUG_LEVEL_INFO)
2933 printk("%s(%d):%s tx_enable(%d)\n",
2934 __FILE__,__LINE__,info->device_name, enable);
2936 spin_lock_irqsave(&info->lock,flags);
2938 if ( !info->tx_enabled ) {
2942 if ( info->tx_enabled )
2945 spin_unlock_irqrestore(&info->lock,flags);
2949 /* abort send HDLC frame
2951 static int tx_abort(SLMP_INFO * info)
2953 unsigned long flags;
2955 if (debug_level >= DEBUG_LEVEL_INFO)
2956 printk("%s(%d):%s tx_abort()\n",
2957 __FILE__,__LINE__,info->device_name);
2959 spin_lock_irqsave(&info->lock,flags);
2960 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2961 info->ie1_value &= ~UDRN;
2962 info->ie1_value |= IDLE;
2963 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2964 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2966 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2967 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2969 write_reg(info, CMD, TXABORT);
2971 spin_unlock_irqrestore(&info->lock,flags);
2975 static int rx_enable(SLMP_INFO * info, int enable)
2977 unsigned long flags;
2979 if (debug_level >= DEBUG_LEVEL_INFO)
2980 printk("%s(%d):%s rx_enable(%d)\n",
2981 __FILE__,__LINE__,info->device_name,enable);
2983 spin_lock_irqsave(&info->lock,flags);
2985 if ( !info->rx_enabled )
2988 if ( info->rx_enabled )
2991 spin_unlock_irqrestore(&info->lock,flags);
2995 /* wait for specified event to occur
2997 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2999 unsigned long flags;
3002 struct mgsl_icount cprev, cnow;
3005 struct _input_signal_events oldsigs, newsigs;
3006 DECLARE_WAITQUEUE(wait, current);
3008 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3013 if (debug_level >= DEBUG_LEVEL_INFO)
3014 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3015 __FILE__,__LINE__,info->device_name,mask);
3017 spin_lock_irqsave(&info->lock,flags);
3019 /* return immediately if state matches requested events */
3021 s = info->serial_signals;
3024 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3025 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3026 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3027 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3029 spin_unlock_irqrestore(&info->lock,flags);
3033 /* save current irq counts */
3034 cprev = info->icount;
3035 oldsigs = info->input_signal_events;
3037 /* enable hunt and idle irqs if needed */
3038 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3039 unsigned char oldval = info->ie1_value;
3040 unsigned char newval = oldval +
3041 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3042 (mask & MgslEvent_IdleReceived ? IDLD:0);
3043 if ( oldval != newval ) {
3044 info->ie1_value = newval;
3045 write_reg(info, IE1, info->ie1_value);
3049 set_current_state(TASK_INTERRUPTIBLE);
3050 add_wait_queue(&info->event_wait_q, &wait);
3052 spin_unlock_irqrestore(&info->lock,flags);
3056 if (signal_pending(current)) {
3061 /* get current irq counts */
3062 spin_lock_irqsave(&info->lock,flags);
3063 cnow = info->icount;
3064 newsigs = info->input_signal_events;
3065 set_current_state(TASK_INTERRUPTIBLE);
3066 spin_unlock_irqrestore(&info->lock,flags);
3068 /* if no change, wait aborted for some reason */
3069 if (newsigs.dsr_up == oldsigs.dsr_up &&
3070 newsigs.dsr_down == oldsigs.dsr_down &&
3071 newsigs.dcd_up == oldsigs.dcd_up &&
3072 newsigs.dcd_down == oldsigs.dcd_down &&
3073 newsigs.cts_up == oldsigs.cts_up &&
3074 newsigs.cts_down == oldsigs.cts_down &&
3075 newsigs.ri_up == oldsigs.ri_up &&
3076 newsigs.ri_down == oldsigs.ri_down &&
3077 cnow.exithunt == cprev.exithunt &&
3078 cnow.rxidle == cprev.rxidle) {
3084 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3085 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3086 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3087 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3088 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3089 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3090 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3091 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3092 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3093 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3101 remove_wait_queue(&info->event_wait_q, &wait);
3102 set_current_state(TASK_RUNNING);
3105 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3106 spin_lock_irqsave(&info->lock,flags);
3107 if (!waitqueue_active(&info->event_wait_q)) {
3108 /* disable enable exit hunt mode/idle rcvd IRQs */
3109 info->ie1_value &= ~(FLGD|IDLD);
3110 write_reg(info, IE1, info->ie1_value);
3112 spin_unlock_irqrestore(&info->lock,flags);
3116 PUT_USER(rc, events, mask_ptr);
3121 static int modem_input_wait(SLMP_INFO *info,int arg)
3123 unsigned long flags;
3125 struct mgsl_icount cprev, cnow;
3126 DECLARE_WAITQUEUE(wait, current);
3128 /* save current irq counts */
3129 spin_lock_irqsave(&info->lock,flags);
3130 cprev = info->icount;
3131 add_wait_queue(&info->status_event_wait_q, &wait);
3132 set_current_state(TASK_INTERRUPTIBLE);
3133 spin_unlock_irqrestore(&info->lock,flags);
3137 if (signal_pending(current)) {
3142 /* get new irq counts */
3143 spin_lock_irqsave(&info->lock,flags);
3144 cnow = info->icount;
3145 set_current_state(TASK_INTERRUPTIBLE);
3146 spin_unlock_irqrestore(&info->lock,flags);
3148 /* if no change, wait aborted for some reason */
3149 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3150 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3155 /* check for change in caller specified modem input */
3156 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3157 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3158 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3159 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3166 remove_wait_queue(&info->status_event_wait_q, &wait);
3167 set_current_state(TASK_RUNNING);
3171 /* return the state of the serial control and status signals
3173 static int tiocmget(struct tty_struct *tty)
3175 SLMP_INFO *info = tty->driver_data;
3176 unsigned int result;
3177 unsigned long flags;
3179 spin_lock_irqsave(&info->lock,flags);
3181 spin_unlock_irqrestore(&info->lock,flags);
3183 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3184 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3185 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3186 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3187 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3188 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3190 if (debug_level >= DEBUG_LEVEL_INFO)
3191 printk("%s(%d):%s tiocmget() value=%08X\n",
3192 __FILE__,__LINE__, info->device_name, result );
3196 /* set modem control signals (DTR/RTS)
3198 static int tiocmset(struct tty_struct *tty,
3199 unsigned int set, unsigned int clear)
3201 SLMP_INFO *info = tty->driver_data;
3202 unsigned long flags;
3204 if (debug_level >= DEBUG_LEVEL_INFO)
3205 printk("%s(%d):%s tiocmset(%x,%x)\n",
3206 __FILE__,__LINE__,info->device_name, set, clear);
3208 if (set & TIOCM_RTS)
3209 info->serial_signals |= SerialSignal_RTS;
3210 if (set & TIOCM_DTR)
3211 info->serial_signals |= SerialSignal_DTR;
3212 if (clear & TIOCM_RTS)
3213 info->serial_signals &= ~SerialSignal_RTS;
3214 if (clear & TIOCM_DTR)
3215 info->serial_signals &= ~SerialSignal_DTR;
3217 spin_lock_irqsave(&info->lock,flags);
3219 spin_unlock_irqrestore(&info->lock,flags);
3224 static int carrier_raised(struct tty_port *port)
3226 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3227 unsigned long flags;
3229 spin_lock_irqsave(&info->lock,flags);
3231 spin_unlock_irqrestore(&info->lock,flags);
3233 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3236 static void dtr_rts(struct tty_port *port, int on)
3238 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3239 unsigned long flags;
3241 spin_lock_irqsave(&info->lock,flags);
3243 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3245 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3247 spin_unlock_irqrestore(&info->lock,flags);
3250 /* Block the current process until the specified port is ready to open.
3252 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3255 DECLARE_WAITQUEUE(wait, current);
3257 bool do_clocal = false;
3258 unsigned long flags;
3260 struct tty_port *port = &info->port;
3262 if (debug_level >= DEBUG_LEVEL_INFO)
3263 printk("%s(%d):%s block_til_ready()\n",
3264 __FILE__,__LINE__, tty->driver->name );
3266 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3267 /* nonblock mode is set or port is not enabled */
3268 /* just verify that callout device is not active */
3269 tty_port_set_active(port, 1);
3276 /* Wait for carrier detect and the line to become
3277 * free (i.e., not in use by the callout). While we are in
3278 * this loop, port->count is dropped by one, so that
3279 * close() knows when to free things. We restore it upon
3280 * exit, either normal or abnormal.
3284 add_wait_queue(&port->open_wait, &wait);
3286 if (debug_level >= DEBUG_LEVEL_INFO)
3287 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3288 __FILE__,__LINE__, tty->driver->name, port->count );
3290 spin_lock_irqsave(&info->lock, flags);
3292 spin_unlock_irqrestore(&info->lock, flags);
3293 port->blocked_open++;
3296 if (C_BAUD(tty) && tty_port_initialized(port))
3297 tty_port_raise_dtr_rts(port);
3299 set_current_state(TASK_INTERRUPTIBLE);
3301 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3302 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3303 -EAGAIN : -ERESTARTSYS;
3307 cd = tty_port_carrier_raised(port);
3308 if (do_clocal || cd)
3311 if (signal_pending(current)) {
3312 retval = -ERESTARTSYS;
3316 if (debug_level >= DEBUG_LEVEL_INFO)
3317 printk("%s(%d):%s block_til_ready() count=%d\n",
3318 __FILE__,__LINE__, tty->driver->name, port->count );
3325 set_current_state(TASK_RUNNING);
3326 remove_wait_queue(&port->open_wait, &wait);
3327 if (!tty_hung_up_p(filp))
3329 port->blocked_open--;
3331 if (debug_level >= DEBUG_LEVEL_INFO)
3332 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3333 __FILE__,__LINE__, tty->driver->name, port->count );
3336 tty_port_set_active(port, 1);
3341 static int alloc_dma_bufs(SLMP_INFO *info)
3343 unsigned short BuffersPerFrame;
3344 unsigned short BufferCount;
3346 // Force allocation to start at 64K boundary for each port.
3347 // This is necessary because *all* buffer descriptors for a port
3348 // *must* be in the same 64K block. All descriptors on a port
3349 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3350 // into the CBP register.
3351 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3353 /* Calculate the number of DMA buffers necessary to hold the */
3354 /* largest allowable frame size. Note: If the max frame size is */
3355 /* not an even multiple of the DMA buffer size then we need to */
3356 /* round the buffer count per frame up one. */
3358 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3359 if ( info->max_frame_size % SCABUFSIZE )
3362 /* calculate total number of data buffers (SCABUFSIZE) possible
3363 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3364 * for the descriptor list (BUFFERLISTSIZE).
3366 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3368 /* limit number of buffers to maximum amount of descriptors */
3369 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3370 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3372 /* use enough buffers to transmit one max size frame */
3373 info->tx_buf_count = BuffersPerFrame + 1;
3375 /* never use more than half the available buffers for transmit */
3376 if (info->tx_buf_count > (BufferCount/2))
3377 info->tx_buf_count = BufferCount/2;
3379 if (info->tx_buf_count > SCAMAXDESC)
3380 info->tx_buf_count = SCAMAXDESC;
3382 /* use remaining buffers for receive */
3383 info->rx_buf_count = BufferCount - info->tx_buf_count;
3385 if (info->rx_buf_count > SCAMAXDESC)
3386 info->rx_buf_count = SCAMAXDESC;
3388 if ( debug_level >= DEBUG_LEVEL_INFO )
3389 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3390 __FILE__,__LINE__, info->device_name,
3391 info->tx_buf_count,info->rx_buf_count);
3393 if ( alloc_buf_list( info ) < 0 ||
3394 alloc_frame_bufs(info,
3396 info->rx_buf_list_ex,
3397 info->rx_buf_count) < 0 ||
3398 alloc_frame_bufs(info,
3400 info->tx_buf_list_ex,
3401 info->tx_buf_count) < 0 ||
3402 alloc_tmp_rx_buf(info) < 0 ) {
3403 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3404 __FILE__,__LINE__, info->device_name);
3408 rx_reset_buffers( info );
3413 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3415 static int alloc_buf_list(SLMP_INFO *info)
3419 /* build list in adapter shared memory */
3420 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3421 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3422 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3424 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3426 /* Save virtual address pointers to the receive and */
3427 /* transmit buffer lists. (Receive 1st). These pointers will */
3428 /* be used by the processor to access the lists. */
3429 info->rx_buf_list = (SCADESC *)info->buffer_list;
3431 info->tx_buf_list = (SCADESC *)info->buffer_list;
3432 info->tx_buf_list += info->rx_buf_count;
3434 /* Build links for circular buffer entry lists (tx and rx)
3436 * Note: links are physical addresses read by the SCA device
3437 * to determine the next buffer entry to use.
3440 for ( i = 0; i < info->rx_buf_count; i++ ) {
3441 /* calculate and store physical address of this buffer entry */
3442 info->rx_buf_list_ex[i].phys_entry =
3443 info->buffer_list_phys + (i * SCABUFSIZE);
3445 /* calculate and store physical address of */
3446 /* next entry in cirular list of entries */
3447 info->rx_buf_list[i].next = info->buffer_list_phys;
3448 if ( i < info->rx_buf_count - 1 )
3449 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3451 info->rx_buf_list[i].length = SCABUFSIZE;
3454 for ( i = 0; i < info->tx_buf_count; i++ ) {
3455 /* calculate and store physical address of this buffer entry */
3456 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3457 ((info->rx_buf_count + i) * sizeof(SCADESC));
3459 /* calculate and store physical address of */
3460 /* next entry in cirular list of entries */
3462 info->tx_buf_list[i].next = info->buffer_list_phys +
3463 info->rx_buf_count * sizeof(SCADESC);
3465 if ( i < info->tx_buf_count - 1 )
3466 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3472 /* Allocate the frame DMA buffers used by the specified buffer list.
3474 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3477 unsigned long phys_addr;
3479 for ( i = 0; i < count; i++ ) {
3480 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3481 phys_addr = info->port_array[0]->last_mem_alloc;
3482 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3484 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3485 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3491 static void free_dma_bufs(SLMP_INFO *info)
3493 info->buffer_list = NULL;
3494 info->rx_buf_list = NULL;
3495 info->tx_buf_list = NULL;
3498 /* allocate buffer large enough to hold max_frame_size.
3499 * This buffer is used to pass an assembled frame to the line discipline.
3501 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3503 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3504 if (info->tmp_rx_buf == NULL)
3506 /* unused flag buffer to satisfy receive_buf calling interface */
3507 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3508 if (!info->flag_buf) {
3509 kfree(info->tmp_rx_buf);
3510 info->tmp_rx_buf = NULL;
3516 static void free_tmp_rx_buf(SLMP_INFO *info)
3518 kfree(info->tmp_rx_buf);
3519 info->tmp_rx_buf = NULL;
3520 kfree(info->flag_buf);
3521 info->flag_buf = NULL;
3524 static int claim_resources(SLMP_INFO *info)
3526 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3527 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3528 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3529 info->init_error = DiagStatus_AddressConflict;
3533 info->shared_mem_requested = true;
3535 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3536 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3537 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3538 info->init_error = DiagStatus_AddressConflict;
3542 info->lcr_mem_requested = true;
3544 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3545 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3546 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3547 info->init_error = DiagStatus_AddressConflict;
3551 info->sca_base_requested = true;
3553 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3554 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3555 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3556 info->init_error = DiagStatus_AddressConflict;
3560 info->sca_statctrl_requested = true;
3562 info->memory_base = ioremap_nocache(info->phys_memory_base,
3564 if (!info->memory_base) {
3565 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3566 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3567 info->init_error = DiagStatus_CantAssignPciResources;
3571 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3572 if (!info->lcr_base) {
3573 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3574 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3575 info->init_error = DiagStatus_CantAssignPciResources;
3578 info->lcr_base += info->lcr_offset;
3580 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3581 if (!info->sca_base) {
3582 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3583 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3584 info->init_error = DiagStatus_CantAssignPciResources;
3587 info->sca_base += info->sca_offset;
3589 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3591 if (!info->statctrl_base) {
3592 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3593 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3594 info->init_error = DiagStatus_CantAssignPciResources;
3597 info->statctrl_base += info->statctrl_offset;
3599 if ( !memory_test(info) ) {
3600 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3601 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3602 info->init_error = DiagStatus_MemoryError;
3609 release_resources( info );
3613 static void release_resources(SLMP_INFO *info)
3615 if ( debug_level >= DEBUG_LEVEL_INFO )
3616 printk( "%s(%d):%s release_resources() entry\n",
3617 __FILE__,__LINE__,info->device_name );
3619 if ( info->irq_requested ) {
3620 free_irq(info->irq_level, info);
3621 info->irq_requested = false;
3624 if ( info->shared_mem_requested ) {
3625 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3626 info->shared_mem_requested = false;
3628 if ( info->lcr_mem_requested ) {
3629 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3630 info->lcr_mem_requested = false;
3632 if ( info->sca_base_requested ) {
3633 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3634 info->sca_base_requested = false;
3636 if ( info->sca_statctrl_requested ) {
3637 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3638 info->sca_statctrl_requested = false;
3641 if (info->memory_base){
3642 iounmap(info->memory_base);
3643 info->memory_base = NULL;
3646 if (info->sca_base) {
3647 iounmap(info->sca_base - info->sca_offset);
3648 info->sca_base=NULL;
3651 if (info->statctrl_base) {
3652 iounmap(info->statctrl_base - info->statctrl_offset);
3653 info->statctrl_base=NULL;
3656 if (info->lcr_base){
3657 iounmap(info->lcr_base - info->lcr_offset);
3658 info->lcr_base = NULL;
3661 if ( debug_level >= DEBUG_LEVEL_INFO )
3662 printk( "%s(%d):%s release_resources() exit\n",
3663 __FILE__,__LINE__,info->device_name );
3666 /* Add the specified device instance data structure to the
3667 * global linked list of devices and increment the device count.
3669 static int add_device(SLMP_INFO *info)
3671 info->next_device = NULL;
3672 info->line = synclinkmp_device_count;
3673 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3675 if (info->line < MAX_DEVICES) {
3676 if (maxframe[info->line])
3677 info->max_frame_size = maxframe[info->line];
3680 synclinkmp_device_count++;
3682 if ( !synclinkmp_device_list )
3683 synclinkmp_device_list = info;
3685 SLMP_INFO *current_dev = synclinkmp_device_list;
3686 while( current_dev->next_device )
3687 current_dev = current_dev->next_device;
3688 current_dev->next_device = info;
3691 if ( info->max_frame_size < 4096 )
3692 info->max_frame_size = 4096;
3693 else if ( info->max_frame_size > 65535 )
3694 info->max_frame_size = 65535;
3696 printk( "SyncLink MultiPort %s: "
3697 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3699 info->phys_sca_base,
3700 info->phys_memory_base,
3701 info->phys_statctrl_base,
3702 info->phys_lcr_base,
3704 info->max_frame_size );
3706 #if SYNCLINK_GENERIC_HDLC
3707 return hdlcdev_init(info);
3713 static const struct tty_port_operations port_ops = {
3714 .carrier_raised = carrier_raised,
3718 /* Allocate and initialize a device instance structure
3720 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3722 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3726 info = kzalloc(sizeof(SLMP_INFO),
3730 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3731 __FILE__,__LINE__, adapter_num, port_num);
3733 tty_port_init(&info->port);
3734 info->port.ops = &port_ops;
3735 info->magic = MGSL_MAGIC;
3736 INIT_WORK(&info->task, bh_handler);
3737 info->max_frame_size = 4096;
3738 info->port.close_delay = 5*HZ/10;
3739 info->port.closing_wait = 30*HZ;
3740 init_waitqueue_head(&info->status_event_wait_q);
3741 init_waitqueue_head(&info->event_wait_q);
3742 spin_lock_init(&info->netlock);
3743 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3744 info->idle_mode = HDLC_TXIDLE_FLAGS;
3745 info->adapter_num = adapter_num;
3746 info->port_num = port_num;
3748 /* Copy configuration info to device instance data */
3749 info->irq_level = pdev->irq;
3750 info->phys_lcr_base = pci_resource_start(pdev,0);
3751 info->phys_sca_base = pci_resource_start(pdev,2);
3752 info->phys_memory_base = pci_resource_start(pdev,3);
3753 info->phys_statctrl_base = pci_resource_start(pdev,4);
3755 /* Because veremap only works on page boundaries we must map
3756 * a larger area than is actually implemented for the LCR
3757 * memory range. We map a full page starting at the page boundary.
3759 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3760 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3762 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3763 info->phys_sca_base &= ~(PAGE_SIZE-1);
3765 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3766 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3768 info->bus_type = MGSL_BUS_TYPE_PCI;
3769 info->irq_flags = IRQF_SHARED;
3771 timer_setup(&info->tx_timer, tx_timeout, 0);
3772 timer_setup(&info->status_timer, status_timeout, 0);
3774 /* Store the PCI9050 misc control register value because a flaw
3775 * in the PCI9050 prevents LCR registers from being read if
3776 * BIOS assigns an LCR base address with bit 7 set.
3778 * Only the misc control register is accessed for which only
3779 * write access is needed, so set an initial value and change
3780 * bits to the device instance data as we write the value
3781 * to the actual misc control register.
3783 info->misc_ctrl_value = 0x087e4546;
3785 /* initial port state is unknown - if startup errors
3786 * occur, init_error will be set to indicate the
3787 * problem. Once the port is fully initialized,
3788 * this value will be set to 0 to indicate the
3789 * port is available.
3791 info->init_error = -1;
3797 static int device_init(int adapter_num, struct pci_dev *pdev)
3799 SLMP_INFO *port_array[SCA_MAX_PORTS];
3802 /* allocate device instances for up to SCA_MAX_PORTS devices */
3803 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3804 port_array[port] = alloc_dev(adapter_num,port,pdev);
3805 if( port_array[port] == NULL ) {
3806 for (--port; port >= 0; --port) {
3807 tty_port_destroy(&port_array[port]->port);
3808 kfree(port_array[port]);
3814 /* give copy of port_array to all ports and add to device list */
3815 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3816 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3817 rc = add_device( port_array[port] );
3820 spin_lock_init(&port_array[port]->lock);
3823 /* Allocate and claim adapter resources */
3824 if ( !claim_resources(port_array[0]) ) {
3826 alloc_dma_bufs(port_array[0]);
3828 /* copy resource information from first port to others */
3829 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3830 port_array[port]->lock = port_array[0]->lock;
3831 port_array[port]->irq_level = port_array[0]->irq_level;
3832 port_array[port]->memory_base = port_array[0]->memory_base;
3833 port_array[port]->sca_base = port_array[0]->sca_base;
3834 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3835 port_array[port]->lcr_base = port_array[0]->lcr_base;
3836 alloc_dma_bufs(port_array[port]);
3839 rc = request_irq(port_array[0]->irq_level,
3840 synclinkmp_interrupt,
3841 port_array[0]->irq_flags,
3842 port_array[0]->device_name,
3845 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3847 port_array[0]->device_name,
3848 port_array[0]->irq_level );
3851 port_array[0]->irq_requested = true;
3852 adapter_test(port_array[0]);
3856 release_resources( port_array[0] );
3858 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3859 tty_port_destroy(&port_array[port]->port);
3860 kfree(port_array[port]);
3865 static const struct tty_operations ops = {
3870 .put_char = put_char,
3871 .flush_chars = flush_chars,
3872 .write_room = write_room,
3873 .chars_in_buffer = chars_in_buffer,
3874 .flush_buffer = flush_buffer,
3876 .throttle = throttle,
3877 .unthrottle = unthrottle,
3878 .send_xchar = send_xchar,
3879 .break_ctl = set_break,
3880 .wait_until_sent = wait_until_sent,
3881 .set_termios = set_termios,
3883 .start = tx_release,
3885 .tiocmget = tiocmget,
3886 .tiocmset = tiocmset,
3887 .get_icount = get_icount,
3888 .proc_show = synclinkmp_proc_show,
3892 static void synclinkmp_cleanup(void)
3898 printk("Unloading %s %s\n", driver_name, driver_version);
3900 if (serial_driver) {
3901 rc = tty_unregister_driver(serial_driver);
3903 printk("%s(%d) failed to unregister tty driver err=%d\n",
3904 __FILE__,__LINE__,rc);
3905 put_tty_driver(serial_driver);
3909 info = synclinkmp_device_list;
3912 info = info->next_device;
3915 /* release devices */
3916 info = synclinkmp_device_list;
3918 #if SYNCLINK_GENERIC_HDLC
3921 free_dma_bufs(info);
3922 free_tmp_rx_buf(info);
3923 if ( info->port_num == 0 ) {
3925 write_reg(info, LPR, 1); /* set low power mode */
3926 release_resources(info);
3929 info = info->next_device;
3930 tty_port_destroy(&tmp->port);
3934 pci_unregister_driver(&synclinkmp_pci_driver);
3937 /* Driver initialization entry point.
3940 static int __init synclinkmp_init(void)
3944 if (break_on_load) {
3945 synclinkmp_get_text_ptr();
3949 printk("%s %s\n", driver_name, driver_version);
3951 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3952 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3956 serial_driver = alloc_tty_driver(128);
3957 if (!serial_driver) {
3962 /* Initialize the tty_driver structure */
3964 serial_driver->driver_name = "synclinkmp";
3965 serial_driver->name = "ttySLM";
3966 serial_driver->major = ttymajor;
3967 serial_driver->minor_start = 64;
3968 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3969 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3970 serial_driver->init_termios = tty_std_termios;
3971 serial_driver->init_termios.c_cflag =
3972 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3973 serial_driver->init_termios.c_ispeed = 9600;
3974 serial_driver->init_termios.c_ospeed = 9600;
3975 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3976 tty_set_operations(serial_driver, &ops);
3977 if ((rc = tty_register_driver(serial_driver)) < 0) {
3978 printk("%s(%d):Couldn't register serial driver\n",
3980 put_tty_driver(serial_driver);
3981 serial_driver = NULL;
3985 printk("%s %s, tty major#%d\n",
3986 driver_name, driver_version,
3987 serial_driver->major);
3992 synclinkmp_cleanup();
3996 static void __exit synclinkmp_exit(void)
3998 synclinkmp_cleanup();
4001 module_init(synclinkmp_init);
4002 module_exit(synclinkmp_exit);
4004 /* Set the port for internal loopback mode.
4005 * The TxCLK and RxCLK signals are generated from the BRG and
4006 * the TxD is looped back to the RxD internally.
4008 static void enable_loopback(SLMP_INFO *info, int enable)
4011 /* MD2 (Mode Register 2)
4012 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4014 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4016 /* degate external TxC clock source */
4017 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4018 write_control_reg(info);
4020 /* RXS/TXS (Rx/Tx clock source)
4021 * 07 Reserved, must be 0
4022 * 06..04 Clock Source, 100=BRG
4023 * 03..00 Clock Divisor, 0000=1
4025 write_reg(info, RXS, 0x40);
4026 write_reg(info, TXS, 0x40);
4029 /* MD2 (Mode Register 2)
4030 * 01..00 CNCT<1..0> Channel connection, 0=normal
4032 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4034 /* RXS/TXS (Rx/Tx clock source)
4035 * 07 Reserved, must be 0
4036 * 06..04 Clock Source, 000=RxC/TxC Pin
4037 * 03..00 Clock Divisor, 0000=1
4039 write_reg(info, RXS, 0x00);
4040 write_reg(info, TXS, 0x00);
4043 /* set LinkSpeed if available, otherwise default to 2Mbps */
4044 if (info->params.clock_speed)
4045 set_rate(info, info->params.clock_speed);
4047 set_rate(info, 3686400);
4050 /* Set the baud rate register to the desired speed
4052 * data_rate data rate of clock in bits per second
4053 * A data rate of 0 disables the AUX clock.
4055 static void set_rate( SLMP_INFO *info, u32 data_rate )
4058 unsigned char BRValue;
4061 /* fBRG = fCLK/(TMC * 2^BR)
4063 if (data_rate != 0) {
4064 Divisor = 14745600/data_rate;
4071 if (TMCValue != 1 && TMCValue != 2) {
4072 /* BRValue of 0 provides 50/50 duty cycle *only* when
4073 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4080 /* while TMCValue is too big for TMC register, divide
4081 * by 2 and increment BR exponent.
4083 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4086 write_reg(info, TXS,
4087 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4088 write_reg(info, RXS,
4089 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4090 write_reg(info, TMC, (unsigned char)TMCValue);
4093 write_reg(info, TXS,0);
4094 write_reg(info, RXS,0);
4095 write_reg(info, TMC, 0);
4101 static void rx_stop(SLMP_INFO *info)
4103 if (debug_level >= DEBUG_LEVEL_ISR)
4104 printk("%s(%d):%s rx_stop()\n",
4105 __FILE__,__LINE__, info->device_name );
4107 write_reg(info, CMD, RXRESET);
4109 info->ie0_value &= ~RXRDYE;
4110 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4112 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4113 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4114 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4116 info->rx_enabled = false;
4117 info->rx_overflow = false;
4120 /* enable the receiver
4122 static void rx_start(SLMP_INFO *info)
4126 if (debug_level >= DEBUG_LEVEL_ISR)
4127 printk("%s(%d):%s rx_start()\n",
4128 __FILE__,__LINE__, info->device_name );
4130 write_reg(info, CMD, RXRESET);
4132 if ( info->params.mode == MGSL_MODE_HDLC ) {
4133 /* HDLC, disabe IRQ on rxdata */
4134 info->ie0_value &= ~RXRDYE;
4135 write_reg(info, IE0, info->ie0_value);
4137 /* Reset all Rx DMA buffers and program rx dma */
4138 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4139 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4141 for (i = 0; i < info->rx_buf_count; i++) {
4142 info->rx_buf_list[i].status = 0xff;
4144 // throttle to 4 shared memory writes at a time to prevent
4145 // hogging local bus (keep latency time for DMA requests low).
4147 read_status_reg(info);
4149 info->current_rx_buf = 0;
4151 /* set current/1st descriptor address */
4152 write_reg16(info, RXDMA + CDA,
4153 info->rx_buf_list_ex[0].phys_entry);
4155 /* set new last rx descriptor address */
4156 write_reg16(info, RXDMA + EDA,
4157 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4159 /* set buffer length (shared by all rx dma data buffers) */
4160 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4162 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4163 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4165 /* async, enable IRQ on rxdata */
4166 info->ie0_value |= RXRDYE;
4167 write_reg(info, IE0, info->ie0_value);
4170 write_reg(info, CMD, RXENABLE);
4172 info->rx_overflow = false;
4173 info->rx_enabled = true;
4176 /* Enable the transmitter and send a transmit frame if
4177 * one is loaded in the DMA buffers.
4179 static void tx_start(SLMP_INFO *info)
4181 if (debug_level >= DEBUG_LEVEL_ISR)
4182 printk("%s(%d):%s tx_start() tx_count=%d\n",
4183 __FILE__,__LINE__, info->device_name,info->tx_count );
4185 if (!info->tx_enabled ) {
4186 write_reg(info, CMD, TXRESET);
4187 write_reg(info, CMD, TXENABLE);
4188 info->tx_enabled = true;
4191 if ( info->tx_count ) {
4193 /* If auto RTS enabled and RTS is inactive, then assert */
4194 /* RTS and set a flag indicating that the driver should */
4195 /* negate RTS when the transmission completes. */
4197 info->drop_rts_on_tx_done = false;
4199 if (info->params.mode != MGSL_MODE_ASYNC) {
4201 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4202 get_signals( info );
4203 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4204 info->serial_signals |= SerialSignal_RTS;
4205 set_signals( info );
4206 info->drop_rts_on_tx_done = true;
4210 write_reg16(info, TRC0,
4211 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4213 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4214 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4216 /* set TX CDA (current descriptor address) */
4217 write_reg16(info, TXDMA + CDA,
4218 info->tx_buf_list_ex[0].phys_entry);
4220 /* set TX EDA (last descriptor address) */
4221 write_reg16(info, TXDMA + EDA,
4222 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4224 /* enable underrun IRQ */
4225 info->ie1_value &= ~IDLE;
4226 info->ie1_value |= UDRN;
4227 write_reg(info, IE1, info->ie1_value);
4228 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4230 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4231 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4233 mod_timer(&info->tx_timer, jiffies +
4234 msecs_to_jiffies(5000));
4238 /* async, enable IRQ on txdata */
4239 info->ie0_value |= TXRDYE;
4240 write_reg(info, IE0, info->ie0_value);
4243 info->tx_active = true;
4247 /* stop the transmitter and DMA
4249 static void tx_stop( SLMP_INFO *info )
4251 if (debug_level >= DEBUG_LEVEL_ISR)
4252 printk("%s(%d):%s tx_stop()\n",
4253 __FILE__,__LINE__, info->device_name );
4255 del_timer(&info->tx_timer);
4257 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4258 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4260 write_reg(info, CMD, TXRESET);
4262 info->ie1_value &= ~(UDRN + IDLE);
4263 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4264 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4266 info->ie0_value &= ~TXRDYE;
4267 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4269 info->tx_enabled = false;
4270 info->tx_active = false;
4273 /* Fill the transmit FIFO until the FIFO is full or
4274 * there is no more data to load.
4276 static void tx_load_fifo(SLMP_INFO *info)
4280 /* do nothing is now tx data available and no XON/XOFF pending */
4282 if ( !info->tx_count && !info->x_char )
4285 /* load the Transmit FIFO until FIFOs full or all data sent */
4287 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4289 /* there is more space in the transmit FIFO and */
4290 /* there is more data in transmit buffer */
4292 if ( (info->tx_count > 1) && !info->x_char ) {
4294 TwoBytes[0] = info->tx_buf[info->tx_get++];
4295 if (info->tx_get >= info->max_frame_size)
4296 info->tx_get -= info->max_frame_size;
4297 TwoBytes[1] = info->tx_buf[info->tx_get++];
4298 if (info->tx_get >= info->max_frame_size)
4299 info->tx_get -= info->max_frame_size;
4301 write_reg16(info, TRB, *((u16 *)TwoBytes));
4303 info->tx_count -= 2;
4304 info->icount.tx += 2;
4306 /* only 1 byte left to transmit or 1 FIFO slot left */
4309 /* transmit pending high priority char */
4310 write_reg(info, TRB, info->x_char);
4313 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4314 if (info->tx_get >= info->max_frame_size)
4315 info->tx_get -= info->max_frame_size;
4323 /* Reset a port to a known state
4325 static void reset_port(SLMP_INFO *info)
4327 if (info->sca_base) {
4332 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4335 /* disable all port interrupts */
4336 info->ie0_value = 0;
4337 info->ie1_value = 0;
4338 info->ie2_value = 0;
4339 write_reg(info, IE0, info->ie0_value);
4340 write_reg(info, IE1, info->ie1_value);
4341 write_reg(info, IE2, info->ie2_value);
4343 write_reg(info, CMD, CHRESET);
4347 /* Reset all the ports to a known state.
4349 static void reset_adapter(SLMP_INFO *info)
4353 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4354 if (info->port_array[i])
4355 reset_port(info->port_array[i]);
4359 /* Program port for asynchronous communications.
4361 static void async_mode(SLMP_INFO *info)
4364 unsigned char RegValue;
4369 /* MD0, Mode Register 0
4371 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4372 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4373 * 03 Reserved, must be 0
4374 * 02 CRCCC, CRC Calculation, 0=disabled
4375 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4380 if (info->params.stop_bits != 1)
4382 write_reg(info, MD0, RegValue);
4384 /* MD1, Mode Register 1
4386 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4387 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4388 * 03..02 RXCHR<1..0>, rx char size
4389 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4394 switch (info->params.data_bits) {
4395 case 7: RegValue |= BIT4 + BIT2; break;
4396 case 6: RegValue |= BIT5 + BIT3; break;
4397 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4399 if (info->params.parity != ASYNC_PARITY_NONE) {
4401 if (info->params.parity == ASYNC_PARITY_ODD)
4404 write_reg(info, MD1, RegValue);
4406 /* MD2, Mode Register 2
4408 * 07..02 Reserved, must be 0
4409 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4414 if (info->params.loopback)
4415 RegValue |= (BIT1 + BIT0);
4416 write_reg(info, MD2, RegValue);
4418 /* RXS, Receive clock source
4420 * 07 Reserved, must be 0
4421 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4422 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4425 write_reg(info, RXS, RegValue);
4427 /* TXS, Transmit clock source
4429 * 07 Reserved, must be 0
4430 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4431 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4434 write_reg(info, TXS, RegValue);
4438 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4440 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4441 write_control_reg(info);
4445 /* RRC Receive Ready Control 0
4447 * 07..05 Reserved, must be 0
4448 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4450 write_reg(info, RRC, 0x00);
4452 /* TRC0 Transmit Ready Control 0
4454 * 07..05 Reserved, must be 0
4455 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4457 write_reg(info, TRC0, 0x10);
4459 /* TRC1 Transmit Ready Control 1
4461 * 07..05 Reserved, must be 0
4462 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4464 write_reg(info, TRC1, 0x1e);
4466 /* CTL, MSCI control register
4468 * 07..06 Reserved, set to 0
4469 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4470 * 04 IDLC, idle control, 0=mark 1=idle register
4471 * 03 BRK, break, 0=off 1 =on (async)
4472 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4473 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4474 * 00 RTS, RTS output control, 0=active 1=inactive
4479 if (!(info->serial_signals & SerialSignal_RTS))
4481 write_reg(info, CTL, RegValue);
4483 /* enable status interrupts */
4484 info->ie0_value |= TXINTE + RXINTE;
4485 write_reg(info, IE0, info->ie0_value);
4487 /* enable break detect interrupt */
4488 info->ie1_value = BRKD;
4489 write_reg(info, IE1, info->ie1_value);
4491 /* enable rx overrun interrupt */
4492 info->ie2_value = OVRN;
4493 write_reg(info, IE2, info->ie2_value);
4495 set_rate( info, info->params.data_rate * 16 );
4498 /* Program the SCA for HDLC communications.
4500 static void hdlc_mode(SLMP_INFO *info)
4502 unsigned char RegValue;
4505 // Can't use DPLL because SCA outputs recovered clock on RxC when
4506 // DPLL mode selected. This causes output contention with RxC receiver.
4507 // Use of DPLL would require external hardware to disable RxC receiver
4508 // when DPLL mode selected.
4509 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4511 /* disable DMA interrupts */
4512 write_reg(info, TXDMA + DIR, 0);
4513 write_reg(info, RXDMA + DIR, 0);
4515 /* MD0, Mode Register 0
4517 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4518 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4519 * 03 Reserved, must be 0
4520 * 02 CRCCC, CRC Calculation, 1=enabled
4521 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4522 * 00 CRC0, CRC initial value, 1 = all 1s
4527 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4529 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4531 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4532 RegValue |= BIT2 + BIT1;
4533 write_reg(info, MD0, RegValue);
4535 /* MD1, Mode Register 1
4537 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4538 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4539 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4540 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4545 write_reg(info, MD1, RegValue);
4547 /* MD2, Mode Register 2
4549 * 07 NRZFM, 0=NRZ, 1=FM
4550 * 06..05 CODE<1..0> Encoding, 00=NRZ
4551 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4552 * 02 Reserved, must be 0
4553 * 01..00 CNCT<1..0> Channel connection, 0=normal
4558 switch(info->params.encoding) {
4559 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4560 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4561 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4562 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4564 case HDLC_ENCODING_NRZB: /* not supported */
4565 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4566 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4569 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4572 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4578 write_reg(info, MD2, RegValue);
4581 /* RXS, Receive clock source
4583 * 07 Reserved, must be 0
4584 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4585 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4588 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4590 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4591 RegValue |= BIT6 + BIT5;
4592 write_reg(info, RXS, RegValue);
4594 /* TXS, Transmit clock source
4596 * 07 Reserved, must be 0
4597 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4598 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4601 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4603 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4604 RegValue |= BIT6 + BIT5;
4605 write_reg(info, TXS, RegValue);
4607 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4608 set_rate(info, info->params.clock_speed * DpllDivisor);
4610 set_rate(info, info->params.clock_speed);
4612 /* GPDATA (General Purpose I/O Data Register)
4614 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4616 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4617 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4619 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4620 write_control_reg(info);
4622 /* RRC Receive Ready Control 0
4624 * 07..05 Reserved, must be 0
4625 * 04..00 RRC<4..0> Rx FIFO trigger active
4627 write_reg(info, RRC, rx_active_fifo_level);
4629 /* TRC0 Transmit Ready Control 0
4631 * 07..05 Reserved, must be 0
4632 * 04..00 TRC<4..0> Tx FIFO trigger active
4634 write_reg(info, TRC0, tx_active_fifo_level);
4636 /* TRC1 Transmit Ready Control 1
4638 * 07..05 Reserved, must be 0
4639 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4641 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4643 /* DMR, DMA Mode Register
4645 * 07..05 Reserved, must be 0
4646 * 04 TMOD, Transfer Mode: 1=chained-block
4647 * 03 Reserved, must be 0
4648 * 02 NF, Number of Frames: 1=multi-frame
4649 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4650 * 00 Reserved, must be 0
4654 write_reg(info, TXDMA + DMR, 0x14);
4655 write_reg(info, RXDMA + DMR, 0x14);
4657 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4658 write_reg(info, RXDMA + CPB,
4659 (unsigned char)(info->buffer_list_phys >> 16));
4661 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4662 write_reg(info, TXDMA + CPB,
4663 (unsigned char)(info->buffer_list_phys >> 16));
4665 /* enable status interrupts. other code enables/disables
4666 * the individual sources for these two interrupt classes.
4668 info->ie0_value |= TXINTE + RXINTE;
4669 write_reg(info, IE0, info->ie0_value);
4671 /* CTL, MSCI control register
4673 * 07..06 Reserved, set to 0
4674 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4675 * 04 IDLC, idle control, 0=mark 1=idle register
4676 * 03 BRK, break, 0=off 1 =on (async)
4677 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4678 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4679 * 00 RTS, RTS output control, 0=active 1=inactive
4684 if (!(info->serial_signals & SerialSignal_RTS))
4686 write_reg(info, CTL, RegValue);
4688 /* preamble not supported ! */
4694 set_rate(info, info->params.clock_speed);
4696 if (info->params.loopback)
4697 enable_loopback(info,1);
4700 /* Set the transmit HDLC idle mode
4702 static void tx_set_idle(SLMP_INFO *info)
4704 unsigned char RegValue = 0xff;
4706 /* Map API idle mode to SCA register bits */
4707 switch(info->idle_mode) {
4708 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4709 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4710 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4711 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4712 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4713 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4714 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4717 write_reg(info, IDL, RegValue);
4720 /* Query the adapter for the state of the V24 status (input) signals.
4722 static void get_signals(SLMP_INFO *info)
4724 u16 status = read_reg(info, SR3);
4725 u16 gpstatus = read_status_reg(info);
4728 /* clear all serial signals except RTS and DTR */
4729 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4731 /* set serial signal bits to reflect MISR */
4733 if (!(status & BIT3))
4734 info->serial_signals |= SerialSignal_CTS;
4736 if ( !(status & BIT2))
4737 info->serial_signals |= SerialSignal_DCD;
4739 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4740 if (!(gpstatus & testbit))
4741 info->serial_signals |= SerialSignal_RI;
4743 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4744 if (!(gpstatus & testbit))
4745 info->serial_signals |= SerialSignal_DSR;
4748 /* Set the state of RTS and DTR based on contents of
4749 * serial_signals member of device context.
4751 static void set_signals(SLMP_INFO *info)
4753 unsigned char RegValue;
4756 RegValue = read_reg(info, CTL);
4757 if (info->serial_signals & SerialSignal_RTS)
4761 write_reg(info, CTL, RegValue);
4763 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4764 EnableBit = BIT1 << (info->port_num*2);
4765 if (info->serial_signals & SerialSignal_DTR)
4766 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4768 info->port_array[0]->ctrlreg_value |= EnableBit;
4769 write_control_reg(info);
4772 /*******************/
4773 /* DMA Buffer Code */
4774 /*******************/
4776 /* Set the count for all receive buffers to SCABUFSIZE
4777 * and set the current buffer to the first buffer. This effectively
4778 * makes all buffers free and discards any data in buffers.
4780 static void rx_reset_buffers(SLMP_INFO *info)
4782 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4785 /* Free the buffers used by a received frame
4787 * info pointer to device instance data
4788 * first index of 1st receive buffer of frame
4789 * last index of last receive buffer of frame
4791 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4796 /* reset current buffer for reuse */
4797 info->rx_buf_list[first].status = 0xff;
4799 if (first == last) {
4801 /* set new last rx descriptor address */
4802 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4806 if (first == info->rx_buf_count)
4810 /* set current buffer to next buffer after last buffer of frame */
4811 info->current_rx_buf = first;
4814 /* Return a received frame from the receive DMA buffers.
4815 * Only frames received without errors are returned.
4817 * Return Value: true if frame returned, otherwise false
4819 static bool rx_get_frame(SLMP_INFO *info)
4821 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4822 unsigned short status;
4823 unsigned int framesize = 0;
4824 bool ReturnCode = false;
4825 unsigned long flags;
4826 struct tty_struct *tty = info->port.tty;
4827 unsigned char addr_field = 0xff;
4829 SCADESC_EX *desc_ex;
4832 /* assume no frame returned, set zero length */
4837 * current_rx_buf points to the 1st buffer of the next available
4838 * receive frame. To find the last buffer of the frame look for
4839 * a non-zero status field in the buffer entries. (The status
4840 * field is set by the 16C32 after completing a receive frame.
4842 StartIndex = EndIndex = info->current_rx_buf;
4845 desc = &info->rx_buf_list[EndIndex];
4846 desc_ex = &info->rx_buf_list_ex[EndIndex];
4848 if (desc->status == 0xff)
4849 goto Cleanup; /* current desc still in use, no frames available */
4851 if (framesize == 0 && info->params.addr_filter != 0xff)
4852 addr_field = desc_ex->virt_addr[0];
4854 framesize += desc->length;
4856 /* Status != 0 means last buffer of frame */
4861 if (EndIndex == info->rx_buf_count)
4864 if (EndIndex == info->current_rx_buf) {
4865 /* all buffers have been 'used' but none mark */
4866 /* the end of a frame. Reset buffers and receiver. */
4867 if ( info->rx_enabled ){
4868 spin_lock_irqsave(&info->lock,flags);
4870 spin_unlock_irqrestore(&info->lock,flags);
4877 /* check status of receive frame */
4879 /* frame status is byte stored after frame data
4881 * 7 EOM (end of msg), 1 = last buffer of frame
4882 * 6 Short Frame, 1 = short frame
4883 * 5 Abort, 1 = frame aborted
4884 * 4 Residue, 1 = last byte is partial
4885 * 3 Overrun, 1 = overrun occurred during frame reception
4886 * 2 CRC, 1 = CRC error detected
4889 status = desc->status;
4891 /* ignore CRC bit if not using CRC (bit is undefined) */
4892 /* Note:CRC is not save to data buffer */
4893 if (info->params.crc_type == HDLC_CRC_NONE)
4896 if (framesize == 0 ||
4897 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4898 /* discard 0 byte frames, this seems to occur sometime
4899 * when remote is idling flags.
4901 rx_free_frame_buffers(info, StartIndex, EndIndex);
4908 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4909 /* received frame has errors,
4910 * update counts and mark frame size as 0
4913 info->icount.rxshort++;
4914 else if (status & BIT5)
4915 info->icount.rxabort++;
4916 else if (status & BIT3)
4917 info->icount.rxover++;
4919 info->icount.rxcrc++;
4922 #if SYNCLINK_GENERIC_HDLC
4924 info->netdev->stats.rx_errors++;
4925 info->netdev->stats.rx_frame_errors++;
4930 if ( debug_level >= DEBUG_LEVEL_BH )
4931 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4932 __FILE__,__LINE__,info->device_name,status,framesize);
4934 if ( debug_level >= DEBUG_LEVEL_DATA )
4935 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4936 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4939 if (framesize > info->max_frame_size)
4940 info->icount.rxlong++;
4942 /* copy dma buffer(s) to contiguous intermediate buffer */
4943 int copy_count = framesize;
4944 int index = StartIndex;
4945 unsigned char *ptmp = info->tmp_rx_buf;
4946 info->tmp_rx_buf_count = framesize;
4948 info->icount.rxok++;
4951 int partial_count = min(copy_count,SCABUFSIZE);
4953 info->rx_buf_list_ex[index].virt_addr,
4955 ptmp += partial_count;
4956 copy_count -= partial_count;
4958 if ( ++index == info->rx_buf_count )
4962 #if SYNCLINK_GENERIC_HDLC
4964 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4967 ldisc_receive_buf(tty,info->tmp_rx_buf,
4968 info->flag_buf, framesize);
4971 /* Free the buffers used by this frame. */
4972 rx_free_frame_buffers( info, StartIndex, EndIndex );
4977 if ( info->rx_enabled && info->rx_overflow ) {
4978 /* Receiver is enabled, but needs to restarted due to
4979 * rx buffer overflow. If buffers are empty, restart receiver.
4981 if (info->rx_buf_list[EndIndex].status == 0xff) {
4982 spin_lock_irqsave(&info->lock,flags);
4984 spin_unlock_irqrestore(&info->lock,flags);
4991 /* load the transmit DMA buffer with data
4993 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4995 unsigned short copy_count;
4998 SCADESC_EX *desc_ex;
5000 if ( debug_level >= DEBUG_LEVEL_DATA )
5001 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5003 /* Copy source buffer to one or more DMA buffers, starting with
5004 * the first transmit dma buffer.
5008 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5010 desc = &info->tx_buf_list[i];
5011 desc_ex = &info->tx_buf_list_ex[i];
5013 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5015 desc->length = copy_count;
5019 count -= copy_count;
5025 if (i >= info->tx_buf_count)
5029 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5030 info->last_tx_buf = ++i;
5033 static bool register_test(SLMP_INFO *info)
5035 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5036 static unsigned int count = ARRAY_SIZE(testval);
5039 unsigned long flags;
5041 spin_lock_irqsave(&info->lock,flags);
5044 /* assume failure */
5045 info->init_error = DiagStatus_AddressFailure;
5047 /* Write bit patterns to various registers but do it out of */
5048 /* sync, then read back and verify values. */
5050 for (i = 0 ; i < count ; i++) {
5051 write_reg(info, TMC, testval[i]);
5052 write_reg(info, IDL, testval[(i+1)%count]);
5053 write_reg(info, SA0, testval[(i+2)%count]);
5054 write_reg(info, SA1, testval[(i+3)%count]);
5056 if ( (read_reg(info, TMC) != testval[i]) ||
5057 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5058 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5059 (read_reg(info, SA1) != testval[(i+3)%count]) )
5067 spin_unlock_irqrestore(&info->lock,flags);
5072 static bool irq_test(SLMP_INFO *info)
5074 unsigned long timeout;
5075 unsigned long flags;
5077 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5079 spin_lock_irqsave(&info->lock,flags);
5082 /* assume failure */
5083 info->init_error = DiagStatus_IrqFailure;
5084 info->irq_occurred = false;
5086 /* setup timer0 on SCA0 to interrupt */
5088 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5089 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5091 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5092 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5095 /* TMCS, Timer Control/Status Register
5097 * 07 CMF, Compare match flag (read only) 1=match
5098 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5099 * 05 Reserved, must be 0
5100 * 04 TME, Timer Enable
5101 * 03..00 Reserved, must be 0
5105 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5107 spin_unlock_irqrestore(&info->lock,flags);
5110 while( timeout-- && !info->irq_occurred ) {
5111 msleep_interruptible(10);
5114 spin_lock_irqsave(&info->lock,flags);
5116 spin_unlock_irqrestore(&info->lock,flags);
5118 return info->irq_occurred;
5121 /* initialize individual SCA device (2 ports)
5123 static bool sca_init(SLMP_INFO *info)
5125 /* set wait controller to single mem partition (low), no wait states */
5126 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5127 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5128 write_reg(info, WCRL, 0); /* wait controller low range */
5129 write_reg(info, WCRM, 0); /* wait controller mid range */
5130 write_reg(info, WCRH, 0); /* wait controller high range */
5132 /* DPCR, DMA Priority Control
5134 * 07..05 Not used, must be 0
5135 * 04 BRC, bus release condition: 0=all transfers complete
5136 * 03 CCC, channel change condition: 0=every cycle
5137 * 02..00 PR<2..0>, priority 100=round robin
5141 write_reg(info, DPCR, dma_priority);
5143 /* DMA Master Enable, BIT7: 1=enable all channels */
5144 write_reg(info, DMER, 0x80);
5146 /* enable all interrupt classes */
5147 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5148 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5149 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5151 /* ITCR, interrupt control register
5152 * 07 IPC, interrupt priority, 0=MSCI->DMA
5153 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5154 * 04 VOS, Vector Output, 0=unmodified vector
5155 * 03..00 Reserved, must be 0
5157 write_reg(info, ITCR, 0);
5162 /* initialize adapter hardware
5164 static bool init_adapter(SLMP_INFO *info)
5168 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5169 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5172 info->misc_ctrl_value |= BIT30;
5173 *MiscCtrl = info->misc_ctrl_value;
5176 * Force at least 170ns delay before clearing
5177 * reset bit. Each read from LCR takes at least
5178 * 30ns so 10 times for 300ns to be safe.
5181 readval = *MiscCtrl;
5183 info->misc_ctrl_value &= ~BIT30;
5184 *MiscCtrl = info->misc_ctrl_value;
5186 /* init control reg (all DTRs off, all clksel=input) */
5187 info->ctrlreg_value = 0xaa;
5188 write_control_reg(info);
5191 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5192 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5194 switch(read_ahead_count)
5197 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5200 lcr1_brdr_value |= BIT5 + BIT4;
5203 lcr1_brdr_value |= BIT5 + BIT3;
5206 lcr1_brdr_value |= BIT5;
5210 *LCR1BRDR = lcr1_brdr_value;
5211 *MiscCtrl = misc_ctrl_value;
5214 sca_init(info->port_array[0]);
5215 sca_init(info->port_array[2]);
5220 /* Loopback an HDLC frame to test the hardware
5221 * interrupt and DMA functions.
5223 static bool loopback_test(SLMP_INFO *info)
5225 #define TESTFRAMESIZE 20
5227 unsigned long timeout;
5228 u16 count = TESTFRAMESIZE;
5229 unsigned char buf[TESTFRAMESIZE];
5231 unsigned long flags;
5233 struct tty_struct *oldtty = info->port.tty;
5234 u32 speed = info->params.clock_speed;
5236 info->params.clock_speed = 3686400;
5237 info->port.tty = NULL;
5239 /* assume failure */
5240 info->init_error = DiagStatus_DmaFailure;
5242 /* build and send transmit frame */
5243 for (count = 0; count < TESTFRAMESIZE;++count)
5244 buf[count] = (unsigned char)count;
5246 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5248 /* program hardware for HDLC and enabled receiver */
5249 spin_lock_irqsave(&info->lock,flags);
5251 enable_loopback(info,1);
5253 info->tx_count = count;
5254 tx_load_dma_buffer(info,buf,count);
5256 spin_unlock_irqrestore(&info->lock,flags);
5258 /* wait for receive complete */
5259 /* Set a timeout for waiting for interrupt. */
5260 for ( timeout = 100; timeout; --timeout ) {
5261 msleep_interruptible(10);
5263 if (rx_get_frame(info)) {
5269 /* verify received frame length and contents */
5271 ( info->tmp_rx_buf_count != count ||
5272 memcmp(buf, info->tmp_rx_buf,count))) {
5276 spin_lock_irqsave(&info->lock,flags);
5277 reset_adapter(info);
5278 spin_unlock_irqrestore(&info->lock,flags);
5280 info->params.clock_speed = speed;
5281 info->port.tty = oldtty;
5286 /* Perform diagnostics on hardware
5288 static int adapter_test( SLMP_INFO *info )
5290 unsigned long flags;
5291 if ( debug_level >= DEBUG_LEVEL_INFO )
5292 printk( "%s(%d):Testing device %s\n",
5293 __FILE__,__LINE__,info->device_name );
5295 spin_lock_irqsave(&info->lock,flags);
5297 spin_unlock_irqrestore(&info->lock,flags);
5299 info->port_array[0]->port_count = 0;
5301 if ( register_test(info->port_array[0]) &&
5302 register_test(info->port_array[1])) {
5304 info->port_array[0]->port_count = 2;
5306 if ( register_test(info->port_array[2]) &&
5307 register_test(info->port_array[3]) )
5308 info->port_array[0]->port_count += 2;
5311 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5312 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5316 if ( !irq_test(info->port_array[0]) ||
5317 !irq_test(info->port_array[1]) ||
5318 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5319 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5320 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5321 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5325 if (!loopback_test(info->port_array[0]) ||
5326 !loopback_test(info->port_array[1]) ||
5327 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5328 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5329 printk( "%s(%d):DMA test failure for device %s\n",
5330 __FILE__,__LINE__,info->device_name);
5334 if ( debug_level >= DEBUG_LEVEL_INFO )
5335 printk( "%s(%d):device %s passed diagnostics\n",
5336 __FILE__,__LINE__,info->device_name );
5338 info->port_array[0]->init_error = 0;
5339 info->port_array[1]->init_error = 0;
5340 if ( info->port_count > 2 ) {
5341 info->port_array[2]->init_error = 0;
5342 info->port_array[3]->init_error = 0;
5348 /* Test the shared memory on a PCI adapter.
5350 static bool memory_test(SLMP_INFO *info)
5352 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5353 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5354 unsigned long count = ARRAY_SIZE(testval);
5356 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5357 unsigned long * addr = (unsigned long *)info->memory_base;
5359 /* Test data lines with test pattern at one location. */
5361 for ( i = 0 ; i < count ; i++ ) {
5363 if ( *addr != testval[i] )
5367 /* Test address lines with incrementing pattern over */
5368 /* entire address range. */
5370 for ( i = 0 ; i < limit ; i++ ) {
5375 addr = (unsigned long *)info->memory_base;
5377 for ( i = 0 ; i < limit ; i++ ) {
5378 if ( *addr != i * 4 )
5383 memset( info->memory_base, 0, SCA_MEM_SIZE );
5387 /* Load data into PCI adapter shared memory.
5389 * The PCI9050 releases control of the local bus
5390 * after completing the current read or write operation.
5392 * While the PCI9050 write FIFO not empty, the
5393 * PCI9050 treats all of the writes as a single transaction
5394 * and does not release the bus. This causes DMA latency problems
5395 * at high speeds when copying large data blocks to the shared memory.
5397 * This function breaks a write into multiple transations by
5398 * interleaving a read which flushes the write FIFO and 'completes'
5399 * the write transation. This allows any pending DMA request to gain control
5400 * of the local bus in a timely fasion.
5402 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5404 /* A load interval of 16 allows for 4 32-bit writes at */
5405 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5407 unsigned short interval = count / sca_pci_load_interval;
5410 for ( i = 0 ; i < interval ; i++ )
5412 memcpy(dest, src, sca_pci_load_interval);
5413 read_status_reg(info);
5414 dest += sca_pci_load_interval;
5415 src += sca_pci_load_interval;
5418 memcpy(dest, src, count % sca_pci_load_interval);
5421 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5426 printk("%s tx data:\n",info->device_name);
5428 printk("%s rx data:\n",info->device_name);
5436 for(i=0;i<linecount;i++)
5437 printk("%02X ",(unsigned char)data[i]);
5440 for(i=0;i<linecount;i++) {
5441 if (data[i]>=040 && data[i]<=0176)
5442 printk("%c",data[i]);
5451 } /* end of trace_block() */
5453 /* called when HDLC frame times out
5454 * update stats and do tx completion processing
5456 static void tx_timeout(struct timer_list *t)
5458 SLMP_INFO *info = from_timer(info, t, tx_timer);
5459 unsigned long flags;
5461 if ( debug_level >= DEBUG_LEVEL_INFO )
5462 printk( "%s(%d):%s tx_timeout()\n",
5463 __FILE__,__LINE__,info->device_name);
5464 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5465 info->icount.txtimeout++;
5467 spin_lock_irqsave(&info->lock,flags);
5468 info->tx_active = false;
5469 info->tx_count = info->tx_put = info->tx_get = 0;
5471 spin_unlock_irqrestore(&info->lock,flags);
5473 #if SYNCLINK_GENERIC_HDLC
5475 hdlcdev_tx_done(info);
5481 /* called to periodically check the DSR/RI modem signal input status
5483 static void status_timeout(struct timer_list *t)
5486 SLMP_INFO *info = from_timer(info, t, status_timer);
5487 unsigned long flags;
5488 unsigned char delta;
5491 spin_lock_irqsave(&info->lock,flags);
5493 spin_unlock_irqrestore(&info->lock,flags);
5495 /* check for DSR/RI state change */
5497 delta = info->old_signals ^ info->serial_signals;
5498 info->old_signals = info->serial_signals;
5500 if (delta & SerialSignal_DSR)
5501 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5503 if (delta & SerialSignal_RI)
5504 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5506 if (delta & SerialSignal_DCD)
5507 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5509 if (delta & SerialSignal_CTS)
5510 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5513 isr_io_pin(info,status);
5515 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5519 /* Register Access Routines -
5520 * All registers are memory mapped
5522 #define CALC_REGADDR() \
5523 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5524 if (info->port_num > 1) \
5525 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5526 if ( info->port_num & 1) { \
5528 RegAddr += 0x40; /* DMA access */ \
5529 else if (Addr > 0x1f && Addr < 0x60) \
5530 RegAddr += 0x20; /* MSCI access */ \
5534 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5539 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5545 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5548 return *((u16 *)RegAddr);
5551 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5554 *((u16 *)RegAddr) = Value;
5557 static unsigned char read_status_reg(SLMP_INFO * info)
5559 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5563 static void write_control_reg(SLMP_INFO * info)
5565 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5566 *RegAddr = info->port_array[0]->ctrlreg_value;
5570 static int synclinkmp_init_one (struct pci_dev *dev,
5571 const struct pci_device_id *ent)
5573 if (pci_enable_device(dev)) {
5574 printk("error enabling pci device %p\n", dev);
5577 return device_init( ++synclinkmp_adapter_count, dev );
5580 static void synclinkmp_remove_one (struct pci_dev *dev)