1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/ioport.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/init.h>
35 #include <linux/of_device.h>
40 #include <asm/setup.h>
42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46 #include <linux/serial_core.h>
47 #include <linux/sunserialcore.h>
51 struct uart_sunsab_port {
52 struct uart_port port; /* Generic UART port */
53 union sab82532_async_regs __iomem *regs; /* Chip registers */
54 unsigned long irqflags; /* IRQ state flags */
55 int dsr; /* Current DSR state */
56 unsigned int cec_timeout; /* Chip poll timeout... */
57 unsigned int tec_timeout; /* likewise */
58 unsigned char interrupt_mask0;/* ISR0 masking */
59 unsigned char interrupt_mask1;/* ISR1 masking */
60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
62 unsigned int gis_shift;
63 int type; /* SAB82532 version */
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
77 * This assumes you have a 29.4912 MHz clock for your UART.
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
96 int timeout = up->tec_timeout;
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
104 int timeout = up->cec_timeout;
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
110 static struct tty_port *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat)
114 struct tty_port *port = NULL;
115 unsigned char buf[32];
116 int saw_console_brk = 0;
121 if (up->port.state != NULL) /* Unopened serial console */
122 port = &up->port.state->port;
124 /* Read number of BYTES (Character + Status) available. */
125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126 count = SAB82532_RECV_FIFO_SIZE;
130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
135 /* Issue a FIFO read command in case we where idle. */
136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
146 for (i = 0; i < count; i++)
147 buf[i] = readb(&up->regs->r.rfifo[i]);
149 /* Issue Receive Message Complete command. */
152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
155 /* Count may be zero for BRK, so we check for it here */
156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157 (up->port.line == up->port.cons->index))
161 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
162 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
164 up->port.icount.brk++;
165 uart_handle_break(&up->port);
169 for (i = 0; i < count; i++) {
170 unsigned char ch = buf[i], flag;
173 up->port.icount.rx++;
175 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
177 SAB82532_ISR0_RFO)) ||
178 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
180 * For statistics only
182 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
183 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
185 up->port.icount.brk++;
187 * We do the SysRQ and SAK checking
188 * here because otherwise the break
189 * may get masked by ignore_status_mask
190 * or read_status_mask.
192 if (uart_handle_break(&up->port))
194 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
195 up->port.icount.parity++;
196 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
197 up->port.icount.frame++;
198 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
199 up->port.icount.overrun++;
202 * Mask off conditions which should be ingored.
204 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
205 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
207 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
209 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
211 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
215 if (uart_handle_sysrq_char(&up->port, ch) || !port)
218 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
219 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
220 tty_insert_flip_char(port, ch, flag);
221 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
222 tty_insert_flip_char(port, 0, TTY_OVERRUN);
231 static void sunsab_stop_tx(struct uart_port *);
232 static void sunsab_tx_idle(struct uart_sunsab_port *);
234 static void transmit_chars(struct uart_sunsab_port *up,
235 union sab82532_irq_status *stat)
237 struct circ_buf *xmit = &up->port.state->xmit;
240 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
241 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
242 writeb(up->interrupt_mask1, &up->regs->w.imr1);
243 set_bit(SAB82532_ALLS, &up->irqflags);
246 #if 0 /* bde@nwlink.com says this check causes problems */
247 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
251 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
254 set_bit(SAB82532_XPR, &up->irqflags);
257 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
258 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
263 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
264 writeb(up->interrupt_mask1, &up->regs->w.imr1);
265 clear_bit(SAB82532_ALLS, &up->irqflags);
267 /* Stuff 32 bytes into Transmit FIFO. */
268 clear_bit(SAB82532_XPR, &up->irqflags);
269 for (i = 0; i < up->port.fifosize; i++) {
270 writeb(xmit->buf[xmit->tail],
271 &up->regs->w.xfifo[i]);
272 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
273 up->port.icount.tx++;
274 if (uart_circ_empty(xmit))
278 /* Issue a Transmit Frame command. */
280 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
282 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
283 uart_write_wakeup(&up->port);
285 if (uart_circ_empty(xmit))
286 sunsab_stop_tx(&up->port);
289 static void check_status(struct uart_sunsab_port *up,
290 union sab82532_irq_status *stat)
292 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
293 uart_handle_dcd_change(&up->port,
294 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
296 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
297 uart_handle_cts_change(&up->port,
298 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
300 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
301 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
302 up->port.icount.dsr++;
305 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
308 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
310 struct uart_sunsab_port *up = dev_id;
311 struct tty_port *port = NULL;
312 union sab82532_irq_status status;
316 spin_lock_irqsave(&up->port.lock, flags);
319 gis = readb(&up->regs->r.gis) >> up->gis_shift;
321 status.sreg.isr0 = readb(&up->regs->r.isr0);
323 status.sreg.isr1 = readb(&up->regs->r.isr1);
326 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
327 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
328 (status.sreg.isr1 & SAB82532_ISR1_BRK))
329 port = receive_chars(up, &status);
330 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
331 (status.sreg.isr1 & SAB82532_ISR1_CSC))
332 check_status(up, &status);
333 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
334 transmit_chars(up, &status);
337 spin_unlock_irqrestore(&up->port.lock, flags);
340 tty_flip_buffer_push(port);
345 /* port->lock is not held. */
346 static unsigned int sunsab_tx_empty(struct uart_port *port)
348 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
351 /* Do not need a lock for a state test like this. */
352 if (test_bit(SAB82532_ALLS, &up->irqflags))
360 /* port->lock held by caller. */
361 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
363 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
365 if (mctrl & TIOCM_RTS) {
366 up->cached_mode &= ~SAB82532_MODE_FRTS;
367 up->cached_mode |= SAB82532_MODE_RTS;
369 up->cached_mode |= (SAB82532_MODE_FRTS |
372 if (mctrl & TIOCM_DTR) {
373 up->cached_pvr &= ~(up->pvr_dtr_bit);
375 up->cached_pvr |= up->pvr_dtr_bit;
378 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
379 if (test_bit(SAB82532_XPR, &up->irqflags))
383 /* port->lock is held by caller and interrupts are disabled. */
384 static unsigned int sunsab_get_mctrl(struct uart_port *port)
386 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
392 val = readb(&up->regs->r.pvr);
393 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
395 val = readb(&up->regs->r.vstr);
396 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
398 val = readb(&up->regs->r.star);
399 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
404 /* port->lock held by caller. */
405 static void sunsab_stop_tx(struct uart_port *port)
407 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
409 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
410 writeb(up->interrupt_mask1, &up->regs->w.imr1);
413 /* port->lock held by caller. */
414 static void sunsab_tx_idle(struct uart_sunsab_port *up)
416 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
419 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
420 writeb(up->cached_mode, &up->regs->rw.mode);
421 writeb(up->cached_pvr, &up->regs->rw.pvr);
422 writeb(up->cached_dafo, &up->regs->w.dafo);
424 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
425 tmp = readb(&up->regs->rw.ccr2);
427 tmp |= (up->cached_ebrg >> 2) & 0xc0;
428 writeb(tmp, &up->regs->rw.ccr2);
432 /* port->lock held by caller. */
433 static void sunsab_start_tx(struct uart_port *port)
435 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
436 struct circ_buf *xmit = &up->port.state->xmit;
439 if (uart_circ_empty(xmit))
442 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
443 writeb(up->interrupt_mask1, &up->regs->w.imr1);
445 if (!test_bit(SAB82532_XPR, &up->irqflags))
448 clear_bit(SAB82532_ALLS, &up->irqflags);
449 clear_bit(SAB82532_XPR, &up->irqflags);
451 for (i = 0; i < up->port.fifosize; i++) {
452 writeb(xmit->buf[xmit->tail],
453 &up->regs->w.xfifo[i]);
454 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
455 up->port.icount.tx++;
456 if (uart_circ_empty(xmit))
460 /* Issue a Transmit Frame command. */
462 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
465 /* port->lock is not held. */
466 static void sunsab_send_xchar(struct uart_port *port, char ch)
468 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
471 spin_lock_irqsave(&up->port.lock, flags);
474 writeb(ch, &up->regs->w.tic);
476 spin_unlock_irqrestore(&up->port.lock, flags);
479 /* port->lock held by caller. */
480 static void sunsab_stop_rx(struct uart_port *port)
482 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
484 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
485 writeb(up->interrupt_mask1, &up->regs->w.imr0);
488 /* port->lock is not held. */
489 static void sunsab_break_ctl(struct uart_port *port, int break_state)
491 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
495 spin_lock_irqsave(&up->port.lock, flags);
497 val = up->cached_dafo;
499 val |= SAB82532_DAFO_XBRK;
501 val &= ~SAB82532_DAFO_XBRK;
502 up->cached_dafo = val;
504 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
505 if (test_bit(SAB82532_XPR, &up->irqflags))
508 spin_unlock_irqrestore(&up->port.lock, flags);
511 /* port->lock is not held. */
512 static int sunsab_startup(struct uart_port *port)
514 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
517 int err = request_irq(up->port.irq, sunsab_interrupt,
518 IRQF_SHARED, "sab", up);
522 spin_lock_irqsave(&up->port.lock, flags);
525 * Wait for any commands or immediate characters
531 * Clear the FIFO buffers.
533 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
535 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
538 * Clear the interrupt registers.
540 (void) readb(&up->regs->r.isr0);
541 (void) readb(&up->regs->r.isr1);
544 * Now, initialize the UART
546 writeb(0, &up->regs->w.ccr0); /* power-down */
547 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
548 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
549 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
550 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
551 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
552 writeb(0, &up->regs->w.ccr3);
553 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
554 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
556 writeb(up->cached_mode, &up->regs->w.mode);
557 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
559 tmp = readb(&up->regs->rw.ccr0);
560 tmp |= SAB82532_CCR0_PU; /* power-up */
561 writeb(tmp, &up->regs->rw.ccr0);
564 * Finally, enable interrupts
566 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
568 writeb(up->interrupt_mask0, &up->regs->w.imr0);
569 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
570 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
571 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
573 writeb(up->interrupt_mask1, &up->regs->w.imr1);
574 set_bit(SAB82532_ALLS, &up->irqflags);
575 set_bit(SAB82532_XPR, &up->irqflags);
577 spin_unlock_irqrestore(&up->port.lock, flags);
582 /* port->lock is not held. */
583 static void sunsab_shutdown(struct uart_port *port)
585 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
588 spin_lock_irqsave(&up->port.lock, flags);
590 /* Disable Interrupts */
591 up->interrupt_mask0 = 0xff;
592 writeb(up->interrupt_mask0, &up->regs->w.imr0);
593 up->interrupt_mask1 = 0xff;
594 writeb(up->interrupt_mask1, &up->regs->w.imr1);
596 /* Disable break condition */
597 up->cached_dafo = readb(&up->regs->rw.dafo);
598 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
599 writeb(up->cached_dafo, &up->regs->rw.dafo);
601 /* Disable Receiver */
602 up->cached_mode &= ~SAB82532_MODE_RAC;
603 writeb(up->cached_mode, &up->regs->rw.mode);
608 * If the chip is powered down here the system hangs/crashes during
609 * reboot or shutdown. This needs to be investigated further,
610 * similar behaviour occurs in 2.4 when the driver is configured
611 * as a module only. One hint may be that data is sometimes
612 * transmitted at 9600 baud during shutdown (regardless of the
613 * speed the chip was configured for when the port was open).
617 tmp = readb(&up->regs->rw.ccr0);
618 tmp &= ~SAB82532_CCR0_PU;
619 writeb(tmp, &up->regs->rw.ccr0);
622 spin_unlock_irqrestore(&up->port.lock, flags);
623 free_irq(up->port.irq, up);
627 * This is used to figure out the divisor speeds.
629 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
631 * with 0 <= N < 64 and 0 <= M < 16
634 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
645 * We scale numbers by 10 so that we get better accuracy
646 * without having to use floating point. Here we increment m
647 * until n is within the valid range.
649 n = (SAB_BASE_BAUD * 10) / baud;
657 * We try very hard to avoid speeds with M == 0 since they may
658 * not work correctly for XTAL frequences above 10 MHz.
660 if ((m == 0) && ((n & 1) == 0)) {
668 /* Internal routine, port->lock is held and local interrupts are disabled. */
669 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
670 unsigned int iflag, unsigned int baud,
676 /* Byte size and parity */
677 switch (cflag & CSIZE) {
678 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
679 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
680 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
681 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
682 /* Never happens, but GCC is too dumb to figure it out */
683 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
686 if (cflag & CSTOPB) {
687 dafo |= SAB82532_DAFO_STOP;
691 if (cflag & PARENB) {
692 dafo |= SAB82532_DAFO_PARE;
696 if (cflag & PARODD) {
697 dafo |= SAB82532_DAFO_PAR_ODD;
699 dafo |= SAB82532_DAFO_PAR_EVEN;
701 up->cached_dafo = dafo;
703 calc_ebrg(baud, &n, &m);
705 up->cached_ebrg = n | (m << 6);
707 up->tec_timeout = (10 * 1000000) / baud;
708 up->cec_timeout = up->tec_timeout >> 2;
710 /* CTS flow control flags */
711 /* We encode read_status_mask and ignore_status_mask like so:
713 * ---------------------
714 * | ... | ISR1 | ISR0 |
715 * ---------------------
719 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
720 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
722 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
724 SAB82532_ISR1_XPR) << 8;
726 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
728 if (iflag & (IGNBRK | BRKINT | PARMRK))
729 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
732 * Characteres to ignore
734 up->port.ignore_status_mask = 0;
736 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
738 if (iflag & IGNBRK) {
739 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
741 * If we're ignoring parity and break indicators,
742 * ignore overruns too (for real raw support).
745 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
749 * ignore all characters if CREAD is not set
751 if ((cflag & CREAD) == 0)
752 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
755 uart_update_timeout(&up->port, cflag,
756 (up->port.uartclk / (16 * quot)));
758 /* Now schedule a register update when the chip's
759 * transmitter is idle.
761 up->cached_mode |= SAB82532_MODE_RAC;
762 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
763 if (test_bit(SAB82532_XPR, &up->irqflags))
767 /* port->lock is not held. */
768 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
769 struct ktermios *old)
771 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
773 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
774 unsigned int quot = uart_get_divisor(port, baud);
776 spin_lock_irqsave(&up->port.lock, flags);
777 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
778 spin_unlock_irqrestore(&up->port.lock, flags);
781 static const char *sunsab_type(struct uart_port *port)
783 struct uart_sunsab_port *up = (void *)port;
786 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
790 static void sunsab_release_port(struct uart_port *port)
794 static int sunsab_request_port(struct uart_port *port)
799 static void sunsab_config_port(struct uart_port *port, int flags)
803 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
808 static struct uart_ops sunsab_pops = {
809 .tx_empty = sunsab_tx_empty,
810 .set_mctrl = sunsab_set_mctrl,
811 .get_mctrl = sunsab_get_mctrl,
812 .stop_tx = sunsab_stop_tx,
813 .start_tx = sunsab_start_tx,
814 .send_xchar = sunsab_send_xchar,
815 .stop_rx = sunsab_stop_rx,
816 .break_ctl = sunsab_break_ctl,
817 .startup = sunsab_startup,
818 .shutdown = sunsab_shutdown,
819 .set_termios = sunsab_set_termios,
821 .release_port = sunsab_release_port,
822 .request_port = sunsab_request_port,
823 .config_port = sunsab_config_port,
824 .verify_port = sunsab_verify_port,
827 static struct uart_driver sunsab_reg = {
828 .owner = THIS_MODULE,
829 .driver_name = "sunsab",
834 static struct uart_sunsab_port *sunsab_ports;
836 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
838 static void sunsab_console_putchar(struct uart_port *port, int c)
840 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
843 writeb(c, &up->regs->w.tic);
846 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
848 struct uart_sunsab_port *up = &sunsab_ports[con->index];
852 if (up->port.sysrq || oops_in_progress)
853 locked = spin_trylock_irqsave(&up->port.lock, flags);
855 spin_lock_irqsave(&up->port.lock, flags);
857 uart_console_write(&up->port, s, n, sunsab_console_putchar);
861 spin_unlock_irqrestore(&up->port.lock, flags);
864 static int sunsab_console_setup(struct console *con, char *options)
866 struct uart_sunsab_port *up = &sunsab_ports[con->index];
868 unsigned int baud, quot;
871 * The console framework calls us for each and every port
872 * registered. Defer the console setup until the requested
873 * port has been properly discovered. A bit of a hack,
876 if (up->port.type != PORT_SUNSAB)
879 printk("Console: ttyS%d (SAB82532)\n",
880 (sunsab_reg.minor - 64) + con->index);
882 sunserial_console_termios(con, up->port.dev->of_node);
884 switch (con->cflag & CBAUD) {
885 case B150: baud = 150; break;
886 case B300: baud = 300; break;
887 case B600: baud = 600; break;
888 case B1200: baud = 1200; break;
889 case B2400: baud = 2400; break;
890 case B4800: baud = 4800; break;
891 default: case B9600: baud = 9600; break;
892 case B19200: baud = 19200; break;
893 case B38400: baud = 38400; break;
894 case B57600: baud = 57600; break;
895 case B115200: baud = 115200; break;
896 case B230400: baud = 230400; break;
897 case B460800: baud = 460800; break;
903 spin_lock_init(&up->port.lock);
906 * Initialize the hardware
908 sunsab_startup(&up->port);
910 spin_lock_irqsave(&up->port.lock, flags);
913 * Finally, enable interrupts
915 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
916 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
917 writeb(up->interrupt_mask0, &up->regs->w.imr0);
918 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
919 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
920 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
922 writeb(up->interrupt_mask1, &up->regs->w.imr1);
924 quot = uart_get_divisor(&up->port, baud);
925 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
926 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
928 spin_unlock_irqrestore(&up->port.lock, flags);
933 static struct console sunsab_console = {
935 .write = sunsab_console_write,
936 .device = uart_console_device,
937 .setup = sunsab_console_setup,
938 .flags = CON_PRINTBUFFER,
943 static inline struct console *SUNSAB_CONSOLE(void)
945 return &sunsab_console;
948 #define SUNSAB_CONSOLE() (NULL)
949 #define sunsab_console_init() do { } while (0)
952 static int sunsab_init_one(struct uart_sunsab_port *up,
953 struct platform_device *op,
954 unsigned long offset,
957 up->port.line = line;
958 up->port.dev = &op->dev;
960 up->port.mapbase = op->resource[0].start + offset;
961 up->port.membase = of_ioremap(&op->resource[0], offset,
962 sizeof(union sab82532_async_regs),
964 if (!up->port.membase)
966 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
968 up->port.irq = op->archdata.irqs[0];
970 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
971 up->port.iotype = UPIO_MEM;
973 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
975 up->port.ops = &sunsab_pops;
976 up->port.type = PORT_SUNSAB;
977 up->port.uartclk = SAB_BASE_BAUD;
979 up->type = readb(&up->regs->r.vstr) & 0x0f;
980 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
981 writeb(0xff, &up->regs->w.pim);
982 if ((up->port.line & 0x1) == 0) {
983 up->pvr_dsr_bit = (1 << 0);
984 up->pvr_dtr_bit = (1 << 1);
987 up->pvr_dsr_bit = (1 << 3);
988 up->pvr_dtr_bit = (1 << 2);
991 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
992 writeb(up->cached_pvr, &up->regs->w.pvr);
993 up->cached_mode = readb(&up->regs->rw.mode);
994 up->cached_mode |= SAB82532_MODE_FRTS;
995 writeb(up->cached_mode, &up->regs->rw.mode);
996 up->cached_mode |= SAB82532_MODE_RTS;
997 writeb(up->cached_mode, &up->regs->rw.mode);
999 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1000 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1005 static int sab_probe(struct platform_device *op)
1008 struct uart_sunsab_port *up;
1011 up = &sunsab_ports[inst * 2];
1013 err = sunsab_init_one(&up[0], op,
1019 err = sunsab_init_one(&up[1], op,
1020 sizeof(union sab82532_async_regs),
1025 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1026 &sunsab_reg, up[0].port.line,
1029 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1030 &sunsab_reg, up[1].port.line,
1033 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1037 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1041 platform_set_drvdata(op, &up[0]);
1048 uart_remove_one_port(&sunsab_reg, &up[0].port);
1050 of_iounmap(&op->resource[0],
1052 sizeof(union sab82532_async_regs));
1054 of_iounmap(&op->resource[0],
1056 sizeof(union sab82532_async_regs));
1061 static int sab_remove(struct platform_device *op)
1063 struct uart_sunsab_port *up = platform_get_drvdata(op);
1065 uart_remove_one_port(&sunsab_reg, &up[1].port);
1066 uart_remove_one_port(&sunsab_reg, &up[0].port);
1067 of_iounmap(&op->resource[0],
1069 sizeof(union sab82532_async_regs));
1070 of_iounmap(&op->resource[0],
1072 sizeof(union sab82532_async_regs));
1077 static const struct of_device_id sab_match[] = {
1083 .compatible = "sab82532",
1087 MODULE_DEVICE_TABLE(of, sab_match);
1089 static struct platform_driver sab_driver = {
1092 .owner = THIS_MODULE,
1093 .of_match_table = sab_match,
1096 .remove = sab_remove,
1099 static int __init sunsab_init(void)
1101 struct device_node *dp;
1103 int num_channels = 0;
1105 for_each_node_by_name(dp, "se")
1107 for_each_node_by_name(dp, "serial") {
1108 if (of_device_is_compatible(dp, "sab82532"))
1113 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1114 num_channels, GFP_KERNEL);
1118 err = sunserial_register_minors(&sunsab_reg, num_channels);
1120 kfree(sunsab_ports);
1121 sunsab_ports = NULL;
1127 return platform_driver_register(&sab_driver);
1130 static void __exit sunsab_exit(void)
1132 platform_driver_unregister(&sab_driver);
1133 if (sunsab_reg.nr) {
1134 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1137 kfree(sunsab_ports);
1138 sunsab_ports = NULL;
1141 module_init(sunsab_init);
1142 module_exit(sunsab_exit);
1144 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1145 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1146 MODULE_LICENSE("GPL");