drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@foss.st.com>
   7  *           Erwan Le Ray <erwan.leray@foss.st.com>
   8  *
   9  * Inspired by st-asc.c from STMicroelectronics (c)
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/clk.h>
  14 #include <linux/console.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-direction.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/irq.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/serial.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/tty_flip.h>
  34 #include <linux/tty.h>
  35
  36 #include "serial_mctrl_gpio.h"
  37 #include "stm32-usart.h"
  38
  39
  40 /* Register offsets */
  41 static struct stm32_usart_info __maybe_unused stm32f4_info = {
  42         .ofs = {
  43                 .isr            = 0x00,
  44                 .rdr            = 0x04,
  45                 .tdr            = 0x04,
  46                 .brr            = 0x08,
  47                 .cr1            = 0x0c,
  48                 .cr2            = 0x10,
  49                 .cr3            = 0x14,
  50                 .gtpr           = 0x18,
  51                 .rtor           = UNDEF_REG,
  52                 .rqr            = UNDEF_REG,
  53                 .icr            = UNDEF_REG,
  54                 .presc          = UNDEF_REG,
  55                 .hwcfgr1        = UNDEF_REG,
  56         },
  57         .cfg = {
  58                 .uart_enable_bit = 13,
  59                 .has_7bits_data = false,
  60         }
  61 };
  62
  63 static struct stm32_usart_info __maybe_unused stm32f7_info = {
  64         .ofs = {
  65                 .cr1            = 0x00,
  66                 .cr2            = 0x04,
  67                 .cr3            = 0x08,
  68                 .brr            = 0x0c,
  69                 .gtpr           = 0x10,
  70                 .rtor           = 0x14,
  71                 .rqr            = 0x18,
  72                 .isr            = 0x1c,
  73                 .icr            = 0x20,
  74                 .rdr            = 0x24,
  75                 .tdr            = 0x28,
  76                 .presc          = UNDEF_REG,
  77                 .hwcfgr1        = UNDEF_REG,
  78         },
  79         .cfg = {
  80                 .uart_enable_bit = 0,
  81                 .has_7bits_data = true,
  82                 .has_swap = true,
  83         }
  84 };
  85
  86 static struct stm32_usart_info __maybe_unused stm32h7_info = {
  87         .ofs = {
  88                 .cr1            = 0x00,
  89                 .cr2            = 0x04,
  90                 .cr3            = 0x08,
  91                 .brr            = 0x0c,
  92                 .gtpr           = 0x10,
  93                 .rtor           = 0x14,
  94                 .rqr            = 0x18,
  95                 .isr            = 0x1c,
  96                 .icr            = 0x20,
  97                 .rdr            = 0x24,
  98                 .tdr            = 0x28,
  99                 .presc          = 0x2c,
 100                 .hwcfgr1        = 0x3f0,
 101         },
 102         .cfg = {
 103                 .uart_enable_bit = 0,
 104                 .has_7bits_data = true,
 105                 .has_swap = true,
 106                 .has_wakeup = true,
 107                 .has_fifo = true,
 108         }
 109 };
 110
 111 static void stm32_usart_stop_tx(struct uart_port *port);
 112 static void stm32_usart_transmit_chars(struct uart_port *port);
 113 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
 114
 115 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
 116 {
 117         return container_of(port, struct stm32_port, port);
 118 }
 119
 120 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
 121 {
 122         u32 val;
 123
 124         val = readl_relaxed(port->membase + reg);
 125         val |= bits;
 126         writel_relaxed(val, port->membase + reg);
 127 }
 128
 129 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
 130 {
 131         u32 val;
 132
 133         val = readl_relaxed(port->membase + reg);
 134         val &= ~bits;
 135         writel_relaxed(val, port->membase + reg);
 136 }
 137
 138 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
 139 {
 140         struct stm32_port *stm32_port = to_stm32_port(port);
 141         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 142
 143         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 144                 return TIOCSER_TEMT;
 145
 146         return 0;
 147 }
 148
 149 static void stm32_usart_rs485_rts_enable(struct uart_port *port)
 150 {
 151         struct stm32_port *stm32_port = to_stm32_port(port);
 152         struct serial_rs485 *rs485conf = &port->rs485;
 153
 154         if (stm32_port->hw_flow_control ||
 155             !(rs485conf->flags & SER_RS485_ENABLED))
 156                 return;
 157
 158         if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 159                 mctrl_gpio_set(stm32_port->gpios,
 160                                stm32_port->port.mctrl | TIOCM_RTS);
 161         } else {
 162                 mctrl_gpio_set(stm32_port->gpios,
 163                                stm32_port->port.mctrl & ~TIOCM_RTS);
 164         }
 165 }
 166
 167 static void stm32_usart_rs485_rts_disable(struct uart_port *port)
 168 {
 169         struct stm32_port *stm32_port = to_stm32_port(port);
 170         struct serial_rs485 *rs485conf = &port->rs485;
 171
 172         if (stm32_port->hw_flow_control ||
 173             !(rs485conf->flags & SER_RS485_ENABLED))
 174                 return;
 175
 176         if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 177                 mctrl_gpio_set(stm32_port->gpios,
 178                                stm32_port->port.mctrl & ~TIOCM_RTS);
 179         } else {
 180                 mctrl_gpio_set(stm32_port->gpios,
 181                                stm32_port->port.mctrl | TIOCM_RTS);
 182         }
 183 }
 184
 185 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
 186                                          u32 delay_DDE, u32 baud)
 187 {
 188         u32 rs485_deat_dedt;
 189         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
 190         bool over8;
 191
 192         *cr3 |= USART_CR3_DEM;
 193         over8 = *cr1 & USART_CR1_OVER8;
 194
 195         *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 196
 197         if (over8)
 198                 rs485_deat_dedt = delay_ADE * baud * 8;
 199         else
 200                 rs485_deat_dedt = delay_ADE * baud * 16;
 201
 202         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
 203         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
 204                           rs485_deat_dedt_max : rs485_deat_dedt;
 205         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
 206                            USART_CR1_DEAT_MASK;
 207         *cr1 |= rs485_deat_dedt;
 208
 209         if (over8)
 210                 rs485_deat_dedt = delay_DDE * baud * 8;
 211         else
 212                 rs485_deat_dedt = delay_DDE * baud * 16;
 213
 214         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
 215         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
 216                           rs485_deat_dedt_max : rs485_deat_dedt;
 217         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
 218                            USART_CR1_DEDT_MASK;
 219         *cr1 |= rs485_deat_dedt;
 220 }
 221
 222 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios,
 223                                     struct serial_rs485 *rs485conf)
 224 {
 225         struct stm32_port *stm32_port = to_stm32_port(port);
 226         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 227         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 228         u32 usartdiv, baud, cr1, cr3;
 229         bool over8;
 230
 231         stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 232
 233         if (rs485conf->flags & SER_RS485_ENABLED) {
 234                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 235                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 236                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 237                 usartdiv = usartdiv & GENMASK(15, 0);
 238                 over8 = cr1 & USART_CR1_OVER8;
 239
 240                 if (over8)
 241                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 242                                    << USART_BRR_04_R_SHIFT;
 243
 244                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 245                 stm32_usart_config_reg_rs485(&cr1, &cr3,
 246                                              rs485conf->delay_rts_before_send,
 247                                              rs485conf->delay_rts_after_send,
 248                                              baud);
 249
 250                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
 251                         cr3 &= ~USART_CR3_DEP;
 252                 else
 253                         cr3 |= USART_CR3_DEP;
 254
 255                 writel_relaxed(cr3, port->membase + ofs->cr3);
 256                 writel_relaxed(cr1, port->membase + ofs->cr1);
 257
 258                 if (!port->rs485_rx_during_tx_gpio)
 259                         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 260
 261         } else {
 262                 stm32_usart_clr_bits(port, ofs->cr3,
 263                                      USART_CR3_DEM | USART_CR3_DEP);
 264                 stm32_usart_clr_bits(port, ofs->cr1,
 265                                      USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 266         }
 267
 268         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 269
 270         /* Adjust RTS polarity in case it's driven in software */
 271         if (stm32_usart_tx_empty(port))
 272                 stm32_usart_rs485_rts_disable(port);
 273         else
 274                 stm32_usart_rs485_rts_enable(port);
 275
 276         return 0;
 277 }
 278
 279 static int stm32_usart_init_rs485(struct uart_port *port,
 280                                   struct platform_device *pdev)
 281 {
 282         struct serial_rs485 *rs485conf = &port->rs485;
 283
 284         rs485conf->flags = 0;
 285         rs485conf->delay_rts_before_send = 0;
 286         rs485conf->delay_rts_after_send = 0;
 287
 288         if (!pdev->dev.of_node)
 289                 return -ENODEV;
 290
 291         return uart_get_rs485_mode(port);
 292 }
 293
 294 static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port)
 295 {
 296         return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false;
 297 }
 298
 299 static void stm32_usart_rx_dma_terminate(struct stm32_port *stm32_port)
 300 {
 301         dmaengine_terminate_async(stm32_port->rx_ch);
 302         stm32_port->rx_dma_busy = false;
 303 }
 304
 305 static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port,
 306                                         struct dma_chan *chan,
 307                                         enum dma_status expected_status,
 308                                         int dmaengine_pause_or_resume(struct dma_chan *),
 309                                         bool stm32_usart_xx_dma_started(struct stm32_port *),
 310                                         void stm32_usart_xx_dma_terminate(struct stm32_port *))
 311 {
 312         struct uart_port *port = &stm32_port->port;
 313         enum dma_status dma_status;
 314         int ret;
 315
 316         if (!stm32_usart_xx_dma_started(stm32_port))
 317                 return -EPERM;
 318
 319         dma_status = dmaengine_tx_status(chan, chan->cookie, NULL);
 320         if (dma_status != expected_status)
 321                 return -EAGAIN;
 322
 323         ret = dmaengine_pause_or_resume(chan);
 324         if (ret) {
 325                 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
 326                 stm32_usart_xx_dma_terminate(stm32_port);
 327         }
 328         return ret;
 329 }
 330
 331 static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port)
 332 {
 333         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
 334                                             DMA_IN_PROGRESS, dmaengine_pause,
 335                                             stm32_usart_rx_dma_started,
 336                                             stm32_usart_rx_dma_terminate);
 337 }
 338
 339 static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port)
 340 {
 341         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
 342                                             DMA_PAUSED, dmaengine_resume,
 343                                             stm32_usart_rx_dma_started,
 344                                             stm32_usart_rx_dma_terminate);
 345 }
 346
 347 /* Return true when data is pending (in pio mode), and false when no data is pending. */
 348 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
 349 {
 350         struct stm32_port *stm32_port = to_stm32_port(port);
 351         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 352
 353         *sr = readl_relaxed(port->membase + ofs->isr);
 354         /* Get pending characters in RDR or FIFO */
 355         if (*sr & USART_SR_RXNE) {
 356                 /* Get all pending characters from the RDR or the FIFO when using interrupts */
 357                 if (!stm32_usart_rx_dma_started(stm32_port))
 358                         return true;
 359
 360                 /* Handle only RX data errors when using DMA */
 361                 if (*sr & USART_SR_ERR_MASK)
 362                         return true;
 363         }
 364
 365         return false;
 366 }
 367
 368 static u8 stm32_usart_get_char_pio(struct uart_port *port)
 369 {
 370         struct stm32_port *stm32_port = to_stm32_port(port);
 371         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 372         unsigned long c;
 373
 374         c = readl_relaxed(port->membase + ofs->rdr);
 375         /* Apply RDR data mask */
 376         c &= stm32_port->rdr_mask;
 377
 378         return c;
 379 }
 380
 381 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
 382 {
 383         struct stm32_port *stm32_port = to_stm32_port(port);
 384         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 385         unsigned int size = 0;
 386         u32 sr;
 387         u8 c, flag;
 388
 389         while (stm32_usart_pending_rx_pio(port, &sr)) {
 390                 sr |= USART_SR_DUMMY_RX;
 391                 flag = TTY_NORMAL;
 392
 393                 /*
 394                  * Status bits has to be cleared before reading the RDR:
 395                  * In FIFO mode, reading the RDR will pop the next data
 396                  * (if any) along with its status bits into the SR.
 397                  * Not doing so leads to misalignement between RDR and SR,
 398                  * and clear status bits of the next rx data.
 399                  *
 400                  * Clear errors flags for stm32f7 and stm32h7 compatible
 401                  * devices. On stm32f4 compatible devices, the error bit is
 402                  * cleared by the sequence [read SR - read DR].
 403                  */
 404                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 405                         writel_relaxed(sr & USART_SR_ERR_MASK,
 406                                        port->membase + ofs->icr);
 407
 408                 c = stm32_usart_get_char_pio(port);
 409                 port->icount.rx++;
 410                 size++;
 411                 if (sr & USART_SR_ERR_MASK) {
 412                         if (sr & USART_SR_ORE) {
 413                                 port->icount.overrun++;
 414                         } else if (sr & USART_SR_PE) {
 415                                 port->icount.parity++;
 416                         } else if (sr & USART_SR_FE) {
 417                                 /* Break detection if character is null */
 418                                 if (!c) {
 419                                         port->icount.brk++;
 420                                         if (uart_handle_break(port))
 421                                                 continue;
 422                                 } else {
 423                                         port->icount.frame++;
 424                                 }
 425                         }
 426
 427                         sr &= port->read_status_mask;
 428
 429                         if (sr & USART_SR_PE) {
 430                                 flag = TTY_PARITY;
 431                         } else if (sr & USART_SR_FE) {
 432                                 if (!c)
 433                                         flag = TTY_BREAK;
 434                                 else
 435                                         flag = TTY_FRAME;
 436                         }
 437                 }
 438
 439                 if (uart_prepare_sysrq_char(port, c))
 440                         continue;
 441                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 442         }
 443
 444         return size;
 445 }
 446
 447 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size)
 448 {
 449         struct stm32_port *stm32_port = to_stm32_port(port);
 450         struct tty_port *ttyport = &stm32_port->port.state->port;
 451         unsigned char *dma_start;
 452         int dma_count, i;
 453
 454         dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
 455
 456         /*
 457          * Apply rdr_mask on buffer in order to mask parity bit.
 458          * This loop is useless in cs8 mode because DMA copies only
 459          * 8 bits and already ignores parity bit.
 460          */
 461         if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
 462                 for (i = 0; i < dma_size; i++)
 463                         *(dma_start + i) &= stm32_port->rdr_mask;
 464
 465         dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size);
 466         port->icount.rx += dma_count;
 467         if (dma_count != dma_size)
 468                 port->icount.buf_overrun++;
 469         stm32_port->last_res -= dma_count;
 470         if (stm32_port->last_res == 0)
 471                 stm32_port->last_res = RX_BUF_L;
 472 }
 473
 474 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port)
 475 {
 476         struct stm32_port *stm32_port = to_stm32_port(port);
 477         unsigned int dma_size, size = 0;
 478
 479         /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */
 480         if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
 481                 /* Conditional first part: from last_res to end of DMA buffer */
 482                 dma_size = stm32_port->last_res;
 483                 stm32_usart_push_buffer_dma(port, dma_size);
 484                 size = dma_size;
 485         }
 486
 487         dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
 488         stm32_usart_push_buffer_dma(port, dma_size);
 489         size += dma_size;
 490
 491         return size;
 492 }
 493
 494 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush)
 495 {
 496         struct stm32_port *stm32_port = to_stm32_port(port);
 497         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 498         enum dma_status rx_dma_status;
 499         u32 sr;
 500         unsigned int size = 0;
 501
 502         if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) {
 503                 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
 504                                                     stm32_port->rx_ch->cookie,
 505                                                     &stm32_port->rx_dma_state);
 506                 if (rx_dma_status == DMA_IN_PROGRESS ||
 507                     rx_dma_status == DMA_PAUSED) {
 508                         /* Empty DMA buffer */
 509                         size = stm32_usart_receive_chars_dma(port);
 510                         sr = readl_relaxed(port->membase + ofs->isr);
 511                         if (sr & USART_SR_ERR_MASK) {
 512                                 /* Disable DMA request line */
 513                                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 514
 515                                 /* Switch to PIO mode to handle the errors */
 516                                 size += stm32_usart_receive_chars_pio(port);
 517
 518                                 /* Switch back to DMA mode */
 519                                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
 520                         }
 521                 } else {
 522                         /* Disable RX DMA */
 523                         stm32_usart_rx_dma_terminate(stm32_port);
 524                         /* Fall back to interrupt mode */
 525                         dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
 526                         size = stm32_usart_receive_chars_pio(port);
 527                 }
 528         } else {
 529                 size = stm32_usart_receive_chars_pio(port);
 530         }
 531
 532         return size;
 533 }
 534
 535 static void stm32_usart_rx_dma_complete(void *arg)
 536 {
 537         struct uart_port *port = arg;
 538         struct tty_port *tport = &port->state->port;
 539         unsigned int size;
 540         unsigned long flags;
 541
 542         uart_port_lock_irqsave(port, &flags);
 543         size = stm32_usart_receive_chars(port, false);
 544         uart_unlock_and_check_sysrq_irqrestore(port, flags);
 545         if (size)
 546                 tty_flip_buffer_push(tport);
 547 }
 548
 549 static int stm32_usart_rx_dma_start_or_resume(struct uart_port *port)
 550 {
 551         struct stm32_port *stm32_port = to_stm32_port(port);
 552         struct dma_async_tx_descriptor *desc;
 553         enum dma_status rx_dma_status;
 554         int ret;
 555
 556         if (stm32_port->throttled)
 557                 return 0;
 558
 559         if (stm32_port->rx_dma_busy) {
 560                 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
 561                                                     stm32_port->rx_ch->cookie,
 562                                                     NULL);
 563                 if (rx_dma_status == DMA_IN_PROGRESS)
 564                         return 0;
 565
 566                 if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port))
 567                         return 0;
 568
 569                 dev_err(port->dev, "DMA failed : status error.\n");
 570                 stm32_usart_rx_dma_terminate(stm32_port);
 571         }
 572
 573         stm32_port->rx_dma_busy = true;
 574
 575         stm32_port->last_res = RX_BUF_L;
 576         /* Prepare a DMA cyclic transaction */
 577         desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
 578                                          stm32_port->rx_dma_buf,
 579                                          RX_BUF_L, RX_BUF_P,
 580                                          DMA_DEV_TO_MEM,
 581                                          DMA_PREP_INTERRUPT);
 582         if (!desc) {
 583                 dev_err(port->dev, "rx dma prep cyclic failed\n");
 584                 stm32_port->rx_dma_busy = false;
 585                 return -ENODEV;
 586         }
 587
 588         desc->callback = stm32_usart_rx_dma_complete;
 589         desc->callback_param = port;
 590
 591         /* Push current DMA transaction in the pending queue */
 592         ret = dma_submit_error(dmaengine_submit(desc));
 593         if (ret) {
 594                 dmaengine_terminate_sync(stm32_port->rx_ch);
 595                 stm32_port->rx_dma_busy = false;
 596                 return ret;
 597         }
 598
 599         /* Issue pending DMA requests */
 600         dma_async_issue_pending(stm32_port->rx_ch);
 601
 602         return 0;
 603 }
 604
 605 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
 606 {
 607         dmaengine_terminate_async(stm32_port->tx_ch);
 608         stm32_port->tx_dma_busy = false;
 609 }
 610
 611 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
 612 {
 613         /*
 614          * We cannot use the function "dmaengine_tx_status" to know the
 615          * status of DMA. This function does not show if the "dma complete"
 616          * callback of the DMA transaction has been called. So we prefer
 617          * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
 618          * same time.
 619          */
 620         return stm32_port->tx_dma_busy;
 621 }
 622
 623 static int stm32_usart_tx_dma_pause(struct stm32_port *stm32_port)
 624 {
 625         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
 626                                             DMA_IN_PROGRESS, dmaengine_pause,
 627                                             stm32_usart_tx_dma_started,
 628                                             stm32_usart_tx_dma_terminate);
 629 }
 630
 631 static int stm32_usart_tx_dma_resume(struct stm32_port *stm32_port)
 632 {
 633         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
 634                                             DMA_PAUSED, dmaengine_resume,
 635                                             stm32_usart_tx_dma_started,
 636                                             stm32_usart_tx_dma_terminate);
 637 }
 638
 639 static void stm32_usart_tx_dma_complete(void *arg)
 640 {
 641         struct uart_port *port = arg;
 642         struct stm32_port *stm32port = to_stm32_port(port);
 643         unsigned long flags;
 644
 645         stm32_usart_tx_dma_terminate(stm32port);
 646
 647         /* Let's see if we have pending data to send */
 648         uart_port_lock_irqsave(port, &flags);
 649         stm32_usart_transmit_chars(port);
 650         uart_port_unlock_irqrestore(port, flags);
 651 }
 652
 653 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
 654 {
 655         struct stm32_port *stm32_port = to_stm32_port(port);
 656         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 657
 658         /*
 659          * Enables TX FIFO threashold irq when FIFO is enabled,
 660          * or TX empty irq when FIFO is disabled
 661          */
 662         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 663                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 664         else
 665                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 666 }
 667
 668 static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
 669 {
 670         struct stm32_port *stm32_port = to_stm32_port(port);
 671         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 672
 673         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
 674 }
 675
 676 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
 677 {
 678         struct stm32_port *stm32_port = to_stm32_port(port);
 679         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 680
 681         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 682                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 683         else
 684                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 685 }
 686
 687 static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
 688 {
 689         struct stm32_port *stm32_port = to_stm32_port(port);
 690         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 691
 692         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
 693 }
 694
 695 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
 696 {
 697         struct stm32_port *stm32_port = to_stm32_port(port);
 698         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 699         struct circ_buf *xmit = &port->state->xmit;
 700
 701         while (!uart_circ_empty(xmit)) {
 702                 /* Check that TDR is empty before filling FIFO */
 703                 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 704                         break;
 705                 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 706                 uart_xmit_advance(port, 1);
 707         }
 708
 709         /* rely on TXE irq (mask or unmask) for sending remaining data */
 710         if (uart_circ_empty(xmit))
 711                 stm32_usart_tx_interrupt_disable(port);
 712         else
 713                 stm32_usart_tx_interrupt_enable(port);
 714 }
 715
 716 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
 717 {
 718         struct stm32_port *stm32port = to_stm32_port(port);
 719         struct circ_buf *xmit = &port->state->xmit;
 720         struct dma_async_tx_descriptor *desc = NULL;
 721         unsigned int count;
 722         int ret;
 723
 724         if (stm32_usart_tx_dma_started(stm32port)) {
 725                 ret = stm32_usart_tx_dma_resume(stm32port);
 726                 if (ret < 0 && ret != -EAGAIN)
 727                         goto fallback_err;
 728                 return;
 729         }
 730
 731         count = uart_circ_chars_pending(xmit);
 732
 733         if (count > TX_BUF_L)
 734                 count = TX_BUF_L;
 735
 736         if (xmit->tail < xmit->head) {
 737                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 738         } else {
 739                 size_t one = UART_XMIT_SIZE - xmit->tail;
 740                 size_t two;
 741
 742                 if (one > count)
 743                         one = count;
 744                 two = count - one;
 745
 746                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 747                 if (two)
 748                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 749         }
 750
 751         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 752                                            stm32port->tx_dma_buf,
 753                                            count,
 754                                            DMA_MEM_TO_DEV,
 755                                            DMA_PREP_INTERRUPT);
 756
 757         if (!desc)
 758                 goto fallback_err;
 759
 760         /*
 761          * Set "tx_dma_busy" flag. This flag will be released when
 762          * dmaengine_terminate_async will be called. This flag helps
 763          * transmit_chars_dma not to start another DMA transaction
 764          * if the callback of the previous is not yet called.
 765          */
 766         stm32port->tx_dma_busy = true;
 767
 768         desc->callback = stm32_usart_tx_dma_complete;
 769         desc->callback_param = port;
 770
 771         /* Push current DMA TX transaction in the pending queue */
 772         /* DMA no yet started, safe to free resources */
 773         ret = dma_submit_error(dmaengine_submit(desc));
 774         if (ret) {
 775                 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
 776                 stm32_usart_tx_dma_terminate(stm32port);
 777                 goto fallback_err;
 778         }
 779
 780         /* Issue pending DMA TX requests */
 781         dma_async_issue_pending(stm32port->tx_ch);
 782
 783         uart_xmit_advance(port, count);
 784
 785         return;
 786
 787 fallback_err:
 788         stm32_usart_transmit_chars_pio(port);
 789 }
 790
 791 static void stm32_usart_transmit_chars(struct uart_port *port)
 792 {
 793         struct stm32_port *stm32_port = to_stm32_port(port);
 794         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 795         struct circ_buf *xmit = &port->state->xmit;
 796         u32 isr;
 797         int ret;
 798
 799         if (!stm32_port->hw_flow_control &&
 800             port->rs485.flags & SER_RS485_ENABLED &&
 801             (port->x_char ||
 802              !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) {
 803                 stm32_usart_tc_interrupt_disable(port);
 804                 stm32_usart_rs485_rts_enable(port);
 805         }
 806
 807         if (port->x_char) {
 808                 /* dma terminate may have been called in case of dma pause failure */
 809                 stm32_usart_tx_dma_pause(stm32_port);
 810
 811                 /* Check that TDR is empty before filling FIFO */
 812                 ret =
 813                 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 814                                                   isr,
 815                                                   (isr & USART_SR_TXE),
 816                                                   10, 1000);
 817                 if (ret)
 818                         dev_warn(port->dev, "1 character may be erased\n");
 819
 820                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 821                 port->x_char = 0;
 822                 port->icount.tx++;
 823
 824                 /* dma terminate may have been called in case of dma resume failure */
 825                 stm32_usart_tx_dma_resume(stm32_port);
 826                 return;
 827         }
 828
 829         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 830                 stm32_usart_tx_interrupt_disable(port);
 831                 return;
 832         }
 833
 834         if (ofs->icr == UNDEF_REG)
 835                 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
 836         else
 837                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 838
 839         if (stm32_port->tx_ch)
 840                 stm32_usart_transmit_chars_dma(port);
 841         else
 842                 stm32_usart_transmit_chars_pio(port);
 843
 844         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 845                 uart_write_wakeup(port);
 846
 847         if (uart_circ_empty(xmit)) {
 848                 stm32_usart_tx_interrupt_disable(port);
 849                 if (!stm32_port->hw_flow_control &&
 850                     port->rs485.flags & SER_RS485_ENABLED) {
 851                         stm32_usart_tc_interrupt_enable(port);
 852                 }
 853         }
 854 }
 855
 856 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
 857 {
 858         struct uart_port *port = ptr;
 859         struct tty_port *tport = &port->state->port;
 860         struct stm32_port *stm32_port = to_stm32_port(port);
 861         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 862         u32 sr;
 863         unsigned int size;
 864
 865         sr = readl_relaxed(port->membase + ofs->isr);
 866
 867         if (!stm32_port->hw_flow_control &&
 868             port->rs485.flags & SER_RS485_ENABLED &&
 869             (sr & USART_SR_TC)) {
 870                 stm32_usart_tc_interrupt_disable(port);
 871                 stm32_usart_rs485_rts_disable(port);
 872         }
 873
 874         if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
 875                 writel_relaxed(USART_ICR_RTOCF,
 876                                port->membase + ofs->icr);
 877
 878         if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
 879                 /* Clear wake up flag and disable wake up interrupt */
 880                 writel_relaxed(USART_ICR_WUCF,
 881                                port->membase + ofs->icr);
 882                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
 883                 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 884                         pm_wakeup_event(tport->tty->dev, 0);
 885         }
 886
 887         /*
 888          * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
 889          * line has been masked by HW and rx data are stacking in FIFO.
 890          */
 891         if (!stm32_port->throttled) {
 892                 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
 893                     ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
 894                         uart_port_lock(port);
 895                         size = stm32_usart_receive_chars(port, false);
 896                         uart_unlock_and_check_sysrq(port);
 897                         if (size)
 898                                 tty_flip_buffer_push(tport);
 899                 }
 900         }
 901
 902         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
 903                 uart_port_lock(port);
 904                 stm32_usart_transmit_chars(port);
 905                 uart_port_unlock(port);
 906         }
 907
 908         /* Receiver timeout irq for DMA RX */
 909         if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
 910                 uart_port_lock(port);
 911                 size = stm32_usart_receive_chars(port, false);
 912                 uart_unlock_and_check_sysrq(port);
 913                 if (size)
 914                         tty_flip_buffer_push(tport);
 915         }
 916
 917         return IRQ_HANDLED;
 918 }
 919
 920 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 921 {
 922         struct stm32_port *stm32_port = to_stm32_port(port);
 923         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 924
 925         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 926                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 927         else
 928                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 929
 930         mctrl_gpio_set(stm32_port->gpios, mctrl);
 931 }
 932
 933 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
 934 {
 935         struct stm32_port *stm32_port = to_stm32_port(port);
 936         unsigned int ret;
 937
 938         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 939         ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 940
 941         return mctrl_gpio_get(stm32_port->gpios, &ret);
 942 }
 943
 944 static void stm32_usart_enable_ms(struct uart_port *port)
 945 {
 946         mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
 947 }
 948
 949 static void stm32_usart_disable_ms(struct uart_port *port)
 950 {
 951         mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
 952 }
 953
 954 /* Transmit stop */
 955 static void stm32_usart_stop_tx(struct uart_port *port)
 956 {
 957         struct stm32_port *stm32_port = to_stm32_port(port);
 958
 959         stm32_usart_tx_interrupt_disable(port);
 960
 961         /* dma terminate may have been called in case of dma pause failure */
 962         stm32_usart_tx_dma_pause(stm32_port);
 963
 964         stm32_usart_rs485_rts_disable(port);
 965 }
 966
 967 /* There are probably characters waiting to be transmitted. */
 968 static void stm32_usart_start_tx(struct uart_port *port)
 969 {
 970         struct circ_buf *xmit = &port->state->xmit;
 971
 972         if (uart_circ_empty(xmit) && !port->x_char) {
 973                 stm32_usart_rs485_rts_disable(port);
 974                 return;
 975         }
 976
 977         stm32_usart_rs485_rts_enable(port);
 978
 979         stm32_usart_transmit_chars(port);
 980 }
 981
 982 /* Flush the transmit buffer. */
 983 static void stm32_usart_flush_buffer(struct uart_port *port)
 984 {
 985         struct stm32_port *stm32_port = to_stm32_port(port);
 986
 987         if (stm32_port->tx_ch)
 988                 stm32_usart_tx_dma_terminate(stm32_port);
 989 }
 990
 991 /* Throttle the remote when input buffer is about to overflow. */
 992 static void stm32_usart_throttle(struct uart_port *port)
 993 {
 994         struct stm32_port *stm32_port = to_stm32_port(port);
 995         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 996         unsigned long flags;
 997
 998         uart_port_lock_irqsave(port, &flags);
 999
1000         /*
1001          * Pause DMA transfer, so the RX data gets queued into the FIFO.
1002          * Hardware flow control is triggered when RX FIFO is full.
1003          */
1004         stm32_usart_rx_dma_pause(stm32_port);
1005
1006         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1007         if (stm32_port->cr3_irq)
1008                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1009
1010         stm32_port->throttled = true;
1011         uart_port_unlock_irqrestore(port, flags);
1012 }
1013
1014 /* Unthrottle the remote, the input buffer can now accept data. */
1015 static void stm32_usart_unthrottle(struct uart_port *port)
1016 {
1017         struct stm32_port *stm32_port = to_stm32_port(port);
1018         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1019         unsigned long flags;
1020
1021         uart_port_lock_irqsave(port, &flags);
1022         stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
1023         if (stm32_port->cr3_irq)
1024                 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
1025
1026         stm32_port->throttled = false;
1027
1028         /*
1029          * Switch back to DMA mode (resume DMA).
1030          * Hardware flow control is stopped when FIFO is not full any more.
1031          */
1032         if (stm32_port->rx_ch)
1033                 stm32_usart_rx_dma_start_or_resume(port);
1034
1035         uart_port_unlock_irqrestore(port, flags);
1036 }
1037
1038 /* Receive stop */
1039 static void stm32_usart_stop_rx(struct uart_port *port)
1040 {
1041         struct stm32_port *stm32_port = to_stm32_port(port);
1042         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1043
1044         /* Disable DMA request line. */
1045         stm32_usart_rx_dma_pause(stm32_port);
1046
1047         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1048         if (stm32_port->cr3_irq)
1049                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1050 }
1051
1052 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
1053 {
1054         struct stm32_port *stm32_port = to_stm32_port(port);
1055         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1056         unsigned long flags;
1057
1058         spin_lock_irqsave(&port->lock, flags);
1059
1060         if (break_state)
1061                 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1062         else
1063                 stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1064
1065         spin_unlock_irqrestore(&port->lock, flags);
1066 }
1067
1068 static int stm32_usart_startup(struct uart_port *port)
1069 {
1070         struct stm32_port *stm32_port = to_stm32_port(port);
1071         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1072         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1073         const char *name = to_platform_device(port->dev)->name;
1074         u32 val;
1075         int ret;
1076
1077         ret = request_irq(port->irq, stm32_usart_interrupt,
1078                           IRQF_NO_SUSPEND, name, port);
1079         if (ret)
1080                 return ret;
1081
1082         if (stm32_port->swap) {
1083                 val = readl_relaxed(port->membase + ofs->cr2);
1084                 val |= USART_CR2_SWAP;
1085                 writel_relaxed(val, port->membase + ofs->cr2);
1086         }
1087
1088         /* RX FIFO Flush */
1089         if (ofs->rqr != UNDEF_REG)
1090                 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
1091
1092         if (stm32_port->rx_ch) {
1093                 ret = stm32_usart_rx_dma_start_or_resume(port);
1094                 if (ret) {
1095                         free_irq(port->irq, port);
1096                         return ret;
1097                 }
1098         }
1099
1100         /* RX enabling */
1101         val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
1102         stm32_usart_set_bits(port, ofs->cr1, val);
1103
1104         return 0;
1105 }
1106
1107 static void stm32_usart_shutdown(struct uart_port *port)
1108 {
1109         struct stm32_port *stm32_port = to_stm32_port(port);
1110         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1111         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1112         u32 val, isr;
1113         int ret;
1114
1115         if (stm32_usart_tx_dma_started(stm32_port))
1116                 stm32_usart_tx_dma_terminate(stm32_port);
1117
1118         if (stm32_port->tx_ch)
1119                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1120
1121         /* Disable modem control interrupts */
1122         stm32_usart_disable_ms(port);
1123
1124         val = USART_CR1_TXEIE | USART_CR1_TE;
1125         val |= stm32_port->cr1_irq | USART_CR1_RE;
1126         val |= BIT(cfg->uart_enable_bit);
1127         if (stm32_port->fifoen)
1128                 val |= USART_CR1_FIFOEN;
1129
1130         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
1131                                          isr, (isr & USART_SR_TC),
1132                                          10, 100000);
1133
1134         /* Send the TC error message only when ISR_TC is not set */
1135         if (ret)
1136                 dev_err(port->dev, "Transmission is not complete\n");
1137
1138         /* Disable RX DMA. */
1139         if (stm32_port->rx_ch) {
1140                 stm32_usart_rx_dma_terminate(stm32_port);
1141                 dmaengine_synchronize(stm32_port->rx_ch);
1142         }
1143
1144         /* flush RX & TX FIFO */
1145         if (ofs->rqr != UNDEF_REG)
1146                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1147                                port->membase + ofs->rqr);
1148
1149         stm32_usart_clr_bits(port, ofs->cr1, val);
1150
1151         free_irq(port->irq, port);
1152 }
1153
1154 static const unsigned int stm32_usart_presc_val[] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
1155
1156 static void stm32_usart_set_termios(struct uart_port *port,
1157                                     struct ktermios *termios,
1158                                     const struct ktermios *old)
1159 {
1160         struct stm32_port *stm32_port = to_stm32_port(port);
1161         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1162         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1163         struct serial_rs485 *rs485conf = &port->rs485;
1164         unsigned int baud, bits, uart_clk, uart_clk_pres;
1165         u32 usartdiv, mantissa, fraction, oversampling;
1166         tcflag_t cflag = termios->c_cflag;
1167         u32 cr1, cr2, cr3, isr, brr, presc;
1168         unsigned long flags;
1169         int ret;
1170
1171         if (!stm32_port->hw_flow_control)
1172                 cflag &= ~CRTSCTS;
1173
1174         uart_clk = clk_get_rate(stm32_port->clk);
1175
1176         baud = uart_get_baud_rate(port, termios, old, 0, uart_clk / 8);
1177
1178         uart_port_lock_irqsave(port, &flags);
1179
1180         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
1181                                                 isr,
1182                                                 (isr & USART_SR_TC),
1183                                                 10, 100000);
1184
1185         /* Send the TC error message only when ISR_TC is not set. */
1186         if (ret)
1187                 dev_err(port->dev, "Transmission is not complete\n");
1188
1189         /* Stop serial port and reset value */
1190         writel_relaxed(0, port->membase + ofs->cr1);
1191
1192         /* flush RX & TX FIFO */
1193         if (ofs->rqr != UNDEF_REG)
1194                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1195                                port->membase + ofs->rqr);
1196
1197         cr1 = USART_CR1_TE | USART_CR1_RE;
1198         if (stm32_port->fifoen)
1199                 cr1 |= USART_CR1_FIFOEN;
1200         cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1201
1202         /* Tx and RX FIFO configuration */
1203         cr3 = readl_relaxed(port->membase + ofs->cr3);
1204         cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
1205         if (stm32_port->fifoen) {
1206                 if (stm32_port->txftcfg >= 0)
1207                         cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1208                 if (stm32_port->rxftcfg >= 0)
1209                         cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1210         }
1211
1212         if (cflag & CSTOPB)
1213                 cr2 |= USART_CR2_STOP_2B;
1214
1215         bits = tty_get_char_size(cflag);
1216         stm32_port->rdr_mask = (BIT(bits) - 1);
1217
1218         if (cflag & PARENB) {
1219                 bits++;
1220                 cr1 |= USART_CR1_PCE;
1221         }
1222
1223         /*
1224          * Word length configuration:
1225          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
1226          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
1227          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1228          * M0 and M1 already cleared by cr1 initialization.
1229          */
1230         if (bits == 9) {
1231                 cr1 |= USART_CR1_M0;
1232         } else if ((bits == 7) && cfg->has_7bits_data) {
1233                 cr1 |= USART_CR1_M1;
1234         } else if (bits != 8) {
1235                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1236                         , bits);
1237                 cflag &= ~CSIZE;
1238                 cflag |= CS8;
1239                 termios->c_cflag = cflag;
1240                 bits = 8;
1241                 if (cflag & PARENB) {
1242                         bits++;
1243                         cr1 |= USART_CR1_M0;
1244                 }
1245         }
1246
1247         if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1248                                        (stm32_port->fifoen &&
1249                                         stm32_port->rxftcfg >= 0))) {
1250                 if (cflag & CSTOPB)
1251                         bits = bits + 3; /* 1 start bit + 2 stop bits */
1252                 else
1253                         bits = bits + 2; /* 1 start bit + 1 stop bit */
1254
1255                 /* RX timeout irq to occur after last stop bit + bits */
1256                 stm32_port->cr1_irq = USART_CR1_RTOIE;
1257                 writel_relaxed(bits, port->membase + ofs->rtor);
1258                 cr2 |= USART_CR2_RTOEN;
1259                 /*
1260                  * Enable fifo threshold irq in two cases, either when there is no DMA, or when
1261                  * wake up over usart, from low power until the DMA gets re-enabled by resume.
1262                  */
1263                 stm32_port->cr3_irq =  USART_CR3_RXFTIE;
1264         }
1265
1266         cr1 |= stm32_port->cr1_irq;
1267         cr3 |= stm32_port->cr3_irq;
1268
1269         if (cflag & PARODD)
1270                 cr1 |= USART_CR1_PS;
1271
1272         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1273         if (cflag & CRTSCTS) {
1274                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1275                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
1276         }
1277
1278         for (presc = 0; presc <= USART_PRESC_MAX; presc++) {
1279                 uart_clk_pres = DIV_ROUND_CLOSEST(uart_clk, stm32_usart_presc_val[presc]);
1280                 usartdiv = DIV_ROUND_CLOSEST(uart_clk_pres, baud);
1281
1282                 /*
1283                  * The USART supports 16 or 8 times oversampling.
1284                  * By default we prefer 16 times oversampling, so that the receiver
1285                  * has a better tolerance to clock deviations.
1286                  * 8 times oversampling is only used to achieve higher speeds.
1287                  */
1288                 if (usartdiv < 16) {
1289                         oversampling = 8;
1290                         cr1 |= USART_CR1_OVER8;
1291                         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1292                 } else {
1293                         oversampling = 16;
1294                         cr1 &= ~USART_CR1_OVER8;
1295                         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1296                 }
1297
1298                 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
1299                 fraction = usartdiv % oversampling;
1300                 brr = mantissa | fraction;
1301
1302                 if (FIELD_FIT(USART_BRR_MASK, brr)) {
1303                         if (ofs->presc != UNDEF_REG) {
1304                                 port->uartclk = uart_clk_pres;
1305                                 writel_relaxed(presc, port->membase + ofs->presc);
1306                         } else if (presc) {
1307                                 /* We need a prescaler but we don't have it (STM32F4, STM32F7) */
1308                                 dev_err(port->dev,
1309                                         "unable to set baudrate, input clock is too high");
1310                         }
1311                         break;
1312                 } else if (presc == USART_PRESC_MAX) {
1313                         /* Even with prescaler and brr at max value we can't set baudrate */
1314                         dev_err(port->dev, "unable to set baudrate, input clock is too high");
1315                         break;
1316                 }
1317         }
1318
1319         writel_relaxed(brr, port->membase + ofs->brr);
1320
1321         uart_update_timeout(port, cflag, baud);
1322
1323         port->read_status_mask = USART_SR_ORE;
1324         if (termios->c_iflag & INPCK)
1325                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
1326         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1327                 port->read_status_mask |= USART_SR_FE;
1328
1329         /* Characters to ignore */
1330         port->ignore_status_mask = 0;
1331         if (termios->c_iflag & IGNPAR)
1332                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
1333         if (termios->c_iflag & IGNBRK) {
1334                 port->ignore_status_mask |= USART_SR_FE;
1335                 /*
1336                  * If we're ignoring parity and break indicators,
1337                  * ignore overruns too (for real raw support).
1338                  */
1339                 if (termios->c_iflag & IGNPAR)
1340                         port->ignore_status_mask |= USART_SR_ORE;
1341         }
1342
1343         /* Ignore all characters if CREAD is not set */
1344         if ((termios->c_cflag & CREAD) == 0)
1345                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
1346
1347         if (stm32_port->rx_ch) {
1348                 /*
1349                  * Setup DMA to collect only valid data and enable error irqs.
1350                  * This also enables break reception when using DMA.
1351                  */
1352                 cr1 |= USART_CR1_PEIE;
1353                 cr3 |= USART_CR3_EIE;
1354                 cr3 |= USART_CR3_DMAR;
1355                 cr3 |= USART_CR3_DDRE;
1356         }
1357
1358         if (stm32_port->tx_ch)
1359                 cr3 |= USART_CR3_DMAT;
1360
1361         if (rs485conf->flags & SER_RS485_ENABLED) {
1362                 stm32_usart_config_reg_rs485(&cr1, &cr3,
1363                                              rs485conf->delay_rts_before_send,
1364                                              rs485conf->delay_rts_after_send,
1365                                              baud);
1366                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1367                         cr3 &= ~USART_CR3_DEP;
1368                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1369                 } else {
1370                         cr3 |= USART_CR3_DEP;
1371                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1372                 }
1373
1374         } else {
1375                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
1376                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1377         }
1378
1379         /* Configure wake up from low power on start bit detection */
1380         if (stm32_port->wakeup_src) {
1381                 cr3 &= ~USART_CR3_WUS_MASK;
1382                 cr3 |= USART_CR3_WUS_START_BIT;
1383         }
1384
1385         writel_relaxed(cr3, port->membase + ofs->cr3);
1386         writel_relaxed(cr2, port->membase + ofs->cr2);
1387         writel_relaxed(cr1, port->membase + ofs->cr1);
1388
1389         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1390         uart_port_unlock_irqrestore(port, flags);
1391
1392         /* Handle modem control interrupts */
1393         if (UART_ENABLE_MS(port, termios->c_cflag))
1394                 stm32_usart_enable_ms(port);
1395         else
1396                 stm32_usart_disable_ms(port);
1397 }
1398
1399 static const char *stm32_usart_type(struct uart_port *port)
1400 {
1401         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
1402 }
1403
1404 static void stm32_usart_release_port(struct uart_port *port)
1405 {
1406 }
1407
1408 static int stm32_usart_request_port(struct uart_port *port)
1409 {
1410         return 0;
1411 }
1412
1413 static void stm32_usart_config_port(struct uart_port *port, int flags)
1414 {
1415         if (flags & UART_CONFIG_TYPE)
1416                 port->type = PORT_STM32;
1417 }
1418
1419 static int
1420 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
1421 {
1422         /* No user changeable parameters */
1423         return -EINVAL;
1424 }
1425
1426 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
1427                            unsigned int oldstate)
1428 {
1429         struct stm32_port *stm32port = container_of(port,
1430                         struct stm32_port, port);
1431         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1432         const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1433         unsigned long flags;
1434
1435         switch (state) {
1436         case UART_PM_STATE_ON:
1437                 pm_runtime_get_sync(port->dev);
1438                 break;
1439         case UART_PM_STATE_OFF:
1440                 uart_port_lock_irqsave(port, &flags);
1441                 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1442                 uart_port_unlock_irqrestore(port, flags);
1443                 pm_runtime_put_sync(port->dev);
1444                 break;
1445         }
1446 }
1447
1448 #if defined(CONFIG_CONSOLE_POLL)
1449
1450  /* Callbacks for characters polling in debug context (i.e. KGDB). */
1451 static int stm32_usart_poll_init(struct uart_port *port)
1452 {
1453         struct stm32_port *stm32_port = to_stm32_port(port);
1454
1455         return clk_prepare_enable(stm32_port->clk);
1456 }
1457
1458 static int stm32_usart_poll_get_char(struct uart_port *port)
1459 {
1460         struct stm32_port *stm32_port = to_stm32_port(port);
1461         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1462
1463         if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1464                 return NO_POLL_CHAR;
1465
1466         return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1467 }
1468
1469 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
1470 {
1471         stm32_usart_console_putchar(port, ch);
1472 }
1473 #endif /* CONFIG_CONSOLE_POLL */
1474
1475 static const struct uart_ops stm32_uart_ops = {
1476         .tx_empty       = stm32_usart_tx_empty,
1477         .set_mctrl      = stm32_usart_set_mctrl,
1478         .get_mctrl      = stm32_usart_get_mctrl,
1479         .stop_tx        = stm32_usart_stop_tx,
1480         .start_tx       = stm32_usart_start_tx,
1481         .throttle       = stm32_usart_throttle,
1482         .unthrottle     = stm32_usart_unthrottle,
1483         .stop_rx        = stm32_usart_stop_rx,
1484         .enable_ms      = stm32_usart_enable_ms,
1485         .break_ctl      = stm32_usart_break_ctl,
1486         .startup        = stm32_usart_startup,
1487         .shutdown       = stm32_usart_shutdown,
1488         .flush_buffer   = stm32_usart_flush_buffer,
1489         .set_termios    = stm32_usart_set_termios,
1490         .pm             = stm32_usart_pm,
1491         .type           = stm32_usart_type,
1492         .release_port   = stm32_usart_release_port,
1493         .request_port   = stm32_usart_request_port,
1494         .config_port    = stm32_usart_config_port,
1495         .verify_port    = stm32_usart_verify_port,
1496 #if defined(CONFIG_CONSOLE_POLL)
1497         .poll_init      = stm32_usart_poll_init,
1498         .poll_get_char  = stm32_usart_poll_get_char,
1499         .poll_put_char  = stm32_usart_poll_put_char,
1500 #endif /* CONFIG_CONSOLE_POLL */
1501 };
1502
1503 struct stm32_usart_thresh_ratio {
1504         int mul;
1505         int div;
1506 };
1507
1508 static const struct stm32_usart_thresh_ratio stm32h7_usart_fifo_thresh_cfg[] = {
1509         {1, 8}, {1, 4}, {1, 2}, {3, 4}, {7, 8}, {1, 1} };
1510
1511 static int stm32_usart_get_thresh_value(u32 fifo_size, int index)
1512 {
1513         return fifo_size * stm32h7_usart_fifo_thresh_cfg[index].mul /
1514                 stm32h7_usart_fifo_thresh_cfg[index].div;
1515 }
1516
1517 static int stm32_usart_get_ftcfg(struct platform_device *pdev, struct stm32_port *stm32port,
1518                                  const char *p, int *ftcfg)
1519 {
1520         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1521         u32 bytes, i, cfg8;
1522         int fifo_size;
1523
1524         if (WARN_ON(ofs->hwcfgr1 == UNDEF_REG))
1525                 return 1;
1526
1527         cfg8 = FIELD_GET(USART_HWCFGR1_CFG8,
1528                          readl_relaxed(stm32port->port.membase + ofs->hwcfgr1));
1529
1530         /* On STM32H7, hwcfgr is not present, so returned value will be 0 */
1531         fifo_size = cfg8 ? 1 << cfg8 : STM32H7_USART_FIFO_SIZE;
1532
1533         /* DT option to get RX & TX FIFO threshold (default to half fifo size) */
1534         if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1535                 bytes = fifo_size / 2;
1536
1537         if (bytes < stm32_usart_get_thresh_value(fifo_size, 0)) {
1538                 *ftcfg = -EINVAL;
1539                 return fifo_size;
1540         }
1541
1542         for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++) {
1543                 if (stm32_usart_get_thresh_value(fifo_size, i) >= bytes)
1544                         break;
1545         }
1546         if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1547                 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1548
1549         dev_dbg(&pdev->dev, "%s set to %d/%d bytes\n", p,
1550                 stm32_usart_get_thresh_value(fifo_size, i), fifo_size);
1551
1552         *ftcfg = i;
1553         return fifo_size;
1554 }
1555
1556 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1557 {
1558         clk_disable_unprepare(stm32port->clk);
1559 }
1560
1561 static const struct serial_rs485 stm32_rs485_supported = {
1562         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1563                  SER_RS485_RX_DURING_TX,
1564         .delay_rts_before_send = 1,
1565         .delay_rts_after_send = 1,
1566 };
1567
1568 static int stm32_usart_init_port(struct stm32_port *stm32port,
1569                                  struct platform_device *pdev)
1570 {
1571         struct uart_port *port = &stm32port->port;
1572         struct resource *res;
1573         int ret, irq;
1574
1575         irq = platform_get_irq(pdev, 0);
1576         if (irq < 0)
1577                 return irq;
1578
1579         port->iotype    = UPIO_MEM;
1580         port->flags     = UPF_BOOT_AUTOCONF;
1581         port->ops       = &stm32_uart_ops;
1582         port->dev       = &pdev->dev;
1583         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1584         port->irq = irq;
1585         port->rs485_config = stm32_usart_config_rs485;
1586         port->rs485_supported = stm32_rs485_supported;
1587
1588         ret = stm32_usart_init_rs485(port, pdev);
1589         if (ret)
1590                 return ret;
1591
1592         stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1593                 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1594
1595         stm32port->swap = stm32port->info->cfg.has_swap &&
1596                 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1597
1598         port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1599         if (IS_ERR(port->membase))
1600                 return PTR_ERR(port->membase);
1601         port->mapbase = res->start;
1602
1603         spin_lock_init(&port->lock);
1604
1605         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1606         if (IS_ERR(stm32port->clk))
1607                 return PTR_ERR(stm32port->clk);
1608
1609         /* Ensure that clk rate is correct by enabling the clk */
1610         ret = clk_prepare_enable(stm32port->clk);
1611         if (ret)
1612                 return ret;
1613
1614         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1615         if (!stm32port->port.uartclk) {
1616                 ret = -EINVAL;
1617                 goto err_clk;
1618         }
1619
1620         stm32port->fifoen = stm32port->info->cfg.has_fifo;
1621         if (stm32port->fifoen) {
1622                 stm32_usart_get_ftcfg(pdev, stm32port, "rx-threshold", &stm32port->rxftcfg);
1623                 port->fifosize = stm32_usart_get_ftcfg(pdev, stm32port, "tx-threshold",
1624                                                        &stm32port->txftcfg);
1625         } else {
1626                 port->fifosize = 1;
1627         }
1628
1629         stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1630         if (IS_ERR(stm32port->gpios)) {
1631                 ret = PTR_ERR(stm32port->gpios);
1632                 goto err_clk;
1633         }
1634
1635         /*
1636          * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1637          * properties should not be specified.
1638          */
1639         if (stm32port->hw_flow_control) {
1640                 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1641                     mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1642                         dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1643                         ret = -EINVAL;
1644                         goto err_clk;
1645                 }
1646         }
1647
1648         return ret;
1649
1650 err_clk:
1651         clk_disable_unprepare(stm32port->clk);
1652
1653         return ret;
1654 }
1655
1656 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1657 {
1658         struct device_node *np = pdev->dev.of_node;
1659         int id;
1660
1661         if (!np)
1662                 return NULL;
1663
1664         id = of_alias_get_id(np, "serial");
1665         if (id < 0) {
1666                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1667                 return NULL;
1668         }
1669
1670         if (WARN_ON(id >= STM32_MAX_PORTS))
1671                 return NULL;
1672
1673         stm32_ports[id].hw_flow_control =
1674                 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1675                 of_property_read_bool (np, "uart-has-rtscts");
1676         stm32_ports[id].port.line = id;
1677         stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1678         stm32_ports[id].cr3_irq = 0;
1679         stm32_ports[id].last_res = RX_BUF_L;
1680         return &stm32_ports[id];
1681 }
1682
1683 #ifdef CONFIG_OF
1684 static const struct of_device_id stm32_match[] = {
1685         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1686         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1687         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1688         {},
1689 };
1690
1691 MODULE_DEVICE_TABLE(of, stm32_match);
1692 #endif
1693
1694 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1695                                          struct platform_device *pdev)
1696 {
1697         if (stm32port->rx_buf)
1698                 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1699                                   stm32port->rx_dma_buf);
1700 }
1701
1702 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1703                                        struct platform_device *pdev)
1704 {
1705         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1706         struct uart_port *port = &stm32port->port;
1707         struct device *dev = &pdev->dev;
1708         struct dma_slave_config config;
1709         int ret;
1710
1711         stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1712                                                &stm32port->rx_dma_buf,
1713                                                GFP_KERNEL);
1714         if (!stm32port->rx_buf)
1715                 return -ENOMEM;
1716
1717         /* Configure DMA channel */
1718         memset(&config, 0, sizeof(config));
1719         config.src_addr = port->mapbase + ofs->rdr;
1720         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1721
1722         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1723         if (ret < 0) {
1724                 dev_err(dev, "rx dma channel config failed\n");
1725                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1726                 return ret;
1727         }
1728
1729         return 0;
1730 }
1731
1732 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1733                                          struct platform_device *pdev)
1734 {
1735         if (stm32port->tx_buf)
1736                 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1737                                   stm32port->tx_dma_buf);
1738 }
1739
1740 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1741                                        struct platform_device *pdev)
1742 {
1743         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1744         struct uart_port *port = &stm32port->port;
1745         struct device *dev = &pdev->dev;
1746         struct dma_slave_config config;
1747         int ret;
1748
1749         stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1750                                                &stm32port->tx_dma_buf,
1751                                                GFP_KERNEL);
1752         if (!stm32port->tx_buf)
1753                 return -ENOMEM;
1754
1755         /* Configure DMA channel */
1756         memset(&config, 0, sizeof(config));
1757         config.dst_addr = port->mapbase + ofs->tdr;
1758         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1759
1760         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1761         if (ret < 0) {
1762                 dev_err(dev, "tx dma channel config failed\n");
1763                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1764                 return ret;
1765         }
1766
1767         return 0;
1768 }
1769
1770 static int stm32_usart_serial_probe(struct platform_device *pdev)
1771 {
1772         struct stm32_port *stm32port;
1773         int ret;
1774
1775         stm32port = stm32_usart_of_get_port(pdev);
1776         if (!stm32port)
1777                 return -ENODEV;
1778
1779         stm32port->info = of_device_get_match_data(&pdev->dev);
1780         if (!stm32port->info)
1781                 return -EINVAL;
1782
1783         stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1784         if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER)
1785                 return -EPROBE_DEFER;
1786
1787         /* Fall back in interrupt mode for any non-deferral error */
1788         if (IS_ERR(stm32port->rx_ch))
1789                 stm32port->rx_ch = NULL;
1790
1791         stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1792         if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1793                 ret = -EPROBE_DEFER;
1794                 goto err_dma_rx;
1795         }
1796         /* Fall back in interrupt mode for any non-deferral error */
1797         if (IS_ERR(stm32port->tx_ch))
1798                 stm32port->tx_ch = NULL;
1799
1800         ret = stm32_usart_init_port(stm32port, pdev);
1801         if (ret)
1802                 goto err_dma_tx;
1803
1804         if (stm32port->wakeup_src) {
1805                 device_set_wakeup_capable(&pdev->dev, true);
1806                 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1807                 if (ret)
1808                         goto err_deinit_port;
1809         }
1810
1811         if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1812                 /* Fall back in interrupt mode */
1813                 dma_release_channel(stm32port->rx_ch);
1814                 stm32port->rx_ch = NULL;
1815         }
1816
1817         if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1818                 /* Fall back in interrupt mode */
1819                 dma_release_channel(stm32port->tx_ch);
1820                 stm32port->tx_ch = NULL;
1821         }
1822
1823         if (!stm32port->rx_ch)
1824                 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1825         if (!stm32port->tx_ch)
1826                 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1827
1828         platform_set_drvdata(pdev, &stm32port->port);
1829
1830         pm_runtime_get_noresume(&pdev->dev);
1831         pm_runtime_set_active(&pdev->dev);
1832         pm_runtime_enable(&pdev->dev);
1833
1834         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1835         if (ret)
1836                 goto err_port;
1837
1838         pm_runtime_put_sync(&pdev->dev);
1839
1840         return 0;
1841
1842 err_port:
1843         pm_runtime_disable(&pdev->dev);
1844         pm_runtime_set_suspended(&pdev->dev);
1845         pm_runtime_put_noidle(&pdev->dev);
1846
1847         if (stm32port->tx_ch)
1848                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1849         if (stm32port->rx_ch)
1850                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1851
1852         if (stm32port->wakeup_src)
1853                 dev_pm_clear_wake_irq(&pdev->dev);
1854
1855 err_deinit_port:
1856         if (stm32port->wakeup_src)
1857                 device_set_wakeup_capable(&pdev->dev, false);
1858
1859         stm32_usart_deinit_port(stm32port);
1860
1861 err_dma_tx:
1862         if (stm32port->tx_ch)
1863                 dma_release_channel(stm32port->tx_ch);
1864
1865 err_dma_rx:
1866         if (stm32port->rx_ch)
1867                 dma_release_channel(stm32port->rx_ch);
1868
1869         return ret;
1870 }
1871
1872 static void stm32_usart_serial_remove(struct platform_device *pdev)
1873 {
1874         struct uart_port *port = platform_get_drvdata(pdev);
1875         struct stm32_port *stm32_port = to_stm32_port(port);
1876         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1877         u32 cr3;
1878
1879         pm_runtime_get_sync(&pdev->dev);
1880         uart_remove_one_port(&stm32_usart_driver, port);
1881
1882         pm_runtime_disable(&pdev->dev);
1883         pm_runtime_set_suspended(&pdev->dev);
1884         pm_runtime_put_noidle(&pdev->dev);
1885
1886         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1887
1888         if (stm32_port->tx_ch) {
1889                 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1890                 dma_release_channel(stm32_port->tx_ch);
1891         }
1892
1893         if (stm32_port->rx_ch) {
1894                 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1895                 dma_release_channel(stm32_port->rx_ch);
1896         }
1897
1898         cr3 = readl_relaxed(port->membase + ofs->cr3);
1899         cr3 &= ~USART_CR3_EIE;
1900         cr3 &= ~USART_CR3_DMAR;
1901         cr3 &= ~USART_CR3_DMAT;
1902         cr3 &= ~USART_CR3_DDRE;
1903         writel_relaxed(cr3, port->membase + ofs->cr3);
1904
1905         if (stm32_port->wakeup_src) {
1906                 dev_pm_clear_wake_irq(&pdev->dev);
1907                 device_init_wakeup(&pdev->dev, false);
1908         }
1909
1910         stm32_usart_deinit_port(stm32_port);
1911 }
1912
1913 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1914 {
1915         struct stm32_port *stm32_port = to_stm32_port(port);
1916         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1917         u32 isr;
1918         int ret;
1919
1920         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1921                                                 (isr & USART_SR_TXE), 100,
1922                                                 STM32_USART_TIMEOUT_USEC);
1923         if (ret != 0) {
1924                 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
1925                 return;
1926         }
1927         writel_relaxed(ch, port->membase + ofs->tdr);
1928 }
1929
1930 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1931 static void stm32_usart_console_write(struct console *co, const char *s,
1932                                       unsigned int cnt)
1933 {
1934         struct uart_port *port = &stm32_ports[co->index].port;
1935         struct stm32_port *stm32_port = to_stm32_port(port);
1936         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1937         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1938         unsigned long flags;
1939         u32 old_cr1, new_cr1;
1940         int locked = 1;
1941
1942         if (oops_in_progress)
1943                 locked = uart_port_trylock_irqsave(port, &flags);
1944         else
1945                 uart_port_lock_irqsave(port, &flags);
1946
1947         /* Save and disable interrupts, enable the transmitter */
1948         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1949         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1950         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1951         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1952
1953         uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1954
1955         /* Restore interrupt state */
1956         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1957
1958         if (locked)
1959                 uart_port_unlock_irqrestore(port, flags);
1960 }
1961
1962 static int stm32_usart_console_setup(struct console *co, char *options)
1963 {
1964         struct stm32_port *stm32port;
1965         int baud = 9600;
1966         int bits = 8;
1967         int parity = 'n';
1968         int flow = 'n';
1969
1970         if (co->index >= STM32_MAX_PORTS)
1971                 return -ENODEV;
1972
1973         stm32port = &stm32_ports[co->index];
1974
1975         /*
1976          * This driver does not support early console initialization
1977          * (use ARM early printk support instead), so we only expect
1978          * this to be called during the uart port registration when the
1979          * driver gets probed and the port should be mapped at that point.
1980          */
1981         if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1982                 return -ENXIO;
1983
1984         if (options)
1985                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1986
1987         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1988 }
1989
1990 static struct console stm32_console = {
1991         .name           = STM32_SERIAL_NAME,
1992         .device         = uart_console_device,
1993         .write          = stm32_usart_console_write,
1994         .setup          = stm32_usart_console_setup,
1995         .flags          = CON_PRINTBUFFER,
1996         .index          = -1,
1997         .data           = &stm32_usart_driver,
1998 };
1999
2000 #define STM32_SERIAL_CONSOLE (&stm32_console)
2001
2002 #else
2003 #define STM32_SERIAL_CONSOLE NULL
2004 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
2005
2006 #ifdef CONFIG_SERIAL_EARLYCON
2007 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
2008 {
2009         struct stm32_usart_info *info = port->private_data;
2010
2011         while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
2012                 cpu_relax();
2013
2014         writel_relaxed(ch, port->membase + info->ofs.tdr);
2015 }
2016
2017 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count)
2018 {
2019         struct earlycon_device *device = console->data;
2020         struct uart_port *port = &device->port;
2021
2022         uart_console_write(port, s, count, early_stm32_usart_console_putchar);
2023 }
2024
2025 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options)
2026 {
2027         if (!(device->port.membase || device->port.iobase))
2028                 return -ENODEV;
2029         device->port.private_data = &stm32h7_info;
2030         device->con->write = early_stm32_serial_write;
2031         return 0;
2032 }
2033
2034 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options)
2035 {
2036         if (!(device->port.membase || device->port.iobase))
2037                 return -ENODEV;
2038         device->port.private_data = &stm32f7_info;
2039         device->con->write = early_stm32_serial_write;
2040         return 0;
2041 }
2042
2043 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options)
2044 {
2045         if (!(device->port.membase || device->port.iobase))
2046                 return -ENODEV;
2047         device->port.private_data = &stm32f4_info;
2048         device->con->write = early_stm32_serial_write;
2049         return 0;
2050 }
2051
2052 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
2053 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
2054 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2055 #endif /* CONFIG_SERIAL_EARLYCON */
2056
2057 static struct uart_driver stm32_usart_driver = {
2058         .driver_name    = DRIVER_NAME,
2059         .dev_name       = STM32_SERIAL_NAME,
2060         .major          = 0,
2061         .minor          = 0,
2062         .nr             = STM32_MAX_PORTS,
2063         .cons           = STM32_SERIAL_CONSOLE,
2064 };
2065
2066 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
2067                                                        bool enable)
2068 {
2069         struct stm32_port *stm32_port = to_stm32_port(port);
2070         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
2071         struct tty_port *tport = &port->state->port;
2072         int ret;
2073         unsigned int size = 0;
2074         unsigned long flags;
2075
2076         if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
2077                 return 0;
2078
2079         /*
2080          * Enable low-power wake-up and wake-up irq if argument is set to
2081          * "enable", disable low-power wake-up and wake-up irq otherwise
2082          */
2083         if (enable) {
2084                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
2085                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
2086                 mctrl_gpio_enable_irq_wake(stm32_port->gpios);
2087
2088                 /*
2089                  * When DMA is used for reception, it must be disabled before
2090                  * entering low-power mode and re-enabled when exiting from
2091                  * low-power mode.
2092                  */
2093                 if (stm32_port->rx_ch) {
2094                         uart_port_lock_irqsave(port, &flags);
2095                         /* Poll data from DMA RX buffer if any */
2096                         if (!stm32_usart_rx_dma_pause(stm32_port))
2097                                 size += stm32_usart_receive_chars(port, true);
2098                         stm32_usart_rx_dma_terminate(stm32_port);
2099                         uart_unlock_and_check_sysrq_irqrestore(port, flags);
2100                         if (size)
2101                                 tty_flip_buffer_push(tport);
2102                 }
2103
2104                 /* Poll data from RX FIFO if any */
2105                 stm32_usart_receive_chars(port, false);
2106         } else {
2107                 if (stm32_port->rx_ch) {
2108                         ret = stm32_usart_rx_dma_start_or_resume(port);
2109                         if (ret)
2110                                 return ret;
2111                 }
2112                 mctrl_gpio_disable_irq_wake(stm32_port->gpios);
2113                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
2114                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
2121 {
2122         struct uart_port *port = dev_get_drvdata(dev);
2123         int ret;
2124
2125         uart_suspend_port(&stm32_usart_driver, port);
2126
2127         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2128                 ret = stm32_usart_serial_en_wakeup(port, true);
2129                 if (ret)
2130                         return ret;
2131         }
2132
2133         /*
2134          * When "no_console_suspend" is enabled, keep the pinctrl default state
2135          * and rely on bootloader stage to restore this state upon resume.
2136          * Otherwise, apply the idle or sleep states depending on wakeup
2137          * capabilities.
2138          */
2139         if (console_suspend_enabled || !uart_console(port)) {
2140                 if (device_may_wakeup(dev) || device_wakeup_path(dev))
2141                         pinctrl_pm_select_idle_state(dev);
2142                 else
2143                         pinctrl_pm_select_sleep_state(dev);
2144         }
2145
2146         return 0;
2147 }
2148
2149 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
2150 {
2151         struct uart_port *port = dev_get_drvdata(dev);
2152         int ret;
2153
2154         pinctrl_pm_select_default_state(dev);
2155
2156         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2157                 ret = stm32_usart_serial_en_wakeup(port, false);
2158                 if (ret)
2159                         return ret;
2160         }
2161
2162         return uart_resume_port(&stm32_usart_driver, port);
2163 }
2164
2165 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
2166 {
2167         struct uart_port *port = dev_get_drvdata(dev);
2168         struct stm32_port *stm32port = container_of(port,
2169                         struct stm32_port, port);
2170
2171         clk_disable_unprepare(stm32port->clk);
2172
2173         return 0;
2174 }
2175
2176 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
2177 {
2178         struct uart_port *port = dev_get_drvdata(dev);
2179         struct stm32_port *stm32port = container_of(port,
2180                         struct stm32_port, port);
2181
2182         return clk_prepare_enable(stm32port->clk);
2183 }
2184
2185 static const struct dev_pm_ops stm32_serial_pm_ops = {
2186         SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
2187                            stm32_usart_runtime_resume, NULL)
2188         SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
2189                                 stm32_usart_serial_resume)
2190 };
2191
2192 static struct platform_driver stm32_serial_driver = {
2193         .probe          = stm32_usart_serial_probe,
2194         .remove_new     = stm32_usart_serial_remove,
2195         .driver = {
2196                 .name   = DRIVER_NAME,
2197                 .pm     = &stm32_serial_pm_ops,
2198                 .of_match_table = of_match_ptr(stm32_match),
2199         },
2200 };
2201
2202 static int __init stm32_usart_init(void)
2203 {
2204         static char banner[] __initdata = "STM32 USART driver initialized";
2205         int ret;
2206
2207         pr_info("%s\n", banner);
2208
2209         ret = uart_register_driver(&stm32_usart_driver);
2210         if (ret)
2211                 return ret;
2212
2213         ret = platform_driver_register(&stm32_serial_driver);
2214         if (ret)
2215                 uart_unregister_driver(&stm32_usart_driver);
2216
2217         return ret;
2218 }
2219
2220 static void __exit stm32_usart_exit(void)
2221 {
2222         platform_driver_unregister(&stm32_serial_driver);
2223         uart_unregister_driver(&stm32_usart_driver);
2224 }
2225
2226 module_init(stm32_usart_init);
2227 module_exit(stm32_usart_exit);
2228
2229 MODULE_ALIAS("platform:" DRIVER_NAME);
2230 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
2231 MODULE_LICENSE("GPL v2");