2 * Copyright (C) Maxime Coquelin 2015
3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * License terms: GNU General Public License (GPL), version 2
6 * Inspired by st-asc.c from STMicroelectronics (c)
9 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13 #include <linux/module.h>
14 #include <linux/serial.h>
15 #include <linux/console.h>
16 #include <linux/sysrq.h>
17 #include <linux/platform_device.h>
19 #include <linux/irq.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/serial_core.h>
28 #include <linux/clk.h>
30 #define DRIVER_NAME "stm32-usart"
32 /* Register offsets */
35 #define USART_BRR 0x08
36 #define USART_CR1 0x0c
37 #define USART_CR2 0x10
38 #define USART_CR3 0x14
39 #define USART_GTPR 0x18
42 #define USART_SR_PE BIT(0)
43 #define USART_SR_FE BIT(1)
44 #define USART_SR_NF BIT(2)
45 #define USART_SR_ORE BIT(3)
46 #define USART_SR_IDLE BIT(4)
47 #define USART_SR_RXNE BIT(5)
48 #define USART_SR_TC BIT(6)
49 #define USART_SR_TXE BIT(7)
50 #define USART_SR_LBD BIT(8)
51 #define USART_SR_CTS BIT(9)
52 #define USART_SR_ERR_MASK (USART_SR_LBD | USART_SR_ORE | \
53 USART_SR_FE | USART_SR_PE)
55 #define USART_SR_DUMMY_RX BIT(16)
58 #define USART_DR_MASK GENMASK(8, 0)
61 #define USART_BRR_DIV_F_MASK GENMASK(3, 0)
62 #define USART_BRR_DIV_M_MASK GENMASK(15, 4)
63 #define USART_BRR_DIV_M_SHIFT 4
66 #define USART_CR1_SBK BIT(0)
67 #define USART_CR1_RWU BIT(1)
68 #define USART_CR1_RE BIT(2)
69 #define USART_CR1_TE BIT(3)
70 #define USART_CR1_IDLEIE BIT(4)
71 #define USART_CR1_RXNEIE BIT(5)
72 #define USART_CR1_TCIE BIT(6)
73 #define USART_CR1_TXEIE BIT(7)
74 #define USART_CR1_PEIE BIT(8)
75 #define USART_CR1_PS BIT(9)
76 #define USART_CR1_PCE BIT(10)
77 #define USART_CR1_WAKE BIT(11)
78 #define USART_CR1_M BIT(12)
79 #define USART_CR1_UE BIT(13)
80 #define USART_CR1_OVER8 BIT(15)
81 #define USART_CR1_IE_MASK GENMASK(8, 4)
84 #define USART_CR2_ADD_MASK GENMASK(3, 0)
85 #define USART_CR2_LBDL BIT(5)
86 #define USART_CR2_LBDIE BIT(6)
87 #define USART_CR2_LBCL BIT(8)
88 #define USART_CR2_CPHA BIT(9)
89 #define USART_CR2_CPOL BIT(10)
90 #define USART_CR2_CLKEN BIT(11)
91 #define USART_CR2_STOP_2B BIT(13)
92 #define USART_CR2_STOP_MASK GENMASK(13, 12)
93 #define USART_CR2_LINEN BIT(14)
96 #define USART_CR3_EIE BIT(0)
97 #define USART_CR3_IREN BIT(1)
98 #define USART_CR3_IRLP BIT(2)
99 #define USART_CR3_HDSEL BIT(3)
100 #define USART_CR3_NACK BIT(4)
101 #define USART_CR3_SCEN BIT(5)
102 #define USART_CR3_DMAR BIT(6)
103 #define USART_CR3_DMAT BIT(7)
104 #define USART_CR3_RTSE BIT(8)
105 #define USART_CR3_CTSE BIT(9)
106 #define USART_CR3_CTSIE BIT(10)
107 #define USART_CR3_ONEBIT BIT(11)
110 #define USART_GTPR_PSC_MASK GENMASK(7, 0)
111 #define USART_GTPR_GT_MASK GENMASK(15, 8)
113 #define DRIVER_NAME "stm32-usart"
114 #define STM32_SERIAL_NAME "ttyS"
115 #define STM32_MAX_PORTS 6
118 struct uart_port port;
120 bool hw_flow_control;
123 static struct stm32_port stm32_ports[STM32_MAX_PORTS];
124 static struct uart_driver stm32_usart_driver;
126 static void stm32_stop_tx(struct uart_port *port);
128 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
130 return container_of(port, struct stm32_port, port);
133 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
137 val = readl_relaxed(port->membase + reg);
139 writel_relaxed(val, port->membase + reg);
142 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
146 val = readl_relaxed(port->membase + reg);
148 writel_relaxed(val, port->membase + reg);
151 static void stm32_receive_chars(struct uart_port *port)
153 struct tty_port *tport = &port->state->port;
159 pm_wakeup_event(tport->tty->dev, 0);
161 while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) {
162 sr |= USART_SR_DUMMY_RX;
163 c = readl_relaxed(port->membase + USART_DR);
167 if (sr & USART_SR_ERR_MASK) {
168 if (sr & USART_SR_LBD) {
170 if (uart_handle_break(port))
172 } else if (sr & USART_SR_ORE) {
173 port->icount.overrun++;
174 } else if (sr & USART_SR_PE) {
175 port->icount.parity++;
176 } else if (sr & USART_SR_FE) {
177 port->icount.frame++;
180 sr &= port->read_status_mask;
182 if (sr & USART_SR_LBD)
184 else if (sr & USART_SR_PE)
186 else if (sr & USART_SR_FE)
190 if (uart_handle_sysrq_char(port, c))
192 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
195 spin_unlock(&port->lock);
196 tty_flip_buffer_push(tport);
197 spin_lock(&port->lock);
200 static void stm32_transmit_chars(struct uart_port *port)
202 struct circ_buf *xmit = &port->state->xmit;
205 writel_relaxed(port->x_char, port->membase + USART_DR);
211 if (uart_tx_stopped(port)) {
216 if (uart_circ_empty(xmit)) {
221 writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR);
222 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
225 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
228 if (uart_circ_empty(xmit))
232 static irqreturn_t stm32_interrupt(int irq, void *ptr)
234 struct uart_port *port = ptr;
237 spin_lock(&port->lock);
239 sr = readl_relaxed(port->membase + USART_SR);
241 if (sr & USART_SR_RXNE)
242 stm32_receive_chars(port);
244 if (sr & USART_SR_TXE)
245 stm32_transmit_chars(port);
247 spin_unlock(&port->lock);
252 static unsigned int stm32_tx_empty(struct uart_port *port)
254 return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE;
257 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
259 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
260 stm32_set_bits(port, USART_CR3, USART_CR3_RTSE);
262 stm32_clr_bits(port, USART_CR3, USART_CR3_RTSE);
265 static unsigned int stm32_get_mctrl(struct uart_port *port)
267 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
268 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
272 static void stm32_stop_tx(struct uart_port *port)
274 stm32_clr_bits(port, USART_CR1, USART_CR1_TXEIE);
277 /* There are probably characters waiting to be transmitted. */
278 static void stm32_start_tx(struct uart_port *port)
280 struct circ_buf *xmit = &port->state->xmit;
282 if (uart_circ_empty(xmit))
285 stm32_set_bits(port, USART_CR1, USART_CR1_TXEIE | USART_CR1_TE);
288 /* Throttle the remote when input buffer is about to overflow. */
289 static void stm32_throttle(struct uart_port *port)
293 spin_lock_irqsave(&port->lock, flags);
294 stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
295 spin_unlock_irqrestore(&port->lock, flags);
298 /* Unthrottle the remote, the input buffer can now accept data. */
299 static void stm32_unthrottle(struct uart_port *port)
303 spin_lock_irqsave(&port->lock, flags);
304 stm32_set_bits(port, USART_CR1, USART_CR1_RXNEIE);
305 spin_unlock_irqrestore(&port->lock, flags);
309 static void stm32_stop_rx(struct uart_port *port)
311 stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
314 /* Handle breaks - ignored by us */
315 static void stm32_break_ctl(struct uart_port *port, int break_state)
319 static int stm32_startup(struct uart_port *port)
321 const char *name = to_platform_device(port->dev)->name;
325 ret = request_irq(port->irq, stm32_interrupt, IRQF_NO_SUSPEND,
330 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
331 stm32_set_bits(port, USART_CR1, val);
336 static void stm32_shutdown(struct uart_port *port)
340 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
341 stm32_set_bits(port, USART_CR1, val);
343 free_irq(port->irq, port);
346 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
347 struct ktermios *old)
349 struct stm32_port *stm32_port = to_stm32_port(port);
351 u32 usartdiv, mantissa, fraction, oversampling;
352 tcflag_t cflag = termios->c_cflag;
356 if (!stm32_port->hw_flow_control)
359 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
361 spin_lock_irqsave(&port->lock, flags);
363 /* Stop serial port and reset value */
364 writel_relaxed(0, port->membase + USART_CR1);
366 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_RXNEIE;
371 cr2 |= USART_CR2_STOP_2B;
373 if (cflag & PARENB) {
374 cr1 |= USART_CR1_PCE;
375 if ((cflag & CSIZE) == CS8)
382 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
383 if (cflag & CRTSCTS) {
384 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
385 cr3 |= USART_CR3_CTSE;
388 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
391 * The USART supports 16 or 8 times oversampling.
392 * By default we prefer 16 times oversampling, so that the receiver
393 * has a better tolerance to clock deviations.
394 * 8 times oversampling is only used to achieve higher speeds.
398 stm32_set_bits(port, USART_CR1, USART_CR1_OVER8);
401 stm32_clr_bits(port, USART_CR1, USART_CR1_OVER8);
404 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
405 fraction = usartdiv % oversampling;
406 writel_relaxed(mantissa | fraction, port->membase + USART_BRR);
408 uart_update_timeout(port, cflag, baud);
410 port->read_status_mask = USART_SR_ORE;
411 if (termios->c_iflag & INPCK)
412 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
413 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
414 port->read_status_mask |= USART_SR_LBD;
416 /* Characters to ignore */
417 port->ignore_status_mask = 0;
418 if (termios->c_iflag & IGNPAR)
419 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
420 if (termios->c_iflag & IGNBRK) {
421 port->ignore_status_mask |= USART_SR_LBD;
423 * If we're ignoring parity and break indicators,
424 * ignore overruns too (for real raw support).
426 if (termios->c_iflag & IGNPAR)
427 port->ignore_status_mask |= USART_SR_ORE;
430 /* Ignore all characters if CREAD is not set */
431 if ((termios->c_cflag & CREAD) == 0)
432 port->ignore_status_mask |= USART_SR_DUMMY_RX;
434 writel_relaxed(cr3, port->membase + USART_CR3);
435 writel_relaxed(cr2, port->membase + USART_CR2);
436 writel_relaxed(cr1, port->membase + USART_CR1);
438 spin_unlock_irqrestore(&port->lock, flags);
441 static const char *stm32_type(struct uart_port *port)
443 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
446 static void stm32_release_port(struct uart_port *port)
450 static int stm32_request_port(struct uart_port *port)
455 static void stm32_config_port(struct uart_port *port, int flags)
457 if (flags & UART_CONFIG_TYPE)
458 port->type = PORT_STM32;
462 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
464 /* No user changeable parameters */
468 static void stm32_pm(struct uart_port *port, unsigned int state,
469 unsigned int oldstate)
471 struct stm32_port *stm32port = container_of(port,
472 struct stm32_port, port);
473 unsigned long flags = 0;
476 case UART_PM_STATE_ON:
477 clk_prepare_enable(stm32port->clk);
479 case UART_PM_STATE_OFF:
480 spin_lock_irqsave(&port->lock, flags);
481 stm32_clr_bits(port, USART_CR1, USART_CR1_UE);
482 spin_unlock_irqrestore(&port->lock, flags);
483 clk_disable_unprepare(stm32port->clk);
488 static const struct uart_ops stm32_uart_ops = {
489 .tx_empty = stm32_tx_empty,
490 .set_mctrl = stm32_set_mctrl,
491 .get_mctrl = stm32_get_mctrl,
492 .stop_tx = stm32_stop_tx,
493 .start_tx = stm32_start_tx,
494 .throttle = stm32_throttle,
495 .unthrottle = stm32_unthrottle,
496 .stop_rx = stm32_stop_rx,
497 .break_ctl = stm32_break_ctl,
498 .startup = stm32_startup,
499 .shutdown = stm32_shutdown,
500 .set_termios = stm32_set_termios,
503 .release_port = stm32_release_port,
504 .request_port = stm32_request_port,
505 .config_port = stm32_config_port,
506 .verify_port = stm32_verify_port,
509 static int stm32_init_port(struct stm32_port *stm32port,
510 struct platform_device *pdev)
512 struct uart_port *port = &stm32port->port;
513 struct resource *res;
516 port->iotype = UPIO_MEM;
517 port->flags = UPF_BOOT_AUTOCONF;
518 port->ops = &stm32_uart_ops;
519 port->dev = &pdev->dev;
520 port->irq = platform_get_irq(pdev, 0);
522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
523 port->membase = devm_ioremap_resource(&pdev->dev, res);
524 if (IS_ERR(port->membase))
525 return PTR_ERR(port->membase);
526 port->mapbase = res->start;
528 spin_lock_init(&port->lock);
530 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
531 if (IS_ERR(stm32port->clk))
532 return PTR_ERR(stm32port->clk);
534 /* Ensure that clk rate is correct by enabling the clk */
535 ret = clk_prepare_enable(stm32port->clk);
539 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
540 if (!stm32port->port.uartclk)
543 clk_disable_unprepare(stm32port->clk);
548 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
550 struct device_node *np = pdev->dev.of_node;
556 id = of_alias_get_id(np, "serial");
560 if (WARN_ON(id >= STM32_MAX_PORTS))
563 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
564 "auto-flow-control");
565 stm32_ports[id].port.line = id;
566 return &stm32_ports[id];
570 static const struct of_device_id stm32_match[] = {
571 { .compatible = "st,stm32-usart", },
572 { .compatible = "st,stm32-uart", },
576 MODULE_DEVICE_TABLE(of, stm32_match);
579 static int stm32_serial_probe(struct platform_device *pdev)
582 struct stm32_port *stm32port;
584 stm32port = stm32_of_get_stm32_port(pdev);
588 ret = stm32_init_port(stm32port, pdev);
592 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
596 platform_set_drvdata(pdev, &stm32port->port);
601 static int stm32_serial_remove(struct platform_device *pdev)
603 struct uart_port *port = platform_get_drvdata(pdev);
605 return uart_remove_one_port(&stm32_usart_driver, port);
609 #ifdef CONFIG_SERIAL_STM32_CONSOLE
610 static void stm32_console_putchar(struct uart_port *port, int ch)
612 while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE))
615 writel_relaxed(ch, port->membase + USART_DR);
618 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
620 struct uart_port *port = &stm32_ports[co->index].port;
622 u32 old_cr1, new_cr1;
625 local_irq_save(flags);
628 else if (oops_in_progress)
629 locked = spin_trylock(&port->lock);
631 spin_lock(&port->lock);
633 /* Save and disable interrupts */
634 old_cr1 = readl_relaxed(port->membase + USART_CR1);
635 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
636 writel_relaxed(new_cr1, port->membase + USART_CR1);
638 uart_console_write(port, s, cnt, stm32_console_putchar);
640 /* Restore interrupt state */
641 writel_relaxed(old_cr1, port->membase + USART_CR1);
644 spin_unlock(&port->lock);
645 local_irq_restore(flags);
648 static int stm32_console_setup(struct console *co, char *options)
650 struct stm32_port *stm32port;
656 if (co->index >= STM32_MAX_PORTS)
659 stm32port = &stm32_ports[co->index];
662 * This driver does not support early console initialization
663 * (use ARM early printk support instead), so we only expect
664 * this to be called during the uart port registration when the
665 * driver gets probed and the port should be mapped at that point.
667 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
671 uart_parse_options(options, &baud, &parity, &bits, &flow);
673 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
676 static struct console stm32_console = {
677 .name = STM32_SERIAL_NAME,
678 .device = uart_console_device,
679 .write = stm32_console_write,
680 .setup = stm32_console_setup,
681 .flags = CON_PRINTBUFFER,
683 .data = &stm32_usart_driver,
686 #define STM32_SERIAL_CONSOLE (&stm32_console)
689 #define STM32_SERIAL_CONSOLE NULL
690 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
692 static struct uart_driver stm32_usart_driver = {
693 .driver_name = DRIVER_NAME,
694 .dev_name = STM32_SERIAL_NAME,
697 .nr = STM32_MAX_PORTS,
698 .cons = STM32_SERIAL_CONSOLE,
701 static struct platform_driver stm32_serial_driver = {
702 .probe = stm32_serial_probe,
703 .remove = stm32_serial_remove,
706 .of_match_table = of_match_ptr(stm32_match),
710 static int __init usart_init(void)
712 static char banner[] __initdata = "STM32 USART driver initialized";
715 pr_info("%s\n", banner);
717 ret = uart_register_driver(&stm32_usart_driver);
721 ret = platform_driver_register(&stm32_serial_driver);
723 uart_unregister_driver(&stm32_usart_driver);
728 static void __exit usart_exit(void)
730 platform_driver_unregister(&stm32_serial_driver);
731 uart_unregister_driver(&stm32_usart_driver);
734 module_init(usart_init);
735 module_exit(usart_exit);
737 MODULE_ALIAS("platform:" DRIVER_NAME);
738 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
739 MODULE_LICENSE("GPL v2");