2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
61 /* Offsets into the sci_port->irqs array */
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79 struct uart_port port;
81 /* Platform configuration */
82 struct plat_sci_port *cfg;
84 unsigned int error_mask;
85 unsigned int sampling_rate;
89 struct timer_list break_timer;
97 int irqs[SCIx_NR_IRQS];
98 char *irqstr[SCIx_NR_IRQS];
100 struct dma_chan *chan_tx;
101 struct dma_chan *chan_rx;
103 #ifdef CONFIG_SERIAL_SH_SCI_DMA
104 struct dma_async_tx_descriptor *desc_tx;
105 struct dma_async_tx_descriptor *desc_rx[2];
106 dma_cookie_t cookie_tx;
107 dma_cookie_t cookie_rx[2];
108 dma_cookie_t active_rx;
109 struct scatterlist sg_tx;
110 unsigned int sg_len_tx;
111 struct scatterlist sg_rx[2];
113 struct sh_dmae_slave param_tx;
114 struct sh_dmae_slave param_rx;
115 struct work_struct work_tx;
116 struct work_struct work_rx;
117 struct timer_list rx_timer;
118 unsigned int rx_timeout;
121 struct notifier_block freq_transition;
124 /* Function prototypes */
125 static void sci_start_tx(struct uart_port *port);
126 static void sci_stop_tx(struct uart_port *port);
127 static void sci_start_rx(struct uart_port *port);
129 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131 static struct sci_port sci_ports[SCI_NPORTS];
132 static struct uart_driver sci_uart_driver;
134 static inline struct sci_port *
135 to_sci_port(struct uart_port *uart)
137 return container_of(uart, struct sci_port, port);
140 struct plat_sci_reg {
144 /* Helper for invalidating specific entries of an inherited map. */
145 #define sci_reg_invalid { .offset = 0, .size = 0 }
147 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
148 [SCIx_PROBE_REGTYPE] = {
149 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
153 * Common SCI definitions, dependent on the port's regshift
156 [SCIx_SCI_REGTYPE] = {
157 [SCSMR] = { 0x00, 8 },
158 [SCBRR] = { 0x01, 8 },
159 [SCSCR] = { 0x02, 8 },
160 [SCxTDR] = { 0x03, 8 },
161 [SCxSR] = { 0x04, 8 },
162 [SCxRDR] = { 0x05, 8 },
163 [SCFCR] = sci_reg_invalid,
164 [SCFDR] = sci_reg_invalid,
165 [SCTFDR] = sci_reg_invalid,
166 [SCRFDR] = sci_reg_invalid,
167 [SCSPTR] = sci_reg_invalid,
168 [SCLSR] = sci_reg_invalid,
169 [HSSRR] = sci_reg_invalid,
173 * Common definitions for legacy IrDA ports, dependent on
176 [SCIx_IRDA_REGTYPE] = {
177 [SCSMR] = { 0x00, 8 },
178 [SCBRR] = { 0x01, 8 },
179 [SCSCR] = { 0x02, 8 },
180 [SCxTDR] = { 0x03, 8 },
181 [SCxSR] = { 0x04, 8 },
182 [SCxRDR] = { 0x05, 8 },
183 [SCFCR] = { 0x06, 8 },
184 [SCFDR] = { 0x07, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 [HSSRR] = sci_reg_invalid,
193 * Common SCIFA definitions.
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
212 * Common SCIFB definitions.
214 [SCIx_SCIFB_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x40, 8 },
219 [SCxSR] = { 0x14, 16 },
220 [SCxRDR] = { 0x60, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = sci_reg_invalid,
223 [SCTFDR] = { 0x38, 16 },
224 [SCRFDR] = { 0x3c, 16 },
225 [SCSPTR] = sci_reg_invalid,
226 [SCLSR] = sci_reg_invalid,
227 [HSSRR] = sci_reg_invalid,
231 * Common SH-2(A) SCIF definitions for ports with FIFO data
234 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
235 [SCSMR] = { 0x00, 16 },
236 [SCBRR] = { 0x04, 8 },
237 [SCSCR] = { 0x08, 16 },
238 [SCxTDR] = { 0x0c, 8 },
239 [SCxSR] = { 0x10, 16 },
240 [SCxRDR] = { 0x14, 8 },
241 [SCFCR] = { 0x18, 16 },
242 [SCFDR] = { 0x1c, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = { 0x20, 16 },
246 [SCLSR] = { 0x24, 16 },
247 [HSSRR] = sci_reg_invalid,
251 * Common SH-3 SCIF definitions.
253 [SCIx_SH3_SCIF_REGTYPE] = {
254 [SCSMR] = { 0x00, 8 },
255 [SCBRR] = { 0x02, 8 },
256 [SCSCR] = { 0x04, 8 },
257 [SCxTDR] = { 0x06, 8 },
258 [SCxSR] = { 0x08, 16 },
259 [SCxRDR] = { 0x0a, 8 },
260 [SCFCR] = { 0x0c, 8 },
261 [SCFDR] = { 0x0e, 16 },
262 [SCTFDR] = sci_reg_invalid,
263 [SCRFDR] = sci_reg_invalid,
264 [SCSPTR] = sci_reg_invalid,
265 [SCLSR] = sci_reg_invalid,
266 [HSSRR] = sci_reg_invalid,
270 * Common SH-4(A) SCIF(B) definitions.
272 [SCIx_SH4_SCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 [HSSRR] = sci_reg_invalid,
289 * Common HSCIF definitions.
291 [SCIx_HSCIF_REGTYPE] = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x04, 8 },
294 [SCSCR] = { 0x08, 16 },
295 [SCxTDR] = { 0x0c, 8 },
296 [SCxSR] = { 0x10, 16 },
297 [SCxRDR] = { 0x14, 8 },
298 [SCFCR] = { 0x18, 16 },
299 [SCFDR] = { 0x1c, 16 },
300 [SCTFDR] = sci_reg_invalid,
301 [SCRFDR] = sci_reg_invalid,
302 [SCSPTR] = { 0x20, 16 },
303 [SCLSR] = { 0x24, 16 },
304 [HSSRR] = { 0x40, 16 },
308 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
311 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = sci_reg_invalid,
321 [SCRFDR] = sci_reg_invalid,
322 [SCSPTR] = sci_reg_invalid,
323 [SCLSR] = { 0x24, 16 },
324 [HSSRR] = sci_reg_invalid,
328 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
331 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x0c, 8 },
336 [SCxSR] = { 0x10, 16 },
337 [SCxRDR] = { 0x14, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
341 [SCRFDR] = { 0x20, 16 },
342 [SCSPTR] = { 0x24, 16 },
343 [SCLSR] = { 0x28, 16 },
344 [HSSRR] = sci_reg_invalid,
348 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
351 [SCIx_SH7705_SCIF_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x20, 8 },
356 [SCxSR] = { 0x14, 16 },
357 [SCxRDR] = { 0x24, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = sci_reg_invalid,
361 [SCRFDR] = sci_reg_invalid,
362 [SCSPTR] = sci_reg_invalid,
363 [SCLSR] = sci_reg_invalid,
364 [HSSRR] = sci_reg_invalid,
368 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
371 * The "offset" here is rather misleading, in that it refers to an enum
372 * value relative to the port mapping rather than the fixed offset
373 * itself, which needs to be manually retrieved from the platform's
374 * register map for the given port.
376 static unsigned int sci_serial_in(struct uart_port *p, int offset)
378 struct plat_sci_reg *reg = sci_getreg(p, offset);
381 return ioread8(p->membase + (reg->offset << p->regshift));
382 else if (reg->size == 16)
383 return ioread16(p->membase + (reg->offset << p->regshift));
385 WARN(1, "Invalid register access\n");
390 static void sci_serial_out(struct uart_port *p, int offset, int value)
392 struct plat_sci_reg *reg = sci_getreg(p, offset);
395 iowrite8(value, p->membase + (reg->offset << p->regshift));
396 else if (reg->size == 16)
397 iowrite16(value, p->membase + (reg->offset << p->regshift));
399 WARN(1, "Invalid register access\n");
402 static int sci_probe_regmap(struct plat_sci_port *cfg)
406 cfg->regtype = SCIx_SCI_REGTYPE;
409 cfg->regtype = SCIx_IRDA_REGTYPE;
412 cfg->regtype = SCIx_SCIFA_REGTYPE;
415 cfg->regtype = SCIx_SCIFB_REGTYPE;
419 * The SH-4 is a bit of a misnomer here, although that's
420 * where this particular port layout originated. This
421 * configuration (or some slight variation thereof)
422 * remains the dominant model for all SCIFs.
424 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
427 cfg->regtype = SCIx_HSCIF_REGTYPE;
430 printk(KERN_ERR "Can't probe register map for given port\n");
437 static void sci_port_enable(struct sci_port *sci_port)
439 if (!sci_port->port.dev)
442 pm_runtime_get_sync(sci_port->port.dev);
444 clk_prepare_enable(sci_port->iclk);
445 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
446 clk_prepare_enable(sci_port->fclk);
449 static void sci_port_disable(struct sci_port *sci_port)
451 if (!sci_port->port.dev)
454 /* Cancel the break timer to ensure that the timer handler will not try
455 * to access the hardware with clocks and power disabled. Reset the
456 * break flag to make the break debouncing state machine ready for the
459 del_timer_sync(&sci_port->break_timer);
460 sci_port->break_flag = 0;
462 clk_disable_unprepare(sci_port->fclk);
463 clk_disable_unprepare(sci_port->iclk);
465 pm_runtime_put_sync(sci_port->port.dev);
468 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
470 #ifdef CONFIG_CONSOLE_POLL
471 static int sci_poll_get_char(struct uart_port *port)
473 unsigned short status;
477 status = serial_port_in(port, SCxSR);
478 if (status & SCxSR_ERRORS(port)) {
479 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
485 if (!(status & SCxSR_RDxF(port)))
488 c = serial_port_in(port, SCxRDR);
491 serial_port_in(port, SCxSR);
492 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
498 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
500 unsigned short status;
503 status = serial_port_in(port, SCxSR);
504 } while (!(status & SCxSR_TDxE(port)));
506 serial_port_out(port, SCxTDR, c);
507 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
509 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
511 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
513 struct sci_port *s = to_sci_port(port);
514 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
517 * Use port-specific handler if provided.
519 if (s->cfg->ops && s->cfg->ops->init_pins) {
520 s->cfg->ops->init_pins(port, cflag);
525 * For the generic path SCSPTR is necessary. Bail out if that's
531 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
532 ((!(cflag & CRTSCTS)))) {
533 unsigned short status;
535 status = serial_port_in(port, SCSPTR);
536 status &= ~SCSPTR_CTSIO;
537 status |= SCSPTR_RTSIO;
538 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
542 static int sci_txfill(struct uart_port *port)
544 struct plat_sci_reg *reg;
546 reg = sci_getreg(port, SCTFDR);
548 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
550 reg = sci_getreg(port, SCFDR);
552 return serial_port_in(port, SCFDR) >> 8;
554 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
557 static int sci_txroom(struct uart_port *port)
559 return port->fifosize - sci_txfill(port);
562 static int sci_rxfill(struct uart_port *port)
564 struct plat_sci_reg *reg;
566 reg = sci_getreg(port, SCRFDR);
568 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
570 reg = sci_getreg(port, SCFDR);
572 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
574 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
578 * SCI helper for checking the state of the muxed port/RXD pins.
580 static inline int sci_rxd_in(struct uart_port *port)
582 struct sci_port *s = to_sci_port(port);
584 if (s->cfg->port_reg <= 0)
587 /* Cast for ARM damage */
588 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
591 /* ********************************************************************** *
592 * the interrupt related routines *
593 * ********************************************************************** */
595 static void sci_transmit_chars(struct uart_port *port)
597 struct circ_buf *xmit = &port->state->xmit;
598 unsigned int stopped = uart_tx_stopped(port);
599 unsigned short status;
603 status = serial_port_in(port, SCxSR);
604 if (!(status & SCxSR_TDxE(port))) {
605 ctrl = serial_port_in(port, SCSCR);
606 if (uart_circ_empty(xmit))
610 serial_port_out(port, SCSCR, ctrl);
614 count = sci_txroom(port);
622 } else if (!uart_circ_empty(xmit) && !stopped) {
623 c = xmit->buf[xmit->tail];
624 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
629 serial_port_out(port, SCxTDR, c);
632 } while (--count > 0);
634 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
636 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
637 uart_write_wakeup(port);
638 if (uart_circ_empty(xmit)) {
641 ctrl = serial_port_in(port, SCSCR);
643 if (port->type != PORT_SCI) {
644 serial_port_in(port, SCxSR); /* Dummy read */
645 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
649 serial_port_out(port, SCSCR, ctrl);
653 /* On SH3, SCIF may read end-of-break as a space->mark char */
654 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
656 static void sci_receive_chars(struct uart_port *port)
658 struct sci_port *sci_port = to_sci_port(port);
659 struct tty_port *tport = &port->state->port;
660 int i, count, copied = 0;
661 unsigned short status;
664 status = serial_port_in(port, SCxSR);
665 if (!(status & SCxSR_RDxF(port)))
669 /* Don't copy more bytes than there is room for in the buffer */
670 count = tty_buffer_request_room(tport, sci_rxfill(port));
672 /* If for any reason we can't copy more data, we're done! */
676 if (port->type == PORT_SCI) {
677 char c = serial_port_in(port, SCxRDR);
678 if (uart_handle_sysrq_char(port, c) ||
679 sci_port->break_flag)
682 tty_insert_flip_char(tport, c, TTY_NORMAL);
684 for (i = 0; i < count; i++) {
685 char c = serial_port_in(port, SCxRDR);
687 status = serial_port_in(port, SCxSR);
688 #if defined(CONFIG_CPU_SH3)
689 /* Skip "chars" during break */
690 if (sci_port->break_flag) {
692 (status & SCxSR_FER(port))) {
697 /* Nonzero => end-of-break */
698 dev_dbg(port->dev, "debounce<%02x>\n", c);
699 sci_port->break_flag = 0;
706 #endif /* CONFIG_CPU_SH3 */
707 if (uart_handle_sysrq_char(port, c)) {
712 /* Store data and status */
713 if (status & SCxSR_FER(port)) {
715 port->icount.frame++;
716 dev_notice(port->dev, "frame error\n");
717 } else if (status & SCxSR_PER(port)) {
719 port->icount.parity++;
720 dev_notice(port->dev, "parity error\n");
724 tty_insert_flip_char(tport, c, flag);
728 serial_port_in(port, SCxSR); /* dummy read */
729 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
732 port->icount.rx += count;
736 /* Tell the rest of the system the news. New characters! */
737 tty_flip_buffer_push(tport);
739 serial_port_in(port, SCxSR); /* dummy read */
740 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
744 #define SCI_BREAK_JIFFIES (HZ/20)
747 * The sci generates interrupts during the break,
748 * 1 per millisecond or so during the break period, for 9600 baud.
749 * So dont bother disabling interrupts.
750 * But dont want more than 1 break event.
751 * Use a kernel timer to periodically poll the rx line until
752 * the break is finished.
754 static inline void sci_schedule_break_timer(struct sci_port *port)
756 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
759 /* Ensure that two consecutive samples find the break over. */
760 static void sci_break_timer(unsigned long data)
762 struct sci_port *port = (struct sci_port *)data;
764 if (sci_rxd_in(&port->port) == 0) {
765 port->break_flag = 1;
766 sci_schedule_break_timer(port);
767 } else if (port->break_flag == 1) {
769 port->break_flag = 2;
770 sci_schedule_break_timer(port);
772 port->break_flag = 0;
775 static int sci_handle_errors(struct uart_port *port)
778 unsigned short status = serial_port_in(port, SCxSR);
779 struct tty_port *tport = &port->state->port;
780 struct sci_port *s = to_sci_port(port);
782 /* Handle overruns */
783 if (status & (1 << s->overrun_bit)) {
784 port->icount.overrun++;
787 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
790 dev_notice(port->dev, "overrun error");
793 if (status & SCxSR_FER(port)) {
794 if (sci_rxd_in(port) == 0) {
795 /* Notify of BREAK */
796 struct sci_port *sci_port = to_sci_port(port);
798 if (!sci_port->break_flag) {
801 sci_port->break_flag = 1;
802 sci_schedule_break_timer(sci_port);
804 /* Do sysrq handling. */
805 if (uart_handle_break(port))
808 dev_dbg(port->dev, "BREAK detected\n");
810 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
816 port->icount.frame++;
818 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
821 dev_notice(port->dev, "frame error\n");
825 if (status & SCxSR_PER(port)) {
827 port->icount.parity++;
829 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
832 dev_notice(port->dev, "parity error");
836 tty_flip_buffer_push(tport);
841 static int sci_handle_fifo_overrun(struct uart_port *port)
843 struct tty_port *tport = &port->state->port;
844 struct sci_port *s = to_sci_port(port);
845 struct plat_sci_reg *reg;
848 reg = sci_getreg(port, SCLSR);
852 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
853 serial_port_out(port, SCLSR, 0);
855 port->icount.overrun++;
857 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
858 tty_flip_buffer_push(tport);
860 dev_notice(port->dev, "overrun error\n");
867 static int sci_handle_breaks(struct uart_port *port)
870 unsigned short status = serial_port_in(port, SCxSR);
871 struct tty_port *tport = &port->state->port;
872 struct sci_port *s = to_sci_port(port);
874 if (uart_handle_break(port))
877 if (!s->break_flag && status & SCxSR_BRK(port)) {
878 #if defined(CONFIG_CPU_SH3)
885 /* Notify of BREAK */
886 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
889 dev_dbg(port->dev, "BREAK detected\n");
893 tty_flip_buffer_push(tport);
895 copied += sci_handle_fifo_overrun(port);
900 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
902 #ifdef CONFIG_SERIAL_SH_SCI_DMA
903 struct uart_port *port = ptr;
904 struct sci_port *s = to_sci_port(port);
907 u16 scr = serial_port_in(port, SCSCR);
908 u16 ssr = serial_port_in(port, SCxSR);
910 /* Disable future Rx interrupts */
911 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
912 disable_irq_nosync(irq);
917 serial_port_out(port, SCSCR, scr);
918 /* Clear current interrupt */
919 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
920 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
921 jiffies, s->rx_timeout);
922 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
928 /* I think sci_receive_chars has to be called irrespective
929 * of whether the I_IXOFF is set, otherwise, how is the interrupt
932 sci_receive_chars(ptr);
937 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
939 struct uart_port *port = ptr;
942 spin_lock_irqsave(&port->lock, flags);
943 sci_transmit_chars(port);
944 spin_unlock_irqrestore(&port->lock, flags);
949 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
951 struct uart_port *port = ptr;
954 if (port->type == PORT_SCI) {
955 if (sci_handle_errors(port)) {
956 /* discard character in rx buffer */
957 serial_port_in(port, SCxSR);
958 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
961 sci_handle_fifo_overrun(port);
962 sci_rx_interrupt(irq, ptr);
965 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
967 /* Kick the transmission */
968 sci_tx_interrupt(irq, ptr);
973 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
975 struct uart_port *port = ptr;
978 sci_handle_breaks(port);
979 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
984 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
987 * Not all ports (such as SCIFA) will support REIE. Rather than
988 * special-casing the port type, we check the port initialization
989 * IRQ enable mask to see whether the IRQ is desired at all. If
990 * it's unset, it's logically inferred that there's no point in
993 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
996 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
998 unsigned short ssr_status, scr_status, err_enabled;
999 struct uart_port *port = ptr;
1000 struct sci_port *s = to_sci_port(port);
1001 irqreturn_t ret = IRQ_NONE;
1003 ssr_status = serial_port_in(port, SCxSR);
1004 scr_status = serial_port_in(port, SCSCR);
1005 err_enabled = scr_status & port_rx_irq_mask(port);
1008 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1010 ret = sci_tx_interrupt(irq, ptr);
1013 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1016 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1017 (scr_status & SCSCR_RIE))
1018 ret = sci_rx_interrupt(irq, ptr);
1020 /* Error Interrupt */
1021 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1022 ret = sci_er_interrupt(irq, ptr);
1024 /* Break Interrupt */
1025 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1026 ret = sci_br_interrupt(irq, ptr);
1032 * Here we define a transition notifier so that we can update all of our
1033 * ports' baud rate when the peripheral clock changes.
1035 static int sci_notifier(struct notifier_block *self,
1036 unsigned long phase, void *p)
1038 struct sci_port *sci_port;
1039 unsigned long flags;
1041 sci_port = container_of(self, struct sci_port, freq_transition);
1043 if ((phase == CPUFREQ_POSTCHANGE) ||
1044 (phase == CPUFREQ_RESUMECHANGE)) {
1045 struct uart_port *port = &sci_port->port;
1047 spin_lock_irqsave(&port->lock, flags);
1048 port->uartclk = clk_get_rate(sci_port->iclk);
1049 spin_unlock_irqrestore(&port->lock, flags);
1055 static struct sci_irq_desc {
1057 irq_handler_t handler;
1058 } sci_irq_desc[] = {
1060 * Split out handlers, the default case.
1064 .handler = sci_er_interrupt,
1069 .handler = sci_rx_interrupt,
1074 .handler = sci_tx_interrupt,
1079 .handler = sci_br_interrupt,
1083 * Special muxed handler.
1087 .handler = sci_mpxed_interrupt,
1091 static int sci_request_irq(struct sci_port *port)
1093 struct uart_port *up = &port->port;
1096 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1097 struct sci_irq_desc *desc;
1100 if (SCIx_IRQ_IS_MUXED(port)) {
1104 irq = port->irqs[i];
1107 * Certain port types won't support all of the
1108 * available interrupt sources.
1110 if (unlikely(irq < 0))
1114 desc = sci_irq_desc + i;
1115 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1116 dev_name(up->dev), desc->desc);
1117 if (!port->irqstr[j]) {
1118 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1123 ret = request_irq(irq, desc->handler, up->irqflags,
1124 port->irqstr[j], port);
1125 if (unlikely(ret)) {
1126 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1135 free_irq(port->irqs[i], port);
1139 kfree(port->irqstr[j]);
1144 static void sci_free_irq(struct sci_port *port)
1149 * Intentionally in reverse order so we iterate over the muxed
1152 for (i = 0; i < SCIx_NR_IRQS; i++) {
1153 int irq = port->irqs[i];
1156 * Certain port types won't support all of the available
1157 * interrupt sources.
1159 if (unlikely(irq < 0))
1162 free_irq(port->irqs[i], port);
1163 kfree(port->irqstr[i]);
1165 if (SCIx_IRQ_IS_MUXED(port)) {
1166 /* If there's only one IRQ, we're done. */
1172 static unsigned int sci_tx_empty(struct uart_port *port)
1174 unsigned short status = serial_port_in(port, SCxSR);
1175 unsigned short in_tx_fifo = sci_txfill(port);
1177 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1181 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1182 * CTS/RTS is supported in hardware by at least one port and controlled
1183 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1184 * handled via the ->init_pins() op, which is a bit of a one-way street,
1185 * lacking any ability to defer pin control -- this will later be
1186 * converted over to the GPIO framework).
1188 * Other modes (such as loopback) are supported generically on certain
1189 * port types, but not others. For these it's sufficient to test for the
1190 * existence of the support register and simply ignore the port type.
1192 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1194 if (mctrl & TIOCM_LOOP) {
1195 struct plat_sci_reg *reg;
1198 * Standard loopback mode for SCFCR ports.
1200 reg = sci_getreg(port, SCFCR);
1202 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1206 static unsigned int sci_get_mctrl(struct uart_port *port)
1209 * CTS/RTS is handled in hardware when supported, while nothing
1210 * else is wired up. Keep it simple and simply assert DSR/CAR.
1212 return TIOCM_DSR | TIOCM_CAR;
1215 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1216 static void sci_dma_tx_complete(void *arg)
1218 struct sci_port *s = arg;
1219 struct uart_port *port = &s->port;
1220 struct circ_buf *xmit = &port->state->xmit;
1221 unsigned long flags;
1223 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1225 spin_lock_irqsave(&port->lock, flags);
1227 xmit->tail += sg_dma_len(&s->sg_tx);
1228 xmit->tail &= UART_XMIT_SIZE - 1;
1230 port->icount.tx += sg_dma_len(&s->sg_tx);
1232 async_tx_ack(s->desc_tx);
1235 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1236 uart_write_wakeup(port);
1238 if (!uart_circ_empty(xmit)) {
1240 schedule_work(&s->work_tx);
1242 s->cookie_tx = -EINVAL;
1243 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1244 u16 ctrl = serial_port_in(port, SCSCR);
1245 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1249 spin_unlock_irqrestore(&port->lock, flags);
1252 /* Locking: called with port lock held */
1253 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1255 struct uart_port *port = &s->port;
1256 struct tty_port *tport = &port->state->port;
1257 int i, active, room;
1259 room = tty_buffer_request_room(tport, count);
1261 if (s->active_rx == s->cookie_rx[0]) {
1263 } else if (s->active_rx == s->cookie_rx[1]) {
1266 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1271 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1276 for (i = 0; i < room; i++)
1277 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1280 port->icount.rx += room;
1285 static void sci_dma_rx_complete(void *arg)
1287 struct sci_port *s = arg;
1288 struct uart_port *port = &s->port;
1289 unsigned long flags;
1292 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1294 spin_lock_irqsave(&port->lock, flags);
1296 count = sci_dma_rx_push(s, s->buf_len_rx);
1298 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1300 spin_unlock_irqrestore(&port->lock, flags);
1303 tty_flip_buffer_push(&port->state->port);
1305 schedule_work(&s->work_rx);
1308 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1310 struct dma_chan *chan = s->chan_rx;
1311 struct uart_port *port = &s->port;
1314 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1315 dma_release_channel(chan);
1316 if (sg_dma_address(&s->sg_rx[0]))
1317 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1318 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1323 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1325 struct dma_chan *chan = s->chan_tx;
1326 struct uart_port *port = &s->port;
1329 s->cookie_tx = -EINVAL;
1330 dma_release_channel(chan);
1335 static void sci_submit_rx(struct sci_port *s)
1337 struct dma_chan *chan = s->chan_rx;
1340 for (i = 0; i < 2; i++) {
1341 struct scatterlist *sg = &s->sg_rx[i];
1342 struct dma_async_tx_descriptor *desc;
1344 desc = dmaengine_prep_slave_sg(chan,
1345 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1348 s->desc_rx[i] = desc;
1349 desc->callback = sci_dma_rx_complete;
1350 desc->callback_param = s;
1351 s->cookie_rx[i] = desc->tx_submit(desc);
1354 if (!desc || s->cookie_rx[i] < 0) {
1356 async_tx_ack(s->desc_rx[0]);
1357 s->cookie_rx[0] = -EINVAL;
1361 s->cookie_rx[i] = -EINVAL;
1363 dev_warn(s->port.dev,
1364 "failed to re-start DMA, using PIO\n");
1365 sci_rx_dma_release(s, true);
1368 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1369 s->cookie_rx[i], i);
1372 s->active_rx = s->cookie_rx[0];
1374 dma_async_issue_pending(chan);
1377 static void work_fn_rx(struct work_struct *work)
1379 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1380 struct uart_port *port = &s->port;
1381 struct dma_async_tx_descriptor *desc;
1384 if (s->active_rx == s->cookie_rx[0]) {
1386 } else if (s->active_rx == s->cookie_rx[1]) {
1389 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1392 desc = s->desc_rx[new];
1394 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1396 /* Handle incomplete DMA receive */
1397 struct dma_chan *chan = s->chan_rx;
1398 struct shdma_desc *sh_desc = container_of(desc,
1399 struct shdma_desc, async_tx);
1400 unsigned long flags;
1403 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1404 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1405 sh_desc->partial, sh_desc->cookie);
1407 spin_lock_irqsave(&port->lock, flags);
1408 count = sci_dma_rx_push(s, sh_desc->partial);
1409 spin_unlock_irqrestore(&port->lock, flags);
1412 tty_flip_buffer_push(&port->state->port);
1419 s->cookie_rx[new] = desc->tx_submit(desc);
1420 if (s->cookie_rx[new] < 0) {
1421 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1422 sci_rx_dma_release(s, true);
1426 s->active_rx = s->cookie_rx[!new];
1428 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1429 s->cookie_rx[new], new, s->active_rx);
1432 static void work_fn_tx(struct work_struct *work)
1434 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1435 struct dma_async_tx_descriptor *desc;
1436 struct dma_chan *chan = s->chan_tx;
1437 struct uart_port *port = &s->port;
1438 struct circ_buf *xmit = &port->state->xmit;
1439 struct scatterlist *sg = &s->sg_tx;
1443 * Port xmit buffer is already mapped, and it is one page... Just adjust
1444 * offsets and lengths. Since it is a circular buffer, we have to
1445 * transmit till the end, and then the rest. Take the port lock to get a
1446 * consistent xmit buffer state.
1448 spin_lock_irq(&port->lock);
1449 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1450 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1452 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1453 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1454 spin_unlock_irq(&port->lock);
1456 BUG_ON(!sg_dma_len(sg));
1458 desc = dmaengine_prep_slave_sg(chan,
1459 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1463 sci_tx_dma_release(s, true);
1467 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1469 spin_lock_irq(&port->lock);
1471 desc->callback = sci_dma_tx_complete;
1472 desc->callback_param = s;
1473 spin_unlock_irq(&port->lock);
1474 s->cookie_tx = desc->tx_submit(desc);
1475 if (s->cookie_tx < 0) {
1476 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1478 sci_tx_dma_release(s, true);
1482 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1483 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1485 dma_async_issue_pending(chan);
1489 static void sci_start_tx(struct uart_port *port)
1491 struct sci_port *s = to_sci_port(port);
1492 unsigned short ctrl;
1494 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1495 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1496 u16 new, scr = serial_port_in(port, SCSCR);
1500 new = scr & ~0x8000;
1502 serial_port_out(port, SCSCR, new);
1505 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1508 schedule_work(&s->work_tx);
1512 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1513 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1514 ctrl = serial_port_in(port, SCSCR);
1515 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1519 static void sci_stop_tx(struct uart_port *port)
1521 unsigned short ctrl;
1523 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1524 ctrl = serial_port_in(port, SCSCR);
1526 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1531 serial_port_out(port, SCSCR, ctrl);
1534 static void sci_start_rx(struct uart_port *port)
1536 unsigned short ctrl;
1538 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1543 serial_port_out(port, SCSCR, ctrl);
1546 static void sci_stop_rx(struct uart_port *port)
1548 unsigned short ctrl;
1550 ctrl = serial_port_in(port, SCSCR);
1552 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1555 ctrl &= ~port_rx_irq_mask(port);
1557 serial_port_out(port, SCSCR, ctrl);
1560 static void sci_enable_ms(struct uart_port *port)
1563 * Not supported by hardware, always a nop.
1567 static void sci_break_ctl(struct uart_port *port, int break_state)
1569 struct sci_port *s = to_sci_port(port);
1570 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1571 unsigned short scscr, scsptr;
1573 /* check wheter the port has SCSPTR */
1576 * Not supported by hardware. Most parts couple break and rx
1577 * interrupts together, with break detection always enabled.
1582 scsptr = serial_port_in(port, SCSPTR);
1583 scscr = serial_port_in(port, SCSCR);
1585 if (break_state == -1) {
1586 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1589 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1593 serial_port_out(port, SCSPTR, scsptr);
1594 serial_port_out(port, SCSCR, scscr);
1597 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1598 static bool filter(struct dma_chan *chan, void *slave)
1600 struct sh_dmae_slave *param = slave;
1602 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1603 param->shdma_slave.slave_id);
1605 chan->private = ¶m->shdma_slave;
1609 static void rx_timer_fn(unsigned long arg)
1611 struct sci_port *s = (struct sci_port *)arg;
1612 struct uart_port *port = &s->port;
1613 u16 scr = serial_port_in(port, SCSCR);
1615 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1617 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1619 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1620 dev_dbg(port->dev, "DMA Rx timed out\n");
1621 schedule_work(&s->work_rx);
1624 static void sci_request_dma(struct uart_port *port)
1626 struct sci_port *s = to_sci_port(port);
1627 struct sh_dmae_slave *param;
1628 struct dma_chan *chan;
1629 dma_cap_mask_t mask;
1632 dev_dbg(port->dev, "%s: port %d\n", __func__,
1635 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1639 dma_cap_set(DMA_SLAVE, mask);
1641 param = &s->param_tx;
1643 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1644 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1646 s->cookie_tx = -EINVAL;
1647 chan = dma_request_channel(mask, filter, param);
1648 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1651 sg_init_table(&s->sg_tx, 1);
1652 /* UART circular tx buffer is an aligned page. */
1653 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1654 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1656 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1657 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1659 sci_tx_dma_release(s, false);
1661 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1662 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1663 &sg_dma_address(&s->sg_tx));
1665 s->sg_len_tx = nent;
1667 INIT_WORK(&s->work_tx, work_fn_tx);
1670 param = &s->param_rx;
1672 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1673 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1675 chan = dma_request_channel(mask, filter, param);
1676 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1684 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1685 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1686 &dma[0], GFP_KERNEL);
1690 "failed to allocate dma buffer, using PIO\n");
1691 sci_rx_dma_release(s, true);
1695 buf[1] = buf[0] + s->buf_len_rx;
1696 dma[1] = dma[0] + s->buf_len_rx;
1698 for (i = 0; i < 2; i++) {
1699 struct scatterlist *sg = &s->sg_rx[i];
1701 sg_init_table(sg, 1);
1702 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1703 (uintptr_t)buf[i] & ~PAGE_MASK);
1704 sg_dma_address(sg) = dma[i];
1707 INIT_WORK(&s->work_rx, work_fn_rx);
1708 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1714 static void sci_free_dma(struct uart_port *port)
1716 struct sci_port *s = to_sci_port(port);
1719 sci_tx_dma_release(s, false);
1721 sci_rx_dma_release(s, false);
1724 static inline void sci_request_dma(struct uart_port *port)
1728 static inline void sci_free_dma(struct uart_port *port)
1733 static int sci_startup(struct uart_port *port)
1735 struct sci_port *s = to_sci_port(port);
1736 unsigned long flags;
1739 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1741 ret = sci_request_irq(s);
1742 if (unlikely(ret < 0))
1745 sci_request_dma(port);
1747 spin_lock_irqsave(&port->lock, flags);
1750 spin_unlock_irqrestore(&port->lock, flags);
1755 static void sci_shutdown(struct uart_port *port)
1757 struct sci_port *s = to_sci_port(port);
1758 unsigned long flags;
1760 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1762 spin_lock_irqsave(&port->lock, flags);
1765 spin_unlock_irqrestore(&port->lock, flags);
1771 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1774 if (s->sampling_rate)
1775 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1777 /* Warn, but use a safe default */
1780 return ((freq + 16 * bps) / (32 * bps) - 1);
1783 /* calculate sample rate, BRR, and clock select for HSCIF */
1784 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1785 int *brr, unsigned int *srr,
1789 int min_err = 1000; /* 100% */
1791 /* Find the combination of sample rate and clock select with the
1792 smallest deviation from the desired baud rate. */
1793 for (sr = 8; sr <= 32; sr++) {
1794 for (c = 0; c <= 3; c++) {
1795 /* integerized formulas from HSCIF documentation */
1796 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1797 if (br < 0 || br > 255)
1799 err = freq / ((br + 1) * bps * sr *
1800 (1 << (2 * c + 1)) / 1000) - 1000;
1801 if (min_err > err) {
1810 if (min_err == 1000) {
1819 static void sci_reset(struct uart_port *port)
1821 struct plat_sci_reg *reg;
1822 unsigned int status;
1825 status = serial_port_in(port, SCxSR);
1826 } while (!(status & SCxSR_TEND(port)));
1828 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1830 reg = sci_getreg(port, SCFCR);
1832 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1835 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1836 struct ktermios *old)
1838 struct sci_port *s = to_sci_port(port);
1839 struct plat_sci_reg *reg;
1840 unsigned int baud, smr_val, max_baud, cks = 0;
1842 unsigned int srr = 15;
1845 * earlyprintk comes here early on with port->uartclk set to zero.
1846 * the clock framework is not up and running at this point so here
1847 * we assume that 115200 is the maximum baud rate. please note that
1848 * the baud rate is not programmed during earlyprintk - it is assumed
1849 * that the previous boot loader has enabled required clocks and
1850 * setup the baud rate generator hardware for us already.
1852 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1854 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1855 if (likely(baud && port->uartclk)) {
1856 if (s->cfg->type == PORT_HSCIF) {
1857 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1860 t = sci_scbrr_calc(s, baud, port->uartclk);
1861 for (cks = 0; t >= 256 && cks <= 3; cks++)
1870 smr_val = serial_port_in(port, SCSMR) & 3;
1872 if ((termios->c_cflag & CSIZE) == CS7)
1874 if (termios->c_cflag & PARENB)
1876 if (termios->c_cflag & PARODD)
1878 if (termios->c_cflag & CSTOPB)
1881 uart_update_timeout(port, termios->c_cflag, baud);
1883 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1884 __func__, smr_val, cks, t, s->cfg->scscr);
1887 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1888 serial_port_out(port, SCBRR, t);
1889 reg = sci_getreg(port, HSSRR);
1891 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1892 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1894 serial_port_out(port, SCSMR, smr_val);
1896 sci_init_pins(port, termios->c_cflag);
1898 reg = sci_getreg(port, SCFCR);
1900 unsigned short ctrl = serial_port_in(port, SCFCR);
1902 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1903 if (termios->c_cflag & CRTSCTS)
1910 * As we've done a sci_reset() above, ensure we don't
1911 * interfere with the FIFOs while toggling MCE. As the
1912 * reset values could still be set, simply mask them out.
1914 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1916 serial_port_out(port, SCFCR, ctrl);
1919 serial_port_out(port, SCSCR, s->cfg->scscr);
1921 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1923 * Calculate delay for 1.5 DMA buffers: see
1924 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1925 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1926 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1927 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1928 * sizes), but it has been found out experimentally, that this is not
1929 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1930 * as a minimum seem to work perfectly.
1933 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1936 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1937 s->rx_timeout * 1000 / HZ, port->timeout);
1938 if (s->rx_timeout < msecs_to_jiffies(20))
1939 s->rx_timeout = msecs_to_jiffies(20);
1943 if ((termios->c_cflag & CREAD) != 0)
1946 sci_port_disable(s);
1949 static void sci_pm(struct uart_port *port, unsigned int state,
1950 unsigned int oldstate)
1952 struct sci_port *sci_port = to_sci_port(port);
1956 sci_port_disable(sci_port);
1959 sci_port_enable(sci_port);
1964 static const char *sci_type(struct uart_port *port)
1966 switch (port->type) {
1984 static inline unsigned long sci_port_size(struct uart_port *port)
1987 * Pick an arbitrary size that encapsulates all of the base
1988 * registers by default. This can be optimized later, or derived
1989 * from platform resource data at such a time that ports begin to
1990 * behave more erratically.
1992 if (port->type == PORT_HSCIF)
1998 static int sci_remap_port(struct uart_port *port)
2000 unsigned long size = sci_port_size(port);
2003 * Nothing to do if there's already an established membase.
2008 if (port->flags & UPF_IOREMAP) {
2009 port->membase = ioremap_nocache(port->mapbase, size);
2010 if (unlikely(!port->membase)) {
2011 dev_err(port->dev, "can't remap port#%d\n", port->line);
2016 * For the simple (and majority of) cases where we don't
2017 * need to do any remapping, just cast the cookie
2020 port->membase = (void __iomem *)port->mapbase;
2026 static void sci_release_port(struct uart_port *port)
2028 if (port->flags & UPF_IOREMAP) {
2029 iounmap(port->membase);
2030 port->membase = NULL;
2033 release_mem_region(port->mapbase, sci_port_size(port));
2036 static int sci_request_port(struct uart_port *port)
2038 unsigned long size = sci_port_size(port);
2039 struct resource *res;
2042 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2043 if (unlikely(res == NULL))
2046 ret = sci_remap_port(port);
2047 if (unlikely(ret != 0)) {
2048 release_resource(res);
2055 static void sci_config_port(struct uart_port *port, int flags)
2057 if (flags & UART_CONFIG_TYPE) {
2058 struct sci_port *sport = to_sci_port(port);
2060 port->type = sport->cfg->type;
2061 sci_request_port(port);
2065 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2067 if (ser->baud_base < 2400)
2068 /* No paper tape reader for Mitch.. */
2074 static struct uart_ops sci_uart_ops = {
2075 .tx_empty = sci_tx_empty,
2076 .set_mctrl = sci_set_mctrl,
2077 .get_mctrl = sci_get_mctrl,
2078 .start_tx = sci_start_tx,
2079 .stop_tx = sci_stop_tx,
2080 .stop_rx = sci_stop_rx,
2081 .enable_ms = sci_enable_ms,
2082 .break_ctl = sci_break_ctl,
2083 .startup = sci_startup,
2084 .shutdown = sci_shutdown,
2085 .set_termios = sci_set_termios,
2088 .release_port = sci_release_port,
2089 .request_port = sci_request_port,
2090 .config_port = sci_config_port,
2091 .verify_port = sci_verify_port,
2092 #ifdef CONFIG_CONSOLE_POLL
2093 .poll_get_char = sci_poll_get_char,
2094 .poll_put_char = sci_poll_put_char,
2098 static int sci_init_single(struct platform_device *dev,
2099 struct sci_port *sci_port, unsigned int index,
2100 struct plat_sci_port *p, bool early)
2102 struct uart_port *port = &sci_port->port;
2103 const struct resource *res;
2104 unsigned int sampling_rate;
2110 port->ops = &sci_uart_ops;
2111 port->iotype = UPIO_MEM;
2114 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2118 port->mapbase = res->start;
2120 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2121 sci_port->irqs[i] = platform_get_irq(dev, i);
2123 /* The SCI generates several interrupts. They can be muxed together or
2124 * connected to different interrupt lines. In the muxed case only one
2125 * interrupt resource is specified. In the non-muxed case three or four
2126 * interrupt resources are specified, as the BRI interrupt is optional.
2128 if (sci_port->irqs[0] < 0)
2131 if (sci_port->irqs[1] < 0) {
2132 sci_port->irqs[1] = sci_port->irqs[0];
2133 sci_port->irqs[2] = sci_port->irqs[0];
2134 sci_port->irqs[3] = sci_port->irqs[0];
2137 if (p->regtype == SCIx_PROBE_REGTYPE) {
2138 ret = sci_probe_regmap(p);
2145 port->fifosize = 256;
2146 sci_port->overrun_bit = 9;
2150 port->fifosize = 128;
2152 sci_port->overrun_bit = 0;
2155 port->fifosize = 64;
2156 sci_port->overrun_bit = 9;
2160 port->fifosize = 16;
2161 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2162 sci_port->overrun_bit = 9;
2165 sci_port->overrun_bit = 0;
2171 sci_port->overrun_bit = 5;
2176 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2177 * match the SoC datasheet, this should be investigated. Let platform
2178 * data override the sampling rate for now.
2180 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2184 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2185 if (IS_ERR(sci_port->iclk)) {
2186 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2187 if (IS_ERR(sci_port->iclk)) {
2188 dev_err(&dev->dev, "can't get iclk\n");
2189 return PTR_ERR(sci_port->iclk);
2194 * The function clock is optional, ignore it if we can't
2197 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2198 if (IS_ERR(sci_port->fclk))
2199 sci_port->fclk = NULL;
2201 port->dev = &dev->dev;
2203 pm_runtime_enable(&dev->dev);
2206 sci_port->break_timer.data = (unsigned long)sci_port;
2207 sci_port->break_timer.function = sci_break_timer;
2208 init_timer(&sci_port->break_timer);
2211 * Establish some sensible defaults for the error detection.
2213 sci_port->error_mask = (p->type == PORT_SCI) ?
2214 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2217 * Establish sensible defaults for the overrun detection, unless
2218 * the part has explicitly disabled support for it.
2222 * Make the error mask inclusive of overrun detection, if
2225 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2227 port->type = p->type;
2228 port->flags = UPF_FIXED_PORT | p->flags;
2229 port->regshift = p->regshift;
2232 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2233 * for the multi-IRQ ports, which is where we are primarily
2234 * concerned with the shutdown path synchronization.
2236 * For the muxed case there's nothing more to do.
2238 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2241 port->serial_in = sci_serial_in;
2242 port->serial_out = sci_serial_out;
2244 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2245 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2246 p->dma_slave_tx, p->dma_slave_rx);
2251 static void sci_cleanup_single(struct sci_port *port)
2253 clk_put(port->iclk);
2254 clk_put(port->fclk);
2256 pm_runtime_disable(port->port.dev);
2259 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2260 static void serial_console_putchar(struct uart_port *port, int ch)
2262 sci_poll_put_char(port, ch);
2266 * Print a string to the serial port trying not to disturb
2267 * any possible real use of the port...
2269 static void serial_console_write(struct console *co, const char *s,
2272 struct sci_port *sci_port = &sci_ports[co->index];
2273 struct uart_port *port = &sci_port->port;
2274 unsigned short bits, ctrl;
2275 unsigned long flags;
2278 local_irq_save(flags);
2281 else if (oops_in_progress)
2282 locked = spin_trylock(&port->lock);
2284 spin_lock(&port->lock);
2286 /* first save the SCSCR then disable the interrupts */
2287 ctrl = serial_port_in(port, SCSCR);
2288 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2290 uart_console_write(port, s, count, serial_console_putchar);
2292 /* wait until fifo is empty and last bit has been transmitted */
2293 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2294 while ((serial_port_in(port, SCxSR) & bits) != bits)
2297 /* restore the SCSCR */
2298 serial_port_out(port, SCSCR, ctrl);
2301 spin_unlock(&port->lock);
2302 local_irq_restore(flags);
2305 static int serial_console_setup(struct console *co, char *options)
2307 struct sci_port *sci_port;
2308 struct uart_port *port;
2316 * Refuse to handle any bogus ports.
2318 if (co->index < 0 || co->index >= SCI_NPORTS)
2321 sci_port = &sci_ports[co->index];
2322 port = &sci_port->port;
2325 * Refuse to handle uninitialized ports.
2330 ret = sci_remap_port(port);
2331 if (unlikely(ret != 0))
2335 uart_parse_options(options, &baud, &parity, &bits, &flow);
2337 return uart_set_options(port, co, baud, parity, bits, flow);
2340 static struct console serial_console = {
2342 .device = uart_console_device,
2343 .write = serial_console_write,
2344 .setup = serial_console_setup,
2345 .flags = CON_PRINTBUFFER,
2347 .data = &sci_uart_driver,
2350 static struct console early_serial_console = {
2351 .name = "early_ttySC",
2352 .write = serial_console_write,
2353 .flags = CON_PRINTBUFFER,
2357 static char early_serial_buf[32];
2359 static int sci_probe_earlyprintk(struct platform_device *pdev)
2361 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2363 if (early_serial_console.data)
2366 early_serial_console.index = pdev->id;
2368 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2370 serial_console_setup(&early_serial_console, early_serial_buf);
2372 if (!strstr(early_serial_buf, "keep"))
2373 early_serial_console.flags |= CON_BOOT;
2375 register_console(&early_serial_console);
2379 #define SCI_CONSOLE (&serial_console)
2382 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2387 #define SCI_CONSOLE NULL
2389 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2391 static char banner[] __initdata =
2392 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2394 static struct uart_driver sci_uart_driver = {
2395 .owner = THIS_MODULE,
2396 .driver_name = "sci",
2397 .dev_name = "ttySC",
2399 .minor = SCI_MINOR_START,
2401 .cons = SCI_CONSOLE,
2404 static int sci_remove(struct platform_device *dev)
2406 struct sci_port *port = platform_get_drvdata(dev);
2408 cpufreq_unregister_notifier(&port->freq_transition,
2409 CPUFREQ_TRANSITION_NOTIFIER);
2411 uart_remove_one_port(&sci_uart_driver, &port->port);
2413 sci_cleanup_single(port);
2418 static int sci_probe_single(struct platform_device *dev,
2420 struct plat_sci_port *p,
2421 struct sci_port *sciport)
2426 if (unlikely(index >= SCI_NPORTS)) {
2427 dev_notice(&dev->dev, "Attempting to register port "
2428 "%d when only %d are available.\n",
2429 index+1, SCI_NPORTS);
2430 dev_notice(&dev->dev, "Consider bumping "
2431 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2435 ret = sci_init_single(dev, sciport, index, p, false);
2439 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2441 sci_cleanup_single(sciport);
2448 static int sci_probe(struct platform_device *dev)
2450 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
2451 struct sci_port *sp = &sci_ports[dev->id];
2455 * If we've come here via earlyprintk initialization, head off to
2456 * the special early probe. We don't have sufficient device state
2457 * to make it beyond this yet.
2459 if (is_early_platform_device(dev))
2460 return sci_probe_earlyprintk(dev);
2462 platform_set_drvdata(dev, sp);
2464 ret = sci_probe_single(dev, dev->id, p, sp);
2468 sp->freq_transition.notifier_call = sci_notifier;
2470 ret = cpufreq_register_notifier(&sp->freq_transition,
2471 CPUFREQ_TRANSITION_NOTIFIER);
2472 if (unlikely(ret < 0)) {
2473 sci_cleanup_single(sp);
2477 #ifdef CONFIG_SH_STANDARD_BIOS
2478 sh_bios_gdb_detach();
2484 static int sci_suspend(struct device *dev)
2486 struct sci_port *sport = dev_get_drvdata(dev);
2489 uart_suspend_port(&sci_uart_driver, &sport->port);
2494 static int sci_resume(struct device *dev)
2496 struct sci_port *sport = dev_get_drvdata(dev);
2499 uart_resume_port(&sci_uart_driver, &sport->port);
2504 static const struct dev_pm_ops sci_dev_pm_ops = {
2505 .suspend = sci_suspend,
2506 .resume = sci_resume,
2509 static struct platform_driver sci_driver = {
2511 .remove = sci_remove,
2514 .owner = THIS_MODULE,
2515 .pm = &sci_dev_pm_ops,
2519 static int __init sci_init(void)
2525 ret = uart_register_driver(&sci_uart_driver);
2526 if (likely(ret == 0)) {
2527 ret = platform_driver_register(&sci_driver);
2529 uart_unregister_driver(&sci_uart_driver);
2535 static void __exit sci_exit(void)
2537 platform_driver_unregister(&sci_driver);
2538 uart_unregister_driver(&sci_uart_driver);
2541 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2542 early_platform_init_buffer("earlyprintk", &sci_driver,
2543 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2545 module_init(sci_init);
2546 module_exit(sci_exit);
2548 MODULE_LICENSE("GPL");
2549 MODULE_ALIAS("platform:sh-sci");
2550 MODULE_AUTHOR("Paul Mundt");
2551 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");