2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
60 #include "serial_mctrl_gpio.h"
63 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
105 struct uart_port port;
107 /* Platform configuration */
108 struct plat_sci_port *cfg;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int error_mask;
112 unsigned int error_clear;
113 unsigned int sampling_rate_mask;
114 resource_size_t reg_size;
115 struct mctrl_gpios *gpios;
118 struct timer_list break_timer;
122 struct clk *clks[SCI_NUM_CLKS];
123 unsigned long clk_rates[SCI_NUM_CLKS];
125 int irqs[SCIx_NR_IRQS];
126 char *irqstr[SCIx_NR_IRQS];
128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
131 #ifdef CONFIG_SERIAL_SH_SCI_DMA
132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx[2];
134 dma_cookie_t active_rx;
135 dma_addr_t tx_dma_addr;
136 unsigned int tx_dma_len;
137 struct scatterlist sg_rx[2];
140 struct work_struct work_tx;
141 struct timer_list rx_timer;
142 unsigned int rx_timeout;
146 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
148 static struct sci_port sci_ports[SCI_NPORTS];
149 static struct uart_driver sci_uart_driver;
151 static inline struct sci_port *
152 to_sci_port(struct uart_port *uart)
154 return container_of(uart, struct sci_port, port);
157 struct plat_sci_reg {
161 /* Helper for invalidating specific entries of an inherited map. */
162 #define sci_reg_invalid { .offset = 0, .size = 0 }
164 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
165 [SCIx_PROBE_REGTYPE] = {
166 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
170 * Common SCI definitions, dependent on the port's regshift
173 [SCIx_SCI_REGTYPE] = {
174 [SCSMR] = { 0x00, 8 },
175 [SCBRR] = { 0x01, 8 },
176 [SCSCR] = { 0x02, 8 },
177 [SCxTDR] = { 0x03, 8 },
178 [SCxSR] = { 0x04, 8 },
179 [SCxRDR] = { 0x05, 8 },
180 [SCFCR] = sci_reg_invalid,
181 [SCFDR] = sci_reg_invalid,
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 [HSSRR] = sci_reg_invalid,
187 [SCPCR] = sci_reg_invalid,
188 [SCPDR] = sci_reg_invalid,
189 [SCDL] = sci_reg_invalid,
190 [SCCKS] = sci_reg_invalid,
194 * Common definitions for legacy IrDA ports, dependent on
197 [SCIx_IRDA_REGTYPE] = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x01, 8 },
200 [SCSCR] = { 0x02, 8 },
201 [SCxTDR] = { 0x03, 8 },
202 [SCxSR] = { 0x04, 8 },
203 [SCxRDR] = { 0x05, 8 },
204 [SCFCR] = { 0x06, 8 },
205 [SCFDR] = { 0x07, 16 },
206 [SCTFDR] = sci_reg_invalid,
207 [SCRFDR] = sci_reg_invalid,
208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
210 [HSSRR] = sci_reg_invalid,
211 [SCPCR] = sci_reg_invalid,
212 [SCPDR] = sci_reg_invalid,
213 [SCDL] = sci_reg_invalid,
214 [SCCKS] = sci_reg_invalid,
218 * Common SCIFA definitions.
220 [SCIx_SCIFA_REGTYPE] = {
221 [SCSMR] = { 0x00, 16 },
222 [SCBRR] = { 0x04, 8 },
223 [SCSCR] = { 0x08, 16 },
224 [SCxTDR] = { 0x20, 8 },
225 [SCxSR] = { 0x14, 16 },
226 [SCxRDR] = { 0x24, 8 },
227 [SCFCR] = { 0x18, 16 },
228 [SCFDR] = { 0x1c, 16 },
229 [SCTFDR] = sci_reg_invalid,
230 [SCRFDR] = sci_reg_invalid,
231 [SCSPTR] = sci_reg_invalid,
232 [SCLSR] = sci_reg_invalid,
233 [HSSRR] = sci_reg_invalid,
234 [SCPCR] = { 0x30, 16 },
235 [SCPDR] = { 0x34, 16 },
236 [SCDL] = sci_reg_invalid,
237 [SCCKS] = sci_reg_invalid,
241 * Common SCIFB definitions.
243 [SCIx_SCIFB_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = sci_reg_invalid,
252 [SCTFDR] = { 0x38, 16 },
253 [SCRFDR] = { 0x3c, 16 },
254 [SCSPTR] = sci_reg_invalid,
255 [SCLSR] = sci_reg_invalid,
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = { 0x30, 16 },
258 [SCPDR] = { 0x34, 16 },
259 [SCDL] = sci_reg_invalid,
260 [SCCKS] = sci_reg_invalid,
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
268 [SCSMR] = { 0x00, 16 },
269 [SCBRR] = { 0x04, 8 },
270 [SCSCR] = { 0x08, 16 },
271 [SCxTDR] = { 0x0c, 8 },
272 [SCxSR] = { 0x10, 16 },
273 [SCxRDR] = { 0x14, 8 },
274 [SCFCR] = { 0x18, 16 },
275 [SCFDR] = { 0x1c, 16 },
276 [SCTFDR] = sci_reg_invalid,
277 [SCRFDR] = sci_reg_invalid,
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 [HSSRR] = sci_reg_invalid,
281 [SCPCR] = sci_reg_invalid,
282 [SCPDR] = sci_reg_invalid,
283 [SCDL] = sci_reg_invalid,
284 [SCCKS] = sci_reg_invalid,
288 * Common SH-3 SCIF definitions.
290 [SCIx_SH3_SCIF_REGTYPE] = {
291 [SCSMR] = { 0x00, 8 },
292 [SCBRR] = { 0x02, 8 },
293 [SCSCR] = { 0x04, 8 },
294 [SCxTDR] = { 0x06, 8 },
295 [SCxSR] = { 0x08, 16 },
296 [SCxRDR] = { 0x0a, 8 },
297 [SCFCR] = { 0x0c, 8 },
298 [SCFDR] = { 0x0e, 16 },
299 [SCTFDR] = sci_reg_invalid,
300 [SCRFDR] = sci_reg_invalid,
301 [SCSPTR] = sci_reg_invalid,
302 [SCLSR] = sci_reg_invalid,
303 [HSSRR] = sci_reg_invalid,
304 [SCPCR] = sci_reg_invalid,
305 [SCPDR] = sci_reg_invalid,
306 [SCDL] = sci_reg_invalid,
307 [SCCKS] = sci_reg_invalid,
311 * Common SH-4(A) SCIF(B) definitions.
313 [SCIx_SH4_SCIF_REGTYPE] = {
314 [SCSMR] = { 0x00, 16 },
315 [SCBRR] = { 0x04, 8 },
316 [SCSCR] = { 0x08, 16 },
317 [SCxTDR] = { 0x0c, 8 },
318 [SCxSR] = { 0x10, 16 },
319 [SCxRDR] = { 0x14, 8 },
320 [SCFCR] = { 0x18, 16 },
321 [SCFDR] = { 0x1c, 16 },
322 [SCTFDR] = sci_reg_invalid,
323 [SCRFDR] = sci_reg_invalid,
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 [HSSRR] = sci_reg_invalid,
327 [SCPCR] = sci_reg_invalid,
328 [SCPDR] = sci_reg_invalid,
329 [SCDL] = sci_reg_invalid,
330 [SCCKS] = sci_reg_invalid,
334 * Common SCIF definitions for ports with a Baud Rate Generator for
335 * External Clock (BRG).
337 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
338 [SCSMR] = { 0x00, 16 },
339 [SCBRR] = { 0x04, 8 },
340 [SCSCR] = { 0x08, 16 },
341 [SCxTDR] = { 0x0c, 8 },
342 [SCxSR] = { 0x10, 16 },
343 [SCxRDR] = { 0x14, 8 },
344 [SCFCR] = { 0x18, 16 },
345 [SCFDR] = { 0x1c, 16 },
346 [SCTFDR] = sci_reg_invalid,
347 [SCRFDR] = sci_reg_invalid,
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [HSSRR] = sci_reg_invalid,
351 [SCPCR] = sci_reg_invalid,
352 [SCPDR] = sci_reg_invalid,
353 [SCDL] = { 0x30, 16 },
354 [SCCKS] = { 0x34, 16 },
358 * Common HSCIF definitions.
360 [SCIx_HSCIF_REGTYPE] = {
361 [SCSMR] = { 0x00, 16 },
362 [SCBRR] = { 0x04, 8 },
363 [SCSCR] = { 0x08, 16 },
364 [SCxTDR] = { 0x0c, 8 },
365 [SCxSR] = { 0x10, 16 },
366 [SCxRDR] = { 0x14, 8 },
367 [SCFCR] = { 0x18, 16 },
368 [SCFDR] = { 0x1c, 16 },
369 [SCTFDR] = sci_reg_invalid,
370 [SCRFDR] = sci_reg_invalid,
371 [SCSPTR] = { 0x20, 16 },
372 [SCLSR] = { 0x24, 16 },
373 [HSSRR] = { 0x40, 16 },
374 [SCPCR] = sci_reg_invalid,
375 [SCPDR] = sci_reg_invalid,
376 [SCDL] = { 0x30, 16 },
377 [SCCKS] = { 0x34, 16 },
381 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
384 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
385 [SCSMR] = { 0x00, 16 },
386 [SCBRR] = { 0x04, 8 },
387 [SCSCR] = { 0x08, 16 },
388 [SCxTDR] = { 0x0c, 8 },
389 [SCxSR] = { 0x10, 16 },
390 [SCxRDR] = { 0x14, 8 },
391 [SCFCR] = { 0x18, 16 },
392 [SCFDR] = { 0x1c, 16 },
393 [SCTFDR] = sci_reg_invalid,
394 [SCRFDR] = sci_reg_invalid,
395 [SCSPTR] = sci_reg_invalid,
396 [SCLSR] = { 0x24, 16 },
397 [HSSRR] = sci_reg_invalid,
398 [SCPCR] = sci_reg_invalid,
399 [SCPDR] = sci_reg_invalid,
400 [SCDL] = sci_reg_invalid,
401 [SCCKS] = sci_reg_invalid,
405 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
408 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
409 [SCSMR] = { 0x00, 16 },
410 [SCBRR] = { 0x04, 8 },
411 [SCSCR] = { 0x08, 16 },
412 [SCxTDR] = { 0x0c, 8 },
413 [SCxSR] = { 0x10, 16 },
414 [SCxRDR] = { 0x14, 8 },
415 [SCFCR] = { 0x18, 16 },
416 [SCFDR] = { 0x1c, 16 },
417 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
418 [SCRFDR] = { 0x20, 16 },
419 [SCSPTR] = { 0x24, 16 },
420 [SCLSR] = { 0x28, 16 },
421 [HSSRR] = sci_reg_invalid,
422 [SCPCR] = sci_reg_invalid,
423 [SCPDR] = sci_reg_invalid,
424 [SCDL] = sci_reg_invalid,
425 [SCCKS] = sci_reg_invalid,
429 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
432 [SCIx_SH7705_SCIF_REGTYPE] = {
433 [SCSMR] = { 0x00, 16 },
434 [SCBRR] = { 0x04, 8 },
435 [SCSCR] = { 0x08, 16 },
436 [SCxTDR] = { 0x20, 8 },
437 [SCxSR] = { 0x14, 16 },
438 [SCxRDR] = { 0x24, 8 },
439 [SCFCR] = { 0x18, 16 },
440 [SCFDR] = { 0x1c, 16 },
441 [SCTFDR] = sci_reg_invalid,
442 [SCRFDR] = sci_reg_invalid,
443 [SCSPTR] = sci_reg_invalid,
444 [SCLSR] = sci_reg_invalid,
445 [HSSRR] = sci_reg_invalid,
446 [SCPCR] = sci_reg_invalid,
447 [SCPDR] = sci_reg_invalid,
448 [SCDL] = sci_reg_invalid,
449 [SCCKS] = sci_reg_invalid,
453 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
456 * The "offset" here is rather misleading, in that it refers to an enum
457 * value relative to the port mapping rather than the fixed offset
458 * itself, which needs to be manually retrieved from the platform's
459 * register map for the given port.
461 static unsigned int sci_serial_in(struct uart_port *p, int offset)
463 const struct plat_sci_reg *reg = sci_getreg(p, offset);
466 return ioread8(p->membase + (reg->offset << p->regshift));
467 else if (reg->size == 16)
468 return ioread16(p->membase + (reg->offset << p->regshift));
470 WARN(1, "Invalid register access\n");
475 static void sci_serial_out(struct uart_port *p, int offset, int value)
477 const struct plat_sci_reg *reg = sci_getreg(p, offset);
480 iowrite8(value, p->membase + (reg->offset << p->regshift));
481 else if (reg->size == 16)
482 iowrite16(value, p->membase + (reg->offset << p->regshift));
484 WARN(1, "Invalid register access\n");
487 static int sci_probe_regmap(struct plat_sci_port *cfg)
491 cfg->regtype = SCIx_SCI_REGTYPE;
494 cfg->regtype = SCIx_IRDA_REGTYPE;
497 cfg->regtype = SCIx_SCIFA_REGTYPE;
500 cfg->regtype = SCIx_SCIFB_REGTYPE;
504 * The SH-4 is a bit of a misnomer here, although that's
505 * where this particular port layout originated. This
506 * configuration (or some slight variation thereof)
507 * remains the dominant model for all SCIFs.
509 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512 cfg->regtype = SCIx_HSCIF_REGTYPE;
515 pr_err("Can't probe register map for given port\n");
522 static void sci_port_enable(struct sci_port *sci_port)
526 if (!sci_port->port.dev)
529 pm_runtime_get_sync(sci_port->port.dev);
531 for (i = 0; i < SCI_NUM_CLKS; i++) {
532 clk_prepare_enable(sci_port->clks[i]);
533 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
535 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
538 static void sci_port_disable(struct sci_port *sci_port)
542 if (!sci_port->port.dev)
545 /* Cancel the break timer to ensure that the timer handler will not try
546 * to access the hardware with clocks and power disabled. Reset the
547 * break flag to make the break debouncing state machine ready for the
550 del_timer_sync(&sci_port->break_timer);
551 sci_port->break_flag = 0;
553 for (i = SCI_NUM_CLKS; i-- > 0; )
554 clk_disable_unprepare(sci_port->clks[i]);
556 pm_runtime_put_sync(sci_port->port.dev);
559 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 * Not all ports (such as SCIFA) will support REIE. Rather than
563 * special-casing the port type, we check the port initialization
564 * IRQ enable mask to see whether the IRQ is desired at all. If
565 * it's unset, it's logically inferred that there's no point in
568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 static void sci_start_tx(struct uart_port *port)
573 struct sci_port *s = to_sci_port(port);
576 #ifdef CONFIG_SERIAL_SH_SCI_DMA
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
578 u16 new, scr = serial_port_in(port, SCSCR);
580 new = scr | SCSCR_TDRQE;
582 new = scr & ~SCSCR_TDRQE;
584 serial_port_out(port, SCSCR, new);
587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
588 dma_submit_error(s->cookie_tx)) {
590 schedule_work(&s->work_tx);
594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
595 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
596 ctrl = serial_port_in(port, SCSCR);
597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
601 static void sci_stop_tx(struct uart_port *port)
605 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
606 ctrl = serial_port_in(port, SCSCR);
608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
609 ctrl &= ~SCSCR_TDRQE;
613 serial_port_out(port, SCSCR, ctrl);
616 static void sci_start_rx(struct uart_port *port)
620 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
622 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
623 ctrl &= ~SCSCR_RDRQE;
625 serial_port_out(port, SCSCR, ctrl);
628 static void sci_stop_rx(struct uart_port *port)
632 ctrl = serial_port_in(port, SCSCR);
634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
635 ctrl &= ~SCSCR_RDRQE;
637 ctrl &= ~port_rx_irq_mask(port);
639 serial_port_out(port, SCSCR, ctrl);
642 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
644 if (port->type == PORT_SCI) {
645 /* Just store the mask */
646 serial_port_out(port, SCxSR, mask);
647 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
648 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
649 /* Only clear the status bits we want to clear */
650 serial_port_out(port, SCxSR,
651 serial_port_in(port, SCxSR) & mask);
653 /* Store the mask, clear parity/framing errors */
654 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
658 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
659 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
661 #ifdef CONFIG_CONSOLE_POLL
662 static int sci_poll_get_char(struct uart_port *port)
664 unsigned short status;
668 status = serial_port_in(port, SCxSR);
669 if (status & SCxSR_ERRORS(port)) {
670 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
676 if (!(status & SCxSR_RDxF(port)))
679 c = serial_port_in(port, SCxRDR);
682 serial_port_in(port, SCxSR);
683 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
689 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
691 unsigned short status;
694 status = serial_port_in(port, SCxSR);
695 } while (!(status & SCxSR_TDxE(port)));
697 serial_port_out(port, SCxTDR, c);
698 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
700 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
701 CONFIG_SERIAL_SH_SCI_EARLYCON */
703 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
705 struct sci_port *s = to_sci_port(port);
708 * Use port-specific handler if provided.
710 if (s->cfg->ops && s->cfg->ops->init_pins) {
711 s->cfg->ops->init_pins(port, cflag);
715 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
716 u16 ctrl = serial_port_in(port, SCPCR);
718 /* Enable RXD and TXD pin functions */
719 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
720 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
721 /* RTS# is output, driven 1 */
723 serial_port_out(port, SCPDR,
724 serial_port_in(port, SCPDR) | SCPDR_RTSD);
725 /* Enable CTS# pin function */
728 serial_port_out(port, SCPCR, ctrl);
729 } else if (sci_getreg(port, SCSPTR)->size) {
730 u16 status = serial_port_in(port, SCSPTR);
732 /* RTS# is output, driven 1 */
733 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
734 /* CTS# and SCK are inputs */
735 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
736 serial_port_out(port, SCSPTR, status);
740 static int sci_txfill(struct uart_port *port)
742 const struct plat_sci_reg *reg;
744 reg = sci_getreg(port, SCTFDR);
746 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
748 reg = sci_getreg(port, SCFDR);
750 return serial_port_in(port, SCFDR) >> 8;
752 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
755 static int sci_txroom(struct uart_port *port)
757 return port->fifosize - sci_txfill(port);
760 static int sci_rxfill(struct uart_port *port)
762 const struct plat_sci_reg *reg;
764 reg = sci_getreg(port, SCRFDR);
766 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
768 reg = sci_getreg(port, SCFDR);
770 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
772 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
776 * SCI helper for checking the state of the muxed port/RXD pins.
778 static inline int sci_rxd_in(struct uart_port *port)
780 struct sci_port *s = to_sci_port(port);
782 if (s->cfg->port_reg <= 0)
785 /* Cast for ARM damage */
786 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
789 /* ********************************************************************** *
790 * the interrupt related routines *
791 * ********************************************************************** */
793 static void sci_transmit_chars(struct uart_port *port)
795 struct circ_buf *xmit = &port->state->xmit;
796 unsigned int stopped = uart_tx_stopped(port);
797 unsigned short status;
801 status = serial_port_in(port, SCxSR);
802 if (!(status & SCxSR_TDxE(port))) {
803 ctrl = serial_port_in(port, SCSCR);
804 if (uart_circ_empty(xmit))
808 serial_port_out(port, SCSCR, ctrl);
812 count = sci_txroom(port);
820 } else if (!uart_circ_empty(xmit) && !stopped) {
821 c = xmit->buf[xmit->tail];
822 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
827 serial_port_out(port, SCxTDR, c);
830 } while (--count > 0);
832 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
834 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
835 uart_write_wakeup(port);
836 if (uart_circ_empty(xmit)) {
839 ctrl = serial_port_in(port, SCSCR);
841 if (port->type != PORT_SCI) {
842 serial_port_in(port, SCxSR); /* Dummy read */
843 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
847 serial_port_out(port, SCSCR, ctrl);
851 /* On SH3, SCIF may read end-of-break as a space->mark char */
852 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
854 static void sci_receive_chars(struct uart_port *port)
856 struct sci_port *sci_port = to_sci_port(port);
857 struct tty_port *tport = &port->state->port;
858 int i, count, copied = 0;
859 unsigned short status;
862 status = serial_port_in(port, SCxSR);
863 if (!(status & SCxSR_RDxF(port)))
867 /* Don't copy more bytes than there is room for in the buffer */
868 count = tty_buffer_request_room(tport, sci_rxfill(port));
870 /* If for any reason we can't copy more data, we're done! */
874 if (port->type == PORT_SCI) {
875 char c = serial_port_in(port, SCxRDR);
876 if (uart_handle_sysrq_char(port, c) ||
877 sci_port->break_flag)
880 tty_insert_flip_char(tport, c, TTY_NORMAL);
882 for (i = 0; i < count; i++) {
883 char c = serial_port_in(port, SCxRDR);
885 status = serial_port_in(port, SCxSR);
886 #if defined(CONFIG_CPU_SH3)
887 /* Skip "chars" during break */
888 if (sci_port->break_flag) {
890 (status & SCxSR_FER(port))) {
895 /* Nonzero => end-of-break */
896 dev_dbg(port->dev, "debounce<%02x>\n", c);
897 sci_port->break_flag = 0;
904 #endif /* CONFIG_CPU_SH3 */
905 if (uart_handle_sysrq_char(port, c)) {
910 /* Store data and status */
911 if (status & SCxSR_FER(port)) {
913 port->icount.frame++;
914 dev_notice(port->dev, "frame error\n");
915 } else if (status & SCxSR_PER(port)) {
917 port->icount.parity++;
918 dev_notice(port->dev, "parity error\n");
922 tty_insert_flip_char(tport, c, flag);
926 serial_port_in(port, SCxSR); /* dummy read */
927 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
930 port->icount.rx += count;
934 /* Tell the rest of the system the news. New characters! */
935 tty_flip_buffer_push(tport);
937 serial_port_in(port, SCxSR); /* dummy read */
938 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
942 #define SCI_BREAK_JIFFIES (HZ/20)
945 * The sci generates interrupts during the break,
946 * 1 per millisecond or so during the break period, for 9600 baud.
947 * So dont bother disabling interrupts.
948 * But dont want more than 1 break event.
949 * Use a kernel timer to periodically poll the rx line until
950 * the break is finished.
952 static inline void sci_schedule_break_timer(struct sci_port *port)
954 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
957 /* Ensure that two consecutive samples find the break over. */
958 static void sci_break_timer(unsigned long data)
960 struct sci_port *port = (struct sci_port *)data;
962 if (sci_rxd_in(&port->port) == 0) {
963 port->break_flag = 1;
964 sci_schedule_break_timer(port);
965 } else if (port->break_flag == 1) {
967 port->break_flag = 2;
968 sci_schedule_break_timer(port);
970 port->break_flag = 0;
973 static int sci_handle_errors(struct uart_port *port)
976 unsigned short status = serial_port_in(port, SCxSR);
977 struct tty_port *tport = &port->state->port;
978 struct sci_port *s = to_sci_port(port);
980 /* Handle overruns */
981 if (status & s->overrun_mask) {
982 port->icount.overrun++;
985 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
988 dev_notice(port->dev, "overrun error\n");
991 if (status & SCxSR_FER(port)) {
992 if (sci_rxd_in(port) == 0) {
993 /* Notify of BREAK */
994 struct sci_port *sci_port = to_sci_port(port);
996 if (!sci_port->break_flag) {
999 sci_port->break_flag = 1;
1000 sci_schedule_break_timer(sci_port);
1002 /* Do sysrq handling. */
1003 if (uart_handle_break(port))
1006 dev_dbg(port->dev, "BREAK detected\n");
1008 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1014 port->icount.frame++;
1016 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1019 dev_notice(port->dev, "frame error\n");
1023 if (status & SCxSR_PER(port)) {
1025 port->icount.parity++;
1027 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1030 dev_notice(port->dev, "parity error\n");
1034 tty_flip_buffer_push(tport);
1039 static int sci_handle_fifo_overrun(struct uart_port *port)
1041 struct tty_port *tport = &port->state->port;
1042 struct sci_port *s = to_sci_port(port);
1043 const struct plat_sci_reg *reg;
1047 reg = sci_getreg(port, s->overrun_reg);
1051 status = serial_port_in(port, s->overrun_reg);
1052 if (status & s->overrun_mask) {
1053 status &= ~s->overrun_mask;
1054 serial_port_out(port, s->overrun_reg, status);
1056 port->icount.overrun++;
1058 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1059 tty_flip_buffer_push(tport);
1061 dev_dbg(port->dev, "overrun error\n");
1068 static int sci_handle_breaks(struct uart_port *port)
1071 unsigned short status = serial_port_in(port, SCxSR);
1072 struct tty_port *tport = &port->state->port;
1073 struct sci_port *s = to_sci_port(port);
1075 if (uart_handle_break(port))
1078 if (!s->break_flag && status & SCxSR_BRK(port)) {
1079 #if defined(CONFIG_CPU_SH3)
1080 /* Debounce break */
1086 /* Notify of BREAK */
1087 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1090 dev_dbg(port->dev, "BREAK detected\n");
1094 tty_flip_buffer_push(tport);
1096 copied += sci_handle_fifo_overrun(port);
1101 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1102 static void sci_dma_tx_complete(void *arg)
1104 struct sci_port *s = arg;
1105 struct uart_port *port = &s->port;
1106 struct circ_buf *xmit = &port->state->xmit;
1107 unsigned long flags;
1109 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1111 spin_lock_irqsave(&port->lock, flags);
1113 xmit->tail += s->tx_dma_len;
1114 xmit->tail &= UART_XMIT_SIZE - 1;
1116 port->icount.tx += s->tx_dma_len;
1118 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1119 uart_write_wakeup(port);
1121 if (!uart_circ_empty(xmit)) {
1123 schedule_work(&s->work_tx);
1125 s->cookie_tx = -EINVAL;
1126 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1127 u16 ctrl = serial_port_in(port, SCSCR);
1128 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1132 spin_unlock_irqrestore(&port->lock, flags);
1135 /* Locking: called with port lock held */
1136 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1138 struct uart_port *port = &s->port;
1139 struct tty_port *tport = &port->state->port;
1142 copied = tty_insert_flip_string(tport, buf, count);
1143 if (copied < count) {
1144 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1146 port->icount.buf_overrun++;
1149 port->icount.rx += copied;
1154 static int sci_dma_rx_find_active(struct sci_port *s)
1158 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1159 if (s->active_rx == s->cookie_rx[i])
1162 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1167 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1169 struct dma_chan *chan = s->chan_rx;
1170 struct uart_port *port = &s->port;
1171 unsigned long flags;
1173 spin_lock_irqsave(&port->lock, flags);
1175 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1176 spin_unlock_irqrestore(&port->lock, flags);
1177 dmaengine_terminate_all(chan);
1178 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1179 sg_dma_address(&s->sg_rx[0]));
1180 dma_release_channel(chan);
1185 static void sci_dma_rx_complete(void *arg)
1187 struct sci_port *s = arg;
1188 struct dma_chan *chan = s->chan_rx;
1189 struct uart_port *port = &s->port;
1190 struct dma_async_tx_descriptor *desc;
1191 unsigned long flags;
1192 int active, count = 0;
1194 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1197 spin_lock_irqsave(&port->lock, flags);
1199 active = sci_dma_rx_find_active(s);
1201 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1203 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1206 tty_flip_buffer_push(&port->state->port);
1208 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1210 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1214 desc->callback = sci_dma_rx_complete;
1215 desc->callback_param = s;
1216 s->cookie_rx[active] = dmaengine_submit(desc);
1217 if (dma_submit_error(s->cookie_rx[active]))
1220 s->active_rx = s->cookie_rx[!active];
1222 dma_async_issue_pending(chan);
1224 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1225 __func__, s->cookie_rx[active], active, s->active_rx);
1226 spin_unlock_irqrestore(&port->lock, flags);
1230 spin_unlock_irqrestore(&port->lock, flags);
1231 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1232 sci_rx_dma_release(s, true);
1235 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1237 struct dma_chan *chan = s->chan_tx;
1238 struct uart_port *port = &s->port;
1239 unsigned long flags;
1241 spin_lock_irqsave(&port->lock, flags);
1243 s->cookie_tx = -EINVAL;
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 dmaengine_terminate_all(chan);
1246 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1248 dma_release_channel(chan);
1253 static void sci_submit_rx(struct sci_port *s)
1255 struct dma_chan *chan = s->chan_rx;
1258 for (i = 0; i < 2; i++) {
1259 struct scatterlist *sg = &s->sg_rx[i];
1260 struct dma_async_tx_descriptor *desc;
1262 desc = dmaengine_prep_slave_sg(chan,
1263 sg, 1, DMA_DEV_TO_MEM,
1264 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1268 desc->callback = sci_dma_rx_complete;
1269 desc->callback_param = s;
1270 s->cookie_rx[i] = dmaengine_submit(desc);
1271 if (dma_submit_error(s->cookie_rx[i]))
1274 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1275 s->cookie_rx[i], i);
1278 s->active_rx = s->cookie_rx[0];
1280 dma_async_issue_pending(chan);
1285 dmaengine_terminate_all(chan);
1286 for (i = 0; i < 2; i++)
1287 s->cookie_rx[i] = -EINVAL;
1288 s->active_rx = -EINVAL;
1289 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1290 sci_rx_dma_release(s, true);
1293 static void work_fn_tx(struct work_struct *work)
1295 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1296 struct dma_async_tx_descriptor *desc;
1297 struct dma_chan *chan = s->chan_tx;
1298 struct uart_port *port = &s->port;
1299 struct circ_buf *xmit = &port->state->xmit;
1304 * Port xmit buffer is already mapped, and it is one page... Just adjust
1305 * offsets and lengths. Since it is a circular buffer, we have to
1306 * transmit till the end, and then the rest. Take the port lock to get a
1307 * consistent xmit buffer state.
1309 spin_lock_irq(&port->lock);
1310 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1311 s->tx_dma_len = min_t(unsigned int,
1312 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1313 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1314 spin_unlock_irq(&port->lock);
1316 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1320 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1322 sci_tx_dma_release(s, true);
1326 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1329 spin_lock_irq(&port->lock);
1330 desc->callback = sci_dma_tx_complete;
1331 desc->callback_param = s;
1332 spin_unlock_irq(&port->lock);
1333 s->cookie_tx = dmaengine_submit(desc);
1334 if (dma_submit_error(s->cookie_tx)) {
1335 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1337 sci_tx_dma_release(s, true);
1341 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1342 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1344 dma_async_issue_pending(chan);
1347 static void rx_timer_fn(unsigned long arg)
1349 struct sci_port *s = (struct sci_port *)arg;
1350 struct dma_chan *chan = s->chan_rx;
1351 struct uart_port *port = &s->port;
1352 struct dma_tx_state state;
1353 enum dma_status status;
1354 unsigned long flags;
1359 spin_lock_irqsave(&port->lock, flags);
1361 dev_dbg(port->dev, "DMA Rx timed out\n");
1363 active = sci_dma_rx_find_active(s);
1365 spin_unlock_irqrestore(&port->lock, flags);
1369 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1370 if (status == DMA_COMPLETE) {
1371 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1372 s->active_rx, active);
1373 spin_unlock_irqrestore(&port->lock, flags);
1375 /* Let packet complete handler take care of the packet */
1379 dmaengine_pause(chan);
1382 * sometimes DMA transfer doesn't stop even if it is stopped and
1383 * data keeps on coming until transaction is complete so check
1384 * for DMA_COMPLETE again
1385 * Let packet complete handler take care of the packet
1387 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1388 if (status == DMA_COMPLETE) {
1389 spin_unlock_irqrestore(&port->lock, flags);
1390 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1394 /* Handle incomplete DMA receive */
1395 dmaengine_terminate_all(s->chan_rx);
1396 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1397 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1401 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1403 tty_flip_buffer_push(&port->state->port);
1406 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1409 /* Direct new serial port interrupts back to CPU */
1410 scr = serial_port_in(port, SCSCR);
1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1412 scr &= ~SCSCR_RDRQE;
1413 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1415 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1417 spin_unlock_irqrestore(&port->lock, flags);
1420 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1421 enum dma_transfer_direction dir,
1424 dma_cap_mask_t mask;
1425 struct dma_chan *chan;
1426 struct dma_slave_config cfg;
1430 dma_cap_set(DMA_SLAVE, mask);
1432 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1433 (void *)(unsigned long)id, port->dev,
1434 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1437 "dma_request_slave_channel_compat failed\n");
1441 memset(&cfg, 0, sizeof(cfg));
1442 cfg.direction = dir;
1443 if (dir == DMA_MEM_TO_DEV) {
1444 cfg.dst_addr = port->mapbase +
1445 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1446 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1448 cfg.src_addr = port->mapbase +
1449 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1450 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1453 ret = dmaengine_slave_config(chan, &cfg);
1455 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1456 dma_release_channel(chan);
1463 static void sci_request_dma(struct uart_port *port)
1465 struct sci_port *s = to_sci_port(port);
1466 struct dma_chan *chan;
1468 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1470 if (!port->dev->of_node &&
1471 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1474 s->cookie_tx = -EINVAL;
1475 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1476 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1479 /* UART circular tx buffer is an aligned page. */
1480 s->tx_dma_addr = dma_map_single(chan->device->dev,
1481 port->state->xmit.buf,
1484 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1485 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1486 dma_release_channel(chan);
1489 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1490 __func__, UART_XMIT_SIZE,
1491 port->state->xmit.buf, &s->tx_dma_addr);
1494 INIT_WORK(&s->work_tx, work_fn_tx);
1497 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1498 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1506 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1507 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1511 "Failed to allocate Rx dma buffer, using PIO\n");
1512 dma_release_channel(chan);
1517 for (i = 0; i < 2; i++) {
1518 struct scatterlist *sg = &s->sg_rx[i];
1520 sg_init_table(sg, 1);
1522 sg_dma_address(sg) = dma;
1523 sg_dma_len(sg) = s->buf_len_rx;
1525 buf += s->buf_len_rx;
1526 dma += s->buf_len_rx;
1529 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1531 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1536 static void sci_free_dma(struct uart_port *port)
1538 struct sci_port *s = to_sci_port(port);
1541 sci_tx_dma_release(s, false);
1543 sci_rx_dma_release(s, false);
1546 static inline void sci_request_dma(struct uart_port *port)
1550 static inline void sci_free_dma(struct uart_port *port)
1555 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1557 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1558 struct uart_port *port = ptr;
1559 struct sci_port *s = to_sci_port(port);
1562 u16 scr = serial_port_in(port, SCSCR);
1563 u16 ssr = serial_port_in(port, SCxSR);
1565 /* Disable future Rx interrupts */
1566 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1567 disable_irq_nosync(irq);
1573 serial_port_out(port, SCSCR, scr);
1574 /* Clear current interrupt */
1575 serial_port_out(port, SCxSR,
1576 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1577 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1578 jiffies, s->rx_timeout);
1579 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1585 /* I think sci_receive_chars has to be called irrespective
1586 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1589 sci_receive_chars(ptr);
1594 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1596 struct uart_port *port = ptr;
1597 unsigned long flags;
1599 spin_lock_irqsave(&port->lock, flags);
1600 sci_transmit_chars(port);
1601 spin_unlock_irqrestore(&port->lock, flags);
1606 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1608 struct uart_port *port = ptr;
1609 struct sci_port *s = to_sci_port(port);
1612 if (port->type == PORT_SCI) {
1613 if (sci_handle_errors(port)) {
1614 /* discard character in rx buffer */
1615 serial_port_in(port, SCxSR);
1616 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1619 sci_handle_fifo_overrun(port);
1621 sci_receive_chars(ptr);
1624 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1626 /* Kick the transmission */
1628 sci_tx_interrupt(irq, ptr);
1633 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1635 struct uart_port *port = ptr;
1638 sci_handle_breaks(port);
1639 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1644 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1646 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1647 struct uart_port *port = ptr;
1648 struct sci_port *s = to_sci_port(port);
1649 irqreturn_t ret = IRQ_NONE;
1651 ssr_status = serial_port_in(port, SCxSR);
1652 scr_status = serial_port_in(port, SCSCR);
1653 if (s->overrun_reg == SCxSR)
1654 orer_status = ssr_status;
1656 if (sci_getreg(port, s->overrun_reg)->size)
1657 orer_status = serial_port_in(port, s->overrun_reg);
1660 err_enabled = scr_status & port_rx_irq_mask(port);
1663 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1665 ret = sci_tx_interrupt(irq, ptr);
1668 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1671 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1672 (scr_status & SCSCR_RIE))
1673 ret = sci_rx_interrupt(irq, ptr);
1675 /* Error Interrupt */
1676 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1677 ret = sci_er_interrupt(irq, ptr);
1679 /* Break Interrupt */
1680 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1681 ret = sci_br_interrupt(irq, ptr);
1683 /* Overrun Interrupt */
1684 if (orer_status & s->overrun_mask) {
1685 sci_handle_fifo_overrun(port);
1692 static const struct sci_irq_desc {
1694 irq_handler_t handler;
1695 } sci_irq_desc[] = {
1697 * Split out handlers, the default case.
1701 .handler = sci_er_interrupt,
1706 .handler = sci_rx_interrupt,
1711 .handler = sci_tx_interrupt,
1716 .handler = sci_br_interrupt,
1720 * Special muxed handler.
1724 .handler = sci_mpxed_interrupt,
1728 static int sci_request_irq(struct sci_port *port)
1730 struct uart_port *up = &port->port;
1733 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1734 const struct sci_irq_desc *desc;
1737 if (SCIx_IRQ_IS_MUXED(port)) {
1741 irq = port->irqs[i];
1744 * Certain port types won't support all of the
1745 * available interrupt sources.
1747 if (unlikely(irq < 0))
1751 desc = sci_irq_desc + i;
1752 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1753 dev_name(up->dev), desc->desc);
1754 if (!port->irqstr[j])
1757 ret = request_irq(irq, desc->handler, up->irqflags,
1758 port->irqstr[j], port);
1759 if (unlikely(ret)) {
1760 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1769 free_irq(port->irqs[i], port);
1773 kfree(port->irqstr[j]);
1778 static void sci_free_irq(struct sci_port *port)
1783 * Intentionally in reverse order so we iterate over the muxed
1786 for (i = 0; i < SCIx_NR_IRQS; i++) {
1787 int irq = port->irqs[i];
1790 * Certain port types won't support all of the available
1791 * interrupt sources.
1793 if (unlikely(irq < 0))
1796 free_irq(port->irqs[i], port);
1797 kfree(port->irqstr[i]);
1799 if (SCIx_IRQ_IS_MUXED(port)) {
1800 /* If there's only one IRQ, we're done. */
1806 static unsigned int sci_tx_empty(struct uart_port *port)
1808 unsigned short status = serial_port_in(port, SCxSR);
1809 unsigned short in_tx_fifo = sci_txfill(port);
1811 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1815 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1816 * CTS/RTS is supported in hardware by at least one port and controlled
1817 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1818 * handled via the ->init_pins() op, which is a bit of a one-way street,
1819 * lacking any ability to defer pin control -- this will later be
1820 * converted over to the GPIO framework).
1822 * Other modes (such as loopback) are supported generically on certain
1823 * port types, but not others. For these it's sufficient to test for the
1824 * existence of the support register and simply ignore the port type.
1826 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1828 struct sci_port *s = to_sci_port(port);
1830 if (mctrl & TIOCM_LOOP) {
1831 const struct plat_sci_reg *reg;
1834 * Standard loopback mode for SCFCR ports.
1836 reg = sci_getreg(port, SCFCR);
1838 serial_port_out(port, SCFCR,
1839 serial_port_in(port, SCFCR) |
1843 mctrl_gpio_set(s->gpios, mctrl);
1846 static unsigned int sci_get_mctrl(struct uart_port *port)
1848 struct sci_port *s = to_sci_port(port);
1849 struct mctrl_gpios *gpios = s->gpios;
1850 unsigned int mctrl = 0;
1852 mctrl_gpio_get(gpios, &mctrl);
1855 * CTS/RTS is handled in hardware when supported, while nothing
1856 * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
1858 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)))
1860 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1862 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1868 static void sci_enable_ms(struct uart_port *port)
1870 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1873 static void sci_break_ctl(struct uart_port *port, int break_state)
1875 unsigned short scscr, scsptr;
1877 /* check wheter the port has SCSPTR */
1878 if (!sci_getreg(port, SCSPTR)->size) {
1880 * Not supported by hardware. Most parts couple break and rx
1881 * interrupts together, with break detection always enabled.
1886 scsptr = serial_port_in(port, SCSPTR);
1887 scscr = serial_port_in(port, SCSCR);
1889 if (break_state == -1) {
1890 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1893 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1897 serial_port_out(port, SCSPTR, scsptr);
1898 serial_port_out(port, SCSCR, scscr);
1901 static int sci_startup(struct uart_port *port)
1903 struct sci_port *s = to_sci_port(port);
1904 unsigned long flags;
1907 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1909 ret = sci_request_irq(s);
1910 if (unlikely(ret < 0))
1913 sci_request_dma(port);
1915 spin_lock_irqsave(&port->lock, flags);
1918 spin_unlock_irqrestore(&port->lock, flags);
1923 static void sci_shutdown(struct uart_port *port)
1925 struct sci_port *s = to_sci_port(port);
1926 unsigned long flags;
1928 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1930 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1932 spin_lock_irqsave(&port->lock, flags);
1935 spin_unlock_irqrestore(&port->lock, flags);
1937 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1939 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1941 del_timer_sync(&s->rx_timer);
1949 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1952 unsigned long freq = s->clk_rates[SCI_SCK];
1953 int err, min_err = INT_MAX;
1956 if (s->port.type != PORT_HSCIF)
1959 for_each_sr(sr, s) {
1960 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1961 if (abs(err) >= abs(min_err))
1971 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1976 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1977 unsigned long freq, unsigned int *dlr,
1980 int err, min_err = INT_MAX;
1981 unsigned int sr, dl;
1983 if (s->port.type != PORT_HSCIF)
1986 for_each_sr(sr, s) {
1987 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1988 dl = clamp(dl, 1U, 65535U);
1990 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1991 if (abs(err) >= abs(min_err))
2002 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2003 min_err, *dlr, *srr + 1);
2007 /* calculate sample rate, BRR, and clock select */
2008 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2009 unsigned int *brr, unsigned int *srr,
2012 unsigned long freq = s->clk_rates[SCI_FCK];
2013 unsigned int sr, br, prediv, scrate, c;
2014 int err, min_err = INT_MAX;
2016 if (s->port.type != PORT_HSCIF)
2020 * Find the combination of sample rate and clock select with the
2021 * smallest deviation from the desired baud rate.
2022 * Prefer high sample rates to maximise the receive margin.
2024 * M: Receive margin (%)
2025 * N: Ratio of bit rate to clock (N = sampling rate)
2026 * D: Clock duty (D = 0 to 1.0)
2027 * L: Frame length (L = 9 to 12)
2028 * F: Absolute value of clock frequency deviation
2030 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2031 * (|D - 0.5| / N * (1 + F))|
2032 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2034 for_each_sr(sr, s) {
2035 for (c = 0; c <= 3; c++) {
2036 /* integerized formulas from HSCIF documentation */
2037 prediv = sr * (1 << (2 * c + 1));
2040 * We need to calculate:
2042 * br = freq / (prediv * bps) clamped to [1..256]
2043 * err = freq / (br * prediv) - bps
2045 * Watch out for overflow when calculating the desired
2046 * sampling clock rate!
2048 if (bps > UINT_MAX / prediv)
2051 scrate = prediv * bps;
2052 br = DIV_ROUND_CLOSEST(freq, scrate);
2053 br = clamp(br, 1U, 256U);
2055 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2056 if (abs(err) >= abs(min_err))
2070 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2071 min_err, *brr, *srr + 1, *cks);
2075 static void sci_reset(struct uart_port *port)
2077 const struct plat_sci_reg *reg;
2078 unsigned int status;
2081 status = serial_port_in(port, SCxSR);
2082 } while (!(status & SCxSR_TEND(port)));
2084 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2086 reg = sci_getreg(port, SCFCR);
2088 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2091 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2092 struct ktermios *old)
2094 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2095 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2096 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2097 struct sci_port *s = to_sci_port(port);
2098 const struct plat_sci_reg *reg;
2099 int min_err = INT_MAX, err;
2100 unsigned long max_freq = 0;
2103 if ((termios->c_cflag & CSIZE) == CS7)
2104 smr_val |= SCSMR_CHR;
2105 if (termios->c_cflag & PARENB)
2106 smr_val |= SCSMR_PE;
2107 if (termios->c_cflag & PARODD)
2108 smr_val |= SCSMR_PE | SCSMR_ODD;
2109 if (termios->c_cflag & CSTOPB)
2110 smr_val |= SCSMR_STOP;
2113 * earlyprintk comes here early on with port->uartclk set to zero.
2114 * the clock framework is not up and running at this point so here
2115 * we assume that 115200 is the maximum baud rate. please note that
2116 * the baud rate is not programmed during earlyprintk - it is assumed
2117 * that the previous boot loader has enabled required clocks and
2118 * setup the baud rate generator hardware for us already.
2120 if (!port->uartclk) {
2121 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2125 for (i = 0; i < SCI_NUM_CLKS; i++)
2126 max_freq = max(max_freq, s->clk_rates[i]);
2128 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2133 * There can be multiple sources for the sampling clock. Find the one
2134 * that gives us the smallest deviation from the desired baud rate.
2137 /* Optional Undivided External Clock */
2138 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2139 port->type != PORT_SCIFB) {
2140 err = sci_sck_calc(s, baud, &srr1);
2141 if (abs(err) < abs(min_err)) {
2143 scr_val = SCSCR_CKE1;
2152 /* Optional BRG Frequency Divided External Clock */
2153 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2154 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2156 if (abs(err) < abs(min_err)) {
2157 best_clk = SCI_SCIF_CLK;
2158 scr_val = SCSCR_CKE1;
2168 /* Optional BRG Frequency Divided Internal Clock */
2169 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2170 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2172 if (abs(err) < abs(min_err)) {
2173 best_clk = SCI_BRG_INT;
2174 scr_val = SCSCR_CKE1;
2184 /* Divided Functional Clock using standard Bit Rate Register */
2185 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2186 if (abs(err) < abs(min_err)) {
2197 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2198 s->clks[best_clk], baud, min_err);
2203 * Program the optional External Baud Rate Generator (BRG) first.
2204 * It controls the mux to select (H)SCK or frequency divided clock.
2206 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2207 serial_port_out(port, SCDL, dl);
2208 serial_port_out(port, SCCKS, sccks);
2213 uart_update_timeout(port, termios->c_cflag, baud);
2215 if (best_clk >= 0) {
2216 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2218 case 5: smr_val |= SCSMR_SRC_5; break;
2219 case 7: smr_val |= SCSMR_SRC_7; break;
2220 case 11: smr_val |= SCSMR_SRC_11; break;
2221 case 13: smr_val |= SCSMR_SRC_13; break;
2222 case 16: smr_val |= SCSMR_SRC_16; break;
2223 case 17: smr_val |= SCSMR_SRC_17; break;
2224 case 19: smr_val |= SCSMR_SRC_19; break;
2225 case 27: smr_val |= SCSMR_SRC_27; break;
2229 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2230 scr_val, smr_val, brr, sccks, dl, srr);
2231 serial_port_out(port, SCSCR, scr_val);
2232 serial_port_out(port, SCSMR, smr_val);
2233 serial_port_out(port, SCBRR, brr);
2234 if (sci_getreg(port, HSSRR)->size)
2235 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2237 /* Wait one bit interval */
2238 udelay((1000000 + (baud - 1)) / baud);
2240 /* Don't touch the bit rate configuration */
2241 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2242 smr_val |= serial_port_in(port, SCSMR) &
2243 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2244 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2245 serial_port_out(port, SCSCR, scr_val);
2246 serial_port_out(port, SCSMR, smr_val);
2249 sci_init_pins(port, termios->c_cflag);
2251 reg = sci_getreg(port, SCFCR);
2253 unsigned short ctrl = serial_port_in(port, SCFCR);
2255 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2256 if (termios->c_cflag & CRTSCTS)
2263 * As we've done a sci_reset() above, ensure we don't
2264 * interfere with the FIFOs while toggling MCE. As the
2265 * reset values could still be set, simply mask them out.
2267 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2269 serial_port_out(port, SCFCR, ctrl);
2272 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2273 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2274 serial_port_out(port, SCSCR, scr_val);
2275 if ((srr + 1 == 5) &&
2276 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2278 * In asynchronous mode, when the sampling rate is 1/5, first
2279 * received data may become invalid on some SCIFA and SCIFB.
2280 * To avoid this problem wait more than 1 serial data time (1
2281 * bit time x serial data number) after setting SCSCR.RE = 1.
2283 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2286 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2288 * Calculate delay for 2 DMA buffers (4 FIFO).
2289 * See serial_core.c::uart_update_timeout().
2290 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2291 * function calculates 1 jiffie for the data plus 5 jiffies for the
2292 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2293 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2294 * value obtained by this formula is too small. Therefore, if the value
2295 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2300 /* byte size and parity */
2301 switch (termios->c_cflag & CSIZE) {
2316 if (termios->c_cflag & CSTOPB)
2318 if (termios->c_cflag & PARENB)
2320 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2322 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2323 s->rx_timeout * 1000 / HZ, port->timeout);
2324 if (s->rx_timeout < msecs_to_jiffies(20))
2325 s->rx_timeout = msecs_to_jiffies(20);
2329 if ((termios->c_cflag & CREAD) != 0)
2332 sci_port_disable(s);
2334 if (UART_ENABLE_MS(port, termios->c_cflag))
2335 sci_enable_ms(port);
2338 static void sci_pm(struct uart_port *port, unsigned int state,
2339 unsigned int oldstate)
2341 struct sci_port *sci_port = to_sci_port(port);
2344 case UART_PM_STATE_OFF:
2345 sci_port_disable(sci_port);
2348 sci_port_enable(sci_port);
2353 static const char *sci_type(struct uart_port *port)
2355 switch (port->type) {
2373 static int sci_remap_port(struct uart_port *port)
2375 struct sci_port *sport = to_sci_port(port);
2378 * Nothing to do if there's already an established membase.
2383 if (port->flags & UPF_IOREMAP) {
2384 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2385 if (unlikely(!port->membase)) {
2386 dev_err(port->dev, "can't remap port#%d\n", port->line);
2391 * For the simple (and majority of) cases where we don't
2392 * need to do any remapping, just cast the cookie
2395 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2401 static void sci_release_port(struct uart_port *port)
2403 struct sci_port *sport = to_sci_port(port);
2405 if (port->flags & UPF_IOREMAP) {
2406 iounmap(port->membase);
2407 port->membase = NULL;
2410 release_mem_region(port->mapbase, sport->reg_size);
2413 static int sci_request_port(struct uart_port *port)
2415 struct resource *res;
2416 struct sci_port *sport = to_sci_port(port);
2419 res = request_mem_region(port->mapbase, sport->reg_size,
2420 dev_name(port->dev));
2421 if (unlikely(res == NULL)) {
2422 dev_err(port->dev, "request_mem_region failed.");
2426 ret = sci_remap_port(port);
2427 if (unlikely(ret != 0)) {
2428 release_resource(res);
2435 static void sci_config_port(struct uart_port *port, int flags)
2437 if (flags & UART_CONFIG_TYPE) {
2438 struct sci_port *sport = to_sci_port(port);
2440 port->type = sport->cfg->type;
2441 sci_request_port(port);
2445 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2447 if (ser->baud_base < 2400)
2448 /* No paper tape reader for Mitch.. */
2454 static struct uart_ops sci_uart_ops = {
2455 .tx_empty = sci_tx_empty,
2456 .set_mctrl = sci_set_mctrl,
2457 .get_mctrl = sci_get_mctrl,
2458 .start_tx = sci_start_tx,
2459 .stop_tx = sci_stop_tx,
2460 .stop_rx = sci_stop_rx,
2461 .enable_ms = sci_enable_ms,
2462 .break_ctl = sci_break_ctl,
2463 .startup = sci_startup,
2464 .shutdown = sci_shutdown,
2465 .set_termios = sci_set_termios,
2468 .release_port = sci_release_port,
2469 .request_port = sci_request_port,
2470 .config_port = sci_config_port,
2471 .verify_port = sci_verify_port,
2472 #ifdef CONFIG_CONSOLE_POLL
2473 .poll_get_char = sci_poll_get_char,
2474 .poll_put_char = sci_poll_put_char,
2478 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2480 const char *clk_names[] = {
2483 [SCI_BRG_INT] = "brg_int",
2484 [SCI_SCIF_CLK] = "scif_clk",
2489 if (sci_port->cfg->type == PORT_HSCIF)
2490 clk_names[SCI_SCK] = "hsck";
2492 for (i = 0; i < SCI_NUM_CLKS; i++) {
2493 clk = devm_clk_get(dev, clk_names[i]);
2494 if (PTR_ERR(clk) == -EPROBE_DEFER)
2495 return -EPROBE_DEFER;
2497 if (IS_ERR(clk) && i == SCI_FCK) {
2499 * "fck" used to be called "sci_ick", and we need to
2500 * maintain DT backward compatibility.
2502 clk = devm_clk_get(dev, "sci_ick");
2503 if (PTR_ERR(clk) == -EPROBE_DEFER)
2504 return -EPROBE_DEFER;
2510 * Not all SH platforms declare a clock lookup entry
2511 * for SCI devices, in which case we need to get the
2512 * global "peripheral_clk" clock.
2514 clk = devm_clk_get(dev, "peripheral_clk");
2518 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2520 return PTR_ERR(clk);
2525 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2528 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2530 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2535 static int sci_init_single(struct platform_device *dev,
2536 struct sci_port *sci_port, unsigned int index,
2537 struct plat_sci_port *p, bool early)
2539 struct uart_port *port = &sci_port->port;
2540 const struct resource *res;
2546 port->ops = &sci_uart_ops;
2547 port->iotype = UPIO_MEM;
2550 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2554 port->mapbase = res->start;
2555 sci_port->reg_size = resource_size(res);
2557 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2558 sci_port->irqs[i] = platform_get_irq(dev, i);
2560 /* The SCI generates several interrupts. They can be muxed together or
2561 * connected to different interrupt lines. In the muxed case only one
2562 * interrupt resource is specified. In the non-muxed case three or four
2563 * interrupt resources are specified, as the BRI interrupt is optional.
2565 if (sci_port->irqs[0] < 0)
2568 if (sci_port->irqs[1] < 0) {
2569 sci_port->irqs[1] = sci_port->irqs[0];
2570 sci_port->irqs[2] = sci_port->irqs[0];
2571 sci_port->irqs[3] = sci_port->irqs[0];
2574 if (p->regtype == SCIx_PROBE_REGTYPE) {
2575 ret = sci_probe_regmap(p);
2582 port->fifosize = 256;
2583 sci_port->overrun_reg = SCxSR;
2584 sci_port->overrun_mask = SCIFA_ORER;
2585 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2588 port->fifosize = 128;
2589 sci_port->overrun_reg = SCLSR;
2590 sci_port->overrun_mask = SCLSR_ORER;
2591 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2594 port->fifosize = 64;
2595 sci_port->overrun_reg = SCxSR;
2596 sci_port->overrun_mask = SCIFA_ORER;
2597 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2600 port->fifosize = 16;
2601 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2602 sci_port->overrun_reg = SCxSR;
2603 sci_port->overrun_mask = SCIFA_ORER;
2604 sci_port->sampling_rate_mask = SCI_SR(16);
2606 sci_port->overrun_reg = SCLSR;
2607 sci_port->overrun_mask = SCLSR_ORER;
2608 sci_port->sampling_rate_mask = SCI_SR(32);
2613 sci_port->overrun_reg = SCxSR;
2614 sci_port->overrun_mask = SCI_ORER;
2615 sci_port->sampling_rate_mask = SCI_SR(32);
2619 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2620 * match the SoC datasheet, this should be investigated. Let platform
2621 * data override the sampling rate for now.
2623 if (p->sampling_rate)
2624 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2627 ret = sci_init_clocks(sci_port, &dev->dev);
2631 port->dev = &dev->dev;
2633 pm_runtime_enable(&dev->dev);
2636 sci_port->break_timer.data = (unsigned long)sci_port;
2637 sci_port->break_timer.function = sci_break_timer;
2638 init_timer(&sci_port->break_timer);
2641 * Establish some sensible defaults for the error detection.
2643 if (p->type == PORT_SCI) {
2644 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2645 sci_port->error_clear = SCI_ERROR_CLEAR;
2647 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2648 sci_port->error_clear = SCIF_ERROR_CLEAR;
2652 * Make the error mask inclusive of overrun detection, if
2655 if (sci_port->overrun_reg == SCxSR) {
2656 sci_port->error_mask |= sci_port->overrun_mask;
2657 sci_port->error_clear &= ~sci_port->overrun_mask;
2660 port->type = p->type;
2661 port->flags = UPF_FIXED_PORT | p->flags;
2662 port->regshift = p->regshift;
2665 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2666 * for the multi-IRQ ports, which is where we are primarily
2667 * concerned with the shutdown path synchronization.
2669 * For the muxed case there's nothing more to do.
2671 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2674 port->serial_in = sci_serial_in;
2675 port->serial_out = sci_serial_out;
2677 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2678 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2679 p->dma_slave_tx, p->dma_slave_rx);
2684 static void sci_cleanup_single(struct sci_port *port)
2686 pm_runtime_disable(port->port.dev);
2689 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2690 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2691 static void serial_console_putchar(struct uart_port *port, int ch)
2693 sci_poll_put_char(port, ch);
2697 * Print a string to the serial port trying not to disturb
2698 * any possible real use of the port...
2700 static void serial_console_write(struct console *co, const char *s,
2703 struct sci_port *sci_port = &sci_ports[co->index];
2704 struct uart_port *port = &sci_port->port;
2705 unsigned short bits, ctrl, ctrl_temp;
2706 unsigned long flags;
2709 local_irq_save(flags);
2710 #if defined(SUPPORT_SYSRQ)
2715 if (oops_in_progress)
2716 locked = spin_trylock(&port->lock);
2718 spin_lock(&port->lock);
2720 /* first save SCSCR then disable interrupts, keep clock source */
2721 ctrl = serial_port_in(port, SCSCR);
2722 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2723 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2724 serial_port_out(port, SCSCR, ctrl_temp);
2726 uart_console_write(port, s, count, serial_console_putchar);
2728 /* wait until fifo is empty and last bit has been transmitted */
2729 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2730 while ((serial_port_in(port, SCxSR) & bits) != bits)
2733 /* restore the SCSCR */
2734 serial_port_out(port, SCSCR, ctrl);
2737 spin_unlock(&port->lock);
2738 local_irq_restore(flags);
2741 static int serial_console_setup(struct console *co, char *options)
2743 struct sci_port *sci_port;
2744 struct uart_port *port;
2752 * Refuse to handle any bogus ports.
2754 if (co->index < 0 || co->index >= SCI_NPORTS)
2757 sci_port = &sci_ports[co->index];
2758 port = &sci_port->port;
2761 * Refuse to handle uninitialized ports.
2766 ret = sci_remap_port(port);
2767 if (unlikely(ret != 0))
2771 uart_parse_options(options, &baud, &parity, &bits, &flow);
2773 return uart_set_options(port, co, baud, parity, bits, flow);
2776 static struct console serial_console = {
2778 .device = uart_console_device,
2779 .write = serial_console_write,
2780 .setup = serial_console_setup,
2781 .flags = CON_PRINTBUFFER,
2783 .data = &sci_uart_driver,
2786 static struct console early_serial_console = {
2787 .name = "early_ttySC",
2788 .write = serial_console_write,
2789 .flags = CON_PRINTBUFFER,
2793 static char early_serial_buf[32];
2795 static int sci_probe_earlyprintk(struct platform_device *pdev)
2797 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2799 if (early_serial_console.data)
2802 early_serial_console.index = pdev->id;
2804 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2806 serial_console_setup(&early_serial_console, early_serial_buf);
2808 if (!strstr(early_serial_buf, "keep"))
2809 early_serial_console.flags |= CON_BOOT;
2811 register_console(&early_serial_console);
2815 #define SCI_CONSOLE (&serial_console)
2818 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2823 #define SCI_CONSOLE NULL
2825 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2827 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2829 static struct uart_driver sci_uart_driver = {
2830 .owner = THIS_MODULE,
2831 .driver_name = "sci",
2832 .dev_name = "ttySC",
2834 .minor = SCI_MINOR_START,
2836 .cons = SCI_CONSOLE,
2839 static int sci_remove(struct platform_device *dev)
2841 struct sci_port *port = platform_get_drvdata(dev);
2843 uart_remove_one_port(&sci_uart_driver, &port->port);
2845 sci_cleanup_single(port);
2851 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2852 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2853 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2855 static const struct of_device_id of_sci_match[] = {
2856 /* SoC-specific types */
2858 .compatible = "renesas,scif-r7s72100",
2859 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2861 /* Family-specific types */
2863 .compatible = "renesas,rcar-gen1-scif",
2864 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2866 .compatible = "renesas,rcar-gen2-scif",
2867 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2869 .compatible = "renesas,rcar-gen3-scif",
2870 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2874 .compatible = "renesas,scif",
2875 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2877 .compatible = "renesas,scifa",
2878 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2880 .compatible = "renesas,scifb",
2881 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2883 .compatible = "renesas,hscif",
2884 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2886 .compatible = "renesas,sci",
2887 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2892 MODULE_DEVICE_TABLE(of, of_sci_match);
2894 static struct plat_sci_port *
2895 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2897 struct device_node *np = pdev->dev.of_node;
2898 const struct of_device_id *match;
2899 struct plat_sci_port *p;
2902 if (!IS_ENABLED(CONFIG_OF) || !np)
2905 match = of_match_node(of_sci_match, np);
2909 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2913 /* Get the line number from the aliases node. */
2914 id = of_alias_get_id(np, "serial");
2916 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2922 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2923 p->type = SCI_OF_TYPE(match->data);
2924 p->regtype = SCI_OF_REGTYPE(match->data);
2925 p->scscr = SCSCR_RE | SCSCR_TE;
2930 static int sci_probe_single(struct platform_device *dev,
2932 struct plat_sci_port *p,
2933 struct sci_port *sciport)
2938 if (unlikely(index >= SCI_NPORTS)) {
2939 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2940 index+1, SCI_NPORTS);
2941 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2945 ret = sci_init_single(dev, sciport, index, p, false);
2949 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
2950 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
2951 return PTR_ERR(sciport->gpios);
2953 if (p->capabilities & SCIx_HAVE_RTSCTS) {
2954 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2956 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2958 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
2963 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2965 sci_cleanup_single(sciport);
2972 static int sci_probe(struct platform_device *dev)
2974 struct plat_sci_port *p;
2975 struct sci_port *sp;
2976 unsigned int dev_id;
2980 * If we've come here via earlyprintk initialization, head off to
2981 * the special early probe. We don't have sufficient device state
2982 * to make it beyond this yet.
2984 if (is_early_platform_device(dev))
2985 return sci_probe_earlyprintk(dev);
2987 if (dev->dev.of_node) {
2988 p = sci_parse_dt(dev, &dev_id);
2992 p = dev->dev.platform_data;
2994 dev_err(&dev->dev, "no platform data supplied\n");
3001 sp = &sci_ports[dev_id];
3002 platform_set_drvdata(dev, sp);
3004 ret = sci_probe_single(dev, dev_id, p, sp);
3008 #ifdef CONFIG_SH_STANDARD_BIOS
3009 sh_bios_gdb_detach();
3015 static __maybe_unused int sci_suspend(struct device *dev)
3017 struct sci_port *sport = dev_get_drvdata(dev);
3020 uart_suspend_port(&sci_uart_driver, &sport->port);
3025 static __maybe_unused int sci_resume(struct device *dev)
3027 struct sci_port *sport = dev_get_drvdata(dev);
3030 uart_resume_port(&sci_uart_driver, &sport->port);
3035 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3037 static struct platform_driver sci_driver = {
3039 .remove = sci_remove,
3042 .pm = &sci_dev_pm_ops,
3043 .of_match_table = of_match_ptr(of_sci_match),
3047 static int __init sci_init(void)
3051 pr_info("%s\n", banner);
3053 ret = uart_register_driver(&sci_uart_driver);
3054 if (likely(ret == 0)) {
3055 ret = platform_driver_register(&sci_driver);
3057 uart_unregister_driver(&sci_uart_driver);
3063 static void __exit sci_exit(void)
3065 platform_driver_unregister(&sci_driver);
3066 uart_unregister_driver(&sci_uart_driver);
3069 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3070 early_platform_init_buffer("earlyprintk", &sci_driver,
3071 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3073 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3074 static struct __init plat_sci_port port_cfg;
3076 static int __init early_console_setup(struct earlycon_device *device,
3079 if (!device->port.membase)
3082 device->port.serial_in = sci_serial_in;
3083 device->port.serial_out = sci_serial_out;
3084 device->port.type = type;
3085 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3086 sci_ports[0].cfg = &port_cfg;
3087 sci_ports[0].cfg->type = type;
3088 sci_probe_regmap(sci_ports[0].cfg);
3089 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3090 SCSCR_RE | SCSCR_TE;
3091 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3093 device->con->write = serial_console_write;
3096 static int __init sci_early_console_setup(struct earlycon_device *device,
3099 return early_console_setup(device, PORT_SCI);
3101 static int __init scif_early_console_setup(struct earlycon_device *device,
3104 return early_console_setup(device, PORT_SCIF);
3106 static int __init scifa_early_console_setup(struct earlycon_device *device,
3109 return early_console_setup(device, PORT_SCIFA);
3111 static int __init scifb_early_console_setup(struct earlycon_device *device,
3114 return early_console_setup(device, PORT_SCIFB);
3116 static int __init hscif_early_console_setup(struct earlycon_device *device,
3119 return early_console_setup(device, PORT_HSCIF);
3122 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3123 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3124 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3125 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3126 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3127 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3129 module_init(sci_init);
3130 module_exit(sci_exit);
3132 MODULE_LICENSE("GPL");
3133 MODULE_ALIAS("platform:sh-sci");
3134 MODULE_AUTHOR("Paul Mundt");
3135 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");