1 // SPDX-License-Identifier: GPL-2.0+
3 * NXP (Philips) SCC+++(SCN+++) serial driver
5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
10 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
26 #include <linux/platform_data/serial-sccnxp.h>
27 #include <linux/regulator/consumer.h>
29 #define SCCNXP_NAME "uart-sccnxp"
30 #define SCCNXP_MAJOR 204
31 #define SCCNXP_MINOR 205
33 #define SCCNXP_MR_REG (0x00)
34 # define MR0_BAUD_NORMAL (0 << 0)
35 # define MR0_BAUD_EXT1 (1 << 0)
36 # define MR0_BAUD_EXT2 (5 << 0)
37 # define MR0_FIFO (1 << 3)
38 # define MR0_TXLVL (1 << 4)
39 # define MR1_BITS_5 (0 << 0)
40 # define MR1_BITS_6 (1 << 0)
41 # define MR1_BITS_7 (2 << 0)
42 # define MR1_BITS_8 (3 << 0)
43 # define MR1_PAR_EVN (0 << 2)
44 # define MR1_PAR_ODD (1 << 2)
45 # define MR1_PAR_NO (4 << 2)
46 # define MR2_STOP1 (7 << 0)
47 # define MR2_STOP2 (0xf << 0)
48 #define SCCNXP_SR_REG (0x01)
49 #define SCCNXP_CSR_REG SCCNXP_SR_REG
50 # define SR_RXRDY (1 << 0)
51 # define SR_FULL (1 << 1)
52 # define SR_TXRDY (1 << 2)
53 # define SR_TXEMT (1 << 3)
54 # define SR_OVR (1 << 4)
55 # define SR_PE (1 << 5)
56 # define SR_FE (1 << 6)
57 # define SR_BRK (1 << 7)
58 #define SCCNXP_CR_REG (0x02)
59 # define CR_RX_ENABLE (1 << 0)
60 # define CR_RX_DISABLE (1 << 1)
61 # define CR_TX_ENABLE (1 << 2)
62 # define CR_TX_DISABLE (1 << 3)
63 # define CR_CMD_MRPTR1 (0x01 << 4)
64 # define CR_CMD_RX_RESET (0x02 << 4)
65 # define CR_CMD_TX_RESET (0x03 << 4)
66 # define CR_CMD_STATUS_RESET (0x04 << 4)
67 # define CR_CMD_BREAK_RESET (0x05 << 4)
68 # define CR_CMD_START_BREAK (0x06 << 4)
69 # define CR_CMD_STOP_BREAK (0x07 << 4)
70 # define CR_CMD_MRPTR0 (0x0b << 4)
71 #define SCCNXP_RHR_REG (0x03)
72 #define SCCNXP_THR_REG SCCNXP_RHR_REG
73 #define SCCNXP_IPCR_REG (0x04)
74 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
75 # define ACR_BAUD0 (0 << 7)
76 # define ACR_BAUD1 (1 << 7)
77 # define ACR_TIMER_MODE (6 << 4)
78 #define SCCNXP_ISR_REG (0x05)
79 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
80 # define IMR_TXRDY (1 << 0)
81 # define IMR_RXRDY (1 << 1)
82 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
83 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
84 #define SCCNXP_IPR_REG (0x0d)
85 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
86 #define SCCNXP_SOP_REG (0x0e)
87 #define SCCNXP_ROP_REG (0x0f)
90 #define MCTRL_MASK(sig) (0xf << (sig))
91 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
92 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
94 #define SCCNXP_HAVE_IO 0x00000001
95 #define SCCNXP_HAVE_MR0 0x00000002
100 unsigned long freq_min;
101 unsigned long freq_std;
102 unsigned long freq_max;
104 unsigned int fifosize;
108 struct uart_driver uart;
109 struct uart_port port[SCCNXP_MAX_UARTS];
110 bool opened[SCCNXP_MAX_UARTS];
115 struct sccnxp_chip *chip;
117 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
118 struct console console;
124 struct timer_list timer;
126 struct sccnxp_pdata pdata;
128 struct regulator *regulator;
131 static const struct sccnxp_chip sc2681 = {
137 .flags = SCCNXP_HAVE_IO,
141 static const struct sccnxp_chip sc2691 = {
151 static const struct sccnxp_chip sc2692 = {
157 .flags = SCCNXP_HAVE_IO,
161 static const struct sccnxp_chip sc2891 = {
167 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
171 static const struct sccnxp_chip sc2892 = {
177 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
181 static const struct sccnxp_chip sc28202 = {
185 .freq_std = 14745600,
186 .freq_max = 50000000,
187 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
191 static const struct sccnxp_chip sc68681 = {
197 .flags = SCCNXP_HAVE_IO,
201 static const struct sccnxp_chip sc68692 = {
207 .flags = SCCNXP_HAVE_IO,
211 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
213 return readb(port->membase + (reg << port->regshift));
216 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
218 writeb(v, port->membase + (reg << port->regshift));
221 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
223 return sccnxp_read(port, (port->line << 3) + reg);
226 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
228 sccnxp_write(port, (port->line << 3) + reg, v);
231 static int sccnxp_update_best_err(int a, int b, int *besterr)
233 int err = abs(a - b);
235 if ((*besterr < 0) || (*besterr > err)) {
243 static const struct {
249 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
250 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
251 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
252 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
253 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
254 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
255 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
256 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
257 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
258 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
259 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
260 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
261 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
262 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
263 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
264 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
265 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
266 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
267 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
268 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
269 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
270 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
271 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
272 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
273 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
274 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
275 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
276 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
280 static int sccnxp_set_baud(struct uart_port *port, int baud)
282 struct sccnxp_port *s = dev_get_drvdata(port->dev);
283 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
284 struct sccnxp_chip *chip = s->chip;
285 u8 i, acr = 0, csr = 0, mr0 = 0;
287 /* Find best baud from table */
288 for (i = 0; baud_std[i].baud && besterr; i++) {
289 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
291 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
292 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
293 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
294 acr = baud_std[i].acr;
295 csr = baud_std[i].csr;
296 mr0 = baud_std[i].mr0;
301 if (chip->flags & SCCNXP_HAVE_MR0) {
302 /* Enable FIFO, set half level for TX */
303 mr0 |= MR0_FIFO | MR0_TXLVL;
305 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
306 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
309 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
310 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
312 if (baud != bestbaud)
313 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
319 static void sccnxp_enable_irq(struct uart_port *port, int mask)
321 struct sccnxp_port *s = dev_get_drvdata(port->dev);
323 s->imr |= mask << (port->line * 4);
324 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
327 static void sccnxp_disable_irq(struct uart_port *port, int mask)
329 struct sccnxp_port *s = dev_get_drvdata(port->dev);
331 s->imr &= ~(mask << (port->line * 4));
332 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
335 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
338 struct sccnxp_port *s = dev_get_drvdata(port->dev);
340 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
341 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
343 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
345 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
349 static void sccnxp_handle_rx(struct uart_port *port)
352 unsigned int ch, flag;
355 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
356 if (!(sr & SR_RXRDY))
358 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
360 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
368 sccnxp_port_write(port, SCCNXP_CR_REG,
370 if (uart_handle_break(port))
372 } else if (sr & SR_PE)
373 port->icount.parity++;
375 port->icount.frame++;
376 else if (sr & SR_OVR) {
377 port->icount.overrun++;
378 sccnxp_port_write(port, SCCNXP_CR_REG,
379 CR_CMD_STATUS_RESET);
382 sr &= port->read_status_mask;
389 else if (sr & SR_OVR)
393 if (uart_handle_sysrq_char(port, ch))
396 if (sr & port->ignore_status_mask)
399 uart_insert_char(port, sr, SR_OVR, ch, flag);
402 tty_flip_buffer_push(&port->state->port);
405 static void sccnxp_handle_tx(struct uart_port *port)
408 struct circ_buf *xmit = &port->state->xmit;
409 struct sccnxp_port *s = dev_get_drvdata(port->dev);
411 if (unlikely(port->x_char)) {
412 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
418 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
419 /* Disable TX if FIFO is empty */
420 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
421 sccnxp_disable_irq(port, IMR_TXRDY);
423 /* Set direction to input */
424 if (s->chip->flags & SCCNXP_HAVE_IO)
425 sccnxp_set_bit(port, DIR_OP, 0);
430 while (!uart_circ_empty(xmit)) {
431 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
432 if (!(sr & SR_TXRDY))
435 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
436 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(port);
444 static void sccnxp_handle_events(struct sccnxp_port *s)
450 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
455 for (i = 0; i < s->uart.nr; i++) {
456 if (s->opened[i] && (isr & ISR_RXRDY(i)))
457 sccnxp_handle_rx(&s->port[i]);
458 if (s->opened[i] && (isr & ISR_TXRDY(i)))
459 sccnxp_handle_tx(&s->port[i]);
464 static void sccnxp_timer(struct timer_list *t)
466 struct sccnxp_port *s = from_timer(s, t, timer);
469 spin_lock_irqsave(&s->lock, flags);
470 sccnxp_handle_events(s);
471 spin_unlock_irqrestore(&s->lock, flags);
473 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
476 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
478 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
481 spin_lock_irqsave(&s->lock, flags);
482 sccnxp_handle_events(s);
483 spin_unlock_irqrestore(&s->lock, flags);
488 static void sccnxp_start_tx(struct uart_port *port)
490 struct sccnxp_port *s = dev_get_drvdata(port->dev);
493 spin_lock_irqsave(&s->lock, flags);
495 /* Set direction to output */
496 if (s->chip->flags & SCCNXP_HAVE_IO)
497 sccnxp_set_bit(port, DIR_OP, 1);
499 sccnxp_enable_irq(port, IMR_TXRDY);
501 spin_unlock_irqrestore(&s->lock, flags);
504 static void sccnxp_stop_tx(struct uart_port *port)
509 static void sccnxp_stop_rx(struct uart_port *port)
511 struct sccnxp_port *s = dev_get_drvdata(port->dev);
514 spin_lock_irqsave(&s->lock, flags);
515 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
516 spin_unlock_irqrestore(&s->lock, flags);
519 static unsigned int sccnxp_tx_empty(struct uart_port *port)
523 struct sccnxp_port *s = dev_get_drvdata(port->dev);
525 spin_lock_irqsave(&s->lock, flags);
526 val = sccnxp_port_read(port, SCCNXP_SR_REG);
527 spin_unlock_irqrestore(&s->lock, flags);
529 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
532 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
534 struct sccnxp_port *s = dev_get_drvdata(port->dev);
537 if (!(s->chip->flags & SCCNXP_HAVE_IO))
540 spin_lock_irqsave(&s->lock, flags);
542 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
543 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
545 spin_unlock_irqrestore(&s->lock, flags);
548 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
552 struct sccnxp_port *s = dev_get_drvdata(port->dev);
553 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
555 if (!(s->chip->flags & SCCNXP_HAVE_IO))
558 spin_lock_irqsave(&s->lock, flags);
560 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
562 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
563 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
566 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
568 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
569 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
572 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
574 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
575 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
578 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
580 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
581 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
584 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
587 spin_unlock_irqrestore(&s->lock, flags);
592 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
594 struct sccnxp_port *s = dev_get_drvdata(port->dev);
597 spin_lock_irqsave(&s->lock, flags);
598 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
599 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
600 spin_unlock_irqrestore(&s->lock, flags);
603 static void sccnxp_set_termios(struct uart_port *port,
604 struct ktermios *termios, struct ktermios *old)
606 struct sccnxp_port *s = dev_get_drvdata(port->dev);
611 spin_lock_irqsave(&s->lock, flags);
613 /* Mask termios capabilities we don't support */
614 termios->c_cflag &= ~CMSPAR;
616 /* Disable RX & TX, reset break condition, status and FIFOs */
617 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
618 CR_RX_DISABLE | CR_TX_DISABLE);
619 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
620 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
624 switch (termios->c_cflag & CSIZE) {
641 if (termios->c_cflag & PARENB) {
642 if (termios->c_cflag & PARODD)
648 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
650 /* Update desired format */
651 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
652 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
653 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
655 /* Set read status mask */
656 port->read_status_mask = SR_OVR;
657 if (termios->c_iflag & INPCK)
658 port->read_status_mask |= SR_PE | SR_FE;
659 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
660 port->read_status_mask |= SR_BRK;
662 /* Set status ignore mask */
663 port->ignore_status_mask = 0;
664 if (termios->c_iflag & IGNBRK)
665 port->ignore_status_mask |= SR_BRK;
666 if (termios->c_iflag & IGNPAR)
667 port->ignore_status_mask |= SR_PE;
668 if (!(termios->c_cflag & CREAD))
669 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
672 baud = uart_get_baud_rate(port, termios, old, 50,
673 (s->chip->flags & SCCNXP_HAVE_MR0) ?
675 baud = sccnxp_set_baud(port, baud);
677 /* Update timeout according to new baud rate */
678 uart_update_timeout(port, termios->c_cflag, baud);
680 /* Report actual baudrate back to core */
681 if (tty_termios_baud_rate(termios))
682 tty_termios_encode_baud_rate(termios, baud, baud);
685 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
687 spin_unlock_irqrestore(&s->lock, flags);
690 static int sccnxp_startup(struct uart_port *port)
692 struct sccnxp_port *s = dev_get_drvdata(port->dev);
695 spin_lock_irqsave(&s->lock, flags);
697 if (s->chip->flags & SCCNXP_HAVE_IO) {
698 /* Outputs are controlled manually */
699 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
702 /* Reset break condition, status and FIFOs */
703 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
704 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
705 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
706 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
709 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
711 /* Enable RX interrupt */
712 sccnxp_enable_irq(port, IMR_RXRDY);
714 s->opened[port->line] = 1;
716 spin_unlock_irqrestore(&s->lock, flags);
721 static void sccnxp_shutdown(struct uart_port *port)
723 struct sccnxp_port *s = dev_get_drvdata(port->dev);
726 spin_lock_irqsave(&s->lock, flags);
728 s->opened[port->line] = 0;
730 /* Disable interrupts */
731 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
733 /* Disable TX & RX */
734 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
736 /* Leave direction to input */
737 if (s->chip->flags & SCCNXP_HAVE_IO)
738 sccnxp_set_bit(port, DIR_OP, 0);
740 spin_unlock_irqrestore(&s->lock, flags);
743 static const char *sccnxp_type(struct uart_port *port)
745 struct sccnxp_port *s = dev_get_drvdata(port->dev);
747 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
750 static void sccnxp_release_port(struct uart_port *port)
755 static int sccnxp_request_port(struct uart_port *port)
761 static void sccnxp_config_port(struct uart_port *port, int flags)
763 if (flags & UART_CONFIG_TYPE)
764 port->type = PORT_SC26XX;
767 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
769 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
771 if (s->irq == port->irq)
777 static const struct uart_ops sccnxp_ops = {
778 .tx_empty = sccnxp_tx_empty,
779 .set_mctrl = sccnxp_set_mctrl,
780 .get_mctrl = sccnxp_get_mctrl,
781 .stop_tx = sccnxp_stop_tx,
782 .start_tx = sccnxp_start_tx,
783 .stop_rx = sccnxp_stop_rx,
784 .break_ctl = sccnxp_break_ctl,
785 .startup = sccnxp_startup,
786 .shutdown = sccnxp_shutdown,
787 .set_termios = sccnxp_set_termios,
789 .release_port = sccnxp_release_port,
790 .request_port = sccnxp_request_port,
791 .config_port = sccnxp_config_port,
792 .verify_port = sccnxp_verify_port,
795 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
796 static void sccnxp_console_putchar(struct uart_port *port, int c)
801 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
802 sccnxp_port_write(port, SCCNXP_THR_REG, c);
809 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
811 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
812 struct uart_port *port = &s->port[co->index];
815 spin_lock_irqsave(&s->lock, flags);
816 uart_console_write(port, c, n, sccnxp_console_putchar);
817 spin_unlock_irqrestore(&s->lock, flags);
820 static int sccnxp_console_setup(struct console *co, char *options)
822 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
823 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
824 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
827 uart_parse_options(options, &baud, &parity, &bits, &flow);
829 return uart_set_options(port, co, baud, parity, bits, flow);
833 static const struct platform_device_id sccnxp_id_table[] = {
834 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
835 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
836 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
837 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
838 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
839 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
840 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
841 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
844 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
846 static int sccnxp_probe(struct platform_device *pdev)
848 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
849 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
851 struct sccnxp_port *s;
852 void __iomem *membase;
855 membase = devm_ioremap_resource(&pdev->dev, res);
857 return PTR_ERR(membase);
859 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
861 dev_err(&pdev->dev, "Error allocating port structure\n");
864 platform_set_drvdata(pdev, s);
866 spin_lock_init(&s->lock);
868 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
870 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
871 if (!IS_ERR(s->regulator)) {
872 ret = regulator_enable(s->regulator);
875 "Failed to enable regulator: %i\n", ret);
878 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
879 return -EPROBE_DEFER;
881 clk = devm_clk_get(&pdev->dev, NULL);
884 if (ret == -EPROBE_DEFER)
888 ret = clk_prepare_enable(clk);
892 ret = devm_add_action_or_reset(&pdev->dev,
893 (void(*)(void *))clk_disable_unprepare,
898 uartclk = clk_get_rate(clk);
902 dev_notice(&pdev->dev, "Using default clock frequency\n");
903 uartclk = s->chip->freq_std;
906 /* Check input frequency */
907 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
908 dev_err(&pdev->dev, "Frequency out of bounds\n");
914 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
916 if (s->pdata.poll_time_us) {
917 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
918 s->pdata.poll_time_us);
923 s->irq = platform_get_irq(pdev, 0);
925 dev_err(&pdev->dev, "Missing irq resource data\n");
931 s->uart.owner = THIS_MODULE;
932 s->uart.dev_name = "ttySC";
933 s->uart.major = SCCNXP_MAJOR;
934 s->uart.minor = SCCNXP_MINOR;
935 s->uart.nr = s->chip->nr;
936 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
937 s->uart.cons = &s->console;
938 s->uart.cons->device = uart_console_device;
939 s->uart.cons->write = sccnxp_console_write;
940 s->uart.cons->setup = sccnxp_console_setup;
941 s->uart.cons->flags = CON_PRINTBUFFER;
942 s->uart.cons->index = -1;
943 s->uart.cons->data = s;
944 strcpy(s->uart.cons->name, "ttySC");
946 ret = uart_register_driver(&s->uart);
948 dev_err(&pdev->dev, "Registering UART driver failed\n");
952 for (i = 0; i < s->uart.nr; i++) {
954 s->port[i].dev = &pdev->dev;
955 s->port[i].irq = s->irq;
956 s->port[i].type = PORT_SC26XX;
957 s->port[i].fifosize = s->chip->fifosize;
958 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
959 s->port[i].iotype = UPIO_MEM;
960 s->port[i].mapbase = res->start;
961 s->port[i].membase = membase;
962 s->port[i].regshift = s->pdata.reg_shift;
963 s->port[i].uartclk = uartclk;
964 s->port[i].ops = &sccnxp_ops;
965 uart_add_one_port(&s->uart, &s->port[i]);
966 /* Set direction to input */
967 if (s->chip->flags & SCCNXP_HAVE_IO)
968 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
971 /* Disable interrupts */
973 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
976 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
978 IRQF_TRIGGER_FALLING |
980 dev_name(&pdev->dev), s);
984 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
986 timer_setup(&s->timer, sccnxp_timer, 0);
987 mod_timer(&s->timer, jiffies +
988 usecs_to_jiffies(s->pdata.poll_time_us));
992 uart_unregister_driver(&s->uart);
994 if (!IS_ERR(s->regulator))
995 regulator_disable(s->regulator);
1000 static int sccnxp_remove(struct platform_device *pdev)
1003 struct sccnxp_port *s = platform_get_drvdata(pdev);
1006 devm_free_irq(&pdev->dev, s->irq, s);
1008 del_timer_sync(&s->timer);
1010 for (i = 0; i < s->uart.nr; i++)
1011 uart_remove_one_port(&s->uart, &s->port[i]);
1013 uart_unregister_driver(&s->uart);
1015 if (!IS_ERR(s->regulator))
1016 return regulator_disable(s->regulator);
1021 static struct platform_driver sccnxp_uart_driver = {
1023 .name = SCCNXP_NAME,
1025 .probe = sccnxp_probe,
1026 .remove = sccnxp_remove,
1027 .id_table = sccnxp_id_table,
1029 module_platform_driver(sccnxp_uart_driver);
1031 MODULE_LICENSE("GPL v2");
1032 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1033 MODULE_DESCRIPTION("SCCNXP serial driver");