1 // SPDX-License-Identifier: GPL-2.0
3 * Driver core for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
9 /* Note on 2410 error handling
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
30 #include <linux/platform_device.h>
31 #include <linux/init.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_s3c.h>
39 #include <linux/delay.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
45 /* UART name and device definitions */
47 #define S3C24XX_SERIAL_NAME "ttySAC"
48 #define S3C24XX_SERIAL_MAJOR 204
49 #define S3C24XX_SERIAL_MINOR 64
51 #define S3C24XX_TX_PIO 1
52 #define S3C24XX_TX_DMA 2
53 #define S3C24XX_RX_PIO 1
54 #define S3C24XX_RX_DMA 2
56 /* flag to ignore all characters coming in */
57 #define RXSTAT_DUMMY_READ (0x10000000)
59 enum s3c24xx_port_type {
65 struct s3c24xx_uart_info {
67 enum s3c24xx_port_type type;
68 unsigned int port_type;
69 unsigned int fifosize;
70 unsigned long rx_fifomask;
71 unsigned long rx_fifoshift;
72 unsigned long rx_fifofull;
73 unsigned long tx_fifomask;
74 unsigned long tx_fifoshift;
75 unsigned long tx_fifofull;
76 unsigned int def_clk_sel;
77 unsigned long num_clks;
78 unsigned long clksel_mask;
79 unsigned long clksel_shift;
80 unsigned long ucon_mask;
82 /* uart port features */
84 unsigned int has_divslot:1;
87 struct s3c24xx_serial_drv_data {
88 const struct s3c24xx_uart_info info;
89 const struct s3c2410_uartcfg def_cfg;
90 const unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
93 struct s3c24xx_uart_dma {
94 unsigned int rx_chan_id;
95 unsigned int tx_chan_id;
97 struct dma_slave_config rx_conf;
98 struct dma_slave_config tx_conf;
100 struct dma_chan *rx_chan;
101 struct dma_chan *tx_chan;
106 dma_cookie_t rx_cookie;
107 dma_cookie_t tx_cookie;
111 dma_addr_t tx_transfer_addr;
116 struct dma_async_tx_descriptor *tx_desc;
117 struct dma_async_tx_descriptor *rx_desc;
119 int tx_bytes_requested;
120 int rx_bytes_requested;
123 struct s3c24xx_uart_port {
124 unsigned char rx_claimed;
125 unsigned char tx_claimed;
126 unsigned char rx_enabled;
127 unsigned char tx_enabled;
128 unsigned int pm_level;
129 unsigned long baudclk_rate;
130 unsigned int min_dma_size;
135 unsigned int tx_in_progress;
136 unsigned int tx_mode;
137 unsigned int rx_mode;
139 const struct s3c24xx_uart_info *info;
142 struct uart_port port;
143 const struct s3c24xx_serial_drv_data *drv_data;
145 /* reference to platform data */
146 const struct s3c2410_uartcfg *cfg;
148 struct s3c24xx_uart_dma *dma;
150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
151 struct notifier_block freq_transition;
155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
157 /* conversion functions */
159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
161 /* register access controls */
163 #define portaddr(port, reg) ((port)->membase + (reg))
164 #define portaddrl(port, reg) \
165 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
167 static u32 rd_reg(const struct uart_port *port, u32 reg)
169 switch (port->iotype) {
171 return readb_relaxed(portaddr(port, reg));
173 return readl_relaxed(portaddr(port, reg));
180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
182 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
184 switch (port->iotype) {
186 writeb_relaxed(val, portaddr(port, reg));
189 writel_relaxed(val, portaddr(port, reg));
194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
196 /* Byte-order aware bit setting/clearing functions. */
198 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
204 local_irq_save(flags);
205 val = rd_regl(port, reg);
207 wr_regl(port, reg, val);
208 local_irq_restore(flags);
211 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
217 local_irq_save(flags);
218 val = rd_regl(port, reg);
220 wr_regl(port, reg, val);
221 local_irq_restore(flags);
224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
226 return container_of(port, struct s3c24xx_uart_port, port);
229 /* translate a port to the device name */
231 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
233 return to_platform_device(port->dev)->name;
236 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
238 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
243 struct s3c24xx_uart_port *ourport = to_ourport(port);
245 unsigned int ucon, ufcon;
248 spin_lock_irqsave(&port->lock, flags);
250 while (--count && !s3c24xx_serial_txempty_nofifo(port))
253 ufcon = rd_regl(port, S3C2410_UFCON);
254 ufcon |= S3C2410_UFCON_RESETRX;
255 wr_regl(port, S3C2410_UFCON, ufcon);
257 ucon = rd_regl(port, S3C2410_UCON);
258 ucon |= S3C2410_UCON_RXIRQMODE;
259 wr_regl(port, S3C2410_UCON, ucon);
261 ourport->rx_enabled = 1;
262 spin_unlock_irqrestore(&port->lock, flags);
265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
267 struct s3c24xx_uart_port *ourport = to_ourport(port);
271 spin_lock_irqsave(&port->lock, flags);
273 ucon = rd_regl(port, S3C2410_UCON);
274 ucon &= ~S3C2410_UCON_RXIRQMODE;
275 wr_regl(port, S3C2410_UCON, ucon);
277 ourport->rx_enabled = 0;
278 spin_unlock_irqrestore(&port->lock, flags);
281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
283 struct s3c24xx_uart_port *ourport = to_ourport(port);
284 struct s3c24xx_uart_dma *dma = ourport->dma;
285 struct circ_buf *xmit = &port->state->xmit;
286 struct dma_tx_state state;
289 if (!ourport->tx_enabled)
292 switch (ourport->info->type) {
294 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
297 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
300 disable_irq_nosync(ourport->tx_irq);
304 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
305 dmaengine_pause(dma->tx_chan);
306 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
307 dmaengine_terminate_all(dma->tx_chan);
308 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
309 dma->tx_transfer_addr, dma->tx_size,
311 async_tx_ack(dma->tx_desc);
312 count = dma->tx_bytes_requested - state.residue;
313 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
314 port->icount.tx += count;
317 ourport->tx_enabled = 0;
318 ourport->tx_in_progress = 0;
320 if (port->flags & UPF_CONS_FLOW)
321 s3c24xx_serial_rx_enable(port);
323 ourport->tx_mode = 0;
326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
328 static void s3c24xx_serial_tx_dma_complete(void *args)
330 struct s3c24xx_uart_port *ourport = args;
331 struct uart_port *port = &ourport->port;
332 struct circ_buf *xmit = &port->state->xmit;
333 struct s3c24xx_uart_dma *dma = ourport->dma;
334 struct dma_tx_state state;
338 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
339 count = dma->tx_bytes_requested - state.residue;
340 async_tx_ack(dma->tx_desc);
342 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
343 dma->tx_transfer_addr, dma->tx_size,
346 spin_lock_irqsave(&port->lock, flags);
348 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
349 port->icount.tx += count;
350 ourport->tx_in_progress = 0;
352 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
353 uart_write_wakeup(port);
355 s3c24xx_serial_start_next_tx(ourport);
356 spin_unlock_irqrestore(&port->lock, flags);
359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
361 const struct uart_port *port = &ourport->port;
364 /* Mask Tx interrupt */
365 switch (ourport->info->type) {
367 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
370 WARN_ON(1); // No DMA
373 disable_irq_nosync(ourport->tx_irq);
377 /* Enable tx dma mode */
378 ucon = rd_regl(port, S3C2410_UCON);
379 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
380 ucon |= S3C64XX_UCON_TXBURST_1;
381 ucon |= S3C64XX_UCON_TXMODE_DMA;
382 wr_regl(port, S3C2410_UCON, ucon);
384 ourport->tx_mode = S3C24XX_TX_DMA;
387 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
389 const struct uart_port *port = &ourport->port;
392 /* Set ufcon txtrig */
393 ourport->tx_in_progress = S3C24XX_TX_PIO;
394 ufcon = rd_regl(port, S3C2410_UFCON);
395 wr_regl(port, S3C2410_UFCON, ufcon);
397 /* Enable tx pio mode */
398 ucon = rd_regl(port, S3C2410_UCON);
399 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
400 ucon |= S3C64XX_UCON_TXMODE_CPU;
401 wr_regl(port, S3C2410_UCON, ucon);
403 /* Unmask Tx interrupt */
404 switch (ourport->info->type) {
406 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
410 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
411 wr_regl(port, S3C2410_UCON, ucon);
414 enable_irq(ourport->tx_irq);
418 ourport->tx_mode = S3C24XX_TX_PIO;
421 * The Apple version only has edge triggered TX IRQs, so we need
422 * to kick off the process by sending some characters here.
424 if (ourport->info->type == TYPE_APPLE_S5L)
425 s3c24xx_serial_tx_chars(ourport);
428 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
430 if (ourport->tx_mode != S3C24XX_TX_PIO)
431 enable_tx_pio(ourport);
434 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
437 struct uart_port *port = &ourport->port;
438 struct circ_buf *xmit = &port->state->xmit;
439 struct s3c24xx_uart_dma *dma = ourport->dma;
441 if (ourport->tx_mode != S3C24XX_TX_DMA)
442 enable_tx_dma(ourport);
444 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
445 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
447 dma_sync_single_for_device(dma->tx_chan->device->dev,
448 dma->tx_transfer_addr, dma->tx_size,
451 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
452 dma->tx_transfer_addr, dma->tx_size,
453 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
455 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
459 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
460 dma->tx_desc->callback_param = ourport;
461 dma->tx_bytes_requested = dma->tx_size;
463 ourport->tx_in_progress = S3C24XX_TX_DMA;
464 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
465 dma_async_issue_pending(dma->tx_chan);
469 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
471 struct uart_port *port = &ourport->port;
472 struct circ_buf *xmit = &port->state->xmit;
475 /* Get data size up to the end of buffer */
476 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
479 s3c24xx_serial_stop_tx(port);
483 if (!ourport->dma || !ourport->dma->tx_chan ||
484 count < ourport->min_dma_size ||
485 xmit->tail & (dma_get_cache_alignment() - 1))
486 s3c24xx_serial_start_tx_pio(ourport);
488 s3c24xx_serial_start_tx_dma(ourport, count);
491 static void s3c24xx_serial_start_tx(struct uart_port *port)
493 struct s3c24xx_uart_port *ourport = to_ourport(port);
494 struct circ_buf *xmit = &port->state->xmit;
496 if (!ourport->tx_enabled) {
497 if (port->flags & UPF_CONS_FLOW)
498 s3c24xx_serial_rx_disable(port);
500 ourport->tx_enabled = 1;
501 if (!ourport->dma || !ourport->dma->tx_chan)
502 s3c24xx_serial_start_tx_pio(ourport);
505 if (ourport->dma && ourport->dma->tx_chan) {
506 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
507 s3c24xx_serial_start_next_tx(ourport);
511 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
512 struct tty_port *tty, int count)
514 struct s3c24xx_uart_dma *dma = ourport->dma;
520 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
521 dma->rx_size, DMA_FROM_DEVICE);
523 ourport->port.icount.rx += count;
525 dev_err(ourport->port.dev, "No tty port\n");
528 copied = tty_insert_flip_string(tty,
529 ((unsigned char *)(ourport->dma->rx_buf)), count);
530 if (copied != count) {
532 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
536 static void s3c24xx_serial_stop_rx(struct uart_port *port)
538 struct s3c24xx_uart_port *ourport = to_ourport(port);
539 struct s3c24xx_uart_dma *dma = ourport->dma;
540 struct tty_port *t = &port->state->port;
541 struct dma_tx_state state;
542 enum dma_status dma_status;
543 unsigned int received;
545 if (ourport->rx_enabled) {
546 dev_dbg(port->dev, "stopping rx\n");
547 switch (ourport->info->type) {
549 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
553 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
554 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
557 disable_irq_nosync(ourport->rx_irq);
560 ourport->rx_enabled = 0;
562 if (dma && dma->rx_chan) {
563 dmaengine_pause(dma->tx_chan);
564 dma_status = dmaengine_tx_status(dma->rx_chan,
565 dma->rx_cookie, &state);
566 if (dma_status == DMA_IN_PROGRESS ||
567 dma_status == DMA_PAUSED) {
568 received = dma->rx_bytes_requested - state.residue;
569 dmaengine_terminate_all(dma->rx_chan);
570 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
575 static inline const struct s3c24xx_uart_info
576 *s3c24xx_port_to_info(struct uart_port *port)
578 return to_ourport(port)->info;
581 static inline const struct s3c2410_uartcfg
582 *s3c24xx_port_to_cfg(const struct uart_port *port)
584 const struct s3c24xx_uart_port *ourport;
586 if (port->dev == NULL)
589 ourport = container_of(port, struct s3c24xx_uart_port, port);
593 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
594 unsigned long ufstat)
596 const struct s3c24xx_uart_info *info = ourport->info;
598 if (ufstat & info->rx_fifofull)
599 return ourport->port.fifosize;
601 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
604 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
605 static void s3c24xx_serial_rx_dma_complete(void *args)
607 struct s3c24xx_uart_port *ourport = args;
608 struct uart_port *port = &ourport->port;
610 struct s3c24xx_uart_dma *dma = ourport->dma;
611 struct tty_port *t = &port->state->port;
612 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
614 struct dma_tx_state state;
618 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
619 received = dma->rx_bytes_requested - state.residue;
620 async_tx_ack(dma->rx_desc);
622 spin_lock_irqsave(&port->lock, flags);
625 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
628 tty_flip_buffer_push(t);
632 s3c64xx_start_rx_dma(ourport);
634 spin_unlock_irqrestore(&port->lock, flags);
637 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
639 struct s3c24xx_uart_dma *dma = ourport->dma;
641 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
642 dma->rx_size, DMA_FROM_DEVICE);
644 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
645 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
648 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
652 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
653 dma->rx_desc->callback_param = ourport;
654 dma->rx_bytes_requested = dma->rx_size;
656 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
657 dma_async_issue_pending(dma->rx_chan);
660 /* ? - where has parity gone?? */
661 #define S3C2410_UERSTAT_PARITY (0x1000)
663 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
665 struct uart_port *port = &ourport->port;
668 /* set Rx mode to DMA mode */
669 ucon = rd_regl(port, S3C2410_UCON);
670 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
671 S3C64XX_UCON_TIMEOUT_MASK |
672 S3C64XX_UCON_EMPTYINT_EN |
673 S3C64XX_UCON_DMASUS_EN |
674 S3C64XX_UCON_TIMEOUT_EN |
675 S3C64XX_UCON_RXMODE_MASK);
676 ucon |= S3C64XX_UCON_RXBURST_1 |
677 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
678 S3C64XX_UCON_EMPTYINT_EN |
679 S3C64XX_UCON_TIMEOUT_EN |
680 S3C64XX_UCON_RXMODE_DMA;
681 wr_regl(port, S3C2410_UCON, ucon);
683 ourport->rx_mode = S3C24XX_RX_DMA;
686 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
688 struct uart_port *port = &ourport->port;
691 /* set Rx mode to DMA mode */
692 ucon = rd_regl(port, S3C2410_UCON);
693 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
694 ucon |= S3C64XX_UCON_RXMODE_CPU;
696 /* Apple types use these bits for IRQ masks */
697 if (ourport->info->type != TYPE_APPLE_S5L) {
698 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
699 S3C64XX_UCON_EMPTYINT_EN |
700 S3C64XX_UCON_DMASUS_EN |
701 S3C64XX_UCON_TIMEOUT_EN);
702 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
703 S3C64XX_UCON_TIMEOUT_EN;
705 wr_regl(port, S3C2410_UCON, ucon);
707 ourport->rx_mode = S3C24XX_RX_PIO;
710 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
712 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
714 unsigned int utrstat, received;
715 struct s3c24xx_uart_port *ourport = dev_id;
716 struct uart_port *port = &ourport->port;
717 struct s3c24xx_uart_dma *dma = ourport->dma;
718 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
719 struct tty_port *t = &port->state->port;
720 struct dma_tx_state state;
722 utrstat = rd_regl(port, S3C2410_UTRSTAT);
723 rd_regl(port, S3C2410_UFSTAT);
725 spin_lock(&port->lock);
727 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
728 s3c64xx_start_rx_dma(ourport);
729 if (ourport->rx_mode == S3C24XX_RX_PIO)
730 enable_rx_dma(ourport);
734 if (ourport->rx_mode == S3C24XX_RX_DMA) {
735 dmaengine_pause(dma->rx_chan);
736 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
737 dmaengine_terminate_all(dma->rx_chan);
738 received = dma->rx_bytes_requested - state.residue;
739 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
741 enable_rx_pio(ourport);
744 s3c24xx_serial_rx_drain_fifo(ourport);
747 tty_flip_buffer_push(t);
751 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
754 spin_unlock(&port->lock);
759 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
761 struct uart_port *port = &ourport->port;
762 unsigned int ufcon, ch, flag, ufstat, uerstat;
763 unsigned int fifocnt = 0;
764 int max_count = port->fifosize;
766 while (max_count-- > 0) {
768 * Receive all characters known to be in FIFO
769 * before reading FIFO level again
772 ufstat = rd_regl(port, S3C2410_UFSTAT);
773 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
779 uerstat = rd_regl(port, S3C2410_UERSTAT);
780 ch = rd_reg(port, S3C2410_URXH);
782 if (port->flags & UPF_CONS_FLOW) {
783 int txe = s3c24xx_serial_txempty_nofifo(port);
785 if (ourport->rx_enabled) {
787 ourport->rx_enabled = 0;
792 ufcon = rd_regl(port, S3C2410_UFCON);
793 ufcon |= S3C2410_UFCON_RESETRX;
794 wr_regl(port, S3C2410_UFCON, ufcon);
795 ourport->rx_enabled = 1;
802 /* insert the character into the buffer */
807 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
809 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
812 /* check for break */
813 if (uerstat & S3C2410_UERSTAT_BREAK) {
814 dev_dbg(port->dev, "break!\n");
816 if (uart_handle_break(port))
817 continue; /* Ignore character */
820 if (uerstat & S3C2410_UERSTAT_FRAME)
821 port->icount.frame++;
822 if (uerstat & S3C2410_UERSTAT_OVERRUN)
823 port->icount.overrun++;
825 uerstat &= port->read_status_mask;
827 if (uerstat & S3C2410_UERSTAT_BREAK)
829 else if (uerstat & S3C2410_UERSTAT_PARITY)
831 else if (uerstat & (S3C2410_UERSTAT_FRAME |
832 S3C2410_UERSTAT_OVERRUN))
836 if (uart_handle_sysrq_char(port, ch))
837 continue; /* Ignore character */
839 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
843 tty_flip_buffer_push(&port->state->port);
846 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
848 struct s3c24xx_uart_port *ourport = dev_id;
849 struct uart_port *port = &ourport->port;
851 spin_lock(&port->lock);
852 s3c24xx_serial_rx_drain_fifo(ourport);
853 spin_unlock(&port->lock);
858 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
860 struct s3c24xx_uart_port *ourport = dev_id;
862 if (ourport->dma && ourport->dma->rx_chan)
863 return s3c24xx_serial_rx_chars_dma(dev_id);
864 return s3c24xx_serial_rx_chars_pio(dev_id);
867 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
869 struct uart_port *port = &ourport->port;
870 struct circ_buf *xmit = &port->state->xmit;
871 int count, dma_count = 0;
873 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
875 if (ourport->dma && ourport->dma->tx_chan &&
876 count >= ourport->min_dma_size) {
877 int align = dma_get_cache_alignment() -
878 (xmit->tail & (dma_get_cache_alignment() - 1));
879 if (count - align >= ourport->min_dma_size) {
880 dma_count = count - align;
886 wr_reg(port, S3C2410_UTXH, port->x_char);
892 /* if there isn't anything more to transmit, or the uart is now
893 * stopped, disable the uart and exit
896 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
897 s3c24xx_serial_stop_tx(port);
901 /* try and drain the buffer... */
903 if (count > port->fifosize) {
904 count = port->fifosize;
908 while (!uart_circ_empty(xmit) && count > 0) {
909 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
912 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
913 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
918 if (!count && dma_count) {
919 s3c24xx_serial_start_tx_dma(ourport, dma_count);
923 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
924 uart_write_wakeup(port);
926 if (uart_circ_empty(xmit))
927 s3c24xx_serial_stop_tx(port);
930 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
932 struct s3c24xx_uart_port *ourport = id;
933 struct uart_port *port = &ourport->port;
935 spin_lock(&port->lock);
937 s3c24xx_serial_tx_chars(ourport);
939 spin_unlock(&port->lock);
943 /* interrupt handler for s3c64xx and later SoC's.*/
944 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
946 const struct s3c24xx_uart_port *ourport = id;
947 const struct uart_port *port = &ourport->port;
948 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
949 irqreturn_t ret = IRQ_HANDLED;
951 if (pend & S3C64XX_UINTM_RXD_MSK) {
952 ret = s3c24xx_serial_rx_irq(irq, id);
953 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
955 if (pend & S3C64XX_UINTM_TXD_MSK) {
956 ret = s3c24xx_serial_tx_irq(irq, id);
957 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
962 /* interrupt handler for Apple SoC's.*/
963 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
965 const struct s3c24xx_uart_port *ourport = id;
966 const struct uart_port *port = &ourport->port;
967 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
968 irqreturn_t ret = IRQ_NONE;
970 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
971 wr_regl(port, S3C2410_UTRSTAT,
972 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
973 ret = s3c24xx_serial_rx_irq(irq, id);
975 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
976 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
977 ret = s3c24xx_serial_tx_irq(irq, id);
983 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
985 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
986 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
987 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
989 if (ufcon & S3C2410_UFCON_FIFOMODE) {
990 if ((ufstat & info->tx_fifomask) != 0 ||
991 (ufstat & info->tx_fifofull))
997 return s3c24xx_serial_txempty_nofifo(port);
1000 /* no modem control lines */
1001 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1003 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1005 if (umstat & S3C2410_UMSTAT_CTS)
1006 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1008 return TIOCM_CAR | TIOCM_DSR;
1011 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1015 if (mctrl & TIOCM_RTS)
1016 umcon |= S3C2410_UMCOM_RTS_LOW;
1018 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020 wr_regl(port, S3C2410_UMCON, umcon);
1023 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1025 unsigned long flags;
1028 spin_lock_irqsave(&port->lock, flags);
1030 ucon = rd_regl(port, S3C2410_UCON);
1033 ucon |= S3C2410_UCON_SBREAK;
1035 ucon &= ~S3C2410_UCON_SBREAK;
1037 wr_regl(port, S3C2410_UCON, ucon);
1039 spin_unlock_irqrestore(&port->lock, flags);
1042 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1044 struct s3c24xx_uart_dma *dma = p->dma;
1045 struct dma_slave_caps dma_caps;
1046 const char *reason = NULL;
1049 /* Default slave configuration parameters */
1050 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1051 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1052 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1053 dma->rx_conf.src_maxburst = 1;
1055 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1056 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1057 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1058 dma->tx_conf.dst_maxburst = 1;
1060 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1062 if (IS_ERR(dma->rx_chan)) {
1063 reason = "DMA RX channel request failed";
1064 ret = PTR_ERR(dma->rx_chan);
1068 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1070 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1071 reason = "insufficient DMA RX engine capabilities";
1073 goto err_release_rx;
1076 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1078 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1079 if (IS_ERR(dma->tx_chan)) {
1080 reason = "DMA TX channel request failed";
1081 ret = PTR_ERR(dma->tx_chan);
1082 goto err_release_rx;
1085 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1087 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1088 reason = "insufficient DMA TX engine capabilities";
1090 goto err_release_tx;
1093 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1096 dma->rx_size = PAGE_SIZE;
1098 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1101 goto err_release_tx;
1104 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1105 dma->rx_size, DMA_FROM_DEVICE);
1106 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1107 reason = "DMA mapping error for RX buffer";
1113 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1114 p->port.state->xmit.buf, UART_XMIT_SIZE,
1116 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1117 reason = "DMA mapping error for TX buffer";
1125 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1126 dma->rx_size, DMA_FROM_DEVICE);
1130 dma_release_channel(dma->tx_chan);
1132 dma_release_channel(dma->rx_chan);
1135 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1139 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1141 struct s3c24xx_uart_dma *dma = p->dma;
1144 dmaengine_terminate_all(dma->rx_chan);
1145 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1146 dma->rx_size, DMA_FROM_DEVICE);
1148 dma_release_channel(dma->rx_chan);
1149 dma->rx_chan = NULL;
1153 dmaengine_terminate_all(dma->tx_chan);
1154 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1155 UART_XMIT_SIZE, DMA_TO_DEVICE);
1156 dma_release_channel(dma->tx_chan);
1157 dma->tx_chan = NULL;
1161 static void s3c24xx_serial_shutdown(struct uart_port *port)
1163 struct s3c24xx_uart_port *ourport = to_ourport(port);
1165 if (ourport->tx_claimed) {
1166 free_irq(ourport->tx_irq, ourport);
1167 ourport->tx_enabled = 0;
1168 ourport->tx_claimed = 0;
1169 ourport->tx_mode = 0;
1172 if (ourport->rx_claimed) {
1173 free_irq(ourport->rx_irq, ourport);
1174 ourport->rx_claimed = 0;
1175 ourport->rx_enabled = 0;
1179 s3c24xx_serial_release_dma(ourport);
1181 ourport->tx_in_progress = 0;
1184 static void s3c64xx_serial_shutdown(struct uart_port *port)
1186 struct s3c24xx_uart_port *ourport = to_ourport(port);
1188 ourport->tx_enabled = 0;
1189 ourport->tx_mode = 0;
1190 ourport->rx_enabled = 0;
1192 free_irq(port->irq, ourport);
1194 wr_regl(port, S3C64XX_UINTP, 0xf);
1195 wr_regl(port, S3C64XX_UINTM, 0xf);
1198 s3c24xx_serial_release_dma(ourport);
1200 ourport->tx_in_progress = 0;
1203 static void apple_s5l_serial_shutdown(struct uart_port *port)
1205 struct s3c24xx_uart_port *ourport = to_ourport(port);
1209 ucon = rd_regl(port, S3C2410_UCON);
1210 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1211 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1212 APPLE_S5L_UCON_RXTO_ENA_MSK);
1213 wr_regl(port, S3C2410_UCON, ucon);
1215 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1217 free_irq(port->irq, ourport);
1219 ourport->tx_enabled = 0;
1220 ourport->tx_mode = 0;
1221 ourport->rx_enabled = 0;
1224 s3c24xx_serial_release_dma(ourport);
1226 ourport->tx_in_progress = 0;
1229 static int s3c24xx_serial_startup(struct uart_port *port)
1231 struct s3c24xx_uart_port *ourport = to_ourport(port);
1234 ourport->rx_enabled = 1;
1236 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1237 s3c24xx_serial_portname(port), ourport);
1240 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1244 ourport->rx_claimed = 1;
1246 dev_dbg(port->dev, "requesting tx irq...\n");
1248 ourport->tx_enabled = 1;
1250 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1251 s3c24xx_serial_portname(port), ourport);
1254 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1258 ourport->tx_claimed = 1;
1260 /* the port reset code should have done the correct
1261 * register setup for the port controls
1267 s3c24xx_serial_shutdown(port);
1271 static int s3c64xx_serial_startup(struct uart_port *port)
1273 struct s3c24xx_uart_port *ourport = to_ourport(port);
1274 unsigned long flags;
1278 wr_regl(port, S3C64XX_UINTM, 0xf);
1280 ret = s3c24xx_serial_request_dma(ourport);
1282 devm_kfree(port->dev, ourport->dma);
1283 ourport->dma = NULL;
1287 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1288 s3c24xx_serial_portname(port), ourport);
1290 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1294 /* For compatibility with s3c24xx Soc's */
1295 ourport->rx_enabled = 1;
1296 ourport->tx_enabled = 0;
1298 spin_lock_irqsave(&port->lock, flags);
1300 ufcon = rd_regl(port, S3C2410_UFCON);
1301 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1302 if (!uart_console(port))
1303 ufcon |= S3C2410_UFCON_RESETTX;
1304 wr_regl(port, S3C2410_UFCON, ufcon);
1306 enable_rx_pio(ourport);
1308 spin_unlock_irqrestore(&port->lock, flags);
1310 /* Enable Rx Interrupt */
1311 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1316 static int apple_s5l_serial_startup(struct uart_port *port)
1318 struct s3c24xx_uart_port *ourport = to_ourport(port);
1319 unsigned long flags;
1323 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1325 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1326 s3c24xx_serial_portname(port), ourport);
1328 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1332 /* For compatibility with s3c24xx Soc's */
1333 ourport->rx_enabled = 1;
1334 ourport->tx_enabled = 0;
1336 spin_lock_irqsave(&port->lock, flags);
1338 ufcon = rd_regl(port, S3C2410_UFCON);
1339 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1340 if (!uart_console(port))
1341 ufcon |= S3C2410_UFCON_RESETTX;
1342 wr_regl(port, S3C2410_UFCON, ufcon);
1344 enable_rx_pio(ourport);
1346 spin_unlock_irqrestore(&port->lock, flags);
1348 /* Enable Rx Interrupt */
1349 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1350 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1355 /* power power management control */
1357 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1360 struct s3c24xx_uart_port *ourport = to_ourport(port);
1361 int timeout = 10000;
1363 ourport->pm_level = level;
1367 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1370 if (!IS_ERR(ourport->baudclk))
1371 clk_disable_unprepare(ourport->baudclk);
1373 clk_disable_unprepare(ourport->clk);
1377 clk_prepare_enable(ourport->clk);
1379 if (!IS_ERR(ourport->baudclk))
1380 clk_prepare_enable(ourport->baudclk);
1383 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1387 /* baud rate calculation
1389 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1390 * of different sources, including the peripheral clock ("pclk") and an
1391 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1392 * with a programmable extra divisor.
1394 * The following code goes through the clock sources, and calculates the
1395 * baud clocks (and the resultant actual baud rates) and then tries to
1396 * pick the closest one and select that.
1400 #define MAX_CLK_NAME_LENGTH 15
1402 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1404 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1407 if (info->num_clks == 1)
1410 ucon = rd_regl(port, S3C2410_UCON);
1411 ucon &= info->clksel_mask;
1412 return ucon >> info->clksel_shift;
1415 static void s3c24xx_serial_setsource(struct uart_port *port,
1416 unsigned int clk_sel)
1418 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1421 if (info->num_clks == 1)
1424 ucon = rd_regl(port, S3C2410_UCON);
1425 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1428 ucon &= ~info->clksel_mask;
1429 ucon |= clk_sel << info->clksel_shift;
1430 wr_regl(port, S3C2410_UCON, ucon);
1433 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1434 unsigned int req_baud, struct clk **best_clk,
1435 unsigned int *clk_num)
1437 const struct s3c24xx_uart_info *info = ourport->info;
1440 unsigned int cnt, baud, quot, best_quot = 0;
1441 char clkname[MAX_CLK_NAME_LENGTH];
1442 int calc_deviation, deviation = (1 << 30) - 1;
1444 for (cnt = 0; cnt < info->num_clks; cnt++) {
1445 /* Keep selected clock if provided */
1446 if (ourport->cfg->clk_sel &&
1447 !(ourport->cfg->clk_sel & (1 << cnt)))
1450 sprintf(clkname, "clk_uart_baud%d", cnt);
1451 clk = clk_get(ourport->port.dev, clkname);
1455 rate = clk_get_rate(clk);
1459 if (ourport->info->has_divslot) {
1460 unsigned long div = rate / req_baud;
1462 /* The UDIVSLOT register on the newer UARTs allows us to
1463 * get a divisor adjustment of 1/16th on the baud clock.
1465 * We don't keep the UDIVSLOT value (the 16ths we
1466 * calculated by not multiplying the baud by 16) as it
1467 * is easy enough to recalculate.
1473 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1474 baud = rate / (quot * 16);
1478 calc_deviation = req_baud - baud;
1479 if (calc_deviation < 0)
1480 calc_deviation = -calc_deviation;
1482 if (calc_deviation < deviation) {
1486 deviation = calc_deviation;
1495 * This table takes the fractional value of the baud divisor and gives
1496 * the recommended setting for the UDIVSLOT register.
1498 static const u16 udivslot_table[16] = {
1517 static void s3c24xx_serial_set_termios(struct uart_port *port,
1518 struct ktermios *termios,
1519 struct ktermios *old)
1521 const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1522 struct s3c24xx_uart_port *ourport = to_ourport(port);
1523 struct clk *clk = ERR_PTR(-EINVAL);
1524 unsigned long flags;
1525 unsigned int baud, quot, clk_sel = 0;
1528 unsigned int udivslot = 0;
1531 * We don't support modem control lines.
1533 termios->c_cflag &= ~(HUPCL | CMSPAR);
1534 termios->c_cflag |= CLOCAL;
1537 * Ask the core to calculate the divisor for us.
1540 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1541 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1542 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1543 quot = port->custom_divisor;
1547 /* check to see if we need to change clock source */
1549 if (ourport->baudclk != clk) {
1550 clk_prepare_enable(clk);
1552 s3c24xx_serial_setsource(port, clk_sel);
1554 if (!IS_ERR(ourport->baudclk)) {
1555 clk_disable_unprepare(ourport->baudclk);
1556 ourport->baudclk = ERR_PTR(-EINVAL);
1559 ourport->baudclk = clk;
1560 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1563 if (ourport->info->has_divslot) {
1564 unsigned int div = ourport->baudclk_rate / baud;
1566 if (cfg->has_fracval) {
1567 udivslot = (div & 15);
1568 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1570 udivslot = udivslot_table[div & 15];
1571 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1572 udivslot, div & 15);
1576 switch (termios->c_cflag & CSIZE) {
1578 dev_dbg(port->dev, "config: 5bits/char\n");
1579 ulcon = S3C2410_LCON_CS5;
1582 dev_dbg(port->dev, "config: 6bits/char\n");
1583 ulcon = S3C2410_LCON_CS6;
1586 dev_dbg(port->dev, "config: 7bits/char\n");
1587 ulcon = S3C2410_LCON_CS7;
1591 dev_dbg(port->dev, "config: 8bits/char\n");
1592 ulcon = S3C2410_LCON_CS8;
1596 /* preserve original lcon IR settings */
1597 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1599 if (termios->c_cflag & CSTOPB)
1600 ulcon |= S3C2410_LCON_STOPB;
1602 if (termios->c_cflag & PARENB) {
1603 if (termios->c_cflag & PARODD)
1604 ulcon |= S3C2410_LCON_PODD;
1606 ulcon |= S3C2410_LCON_PEVEN;
1608 ulcon |= S3C2410_LCON_PNONE;
1611 spin_lock_irqsave(&port->lock, flags);
1614 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1615 ulcon, quot, udivslot);
1617 wr_regl(port, S3C2410_ULCON, ulcon);
1618 wr_regl(port, S3C2410_UBRDIV, quot);
1620 port->status &= ~UPSTAT_AUTOCTS;
1622 umcon = rd_regl(port, S3C2410_UMCON);
1623 if (termios->c_cflag & CRTSCTS) {
1624 umcon |= S3C2410_UMCOM_AFC;
1625 /* Disable RTS when RX FIFO contains 63 bytes */
1626 umcon &= ~S3C2412_UMCON_AFC_8;
1627 port->status = UPSTAT_AUTOCTS;
1629 umcon &= ~S3C2410_UMCOM_AFC;
1631 wr_regl(port, S3C2410_UMCON, umcon);
1633 if (ourport->info->has_divslot)
1634 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1637 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1638 rd_regl(port, S3C2410_ULCON),
1639 rd_regl(port, S3C2410_UCON),
1640 rd_regl(port, S3C2410_UFCON));
1643 * Update the per-port timeout.
1645 uart_update_timeout(port, termios->c_cflag, baud);
1648 * Which character status flags are we interested in?
1650 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1651 if (termios->c_iflag & INPCK)
1652 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1653 S3C2410_UERSTAT_PARITY;
1655 * Which character status flags should we ignore?
1657 port->ignore_status_mask = 0;
1658 if (termios->c_iflag & IGNPAR)
1659 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1660 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1661 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1664 * Ignore all characters if CREAD is not set.
1666 if ((termios->c_cflag & CREAD) == 0)
1667 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1669 spin_unlock_irqrestore(&port->lock, flags);
1672 static const char *s3c24xx_serial_type(struct uart_port *port)
1674 const struct s3c24xx_uart_port *ourport = to_ourport(port);
1676 switch (ourport->info->type) {
1680 return "S3C6400/10";
1681 case TYPE_APPLE_S5L:
1688 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1690 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1692 if (flags & UART_CONFIG_TYPE)
1693 port->type = info->port_type;
1697 * verify the new serial_struct (for TIOCSSERIAL).
1700 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1702 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1704 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1710 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1712 static struct console s3c24xx_serial_console;
1714 static void __init s3c24xx_serial_register_console(void)
1716 register_console(&s3c24xx_serial_console);
1719 static void s3c24xx_serial_unregister_console(void)
1721 if (s3c24xx_serial_console.flags & CON_ENABLED)
1722 unregister_console(&s3c24xx_serial_console);
1725 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1727 static inline void s3c24xx_serial_register_console(void) { }
1728 static inline void s3c24xx_serial_unregister_console(void) { }
1729 #define S3C24XX_SERIAL_CONSOLE NULL
1732 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1733 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1734 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1738 static const struct uart_ops s3c24xx_serial_ops = {
1739 .pm = s3c24xx_serial_pm,
1740 .tx_empty = s3c24xx_serial_tx_empty,
1741 .get_mctrl = s3c24xx_serial_get_mctrl,
1742 .set_mctrl = s3c24xx_serial_set_mctrl,
1743 .stop_tx = s3c24xx_serial_stop_tx,
1744 .start_tx = s3c24xx_serial_start_tx,
1745 .stop_rx = s3c24xx_serial_stop_rx,
1746 .break_ctl = s3c24xx_serial_break_ctl,
1747 .startup = s3c24xx_serial_startup,
1748 .shutdown = s3c24xx_serial_shutdown,
1749 .set_termios = s3c24xx_serial_set_termios,
1750 .type = s3c24xx_serial_type,
1751 .config_port = s3c24xx_serial_config_port,
1752 .verify_port = s3c24xx_serial_verify_port,
1753 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1754 .poll_get_char = s3c24xx_serial_get_poll_char,
1755 .poll_put_char = s3c24xx_serial_put_poll_char,
1759 static const struct uart_ops s3c64xx_serial_ops = {
1760 .pm = s3c24xx_serial_pm,
1761 .tx_empty = s3c24xx_serial_tx_empty,
1762 .get_mctrl = s3c24xx_serial_get_mctrl,
1763 .set_mctrl = s3c24xx_serial_set_mctrl,
1764 .stop_tx = s3c24xx_serial_stop_tx,
1765 .start_tx = s3c24xx_serial_start_tx,
1766 .stop_rx = s3c24xx_serial_stop_rx,
1767 .break_ctl = s3c24xx_serial_break_ctl,
1768 .startup = s3c64xx_serial_startup,
1769 .shutdown = s3c64xx_serial_shutdown,
1770 .set_termios = s3c24xx_serial_set_termios,
1771 .type = s3c24xx_serial_type,
1772 .config_port = s3c24xx_serial_config_port,
1773 .verify_port = s3c24xx_serial_verify_port,
1774 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1775 .poll_get_char = s3c24xx_serial_get_poll_char,
1776 .poll_put_char = s3c24xx_serial_put_poll_char,
1780 static const struct uart_ops apple_s5l_serial_ops = {
1781 .pm = s3c24xx_serial_pm,
1782 .tx_empty = s3c24xx_serial_tx_empty,
1783 .get_mctrl = s3c24xx_serial_get_mctrl,
1784 .set_mctrl = s3c24xx_serial_set_mctrl,
1785 .stop_tx = s3c24xx_serial_stop_tx,
1786 .start_tx = s3c24xx_serial_start_tx,
1787 .stop_rx = s3c24xx_serial_stop_rx,
1788 .break_ctl = s3c24xx_serial_break_ctl,
1789 .startup = apple_s5l_serial_startup,
1790 .shutdown = apple_s5l_serial_shutdown,
1791 .set_termios = s3c24xx_serial_set_termios,
1792 .type = s3c24xx_serial_type,
1793 .config_port = s3c24xx_serial_config_port,
1794 .verify_port = s3c24xx_serial_verify_port,
1795 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1796 .poll_get_char = s3c24xx_serial_get_poll_char,
1797 .poll_put_char = s3c24xx_serial_put_poll_char,
1801 static struct uart_driver s3c24xx_uart_drv = {
1802 .owner = THIS_MODULE,
1803 .driver_name = "s3c2410_serial",
1804 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1805 .cons = S3C24XX_SERIAL_CONSOLE,
1806 .dev_name = S3C24XX_SERIAL_NAME,
1807 .major = S3C24XX_SERIAL_MAJOR,
1808 .minor = S3C24XX_SERIAL_MINOR,
1811 #define __PORT_LOCK_UNLOCKED(i) \
1812 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1813 static struct s3c24xx_uart_port
1814 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1817 .lock = __PORT_LOCK_UNLOCKED(0),
1821 .ops = &s3c24xx_serial_ops,
1822 .flags = UPF_BOOT_AUTOCONF,
1828 .lock = __PORT_LOCK_UNLOCKED(1),
1832 .ops = &s3c24xx_serial_ops,
1833 .flags = UPF_BOOT_AUTOCONF,
1837 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1840 .lock = __PORT_LOCK_UNLOCKED(2),
1844 .ops = &s3c24xx_serial_ops,
1845 .flags = UPF_BOOT_AUTOCONF,
1850 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1853 .lock = __PORT_LOCK_UNLOCKED(3),
1857 .ops = &s3c24xx_serial_ops,
1858 .flags = UPF_BOOT_AUTOCONF,
1864 #undef __PORT_LOCK_UNLOCKED
1866 /* s3c24xx_serial_resetport
1868 * reset the fifos and other the settings.
1871 static void s3c24xx_serial_resetport(struct uart_port *port,
1872 const struct s3c2410_uartcfg *cfg)
1874 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1875 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1877 ucon &= (info->clksel_mask | info->ucon_mask);
1878 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1880 /* reset both fifos */
1881 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1882 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1884 /* some delay is required after fifo reset */
1888 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1890 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1891 unsigned long val, void *data)
1893 struct s3c24xx_uart_port *port;
1894 struct uart_port *uport;
1896 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1897 uport = &port->port;
1899 /* check to see if port is enabled */
1901 if (port->pm_level != 0)
1904 /* try and work out if the baudrate is changing, we can detect
1905 * a change in rate, but we do not have support for detecting
1906 * a disturbance in the clock-rate over the change.
1909 if (IS_ERR(port->baudclk))
1912 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1915 if (val == CPUFREQ_PRECHANGE) {
1916 /* we should really shut the port down whilst the
1917 * frequency change is in progress.
1920 } else if (val == CPUFREQ_POSTCHANGE) {
1921 struct ktermios *termios;
1922 struct tty_struct *tty;
1924 if (uport->state == NULL)
1927 tty = uport->state->port.tty;
1932 termios = &tty->termios;
1934 if (termios == NULL) {
1935 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1939 s3c24xx_serial_set_termios(uport, termios, NULL);
1947 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1949 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1951 return cpufreq_register_notifier(&port->freq_transition,
1952 CPUFREQ_TRANSITION_NOTIFIER);
1956 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1958 cpufreq_unregister_notifier(&port->freq_transition,
1959 CPUFREQ_TRANSITION_NOTIFIER);
1964 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1970 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1975 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1977 struct device *dev = ourport->port.dev;
1978 const struct s3c24xx_uart_info *info = ourport->info;
1979 char clk_name[MAX_CLK_NAME_LENGTH];
1980 unsigned int clk_sel;
1985 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1986 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1987 if (!(clk_sel & (1 << clk_num)))
1990 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1991 clk = clk_get(dev, clk_name);
1995 ret = clk_prepare_enable(clk);
2001 ourport->baudclk = clk;
2002 ourport->baudclk_rate = clk_get_rate(clk);
2003 s3c24xx_serial_setsource(&ourport->port, clk_num);
2011 /* s3c24xx_serial_init_port
2013 * initialise a single serial port from the platform device given
2016 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
2017 struct platform_device *platdev)
2019 struct uart_port *port = &ourport->port;
2020 const struct s3c2410_uartcfg *cfg = ourport->cfg;
2021 struct resource *res;
2024 if (platdev == NULL)
2027 if (port->mapbase != 0)
2030 /* setup info for port */
2031 port->dev = &platdev->dev;
2035 if (cfg->uart_flags & UPF_CONS_FLOW) {
2036 dev_dbg(port->dev, "enabling flow control\n");
2037 port->flags |= UPF_CONS_FLOW;
2040 /* sort our the physical and virtual addresses for each UART */
2042 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2044 dev_err(port->dev, "failed to find memory resource for uart\n");
2048 dev_dbg(port->dev, "resource %pR)\n", res);
2050 port->membase = devm_ioremap_resource(port->dev, res);
2051 if (IS_ERR(port->membase)) {
2052 dev_err(port->dev, "failed to remap controller address\n");
2056 port->mapbase = res->start;
2057 ret = platform_get_irq(platdev, 0);
2062 ourport->rx_irq = ret;
2063 ourport->tx_irq = ret + 1;
2066 switch (ourport->info->type) {
2068 ret = platform_get_irq(platdev, 1);
2070 ourport->tx_irq = ret;
2077 * DMA is currently supported only on DT platforms, if DMA properties
2080 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2082 ourport->dma = devm_kzalloc(port->dev,
2083 sizeof(*ourport->dma),
2085 if (!ourport->dma) {
2091 ourport->clk = clk_get(&platdev->dev, "uart");
2092 if (IS_ERR(ourport->clk)) {
2093 pr_err("%s: Controller clock not found\n",
2094 dev_name(&platdev->dev));
2095 ret = PTR_ERR(ourport->clk);
2099 ret = clk_prepare_enable(ourport->clk);
2101 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2102 clk_put(ourport->clk);
2106 ret = s3c24xx_serial_enable_baudclk(ourport);
2108 pr_warn("uart: failed to enable baudclk\n");
2110 /* Keep all interrupts masked and cleared */
2111 switch (ourport->info->type) {
2113 wr_regl(port, S3C64XX_UINTM, 0xf);
2114 wr_regl(port, S3C64XX_UINTP, 0xf);
2115 wr_regl(port, S3C64XX_UINTSP, 0xf);
2117 case TYPE_APPLE_S5L: {
2120 ucon = rd_regl(port, S3C2410_UCON);
2121 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2122 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2123 APPLE_S5L_UCON_RXTO_ENA_MSK);
2124 wr_regl(port, S3C2410_UCON, ucon);
2126 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2133 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2134 &port->mapbase, port->membase, port->irq,
2135 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2137 /* reset the fifos (and setup the uart) */
2138 s3c24xx_serial_resetport(port, cfg);
2147 /* Device driver serial port probe */
2149 static int probe_index;
2151 static inline const struct s3c24xx_serial_drv_data *
2152 s3c24xx_get_driver_data(struct platform_device *pdev)
2154 if (dev_of_node(&pdev->dev))
2155 return of_device_get_match_data(&pdev->dev);
2157 return (struct s3c24xx_serial_drv_data *)
2158 platform_get_device_id(pdev)->driver_data;
2161 static int s3c24xx_serial_probe(struct platform_device *pdev)
2163 struct device_node *np = pdev->dev.of_node;
2164 struct s3c24xx_uart_port *ourport;
2165 int index = probe_index;
2169 ret = of_alias_get_id(np, "serial");
2174 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2175 dev_err(&pdev->dev, "serial%d out of range\n", index);
2178 ourport = &s3c24xx_serial_ports[index];
2180 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2181 if (!ourport->drv_data) {
2182 dev_err(&pdev->dev, "could not find driver data\n");
2186 ourport->baudclk = ERR_PTR(-EINVAL);
2187 ourport->info = &ourport->drv_data->info;
2188 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2189 dev_get_platdata(&pdev->dev) :
2190 &ourport->drv_data->def_cfg;
2192 switch (ourport->info->type) {
2194 ourport->port.ops = &s3c24xx_serial_ops;
2197 ourport->port.ops = &s3c64xx_serial_ops;
2199 case TYPE_APPLE_S5L:
2200 ourport->port.ops = &apple_s5l_serial_ops;
2205 of_property_read_u32(np,
2206 "samsung,uart-fifosize", &ourport->port.fifosize);
2208 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2211 ourport->port.iotype = UPIO_MEM;
2214 ourport->port.iotype = UPIO_MEM32;
2217 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2224 if (ourport->drv_data->fifosize[index])
2225 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2226 else if (ourport->info->fifosize)
2227 ourport->port.fifosize = ourport->info->fifosize;
2228 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2231 * DMA transfers must be aligned at least to cache line size,
2232 * so find minimal transfer size suitable for DMA mode
2234 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2235 dma_get_cache_alignment());
2237 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2239 ret = s3c24xx_serial_init_port(ourport, pdev);
2243 if (!s3c24xx_uart_drv.state) {
2244 ret = uart_register_driver(&s3c24xx_uart_drv);
2246 pr_err("Failed to register Samsung UART driver\n");
2251 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2252 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2253 platform_set_drvdata(pdev, &ourport->port);
2256 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2257 * so that a potential re-enablement through the pm-callback overlaps
2258 * and keeps the clock enabled in this case.
2260 clk_disable_unprepare(ourport->clk);
2261 if (!IS_ERR(ourport->baudclk))
2262 clk_disable_unprepare(ourport->baudclk);
2264 ret = s3c24xx_serial_cpufreq_register(ourport);
2266 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2273 static int s3c24xx_serial_remove(struct platform_device *dev)
2275 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2278 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2279 uart_remove_one_port(&s3c24xx_uart_drv, port);
2282 uart_unregister_driver(&s3c24xx_uart_drv);
2287 /* UART power management code */
2288 #ifdef CONFIG_PM_SLEEP
2289 static int s3c24xx_serial_suspend(struct device *dev)
2291 struct uart_port *port = s3c24xx_dev_to_port(dev);
2294 uart_suspend_port(&s3c24xx_uart_drv, port);
2299 static int s3c24xx_serial_resume(struct device *dev)
2301 struct uart_port *port = s3c24xx_dev_to_port(dev);
2302 struct s3c24xx_uart_port *ourport = to_ourport(port);
2305 clk_prepare_enable(ourport->clk);
2306 if (!IS_ERR(ourport->baudclk))
2307 clk_prepare_enable(ourport->baudclk);
2308 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2309 if (!IS_ERR(ourport->baudclk))
2310 clk_disable_unprepare(ourport->baudclk);
2311 clk_disable_unprepare(ourport->clk);
2313 uart_resume_port(&s3c24xx_uart_drv, port);
2319 static int s3c24xx_serial_resume_noirq(struct device *dev)
2321 struct uart_port *port = s3c24xx_dev_to_port(dev);
2322 struct s3c24xx_uart_port *ourport = to_ourport(port);
2325 /* restore IRQ mask */
2326 switch (ourport->info->type) {
2327 case TYPE_S3C6400: {
2328 unsigned int uintm = 0xf;
2330 if (ourport->tx_enabled)
2331 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2332 if (ourport->rx_enabled)
2333 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2334 clk_prepare_enable(ourport->clk);
2335 if (!IS_ERR(ourport->baudclk))
2336 clk_prepare_enable(ourport->baudclk);
2337 wr_regl(port, S3C64XX_UINTM, uintm);
2338 if (!IS_ERR(ourport->baudclk))
2339 clk_disable_unprepare(ourport->baudclk);
2340 clk_disable_unprepare(ourport->clk);
2343 case TYPE_APPLE_S5L: {
2347 ret = clk_prepare_enable(ourport->clk);
2349 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2352 if (!IS_ERR(ourport->baudclk)) {
2353 ret = clk_prepare_enable(ourport->baudclk);
2355 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2356 clk_disable_unprepare(ourport->clk);
2361 ucon = rd_regl(port, S3C2410_UCON);
2363 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2364 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2365 APPLE_S5L_UCON_RXTO_ENA_MSK);
2367 if (ourport->tx_enabled)
2368 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2369 if (ourport->rx_enabled)
2370 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2371 APPLE_S5L_UCON_RXTO_ENA_MSK;
2373 wr_regl(port, S3C2410_UCON, ucon);
2375 if (!IS_ERR(ourport->baudclk))
2376 clk_disable_unprepare(ourport->baudclk);
2377 clk_disable_unprepare(ourport->clk);
2388 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2389 .suspend = s3c24xx_serial_suspend,
2390 .resume = s3c24xx_serial_resume,
2391 .resume_noirq = s3c24xx_serial_resume_noirq,
2393 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2395 #else /* !CONFIG_PM_SLEEP */
2397 #define SERIAL_SAMSUNG_PM_OPS NULL
2398 #endif /* CONFIG_PM_SLEEP */
2402 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2404 static struct uart_port *cons_uart;
2407 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2409 const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2410 unsigned long ufstat, utrstat;
2412 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2413 /* fifo mode - check amount of data in fifo registers... */
2415 ufstat = rd_regl(port, S3C2410_UFSTAT);
2416 return (ufstat & info->tx_fifofull) ? 0 : 1;
2419 /* in non-fifo mode, we go and use the tx buffer empty */
2421 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2422 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2426 s3c24xx_port_configured(unsigned int ucon)
2428 /* consider the serial port configured if the tx/rx mode set */
2429 return (ucon & 0xf) != 0;
2432 #ifdef CONFIG_CONSOLE_POLL
2434 * Console polling routines for writing and reading from the uart while
2435 * in an interrupt or debug context.
2438 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2440 const struct s3c24xx_uart_port *ourport = to_ourport(port);
2441 unsigned int ufstat;
2443 ufstat = rd_regl(port, S3C2410_UFSTAT);
2444 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2445 return NO_POLL_CHAR;
2447 return rd_reg(port, S3C2410_URXH);
2450 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2453 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2454 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2456 /* not possible to xmit on unconfigured port */
2457 if (!s3c24xx_port_configured(ucon))
2460 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2462 wr_reg(port, S3C2410_UTXH, c);
2465 #endif /* CONFIG_CONSOLE_POLL */
2468 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2470 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2472 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2474 wr_reg(port, S3C2410_UTXH, ch);
2478 s3c24xx_serial_console_write(struct console *co, const char *s,
2481 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2482 unsigned long flags;
2485 /* not possible to xmit on unconfigured port */
2486 if (!s3c24xx_port_configured(ucon))
2489 if (cons_uart->sysrq)
2491 else if (oops_in_progress)
2492 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2494 spin_lock_irqsave(&cons_uart->lock, flags);
2496 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2499 spin_unlock_irqrestore(&cons_uart->lock, flags);
2502 /* Shouldn't be __init, as it can be instantiated from other module */
2504 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2505 int *parity, int *bits)
2510 unsigned int ubrdiv;
2512 unsigned int clk_sel;
2513 char clk_name[MAX_CLK_NAME_LENGTH];
2515 ulcon = rd_regl(port, S3C2410_ULCON);
2516 ucon = rd_regl(port, S3C2410_UCON);
2517 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2519 if (s3c24xx_port_configured(ucon)) {
2520 switch (ulcon & S3C2410_LCON_CSMASK) {
2521 case S3C2410_LCON_CS5:
2524 case S3C2410_LCON_CS6:
2527 case S3C2410_LCON_CS7:
2530 case S3C2410_LCON_CS8:
2536 switch (ulcon & S3C2410_LCON_PMASK) {
2537 case S3C2410_LCON_PEVEN:
2541 case S3C2410_LCON_PODD:
2545 case S3C2410_LCON_PNONE:
2550 /* now calculate the baud rate */
2552 clk_sel = s3c24xx_serial_getsource(port);
2553 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2555 clk = clk_get(port->dev, clk_name);
2557 rate = clk_get_rate(clk);
2561 *baud = rate / (16 * (ubrdiv + 1));
2562 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2566 /* Shouldn't be __init, as it can be instantiated from other module */
2568 s3c24xx_serial_console_setup(struct console *co, char *options)
2570 struct uart_port *port;
2576 /* is this a valid port */
2578 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2581 port = &s3c24xx_serial_ports[co->index].port;
2583 /* is the port configured? */
2585 if (port->mapbase == 0x0)
2591 * Check whether an invalid uart number has been specified, and
2592 * if so, search for the first available port that does have
2596 uart_parse_options(options, &baud, &parity, &bits, &flow);
2598 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2600 dev_dbg(port->dev, "baud %d\n", baud);
2602 return uart_set_options(port, co, baud, parity, bits, flow);
2605 static struct console s3c24xx_serial_console = {
2606 .name = S3C24XX_SERIAL_NAME,
2607 .device = uart_console_device,
2608 .flags = CON_PRINTBUFFER,
2610 .write = s3c24xx_serial_console_write,
2611 .setup = s3c24xx_serial_console_setup,
2612 .data = &s3c24xx_uart_drv,
2614 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2616 #ifdef CONFIG_CPU_S3C2410
2617 static const struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2619 .name = "Samsung S3C2410 UART",
2620 .type = TYPE_S3C24XX,
2621 .port_type = PORT_S3C2410,
2623 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2624 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2625 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2626 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2627 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2628 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2629 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2631 .clksel_mask = S3C2410_UCON_CLKMASK,
2632 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2635 .ucon = S3C2410_UCON_DEFAULT,
2636 .ufcon = S3C2410_UFCON_DEFAULT,
2639 #define S3C2410_SERIAL_DRV_DATA (&s3c2410_serial_drv_data)
2641 #define S3C2410_SERIAL_DRV_DATA NULL
2644 #ifdef CONFIG_CPU_S3C2412
2645 static const struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2647 .name = "Samsung S3C2412 UART",
2648 .type = TYPE_S3C24XX,
2649 .port_type = PORT_S3C2412,
2652 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2653 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2654 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2655 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2656 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2657 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2658 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2660 .clksel_mask = S3C2412_UCON_CLKMASK,
2661 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2664 .ucon = S3C2410_UCON_DEFAULT,
2665 .ufcon = S3C2410_UFCON_DEFAULT,
2668 #define S3C2412_SERIAL_DRV_DATA (&s3c2412_serial_drv_data)
2670 #define S3C2412_SERIAL_DRV_DATA NULL
2673 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2674 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2675 static const struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2677 .name = "Samsung S3C2440 UART",
2678 .type = TYPE_S3C24XX,
2679 .port_type = PORT_S3C2440,
2682 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2683 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2684 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2685 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2686 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2687 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2688 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2690 .clksel_mask = S3C2412_UCON_CLKMASK,
2691 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2692 .ucon_mask = S3C2440_UCON0_DIVMASK,
2695 .ucon = S3C2410_UCON_DEFAULT,
2696 .ufcon = S3C2410_UFCON_DEFAULT,
2699 #define S3C2440_SERIAL_DRV_DATA (&s3c2440_serial_drv_data)
2701 #define S3C2440_SERIAL_DRV_DATA NULL
2704 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2705 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2707 .name = "Samsung S3C6400 UART",
2708 .type = TYPE_S3C6400,
2709 .port_type = PORT_S3C6400,
2712 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2713 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2714 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2715 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2716 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2717 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2718 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2720 .clksel_mask = S3C6400_UCON_CLKMASK,
2721 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2724 .ucon = S3C2410_UCON_DEFAULT,
2725 .ufcon = S3C2410_UFCON_DEFAULT,
2728 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2730 #define S3C6400_SERIAL_DRV_DATA NULL
2733 #ifdef CONFIG_CPU_S5PV210
2734 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2736 .name = "Samsung S5PV210 UART",
2737 .type = TYPE_S3C6400,
2738 .port_type = PORT_S3C6400,
2740 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2741 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2742 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2743 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2744 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2745 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2746 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2748 .clksel_mask = S5PV210_UCON_CLKMASK,
2749 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2752 .ucon = S5PV210_UCON_DEFAULT,
2753 .ufcon = S5PV210_UFCON_DEFAULT,
2755 .fifosize = { 256, 64, 16, 16 },
2757 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2759 #define S5PV210_SERIAL_DRV_DATA NULL
2762 #if defined(CONFIG_ARCH_EXYNOS)
2763 #define EXYNOS_COMMON_SERIAL_DRV_DATA() \
2765 .name = "Samsung Exynos UART", \
2766 .type = TYPE_S3C6400, \
2767 .port_type = PORT_S3C6400, \
2769 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2770 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2771 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2772 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2773 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2774 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2775 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2778 .clksel_shift = 0, \
2781 .ucon = S5PV210_UCON_DEFAULT, \
2782 .ufcon = S5PV210_UFCON_DEFAULT, \
2786 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2787 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2788 .fifosize = { 256, 64, 16, 16 },
2791 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2792 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2793 .fifosize = { 64, 256, 16, 256 },
2796 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2797 EXYNOS_COMMON_SERIAL_DRV_DATA(),
2798 .fifosize = { 256, 64, 64, 64 },
2801 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2802 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2803 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2806 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2807 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2808 #define EXYNOS850_SERIAL_DRV_DATA NULL
2811 #ifdef CONFIG_ARCH_APPLE
2812 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2814 .name = "Apple S5L UART",
2815 .type = TYPE_APPLE_S5L,
2816 .port_type = PORT_8250,
2818 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2819 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2820 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2821 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2822 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2823 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2824 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2828 .ucon_mask = APPLE_S5L_UCON_MASK,
2831 .ucon = APPLE_S5L_UCON_DEFAULT,
2832 .ufcon = S3C2410_UFCON_DEFAULT,
2835 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2837 #define S5L_SERIAL_DRV_DATA NULL
2840 #if defined(CONFIG_ARCH_ARTPEC)
2841 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2843 .name = "Axis ARTPEC-8 UART",
2844 .type = TYPE_S3C6400,
2845 .port_type = PORT_S3C6400,
2848 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2849 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2850 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2851 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2852 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2853 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2854 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2860 .ucon = S5PV210_UCON_DEFAULT,
2861 .ufcon = S5PV210_UFCON_DEFAULT,
2865 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2867 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2870 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2872 .name = "s3c2410-uart",
2873 .driver_data = (kernel_ulong_t)S3C2410_SERIAL_DRV_DATA,
2875 .name = "s3c2412-uart",
2876 .driver_data = (kernel_ulong_t)S3C2412_SERIAL_DRV_DATA,
2878 .name = "s3c2440-uart",
2879 .driver_data = (kernel_ulong_t)S3C2440_SERIAL_DRV_DATA,
2881 .name = "s3c6400-uart",
2882 .driver_data = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2884 .name = "s5pv210-uart",
2885 .driver_data = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2887 .name = "exynos4210-uart",
2888 .driver_data = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2890 .name = "exynos5433-uart",
2891 .driver_data = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2894 .driver_data = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2896 .name = "exynos850-uart",
2897 .driver_data = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2899 .name = "artpec8-uart",
2900 .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2904 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2907 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2908 { .compatible = "samsung,s3c2410-uart",
2909 .data = S3C2410_SERIAL_DRV_DATA },
2910 { .compatible = "samsung,s3c2412-uart",
2911 .data = S3C2412_SERIAL_DRV_DATA },
2912 { .compatible = "samsung,s3c2440-uart",
2913 .data = S3C2440_SERIAL_DRV_DATA },
2914 { .compatible = "samsung,s3c6400-uart",
2915 .data = S3C6400_SERIAL_DRV_DATA },
2916 { .compatible = "samsung,s5pv210-uart",
2917 .data = S5PV210_SERIAL_DRV_DATA },
2918 { .compatible = "samsung,exynos4210-uart",
2919 .data = EXYNOS4210_SERIAL_DRV_DATA },
2920 { .compatible = "samsung,exynos5433-uart",
2921 .data = EXYNOS5433_SERIAL_DRV_DATA },
2922 { .compatible = "apple,s5l-uart",
2923 .data = S5L_SERIAL_DRV_DATA },
2924 { .compatible = "samsung,exynos850-uart",
2925 .data = EXYNOS850_SERIAL_DRV_DATA },
2926 { .compatible = "axis,artpec8-uart",
2927 .data = ARTPEC8_SERIAL_DRV_DATA },
2930 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2933 static struct platform_driver samsung_serial_driver = {
2934 .probe = s3c24xx_serial_probe,
2935 .remove = s3c24xx_serial_remove,
2936 .id_table = s3c24xx_serial_driver_ids,
2938 .name = "samsung-uart",
2939 .pm = SERIAL_SAMSUNG_PM_OPS,
2940 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2944 static int __init samsung_serial_init(void)
2948 s3c24xx_serial_register_console();
2950 ret = platform_driver_register(&samsung_serial_driver);
2952 s3c24xx_serial_unregister_console();
2959 static void __exit samsung_serial_exit(void)
2961 platform_driver_unregister(&samsung_serial_driver);
2962 s3c24xx_serial_unregister_console();
2965 module_init(samsung_serial_init);
2966 module_exit(samsung_serial_exit);
2968 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2973 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2975 switch (port->iotype) {
2977 writeb(val, portaddr(port, reg));
2980 writel(val, portaddr(port, reg));
2985 struct samsung_early_console_data {
2990 static void samsung_early_busyuart(const struct uart_port *port)
2992 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2996 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2998 const struct samsung_early_console_data *data = port->private_data;
3000 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
3004 static void samsung_early_putc(struct uart_port *port, unsigned char c)
3006 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
3007 samsung_early_busyuart_fifo(port);
3009 samsung_early_busyuart(port);
3011 wr_reg_barrier(port, S3C2410_UTXH, c);
3014 static void samsung_early_write(struct console *con, const char *s,
3017 struct earlycon_device *dev = con->data;
3019 uart_console_write(&dev->port, s, n, samsung_early_putc);
3022 static int samsung_early_read(struct console *con, char *s, unsigned int n)
3024 struct earlycon_device *dev = con->data;
3025 const struct samsung_early_console_data *data = dev->port.private_data;
3026 int ch, ufstat, num_read = 0;
3028 while (num_read < n) {
3029 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
3030 if (!(ufstat & data->rxfifo_mask))
3032 ch = rd_reg(&dev->port, S3C2410_URXH);
3033 if (ch == NO_POLL_CHAR)
3042 static int __init samsung_early_console_setup(struct earlycon_device *device,
3045 if (!device->port.membase)
3048 device->con->write = samsung_early_write;
3049 device->con->read = samsung_early_read;
3054 static struct samsung_early_console_data s3c2410_early_console_data = {
3055 .txfull_mask = S3C2410_UFSTAT_TXFULL,
3056 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
3059 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
3062 device->port.private_data = &s3c2410_early_console_data;
3063 return samsung_early_console_setup(device, opt);
3066 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
3067 s3c2410_early_console_setup);
3069 /* S3C2412, S3C2440, S3C64xx */
3070 static struct samsung_early_console_data s3c2440_early_console_data = {
3071 .txfull_mask = S3C2440_UFSTAT_TXFULL,
3072 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
3075 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
3078 device->port.private_data = &s3c2440_early_console_data;
3079 return samsung_early_console_setup(device, opt);
3082 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
3083 s3c2440_early_console_setup);
3084 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
3085 s3c2440_early_console_setup);
3086 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
3087 s3c2440_early_console_setup);
3089 /* S5PV210, Exynos */
3090 static struct samsung_early_console_data s5pv210_early_console_data = {
3091 .txfull_mask = S5PV210_UFSTAT_TXFULL,
3092 .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
3095 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
3098 device->port.private_data = &s5pv210_early_console_data;
3099 return samsung_early_console_setup(device, opt);
3102 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
3103 s5pv210_early_console_setup);
3104 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
3105 s5pv210_early_console_setup);
3106 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
3107 s5pv210_early_console_setup);
3110 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3113 /* Close enough to S3C2410 for earlycon... */
3114 device->port.private_data = &s3c2410_early_console_data;
3117 /* ... but we need to override the existing fixmap entry as nGnRnE */
3118 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3119 __pgprot(PROT_DEVICE_nGnRnE));
3121 return samsung_early_console_setup(device, opt);
3124 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3127 MODULE_ALIAS("platform:samsung-uart");
3128 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3129 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3130 MODULE_LICENSE("GPL v2");