drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/console.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/qcom-geni-se.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/slab.h>
  16 #include <linux/tty.h>
  17 #include <linux/tty_flip.h>
  18
  19 /* UART specific GENI registers */
  20 #define SE_UART_TX_TRANS_CFG            0x25c
  21 #define SE_UART_TX_WORD_LEN             0x268
  22 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  23 #define SE_UART_TX_TRANS_LEN            0x270
  24 #define SE_UART_RX_TRANS_CFG            0x280
  25 #define SE_UART_RX_WORD_LEN             0x28c
  26 #define SE_UART_RX_STALE_CNT            0x294
  27 #define SE_UART_TX_PARITY_CFG           0x2a4
  28 #define SE_UART_RX_PARITY_CFG           0x2a8
  29
  30 /* SE_UART_TRANS_CFG */
  31 #define UART_TX_PAR_EN          BIT(0)
  32 #define UART_CTS_MASK           BIT(1)
  33
  34 /* SE_UART_TX_WORD_LEN */
  35 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  36
  37 /* SE_UART_TX_STOP_BIT_LEN */
  38 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  39 #define TX_STOP_BIT_LEN_1       0
  40 #define TX_STOP_BIT_LEN_1_5     1
  41 #define TX_STOP_BIT_LEN_2       2
  42
  43 /* SE_UART_TX_TRANS_LEN */
  44 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  45
  46 /* SE_UART_RX_TRANS_CFG */
  47 #define UART_RX_INS_STATUS_BIT  BIT(2)
  48 #define UART_RX_PAR_EN          BIT(3)
  49
  50 /* SE_UART_RX_WORD_LEN */
  51 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  52
  53 /* SE_UART_RX_STALE_CNT */
  54 #define RX_STALE_CNT            GENMASK(23, 0)
  55
  56 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  57 #define PAR_CALC_EN             BIT(0)
  58 #define PAR_MODE_MSK            GENMASK(2, 1)
  59 #define PAR_MODE_SHFT           1
  60 #define PAR_EVEN                0x00
  61 #define PAR_ODD                 0x01
  62 #define PAR_SPACE               0x10
  63 #define PAR_MARK                0x11
  64
  65 /* UART M_CMD OP codes */
  66 #define UART_START_TX           0x1
  67 #define UART_START_BREAK        0x4
  68 #define UART_STOP_BREAK         0x5
  69 /* UART S_CMD OP codes */
  70 #define UART_START_READ         0x1
  71 #define UART_PARAM              0x1
  72
  73 #define UART_OVERSAMPLING       32
  74 #define STALE_TIMEOUT           16
  75 #define DEFAULT_BITS_PER_CHAR   10
  76 #define GENI_UART_CONS_PORTS    1
  77 #define DEF_FIFO_DEPTH_WORDS    16
  78 #define DEF_TX_WM               2
  79 #define DEF_FIFO_WIDTH_BITS     32
  80 #define UART_CONSOLE_RX_WM      2
  81
  82 #ifdef CONFIG_CONSOLE_POLL
  83 #define RX_BYTES_PW 1
  84 #else
  85 #define RX_BYTES_PW 4
  86 #endif
  87
  88 struct qcom_geni_serial_port {
  89         struct uart_port uport;
  90         struct geni_se se;
  91         char name[20];
  92         u32 tx_fifo_depth;
  93         u32 tx_fifo_width;
  94         u32 rx_fifo_depth;
  95         u32 tx_wm;
  96         u32 rx_wm;
  97         u32 rx_rfr;
  98         enum geni_se_xfer_mode xfer_mode;
  99         bool setup;
 100         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 101         unsigned int xmit_size;
 102         unsigned int baud;
 103         unsigned int tx_bytes_pw;
 104         unsigned int rx_bytes_pw;
 105         bool brk;
 106 };
 107
 108 static const struct uart_ops qcom_geni_console_pops;
 109 static struct uart_driver qcom_geni_console_driver;
 110 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 111 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 112 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 113
 114 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 115                                         32000000, 48000000, 64000000, 80000000,
 116                                         96000000, 100000000};
 117
 118 #define to_dev_port(ptr, member) \
 119                 container_of(ptr, struct qcom_geni_serial_port, member)
 120
 121 static struct qcom_geni_serial_port qcom_geni_console_port = {
 122         .uport = {
 123                 .iotype = UPIO_MEM,
 124                 .ops = &qcom_geni_console_pops,
 125                 .flags = UPF_BOOT_AUTOCONF,
 126                 .line = 0,
 127         },
 128 };
 129
 130 static int qcom_geni_serial_request_port(struct uart_port *uport)
 131 {
 132         struct platform_device *pdev = to_platform_device(uport->dev);
 133         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 134         struct resource *res;
 135
 136         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 137         uport->membase = devm_ioremap_resource(&pdev->dev, res);
 138         if (IS_ERR(uport->membase))
 139                 return PTR_ERR(uport->membase);
 140         port->se.base = uport->membase;
 141         return 0;
 142 }
 143
 144 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 145 {
 146         if (cfg_flags & UART_CONFIG_TYPE) {
 147                 uport->type = PORT_MSM;
 148                 qcom_geni_serial_request_port(uport);
 149         }
 150 }
 151
 152 static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
 153 {
 154         return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
 155 }
 156
 157 static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
 158                                                         unsigned int mctrl)
 159 {
 160 }
 161
 162 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 163 {
 164         return "MSM";
 165 }
 166
 167 static struct qcom_geni_serial_port *get_port_from_line(int line)
 168 {
 169         if (line < 0 || line >= GENI_UART_CONS_PORTS)
 170                 return ERR_PTR(-ENXIO);
 171         return &qcom_geni_console_port;
 172 }
 173
 174 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 175                                 int offset, int field, bool set)
 176 {
 177         u32 reg;
 178         struct qcom_geni_serial_port *port;
 179         unsigned int baud;
 180         unsigned int fifo_bits;
 181         unsigned long timeout_us = 20000;
 182
 183         /* Ensure polling is not re-ordered before the prior writes/reads */
 184         mb();
 185
 186         if (uport->private_data) {
 187                 port = to_dev_port(uport, uport);
 188                 baud = port->baud;
 189                 if (!baud)
 190                         baud = 115200;
 191                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 192                 /*
 193                  * Total polling iterations based on FIFO worth of bytes to be
 194                  * sent at current baud. Add a little fluff to the wait.
 195                  */
 196                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 197         }
 198
 199         return !readl_poll_timeout_atomic(uport->membase + offset, reg,
 200                          (bool)(reg & field) == set, 10, timeout_us);
 201 }
 202
 203 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 204 {
 205         u32 m_cmd;
 206
 207         writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 208         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 209         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 210 }
 211
 212 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 213 {
 214         int done;
 215         u32 irq_clear = M_CMD_DONE_EN;
 216
 217         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 218                                                 M_CMD_DONE_EN, true);
 219         if (!done) {
 220                 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
 221                                                 SE_GENI_M_CMD_CTRL_REG);
 222                 irq_clear |= M_CMD_ABORT_EN;
 223                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 224                                                         M_CMD_ABORT_EN, true);
 225         }
 226         writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 227 }
 228
 229 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 230 {
 231         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 232
 233         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 234         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 235                                         S_GENI_CMD_ABORT, false);
 236         writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 237         writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 238 }
 239
 240 #ifdef CONFIG_CONSOLE_POLL
 241 static int qcom_geni_serial_get_char(struct uart_port *uport)
 242 {
 243         u32 rx_fifo;
 244         u32 status;
 245
 246         status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
 247         writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 248
 249         status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
 250         writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 251
 252         /*
 253          * Ensure the writes to clear interrupts is not re-ordered after
 254          * reading the data.
 255          */
 256         mb();
 257
 258         status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
 259         if (!(status & RX_FIFO_WC_MSK))
 260                 return NO_POLL_CHAR;
 261
 262         rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
 263         return rx_fifo & 0xff;
 264 }
 265
 266 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 267                                                         unsigned char c)
 268 {
 269         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 270
 271         writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
 272         qcom_geni_serial_setup_tx(uport, 1);
 273         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 274                                                 M_TX_FIFO_WATERMARK_EN, true));
 275         writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
 276         writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
 277                                                         SE_GENI_M_IRQ_CLEAR);
 278         qcom_geni_serial_poll_tx_done(uport);
 279 }
 280 #endif
 281
 282 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 283 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 284 {
 285         writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
 286 }
 287
 288 static void
 289 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 290                                  unsigned int count)
 291 {
 292         int i;
 293         u32 bytes_to_send = count;
 294
 295         for (i = 0; i < count; i++) {
 296                 /*
 297                  * uart_console_write() adds a carriage return for each newline.
 298                  * Account for additional bytes to be written.
 299                  */
 300                 if (s[i] == '\n')
 301                         bytes_to_send++;
 302         }
 303
 304         writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 305         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 306         for (i = 0; i < count; ) {
 307                 size_t chars_to_write = 0;
 308                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 309
 310                 /*
 311                  * If the WM bit never set, then the Tx state machine is not
 312                  * in a valid state, so break, cancel/abort any existing
 313                  * command. Unfortunately the current data being written is
 314                  * lost.
 315                  */
 316                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 317                                                 M_TX_FIFO_WATERMARK_EN, true))
 318                         break;
 319                 chars_to_write = min_t(size_t, count - i, avail / 2);
 320                 uart_console_write(uport, s + i, chars_to_write,
 321                                                 qcom_geni_serial_wr_char);
 322                 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
 323                                                         SE_GENI_M_IRQ_CLEAR);
 324                 i += chars_to_write;
 325         }
 326         qcom_geni_serial_poll_tx_done(uport);
 327 }
 328
 329 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 330                               unsigned int count)
 331 {
 332         struct uart_port *uport;
 333         struct qcom_geni_serial_port *port;
 334         bool locked = true;
 335         unsigned long flags;
 336
 337         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 338
 339         port = get_port_from_line(co->index);
 340         if (IS_ERR(port))
 341                 return;
 342
 343         uport = &port->uport;
 344         if (oops_in_progress)
 345                 locked = spin_trylock_irqsave(&uport->lock, flags);
 346         else
 347                 spin_lock_irqsave(&uport->lock, flags);
 348
 349         /* Cancel the current write to log the fault */
 350         if (!locked) {
 351                 geni_se_cancel_m_cmd(&port->se);
 352                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 353                                                 M_CMD_CANCEL_EN, true)) {
 354                         geni_se_abort_m_cmd(&port->se);
 355                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 356                                                         M_CMD_ABORT_EN, true);
 357                         writel_relaxed(M_CMD_ABORT_EN, uport->membase +
 358                                                         SE_GENI_M_IRQ_CLEAR);
 359                 }
 360                 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
 361                                                         SE_GENI_M_IRQ_CLEAR);
 362         }
 363
 364         __qcom_geni_serial_console_write(uport, s, count);
 365         if (locked)
 366                 spin_unlock_irqrestore(&uport->lock, flags);
 367 }
 368
 369 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 370 {
 371         u32 i;
 372         unsigned char buf[sizeof(u32)];
 373         struct tty_port *tport;
 374         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 375
 376         tport = &uport->state->port;
 377         for (i = 0; i < bytes; ) {
 378                 int c;
 379                 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
 380
 381                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 382                 i += chunk;
 383                 if (drop)
 384                         continue;
 385
 386                 for (c = 0; c < chunk; c++) {
 387                         int sysrq;
 388
 389                         uport->icount.rx++;
 390                         if (port->brk && buf[c] == 0) {
 391                                 port->brk = false;
 392                                 if (uart_handle_break(uport))
 393                                         continue;
 394                         }
 395
 396                         sysrq = uart_handle_sysrq_char(uport, buf[c]);
 397                         if (!sysrq)
 398                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 399                 }
 400         }
 401         if (!drop)
 402                 tty_flip_buffer_push(tport);
 403         return 0;
 404 }
 405 #else
 406 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 407 {
 408         return -EPERM;
 409 }
 410
 411 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 412
 413 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 414 {
 415         u32 irq_en;
 416         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 417         u32 status;
 418
 419         if (port->xfer_mode == GENI_SE_FIFO) {
 420                 /*
 421                  * readl ensures reading & writing of IRQ_EN register
 422                  * is not re-ordered before checking the status of the
 423                  * Serial Engine.
 424                  */
 425                 status = readl(uport->membase + SE_GENI_STATUS);
 426                 if (status & M_GENI_CMD_ACTIVE)
 427                         return;
 428
 429                 if (!qcom_geni_serial_tx_empty(uport))
 430                         return;
 431
 432                 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
 433                 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 434
 435                 writel_relaxed(port->tx_wm, uport->membase +
 436                                                 SE_GENI_TX_WATERMARK_REG);
 437                 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 438         }
 439 }
 440
 441 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 442 {
 443         u32 irq_en;
 444         u32 status;
 445         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 446
 447         irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
 448         irq_en &= ~M_CMD_DONE_EN;
 449         if (port->xfer_mode == GENI_SE_FIFO) {
 450                 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
 451                 writel_relaxed(0, uport->membase +
 452                                      SE_GENI_TX_WATERMARK_REG);
 453         }
 454         port->xmit_size = 0;
 455         writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 456         status = readl_relaxed(uport->membase + SE_GENI_STATUS);
 457         /* Possible stop tx is called multiple times. */
 458         if (!(status & M_GENI_CMD_ACTIVE))
 459                 return;
 460
 461         /*
 462          * Ensure cancel command write is not re-ordered before checking
 463          * the status of the Primary Sequencer.
 464          */
 465         mb();
 466
 467         geni_se_cancel_m_cmd(&port->se);
 468         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 469                                                 M_CMD_CANCEL_EN, true)) {
 470                 geni_se_abort_m_cmd(&port->se);
 471                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 472                                                 M_CMD_ABORT_EN, true);
 473                 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
 474                                                         SE_GENI_M_IRQ_CLEAR);
 475         }
 476         writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 477 }
 478
 479 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 480 {
 481         u32 irq_en;
 482         u32 status;
 483         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 484
 485         status = readl_relaxed(uport->membase + SE_GENI_STATUS);
 486         if (status & S_GENI_CMD_ACTIVE)
 487                 qcom_geni_serial_stop_rx(uport);
 488
 489         /*
 490          * Ensure setup command write is not re-ordered before checking
 491          * the status of the Secondary Sequencer.
 492          */
 493         mb();
 494
 495         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 496
 497         if (port->xfer_mode == GENI_SE_FIFO) {
 498                 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
 499                 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 500                 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 501
 502                 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
 503                 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 504                 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 505         }
 506 }
 507
 508 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 509 {
 510         u32 irq_en;
 511         u32 status;
 512         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 513         u32 irq_clear = S_CMD_DONE_EN;
 514
 515         if (port->xfer_mode == GENI_SE_FIFO) {
 516                 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
 517                 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 518                 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 519
 520                 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
 521                 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 522                 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 523         }
 524
 525         status = readl_relaxed(uport->membase + SE_GENI_STATUS);
 526         /* Possible stop rx is called multiple times. */
 527         if (!(status & S_GENI_CMD_ACTIVE))
 528                 return;
 529
 530         /*
 531          * Ensure cancel command write is not re-ordered before checking
 532          * the status of the Secondary Sequencer.
 533          */
 534         mb();
 535
 536         geni_se_cancel_s_cmd(&port->se);
 537         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 538                                         S_GENI_CMD_CANCEL, false);
 539         status = readl_relaxed(uport->membase + SE_GENI_STATUS);
 540         writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 541         if (status & S_GENI_CMD_ACTIVE)
 542                 qcom_geni_serial_abort_rx(uport);
 543 }
 544
 545 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 546 {
 547         u32 status;
 548         u32 word_cnt;
 549         u32 last_word_byte_cnt;
 550         u32 last_word_partial;
 551         u32 total_bytes;
 552         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 553
 554         status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
 555         word_cnt = status & RX_FIFO_WC_MSK;
 556         last_word_partial = status & RX_LAST;
 557         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 558                                                 RX_LAST_BYTE_VALID_SHFT;
 559
 560         if (!word_cnt)
 561                 return;
 562         total_bytes = port->rx_bytes_pw * (word_cnt - 1);
 563         if (last_word_partial && last_word_byte_cnt)
 564                 total_bytes += last_word_byte_cnt;
 565         else
 566                 total_bytes += port->rx_bytes_pw;
 567         port->handle_rx(uport, total_bytes, drop);
 568 }
 569
 570 static void qcom_geni_serial_handle_tx(struct uart_port *uport)
 571 {
 572         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 573         struct circ_buf *xmit = &uport->state->xmit;
 574         size_t avail;
 575         size_t remaining;
 576         int i;
 577         u32 status;
 578         unsigned int chunk;
 579         int tail;
 580
 581         chunk = uart_circ_chars_pending(xmit);
 582         status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
 583         /* Both FIFO and framework buffer are drained */
 584         if (chunk == port->xmit_size && !status) {
 585                 port->xmit_size = 0;
 586                 uart_circ_clear(xmit);
 587                 qcom_geni_serial_stop_tx(uport);
 588                 goto out_write_wakeup;
 589         }
 590         chunk -= port->xmit_size;
 591
 592         avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
 593         tail = (xmit->tail + port->xmit_size) & (UART_XMIT_SIZE - 1);
 594         chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail);
 595         if (!chunk)
 596                 goto out_write_wakeup;
 597
 598         qcom_geni_serial_setup_tx(uport, chunk);
 599
 600         remaining = chunk;
 601         for (i = 0; i < chunk; ) {
 602                 unsigned int tx_bytes;
 603                 u8 buf[sizeof(u32)];
 604                 int c;
 605
 606                 memset(buf, 0, ARRAY_SIZE(buf));
 607                 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
 608                 for (c = 0; c < tx_bytes ; c++)
 609                         buf[c] = xmit->buf[tail + c];
 610
 611                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 612
 613                 i += tx_bytes;
 614                 tail = (tail + tx_bytes) & (UART_XMIT_SIZE - 1);
 615                 uport->icount.tx += tx_bytes;
 616                 remaining -= tx_bytes;
 617         }
 618         qcom_geni_serial_poll_tx_done(uport);
 619         port->xmit_size += chunk;
 620 out_write_wakeup:
 621         uart_write_wakeup(uport);
 622 }
 623
 624 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 625 {
 626         unsigned int m_irq_status;
 627         unsigned int s_irq_status;
 628         struct uart_port *uport = dev;
 629         unsigned long flags;
 630         unsigned int m_irq_en;
 631         bool drop_rx = false;
 632         struct tty_port *tport = &uport->state->port;
 633         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 634
 635         if (uport->suspended)
 636                 return IRQ_NONE;
 637
 638         spin_lock_irqsave(&uport->lock, flags);
 639         m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
 640         s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
 641         m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
 642         writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 643         writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 644
 645         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 646                 goto out_unlock;
 647
 648         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 649                 uport->icount.overrun++;
 650                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 651         }
 652
 653         if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
 654             m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 655                 qcom_geni_serial_handle_tx(uport);
 656
 657         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 658                 if (s_irq_status & S_GP_IRQ_0_EN)
 659                         uport->icount.parity++;
 660                 drop_rx = true;
 661         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 662                                         s_irq_status & S_GP_IRQ_3_EN) {
 663                 uport->icount.brk++;
 664                 port->brk = true;
 665         }
 666
 667         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 668                                         s_irq_status & S_RX_FIFO_LAST_EN)
 669                 qcom_geni_serial_handle_rx(uport, drop_rx);
 670
 671 out_unlock:
 672         spin_unlock_irqrestore(&uport->lock, flags);
 673         return IRQ_HANDLED;
 674 }
 675
 676 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 677 {
 678         struct uart_port *uport;
 679
 680         uport = &port->uport;
 681         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 682         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 683         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 684         uport->fifosize =
 685                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 686 }
 687
 688 static void set_rfr_wm(struct qcom_geni_serial_port *port)
 689 {
 690         /*
 691          * Set RFR (Flow off) to FIFO_DEPTH - 2.
 692          * RX WM level at 10% RX_FIFO_DEPTH.
 693          * TX WM level at 10% TX_FIFO_DEPTH.
 694          */
 695         port->rx_rfr = port->rx_fifo_depth - 2;
 696         port->rx_wm = UART_CONSOLE_RX_WM;
 697         port->tx_wm = DEF_TX_WM;
 698 }
 699
 700 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 701 {
 702         unsigned long flags;
 703
 704         /* Stop the console before stopping the current tx */
 705         console_stop(uport->cons);
 706
 707         free_irq(uport->irq, uport);
 708         spin_lock_irqsave(&uport->lock, flags);
 709         qcom_geni_serial_stop_tx(uport);
 710         qcom_geni_serial_stop_rx(uport);
 711         spin_unlock_irqrestore(&uport->lock, flags);
 712 }
 713
 714 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 715 {
 716         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 717         unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 718
 719         set_rfr_wm(port);
 720         writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 721         /*
 722          * Make an unconditional cancel on the main sequencer to reset
 723          * it else we could end up in data loss scenarios.
 724          */
 725         port->xfer_mode = GENI_SE_FIFO;
 726         qcom_geni_serial_poll_tx_done(uport);
 727         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
 728                                                 false, true, false);
 729         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
 730                                                 false, false, true);
 731         geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
 732         geni_se_select_mode(&port->se, port->xfer_mode);
 733         port->setup = true;
 734         return 0;
 735 }
 736
 737 static int qcom_geni_serial_startup(struct uart_port *uport)
 738 {
 739         int ret;
 740         u32 proto;
 741         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 742
 743         scnprintf(port->name, sizeof(port->name),
 744                   "qcom_serial_geni%d", uport->line);
 745
 746         proto = geni_se_read_proto(&port->se);
 747         if (proto != GENI_SE_UART) {
 748                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 749                 return -ENXIO;
 750         }
 751
 752         get_tx_fifo_size(port);
 753         if (!port->setup) {
 754                 ret = qcom_geni_serial_port_setup(uport);
 755                 if (ret)
 756                         return ret;
 757         }
 758
 759         ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
 760                                                         port->name, uport);
 761         if (ret)
 762                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
 763         return ret;
 764 }
 765
 766 static unsigned long get_clk_cfg(unsigned long clk_freq)
 767 {
 768         int i;
 769
 770         for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 771                 if (!(root_freq[i] % clk_freq))
 772                         return root_freq[i];
 773         }
 774         return 0;
 775 }
 776
 777 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
 778 {
 779         unsigned long ser_clk;
 780         unsigned long desired_clk;
 781
 782         desired_clk = baud * UART_OVERSAMPLING;
 783         ser_clk = get_clk_cfg(desired_clk);
 784         if (!ser_clk) {
 785                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 786                                                                 __func__, baud);
 787                 return ser_clk;
 788         }
 789
 790         *clk_div = ser_clk / desired_clk;
 791         return ser_clk;
 792 }
 793
 794 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 795                                 struct ktermios *termios, struct ktermios *old)
 796 {
 797         unsigned int baud;
 798         unsigned int bits_per_char;
 799         unsigned int tx_trans_cfg;
 800         unsigned int tx_parity_cfg;
 801         unsigned int rx_trans_cfg;
 802         unsigned int rx_parity_cfg;
 803         unsigned int stop_bit_len;
 804         unsigned int clk_div;
 805         unsigned long ser_clk_cfg;
 806         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 807         unsigned long clk_rate;
 808
 809         qcom_geni_serial_stop_rx(uport);
 810         /* baud rate */
 811         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 812         port->baud = baud;
 813         clk_rate = get_clk_div_rate(baud, &clk_div);
 814         if (!clk_rate)
 815                 goto out_restart_rx;
 816
 817         uport->uartclk = clk_rate;
 818         clk_set_rate(port->se.clk, clk_rate);
 819         ser_clk_cfg = SER_CLK_EN;
 820         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 821
 822         /* parity */
 823         tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
 824         tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
 825         rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
 826         rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
 827         if (termios->c_cflag & PARENB) {
 828                 tx_trans_cfg |= UART_TX_PAR_EN;
 829                 rx_trans_cfg |= UART_RX_PAR_EN;
 830                 tx_parity_cfg |= PAR_CALC_EN;
 831                 rx_parity_cfg |= PAR_CALC_EN;
 832                 if (termios->c_cflag & PARODD) {
 833                         tx_parity_cfg |= PAR_ODD;
 834                         rx_parity_cfg |= PAR_ODD;
 835                 } else if (termios->c_cflag & CMSPAR) {
 836                         tx_parity_cfg |= PAR_SPACE;
 837                         rx_parity_cfg |= PAR_SPACE;
 838                 } else {
 839                         tx_parity_cfg |= PAR_EVEN;
 840                         rx_parity_cfg |= PAR_EVEN;
 841                 }
 842         } else {
 843                 tx_trans_cfg &= ~UART_TX_PAR_EN;
 844                 rx_trans_cfg &= ~UART_RX_PAR_EN;
 845                 tx_parity_cfg &= ~PAR_CALC_EN;
 846                 rx_parity_cfg &= ~PAR_CALC_EN;
 847         }
 848
 849         /* bits per char */
 850         switch (termios->c_cflag & CSIZE) {
 851         case CS5:
 852                 bits_per_char = 5;
 853                 break;
 854         case CS6:
 855                 bits_per_char = 6;
 856                 break;
 857         case CS7:
 858                 bits_per_char = 7;
 859                 break;
 860         case CS8:
 861         default:
 862                 bits_per_char = 8;
 863                 break;
 864         }
 865
 866         /* stop bits */
 867         if (termios->c_cflag & CSTOPB)
 868                 stop_bit_len = TX_STOP_BIT_LEN_2;
 869         else
 870                 stop_bit_len = TX_STOP_BIT_LEN_1;
 871
 872         /* flow control, clear the CTS_MASK bit if using flow control. */
 873         if (termios->c_cflag & CRTSCTS)
 874                 tx_trans_cfg &= ~UART_CTS_MASK;
 875         else
 876                 tx_trans_cfg |= UART_CTS_MASK;
 877
 878         if (baud)
 879                 uart_update_timeout(uport, termios->c_cflag, baud);
 880
 881         writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
 882         writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
 883         writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
 884         writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
 885         writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
 886         writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
 887         writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
 888         writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
 889         writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
 890 out_restart_rx:
 891         qcom_geni_serial_start_rx(uport);
 892 }
 893
 894 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
 895 {
 896         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 897 }
 898
 899 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 900 static int __init qcom_geni_console_setup(struct console *co, char *options)
 901 {
 902         struct uart_port *uport;
 903         struct qcom_geni_serial_port *port;
 904         int baud;
 905         int bits = 8;
 906         int parity = 'n';
 907         int flow = 'n';
 908
 909         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
 910                 return -ENXIO;
 911
 912         port = get_port_from_line(co->index);
 913         if (IS_ERR(port)) {
 914                 pr_err("Invalid line %d\n", co->index);
 915                 return PTR_ERR(port);
 916         }
 917
 918         uport = &port->uport;
 919
 920         if (unlikely(!uport->membase))
 921                 return -ENXIO;
 922
 923         if (geni_se_resources_on(&port->se)) {
 924                 dev_err(port->se.dev, "Error turning on resources\n");
 925                 return -ENXIO;
 926         }
 927
 928         if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
 929                 geni_se_resources_off(&port->se);
 930                 return -ENXIO;
 931         }
 932
 933         if (!port->setup) {
 934                 port->tx_bytes_pw = 1;
 935                 port->rx_bytes_pw = RX_BYTES_PW;
 936                 qcom_geni_serial_stop_rx(uport);
 937                 qcom_geni_serial_port_setup(uport);
 938         }
 939
 940         if (options)
 941                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 942
 943         return uart_set_options(uport, co, baud, parity, bits, flow);
 944 }
 945
 946 static int __init console_register(struct uart_driver *drv)
 947 {
 948         return uart_register_driver(drv);
 949 }
 950
 951 static void console_unregister(struct uart_driver *drv)
 952 {
 953         uart_unregister_driver(drv);
 954 }
 955
 956 static struct console cons_ops = {
 957         .name = "ttyMSM",
 958         .write = qcom_geni_serial_console_write,
 959         .device = uart_console_device,
 960         .setup = qcom_geni_console_setup,
 961         .flags = CON_PRINTBUFFER,
 962         .index = -1,
 963         .data = &qcom_geni_console_driver,
 964 };
 965
 966 static struct uart_driver qcom_geni_console_driver = {
 967         .owner = THIS_MODULE,
 968         .driver_name = "qcom_geni_console",
 969         .dev_name = "ttyMSM",
 970         .nr =  GENI_UART_CONS_PORTS,
 971         .cons = &cons_ops,
 972 };
 973 #else
 974 static int console_register(struct uart_driver *drv)
 975 {
 976         return 0;
 977 }
 978
 979 static void console_unregister(struct uart_driver *drv)
 980 {
 981 }
 982 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 983
 984 static void qcom_geni_serial_cons_pm(struct uart_port *uport,
 985                 unsigned int new_state, unsigned int old_state)
 986 {
 987         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 988
 989         if (unlikely(!uart_console(uport)))
 990                 return;
 991
 992         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
 993                 geni_se_resources_on(&port->se);
 994         else if (new_state == UART_PM_STATE_OFF &&
 995                         old_state == UART_PM_STATE_ON)
 996                 geni_se_resources_off(&port->se);
 997 }
 998
 999 static const struct uart_ops qcom_geni_console_pops = {
1000         .tx_empty = qcom_geni_serial_tx_empty,
1001         .stop_tx = qcom_geni_serial_stop_tx,
1002         .start_tx = qcom_geni_serial_start_tx,
1003         .stop_rx = qcom_geni_serial_stop_rx,
1004         .set_termios = qcom_geni_serial_set_termios,
1005         .startup = qcom_geni_serial_startup,
1006         .request_port = qcom_geni_serial_request_port,
1007         .config_port = qcom_geni_serial_config_port,
1008         .shutdown = qcom_geni_serial_shutdown,
1009         .type = qcom_geni_serial_get_type,
1010         .set_mctrl = qcom_geni_cons_set_mctrl,
1011         .get_mctrl = qcom_geni_cons_get_mctrl,
1012 #ifdef CONFIG_CONSOLE_POLL
1013         .poll_get_char  = qcom_geni_serial_get_char,
1014         .poll_put_char  = qcom_geni_serial_poll_put_char,
1015 #endif
1016         .pm = qcom_geni_serial_cons_pm,
1017 };
1018
1019 static int qcom_geni_serial_probe(struct platform_device *pdev)
1020 {
1021         int ret = 0;
1022         int line = -1;
1023         struct qcom_geni_serial_port *port;
1024         struct uart_port *uport;
1025         struct resource *res;
1026         int irq;
1027
1028         if (pdev->dev.of_node)
1029                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1030
1031         if (line < 0 || line >= GENI_UART_CONS_PORTS)
1032                 return -ENXIO;
1033         port = get_port_from_line(line);
1034         if (IS_ERR(port)) {
1035                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1036                 return PTR_ERR(port);
1037         }
1038
1039         uport = &port->uport;
1040         /* Don't allow 2 drivers to access the same port */
1041         if (uport->private_data)
1042                 return -ENODEV;
1043
1044         uport->dev = &pdev->dev;
1045         port->se.dev = &pdev->dev;
1046         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1047         port->se.clk = devm_clk_get(&pdev->dev, "se");
1048         if (IS_ERR(port->se.clk)) {
1049                 ret = PTR_ERR(port->se.clk);
1050                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1051                 return ret;
1052         }
1053
1054         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055         if (!res)
1056                 return -EINVAL;
1057         uport->mapbase = res->start;
1058
1059         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1060         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1061         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1062
1063         irq = platform_get_irq(pdev, 0);
1064         if (irq < 0) {
1065                 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1066                 return irq;
1067         }
1068         uport->irq = irq;
1069
1070         uport->private_data = &qcom_geni_console_driver;
1071         platform_set_drvdata(pdev, port);
1072         port->handle_rx = handle_rx_console;
1073         return uart_add_one_port(&qcom_geni_console_driver, uport);
1074 }
1075
1076 static int qcom_geni_serial_remove(struct platform_device *pdev)
1077 {
1078         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1079         struct uart_driver *drv = port->uport.private_data;
1080
1081         uart_remove_one_port(drv, &port->uport);
1082         return 0;
1083 }
1084
1085 static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1086 {
1087         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1088         struct uart_port *uport = &port->uport;
1089
1090         uart_suspend_port(uport->private_data, uport);
1091         return 0;
1092 }
1093
1094 static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1095 {
1096         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1097         struct uart_port *uport = &port->uport;
1098
1099         if (console_suspend_enabled && uport->suspended) {
1100                 uart_resume_port(uport->private_data, uport);
1101                 /*
1102                  * uart_suspend_port() invokes port shutdown which in turn
1103                  * frees the irq. uart_resume_port invokes port startup which
1104                  * performs request_irq. The request_irq auto-enables the IRQ.
1105                  * In addition, resume_noirq implicitly enables the IRQ and
1106                  * leads to an unbalanced IRQ enable warning. Disable the IRQ
1107                  * before returning so that the warning is suppressed.
1108                  */
1109                 disable_irq(uport->irq);
1110         }
1111         return 0;
1112 }
1113
1114 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1115         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1116                                         qcom_geni_serial_sys_resume_noirq)
1117 };
1118
1119 static const struct of_device_id qcom_geni_serial_match_table[] = {
1120         { .compatible = "qcom,geni-debug-uart", },
1121         {}
1122 };
1123 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1124
1125 static struct platform_driver qcom_geni_serial_platform_driver = {
1126         .remove = qcom_geni_serial_remove,
1127         .probe = qcom_geni_serial_probe,
1128         .driver = {
1129                 .name = "qcom_geni_serial",
1130                 .of_match_table = qcom_geni_serial_match_table,
1131                 .pm = &qcom_geni_serial_pm_ops,
1132         },
1133 };
1134
1135 static int __init qcom_geni_serial_init(void)
1136 {
1137         int ret;
1138
1139         ret = console_register(&qcom_geni_console_driver);
1140         if (ret)
1141                 return ret;
1142
1143         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1144         if (ret)
1145                 console_unregister(&qcom_geni_console_driver);
1146         return ret;
1147 }
1148 module_init(qcom_geni_serial_init);
1149
1150 static void __exit qcom_geni_serial_exit(void)
1151 {
1152         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1153         console_unregister(&qcom_geni_console_driver);
1154 }
1155 module_exit(qcom_geni_serial_exit);
1156
1157 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1158 MODULE_LICENSE("GPL v2");