drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28 #include <linux/console.h>
  29 #include <linux/nmi.h>
  30 #include <linux/delay.h>
  31
  32 #include <linux/debugfs.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/pch_dma.h>
  35
  36 enum {
  37         PCH_UART_HANDLED_RX_INT_SHIFT,
  38         PCH_UART_HANDLED_TX_INT_SHIFT,
  39         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  40         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  41         PCH_UART_HANDLED_MS_INT_SHIFT,
  42 };
  43
  44 enum {
  45         PCH_UART_8LINE,
  46         PCH_UART_2LINE,
  47 };
  48
  49 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  50
  51 /* Set the max number of UART port
  52  * Intel EG20T PCH: 4 port
  53  * LAPIS Semiconductor ML7213 IOH: 3 port
  54  * LAPIS Semiconductor ML7223 IOH: 2 port
  55 */
  56 #define PCH_UART_NR     4
  57
  58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  61                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  62 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  63                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  65
  66 #define PCH_UART_RBR            0x00
  67 #define PCH_UART_THR            0x00
  68
  69 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  70                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  71 #define PCH_UART_IER_ERBFI      0x00000001
  72 #define PCH_UART_IER_ETBEI      0x00000002
  73 #define PCH_UART_IER_ELSI       0x00000004
  74 #define PCH_UART_IER_EDSSI      0x00000008
  75
  76 #define PCH_UART_IIR_IP                 0x00000001
  77 #define PCH_UART_IIR_IID                0x00000006
  78 #define PCH_UART_IIR_MSI                0x00000000
  79 #define PCH_UART_IIR_TRI                0x00000002
  80 #define PCH_UART_IIR_RRI                0x00000004
  81 #define PCH_UART_IIR_REI                0x00000006
  82 #define PCH_UART_IIR_TOI                0x00000008
  83 #define PCH_UART_IIR_FIFO256            0x00000020
  84 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  85 #define PCH_UART_IIR_FE                 0x000000C0
  86
  87 #define PCH_UART_FCR_FIFOE              0x00000001
  88 #define PCH_UART_FCR_RFR                0x00000002
  89 #define PCH_UART_FCR_TFR                0x00000004
  90 #define PCH_UART_FCR_DMS                0x00000008
  91 #define PCH_UART_FCR_FIFO256            0x00000020
  92 #define PCH_UART_FCR_RFTL               0x000000C0
  93
  94 #define PCH_UART_FCR_RFTL1              0x00000000
  95 #define PCH_UART_FCR_RFTL64             0x00000040
  96 #define PCH_UART_FCR_RFTL128            0x00000080
  97 #define PCH_UART_FCR_RFTL224            0x000000C0
  98 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  99 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 100 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 101 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 102 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 103 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 104 #define PCH_UART_FCR_RFTL_SHIFT         6
 105
 106 #define PCH_UART_LCR_WLS        0x00000003
 107 #define PCH_UART_LCR_STB        0x00000004
 108 #define PCH_UART_LCR_PEN        0x00000008
 109 #define PCH_UART_LCR_EPS        0x00000010
 110 #define PCH_UART_LCR_SP         0x00000020
 111 #define PCH_UART_LCR_SB         0x00000040
 112 #define PCH_UART_LCR_DLAB       0x00000080
 113 #define PCH_UART_LCR_NP         0x00000000
 114 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 115 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 116 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 117 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 118                                 PCH_UART_LCR_SP)
 119
 120 #define PCH_UART_LCR_5BIT       0x00000000
 121 #define PCH_UART_LCR_6BIT       0x00000001
 122 #define PCH_UART_LCR_7BIT       0x00000002
 123 #define PCH_UART_LCR_8BIT       0x00000003
 124
 125 #define PCH_UART_MCR_DTR        0x00000001
 126 #define PCH_UART_MCR_RTS        0x00000002
 127 #define PCH_UART_MCR_OUT        0x0000000C
 128 #define PCH_UART_MCR_LOOP       0x00000010
 129 #define PCH_UART_MCR_AFE        0x00000020
 130
 131 #define PCH_UART_LSR_DR         0x00000001
 132 #define PCH_UART_LSR_ERR        (1<<7)
 133
 134 #define PCH_UART_MSR_DCTS       0x00000001
 135 #define PCH_UART_MSR_DDSR       0x00000002
 136 #define PCH_UART_MSR_TERI       0x00000004
 137 #define PCH_UART_MSR_DDCD       0x00000008
 138 #define PCH_UART_MSR_CTS        0x00000010
 139 #define PCH_UART_MSR_DSR        0x00000020
 140 #define PCH_UART_MSR_RI         0x00000040
 141 #define PCH_UART_MSR_DCD        0x00000080
 142 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 143                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 144
 145 #define PCH_UART_DLL            0x00
 146 #define PCH_UART_DLM            0x01
 147
 148 #define PCH_UART_BRCSR          0x0E
 149
 150 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 151 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 152 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 153 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 154 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 155
 156 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 157 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 158 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 159 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 160 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 161 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 162 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 163 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 164 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 165 #define PCH_UART_HAL_STB1               0
 166 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 167
 168 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 169 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 170 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 171                                         PCH_UART_HAL_CLR_RX_FIFO)
 172
 173 #define PCH_UART_HAL_DMA_MODE0          0
 174 #define PCH_UART_HAL_FIFO_DIS           0
 175 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 176 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 177                                         PCH_UART_FCR_FIFO256)
 178 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 179 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 180 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 181 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 182 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 183 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 184 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 185 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 186 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 187 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 188 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 189 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 190 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 191 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 192
 193 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 194 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 195 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 196 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 197 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 198
 199 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 200 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 201 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 202 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 203 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 204
 205 #define PCI_VENDOR_ID_ROHM              0x10DB
 206
 207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 208
 209 #define DEFAULT_BAUD_RATE 1843200 /* 1.8432MHz */
 210
 211 struct pch_uart_buffer {
 212         unsigned char *buf;
 213         int size;
 214 };
 215
 216 struct eg20t_port {
 217         struct uart_port port;
 218         int port_type;
 219         void __iomem *membase;
 220         resource_size_t mapbase;
 221         unsigned int iobase;
 222         struct pci_dev *pdev;
 223         int fifo_size;
 224         int base_baud;
 225         int start_tx;
 226         int start_rx;
 227         int tx_empty;
 228         int int_dis_flag;
 229         int trigger;
 230         int trigger_level;
 231         struct pch_uart_buffer rxbuf;
 232         unsigned int dmsr;
 233         unsigned int fcr;
 234         unsigned int mcr;
 235         unsigned int use_dma;
 236         unsigned int use_dma_flag;
 237         struct dma_async_tx_descriptor  *desc_tx;
 238         struct dma_async_tx_descriptor  *desc_rx;
 239         struct pch_dma_slave            param_tx;
 240         struct pch_dma_slave            param_rx;
 241         struct dma_chan                 *chan_tx;
 242         struct dma_chan                 *chan_rx;
 243         struct scatterlist              *sg_tx_p;
 244         int                             nent;
 245         struct scatterlist              sg_rx;
 246         int                             tx_dma_use;
 247         void                            *rx_buf_virt;
 248         dma_addr_t                      rx_buf_dma;
 249
 250         struct dentry   *debugfs;
 251 };
 252
 253 /**
 254  * struct pch_uart_driver_data - private data structure for UART-DMA
 255  * @port_type:                  The number of DMA channel
 256  * @line_no:                    UART port line number (0, 1, 2...)
 257  */
 258 struct pch_uart_driver_data {
 259         int port_type;
 260         int line_no;
 261 };
 262
 263 enum pch_uart_num_t {
 264         pch_et20t_uart0 = 0,
 265         pch_et20t_uart1,
 266         pch_et20t_uart2,
 267         pch_et20t_uart3,
 268         pch_ml7213_uart0,
 269         pch_ml7213_uart1,
 270         pch_ml7213_uart2,
 271         pch_ml7223_uart0,
 272         pch_ml7223_uart1,
 273         pch_ml7831_uart0,
 274         pch_ml7831_uart1,
 275 };
 276
 277 static struct pch_uart_driver_data drv_dat[] = {
 278         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 279         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 280         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 281         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 282         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 283         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 284         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 285         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 286         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 287         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 288         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 289 };
 290
 291 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 292 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 293 #endif
 294 static unsigned int default_baud = 9600;
 295 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 296 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 297 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 298 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 299
 300 #ifdef CONFIG_DEBUG_FS
 301
 302 #define PCH_REGS_BUFSIZE        1024
 303 static int pch_show_regs_open(struct inode *inode, struct file *file)
 304 {
 305         file->private_data = inode->i_private;
 306         return 0;
 307 }
 308
 309 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 310                                 size_t count, loff_t *ppos)
 311 {
 312         struct eg20t_port *priv = file->private_data;
 313         char *buf;
 314         u32 len = 0;
 315         ssize_t ret;
 316         unsigned char lcr;
 317
 318         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 319         if (!buf)
 320                 return 0;
 321
 322         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 323                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 324
 325         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 326                         "=================================\n");
 327         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 328                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 329         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 330                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 331         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 332                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 337         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "BRCSR: \t0x%02x\n",
 341                         ioread8(priv->membase + PCH_UART_BRCSR));
 342
 343         lcr = ioread8(priv->membase + UART_LCR);
 344         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 345         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 346                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 347         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 349         iowrite8(lcr, priv->membase + UART_LCR);
 350
 351         if (len > PCH_REGS_BUFSIZE)
 352                 len = PCH_REGS_BUFSIZE;
 353
 354         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 355         kfree(buf);
 356         return ret;
 357 }
 358
 359 static const struct file_operations port_regs_ops = {
 360         .owner          = THIS_MODULE,
 361         .open           = pch_show_regs_open,
 362         .read           = port_show_regs,
 363         .llseek         = default_llseek,
 364 };
 365 #endif  /* CONFIG_DEBUG_FS */
 366
 367 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 368                                  int base_baud)
 369 {
 370         struct eg20t_port *priv = pci_get_drvdata(pdev);
 371
 372         priv->trigger_level = 1;
 373         priv->fcr = 0;
 374 }
 375
 376 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 377                                           unsigned int flag)
 378 {
 379         u8 ier = ioread8(priv->membase + UART_IER);
 380         ier |= flag & PCH_UART_IER_MASK;
 381         iowrite8(ier, priv->membase + UART_IER);
 382 }
 383
 384 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 385                                            unsigned int flag)
 386 {
 387         u8 ier = ioread8(priv->membase + UART_IER);
 388         ier &= ~(flag & PCH_UART_IER_MASK);
 389         iowrite8(ier, priv->membase + UART_IER);
 390 }
 391
 392 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 393                                  unsigned int parity, unsigned int bits,
 394                                  unsigned int stb)
 395 {
 396         unsigned int dll, dlm, lcr;
 397         int div;
 398
 399         div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
 400         if (div < 0 || USHRT_MAX <= div) {
 401                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 402                 return -EINVAL;
 403         }
 404
 405         dll = (unsigned int)div & 0x00FFU;
 406         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 407
 408         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 409                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 410                 return -EINVAL;
 411         }
 412
 413         if (bits & ~PCH_UART_LCR_WLS) {
 414                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 415                 return -EINVAL;
 416         }
 417
 418         if (stb & ~PCH_UART_LCR_STB) {
 419                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 420                 return -EINVAL;
 421         }
 422
 423         lcr = parity;
 424         lcr |= bits;
 425         lcr |= stb;
 426
 427         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 428                  __func__, baud, div, lcr, jiffies);
 429         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 430         iowrite8(dll, priv->membase + PCH_UART_DLL);
 431         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 432         iowrite8(lcr, priv->membase + UART_LCR);
 433
 434         return 0;
 435 }
 436
 437 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 438                                     unsigned int flag)
 439 {
 440         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 441                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 442                         __func__, flag);
 443                 return -EINVAL;
 444         }
 445
 446         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 447         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 448                  priv->membase + UART_FCR);
 449         iowrite8(priv->fcr, priv->membase + UART_FCR);
 450
 451         return 0;
 452 }
 453
 454 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 455                                  unsigned int dmamode,
 456                                  unsigned int fifo_size, unsigned int trigger)
 457 {
 458         u8 fcr;
 459
 460         if (dmamode & ~PCH_UART_FCR_DMS) {
 461                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 462                         __func__, dmamode);
 463                 return -EINVAL;
 464         }
 465
 466         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 467                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 468                         __func__, fifo_size);
 469                 return -EINVAL;
 470         }
 471
 472         if (trigger & ~PCH_UART_FCR_RFTL) {
 473                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 474                         __func__, trigger);
 475                 return -EINVAL;
 476         }
 477
 478         switch (priv->fifo_size) {
 479         case 256:
 480                 priv->trigger_level =
 481                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 482                 break;
 483         case 64:
 484                 priv->trigger_level =
 485                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 486                 break;
 487         case 16:
 488                 priv->trigger_level =
 489                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 490                 break;
 491         default:
 492                 priv->trigger_level =
 493                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 494                 break;
 495         }
 496         fcr =
 497             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 498         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 499         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 500                  priv->membase + UART_FCR);
 501         iowrite8(fcr, priv->membase + UART_FCR);
 502         priv->fcr = fcr;
 503
 504         return 0;
 505 }
 506
 507 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 508 {
 509         unsigned int msr = ioread8(priv->membase + UART_MSR);
 510         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 511         return (u8)msr;
 512 }
 513
 514 static void pch_uart_hal_write(struct eg20t_port *priv,
 515                               const unsigned char *buf, int tx_size)
 516 {
 517         int i;
 518         unsigned int thr;
 519
 520         for (i = 0; i < tx_size;) {
 521                 thr = buf[i++];
 522                 iowrite8(thr, priv->membase + PCH_UART_THR);
 523         }
 524 }
 525
 526 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 527                              int rx_size)
 528 {
 529         int i;
 530         u8 rbr, lsr;
 531
 532         lsr = ioread8(priv->membase + UART_LSR);
 533         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 534              i < rx_size && lsr & UART_LSR_DR;
 535              lsr = ioread8(priv->membase + UART_LSR)) {
 536                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 537                 buf[i++] = rbr;
 538         }
 539         return i;
 540 }
 541
 542 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 543 {
 544         unsigned int iir;
 545         int ret;
 546
 547         iir = ioread8(priv->membase + UART_IIR);
 548         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 549         return ret;
 550 }
 551
 552 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 553 {
 554         return ioread8(priv->membase + UART_LSR);
 555 }
 556
 557 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 558 {
 559         unsigned int lcr;
 560
 561         lcr = ioread8(priv->membase + UART_LCR);
 562         if (on)
 563                 lcr |= PCH_UART_LCR_SB;
 564         else
 565                 lcr &= ~PCH_UART_LCR_SB;
 566
 567         iowrite8(lcr, priv->membase + UART_LCR);
 568 }
 569
 570 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 571                    int size)
 572 {
 573         struct uart_port *port;
 574         struct tty_struct *tty;
 575
 576         port = &priv->port;
 577         tty = tty_port_tty_get(&port->state->port);
 578         if (!tty) {
 579                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 580                 return -EBUSY;
 581         }
 582
 583         tty_insert_flip_string(tty, buf, size);
 584         tty_flip_buffer_push(tty);
 585         tty_kref_put(tty);
 586
 587         return 0;
 588 }
 589
 590 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 591 {
 592         int ret = 0;
 593         struct uart_port *port = &priv->port;
 594
 595         if (port->x_char) {
 596                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 597                         __func__, port->x_char, jiffies);
 598                 buf[0] = port->x_char;
 599                 port->x_char = 0;
 600                 ret = 1;
 601         }
 602
 603         return ret;
 604 }
 605
 606 static int dma_push_rx(struct eg20t_port *priv, int size)
 607 {
 608         struct tty_struct *tty;
 609         int room;
 610         struct uart_port *port = &priv->port;
 611
 612         port = &priv->port;
 613         tty = tty_port_tty_get(&port->state->port);
 614         if (!tty) {
 615                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 616                 return 0;
 617         }
 618
 619         room = tty_buffer_request_room(tty, size);
 620
 621         if (room < size)
 622                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 623                          size - room);
 624         if (!room)
 625                 return room;
 626
 627         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 628
 629         port->icount.rx += room;
 630         tty_kref_put(tty);
 631
 632         return room;
 633 }
 634
 635 static void pch_free_dma(struct uart_port *port)
 636 {
 637         struct eg20t_port *priv;
 638         priv = container_of(port, struct eg20t_port, port);
 639
 640         if (priv->chan_tx) {
 641                 dma_release_channel(priv->chan_tx);
 642                 priv->chan_tx = NULL;
 643         }
 644         if (priv->chan_rx) {
 645                 dma_release_channel(priv->chan_rx);
 646                 priv->chan_rx = NULL;
 647         }
 648         if (sg_dma_address(&priv->sg_rx))
 649                 dma_free_coherent(port->dev, port->fifosize,
 650                                   sg_virt(&priv->sg_rx),
 651                                   sg_dma_address(&priv->sg_rx));
 652
 653         return;
 654 }
 655
 656 static bool filter(struct dma_chan *chan, void *slave)
 657 {
 658         struct pch_dma_slave *param = slave;
 659
 660         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 661                                                   chan->device->dev)) {
 662                 chan->private = param;
 663                 return true;
 664         } else {
 665                 return false;
 666         }
 667 }
 668
 669 static void pch_request_dma(struct uart_port *port)
 670 {
 671         dma_cap_mask_t mask;
 672         struct dma_chan *chan;
 673         struct pci_dev *dma_dev;
 674         struct pch_dma_slave *param;
 675         struct eg20t_port *priv =
 676                                 container_of(port, struct eg20t_port, port);
 677         dma_cap_zero(mask);
 678         dma_cap_set(DMA_SLAVE, mask);
 679
 680         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 681                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 682                                                                 information */
 683         /* Set Tx DMA */
 684         param = &priv->param_tx;
 685         param->dma_dev = &dma_dev->dev;
 686         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 687
 688         param->tx_reg = port->mapbase + UART_TX;
 689         chan = dma_request_channel(mask, filter, param);
 690         if (!chan) {
 691                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 692                         __func__);
 693                 return;
 694         }
 695         priv->chan_tx = chan;
 696
 697         /* Set Rx DMA */
 698         param = &priv->param_rx;
 699         param->dma_dev = &dma_dev->dev;
 700         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 701
 702         param->rx_reg = port->mapbase + UART_RX;
 703         chan = dma_request_channel(mask, filter, param);
 704         if (!chan) {
 705                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 706                         __func__);
 707                 dma_release_channel(priv->chan_tx);
 708                 priv->chan_tx = NULL;
 709                 return;
 710         }
 711
 712         /* Get Consistent memory for DMA */
 713         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 714                                     &priv->rx_buf_dma, GFP_KERNEL);
 715         priv->chan_rx = chan;
 716 }
 717
 718 static void pch_dma_rx_complete(void *arg)
 719 {
 720         struct eg20t_port *priv = arg;
 721         struct uart_port *port = &priv->port;
 722         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 723         int count;
 724
 725         if (!tty) {
 726                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 727                 return;
 728         }
 729
 730         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 731         count = dma_push_rx(priv, priv->trigger_level);
 732         if (count)
 733                 tty_flip_buffer_push(tty);
 734         tty_kref_put(tty);
 735         async_tx_ack(priv->desc_rx);
 736         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 737 }
 738
 739 static void pch_dma_tx_complete(void *arg)
 740 {
 741         struct eg20t_port *priv = arg;
 742         struct uart_port *port = &priv->port;
 743         struct circ_buf *xmit = &port->state->xmit;
 744         struct scatterlist *sg = priv->sg_tx_p;
 745         int i;
 746
 747         for (i = 0; i < priv->nent; i++, sg++) {
 748                 xmit->tail += sg_dma_len(sg);
 749                 port->icount.tx += sg_dma_len(sg);
 750         }
 751         xmit->tail &= UART_XMIT_SIZE - 1;
 752         async_tx_ack(priv->desc_tx);
 753         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 754         priv->tx_dma_use = 0;
 755         priv->nent = 0;
 756         kfree(priv->sg_tx_p);
 757         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 758 }
 759
 760 static int pop_tx(struct eg20t_port *priv, int size)
 761 {
 762         int count = 0;
 763         struct uart_port *port = &priv->port;
 764         struct circ_buf *xmit = &port->state->xmit;
 765
 766         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 767                 goto pop_tx_end;
 768
 769         do {
 770                 int cnt_to_end =
 771                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 772                 int sz = min(size - count, cnt_to_end);
 773                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 774                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 775                 count += sz;
 776         } while (!uart_circ_empty(xmit) && count < size);
 777
 778 pop_tx_end:
 779         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 780                  count, size - count, jiffies);
 781
 782         return count;
 783 }
 784
 785 static int handle_rx_to(struct eg20t_port *priv)
 786 {
 787         struct pch_uart_buffer *buf;
 788         int rx_size;
 789         int ret;
 790         if (!priv->start_rx) {
 791                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 792                 return 0;
 793         }
 794         buf = &priv->rxbuf;
 795         do {
 796                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 797                 ret = push_rx(priv, buf->buf, rx_size);
 798                 if (ret)
 799                         return 0;
 800         } while (rx_size == buf->size);
 801
 802         return PCH_UART_HANDLED_RX_INT;
 803 }
 804
 805 static int handle_rx(struct eg20t_port *priv)
 806 {
 807         return handle_rx_to(priv);
 808 }
 809
 810 static int dma_handle_rx(struct eg20t_port *priv)
 811 {
 812         struct uart_port *port = &priv->port;
 813         struct dma_async_tx_descriptor *desc;
 814         struct scatterlist *sg;
 815
 816         priv = container_of(port, struct eg20t_port, port);
 817         sg = &priv->sg_rx;
 818
 819         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 820
 821         sg_dma_len(sg) = priv->trigger_level;
 822
 823         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 824                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 825                      ~PAGE_MASK);
 826
 827         sg_dma_address(sg) = priv->rx_buf_dma;
 828
 829         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 830                         sg, 1, DMA_DEV_TO_MEM,
 831                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 832
 833         if (!desc)
 834                 return 0;
 835
 836         priv->desc_rx = desc;
 837         desc->callback = pch_dma_rx_complete;
 838         desc->callback_param = priv;
 839         desc->tx_submit(desc);
 840         dma_async_issue_pending(priv->chan_rx);
 841
 842         return PCH_UART_HANDLED_RX_INT;
 843 }
 844
 845 static unsigned int handle_tx(struct eg20t_port *priv)
 846 {
 847         struct uart_port *port = &priv->port;
 848         struct circ_buf *xmit = &port->state->xmit;
 849         int fifo_size;
 850         int tx_size;
 851         int size;
 852         int tx_empty;
 853
 854         if (!priv->start_tx) {
 855                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 856                         __func__, jiffies);
 857                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 858                 priv->tx_empty = 1;
 859                 return 0;
 860         }
 861
 862         fifo_size = max(priv->fifo_size, 1);
 863         tx_empty = 1;
 864         if (pop_tx_x(priv, xmit->buf)) {
 865                 pch_uart_hal_write(priv, xmit->buf, 1);
 866                 port->icount.tx++;
 867                 tx_empty = 0;
 868                 fifo_size--;
 869         }
 870         size = min(xmit->head - xmit->tail, fifo_size);
 871         if (size < 0)
 872                 size = fifo_size;
 873
 874         tx_size = pop_tx(priv, size);
 875         if (tx_size > 0) {
 876                 port->icount.tx += tx_size;
 877                 tx_empty = 0;
 878         }
 879
 880         priv->tx_empty = tx_empty;
 881
 882         if (tx_empty) {
 883                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 884                 uart_write_wakeup(port);
 885         }
 886
 887         return PCH_UART_HANDLED_TX_INT;
 888 }
 889
 890 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 891 {
 892         struct uart_port *port = &priv->port;
 893         struct circ_buf *xmit = &port->state->xmit;
 894         struct scatterlist *sg;
 895         int nent;
 896         int fifo_size;
 897         int tx_empty;
 898         struct dma_async_tx_descriptor *desc;
 899         int num;
 900         int i;
 901         int bytes;
 902         int size;
 903         int rem;
 904
 905         if (!priv->start_tx) {
 906                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 907                         __func__, jiffies);
 908                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 909                 priv->tx_empty = 1;
 910                 return 0;
 911         }
 912
 913         if (priv->tx_dma_use) {
 914                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 915                         __func__, jiffies);
 916                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 917                 priv->tx_empty = 1;
 918                 return 0;
 919         }
 920
 921         fifo_size = max(priv->fifo_size, 1);
 922         tx_empty = 1;
 923         if (pop_tx_x(priv, xmit->buf)) {
 924                 pch_uart_hal_write(priv, xmit->buf, 1);
 925                 port->icount.tx++;
 926                 tx_empty = 0;
 927                 fifo_size--;
 928         }
 929
 930         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 931                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 932                              xmit->tail, UART_XMIT_SIZE));
 933         if (!bytes) {
 934                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 935                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 936                 uart_write_wakeup(port);
 937                 return 0;
 938         }
 939
 940         if (bytes > fifo_size) {
 941                 num = bytes / fifo_size + 1;
 942                 size = fifo_size;
 943                 rem = bytes % fifo_size;
 944         } else {
 945                 num = 1;
 946                 size = bytes;
 947                 rem = bytes;
 948         }
 949
 950         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 951                 __func__, num, size, rem);
 952
 953         priv->tx_dma_use = 1;
 954
 955         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 956
 957         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 958         sg = priv->sg_tx_p;
 959
 960         for (i = 0; i < num; i++, sg++) {
 961                 if (i == (num - 1))
 962                         sg_set_page(sg, virt_to_page(xmit->buf),
 963                                     rem, fifo_size * i);
 964                 else
 965                         sg_set_page(sg, virt_to_page(xmit->buf),
 966                                     size, fifo_size * i);
 967         }
 968
 969         sg = priv->sg_tx_p;
 970         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 971         if (!nent) {
 972                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 973                 return 0;
 974         }
 975         priv->nent = nent;
 976
 977         for (i = 0; i < nent; i++, sg++) {
 978                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 979                               fifo_size * i;
 980                 sg_dma_address(sg) = (sg_dma_address(sg) &
 981                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 982                 if (i == (nent - 1))
 983                         sg_dma_len(sg) = rem;
 984                 else
 985                         sg_dma_len(sg) = size;
 986         }
 987
 988         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 989                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
 990                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 991         if (!desc) {
 992                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 993                         __func__);
 994                 return 0;
 995         }
 996         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 997         priv->desc_tx = desc;
 998         desc->callback = pch_dma_tx_complete;
 999         desc->callback_param = priv;
1000
1001         desc->tx_submit(desc);
1002
1003         dma_async_issue_pending(priv->chan_tx);
1004
1005         return PCH_UART_HANDLED_TX_INT;
1006 }
1007
1008 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1009 {
1010         u8 fcr = ioread8(priv->membase + UART_FCR);
1011
1012         /* Reset FIFO */
1013         fcr |= UART_FCR_CLEAR_RCVR;
1014         iowrite8(fcr, priv->membase + UART_FCR);
1015
1016         if (lsr & PCH_UART_LSR_ERR)
1017                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
1018
1019         if (lsr & UART_LSR_FE)
1020                 dev_err(&priv->pdev->dev, "Framing Error\n");
1021
1022         if (lsr & UART_LSR_PE)
1023                 dev_err(&priv->pdev->dev, "Parity Error\n");
1024
1025         if (lsr & UART_LSR_OE)
1026                 dev_err(&priv->pdev->dev, "Overrun Error\n");
1027 }
1028
1029 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1030 {
1031         struct eg20t_port *priv = dev_id;
1032         unsigned int handled;
1033         u8 lsr;
1034         int ret = 0;
1035         unsigned int iid;
1036         unsigned long flags;
1037
1038         spin_lock_irqsave(&priv->port.lock, flags);
1039         handled = 0;
1040         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
1041                 switch (iid) {
1042                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1043                         lsr = pch_uart_hal_get_line_status(priv);
1044                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1045                                                 UART_LSR_PE | UART_LSR_OE)) {
1046                                 pch_uart_err_ir(priv, lsr);
1047                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1048                         }
1049                         break;
1050                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1051                         if (priv->use_dma) {
1052                                 pch_uart_hal_disable_interrupt(priv,
1053                                                         PCH_UART_HAL_RX_INT);
1054                                 ret = dma_handle_rx(priv);
1055                                 if (!ret)
1056                                         pch_uart_hal_enable_interrupt(priv,
1057                                                         PCH_UART_HAL_RX_INT);
1058                         } else {
1059                                 ret = handle_rx(priv);
1060                         }
1061                         break;
1062                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1063                                                    (FIFO Timeout) */
1064                         ret = handle_rx_to(priv);
1065                         break;
1066                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1067                                                    Empty */
1068                         if (priv->use_dma)
1069                                 ret = dma_handle_tx(priv);
1070                         else
1071                                 ret = handle_tx(priv);
1072                         break;
1073                 case PCH_UART_IID_MS:   /* Modem Status */
1074                         ret = PCH_UART_HANDLED_MS_INT;
1075                         break;
1076                 default:        /* Never junp to this label */
1077                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1078                                 iid, jiffies);
1079                         ret = -1;
1080                         break;
1081                 }
1082                 handled |= (unsigned int)ret;
1083         }
1084         if (handled == 0 && iid <= 1) {
1085                 if (priv->int_dis_flag)
1086                         priv->int_dis_flag = 0;
1087         }
1088
1089         spin_unlock_irqrestore(&priv->port.lock, flags);
1090         return IRQ_RETVAL(handled);
1091 }
1092
1093 /* This function tests whether the transmitter fifo and shifter for the port
1094                                                 described by 'port' is empty. */
1095 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1096 {
1097         struct eg20t_port *priv;
1098
1099         priv = container_of(port, struct eg20t_port, port);
1100         if (priv->tx_empty)
1101                 return TIOCSER_TEMT;
1102         else
1103                 return 0;
1104 }
1105
1106 /* Returns the current state of modem control inputs. */
1107 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1108 {
1109         struct eg20t_port *priv;
1110         u8 modem;
1111         unsigned int ret = 0;
1112
1113         priv = container_of(port, struct eg20t_port, port);
1114         modem = pch_uart_hal_get_modem(priv);
1115
1116         if (modem & UART_MSR_DCD)
1117                 ret |= TIOCM_CAR;
1118
1119         if (modem & UART_MSR_RI)
1120                 ret |= TIOCM_RNG;
1121
1122         if (modem & UART_MSR_DSR)
1123                 ret |= TIOCM_DSR;
1124
1125         if (modem & UART_MSR_CTS)
1126                 ret |= TIOCM_CTS;
1127
1128         return ret;
1129 }
1130
1131 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1132 {
1133         u32 mcr = 0;
1134         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1135
1136         if (mctrl & TIOCM_DTR)
1137                 mcr |= UART_MCR_DTR;
1138         if (mctrl & TIOCM_RTS)
1139                 mcr |= UART_MCR_RTS;
1140         if (mctrl & TIOCM_LOOP)
1141                 mcr |= UART_MCR_LOOP;
1142
1143         if (priv->mcr & UART_MCR_AFE)
1144                 mcr |= UART_MCR_AFE;
1145
1146         if (mctrl)
1147                 iowrite8(mcr, priv->membase + UART_MCR);
1148 }
1149
1150 static void pch_uart_stop_tx(struct uart_port *port)
1151 {
1152         struct eg20t_port *priv;
1153         priv = container_of(port, struct eg20t_port, port);
1154         priv->start_tx = 0;
1155         priv->tx_dma_use = 0;
1156 }
1157
1158 static void pch_uart_start_tx(struct uart_port *port)
1159 {
1160         struct eg20t_port *priv;
1161
1162         priv = container_of(port, struct eg20t_port, port);
1163
1164         if (priv->use_dma) {
1165                 if (priv->tx_dma_use) {
1166                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1167                                 __func__);
1168                         return;
1169                 }
1170         }
1171
1172         priv->start_tx = 1;
1173         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1174 }
1175
1176 static void pch_uart_stop_rx(struct uart_port *port)
1177 {
1178         struct eg20t_port *priv;
1179         priv = container_of(port, struct eg20t_port, port);
1180         priv->start_rx = 0;
1181         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1182         priv->int_dis_flag = 1;
1183 }
1184
1185 /* Enable the modem status interrupts. */
1186 static void pch_uart_enable_ms(struct uart_port *port)
1187 {
1188         struct eg20t_port *priv;
1189         priv = container_of(port, struct eg20t_port, port);
1190         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1191 }
1192
1193 /* Control the transmission of a break signal. */
1194 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1195 {
1196         struct eg20t_port *priv;
1197         unsigned long flags;
1198
1199         priv = container_of(port, struct eg20t_port, port);
1200         spin_lock_irqsave(&port->lock, flags);
1201         pch_uart_hal_set_break(priv, ctl);
1202         spin_unlock_irqrestore(&port->lock, flags);
1203 }
1204
1205 /* Grab any interrupt resources and initialise any low level driver state. */
1206 static int pch_uart_startup(struct uart_port *port)
1207 {
1208         struct eg20t_port *priv;
1209         int ret;
1210         int fifo_size;
1211         int trigger_level;
1212
1213         priv = container_of(port, struct eg20t_port, port);
1214         priv->tx_empty = 1;
1215
1216         if (port->uartclk)
1217                 priv->base_baud = port->uartclk;
1218         else
1219                 port->uartclk = priv->base_baud;
1220
1221         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1222         ret = pch_uart_hal_set_line(priv, default_baud,
1223                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1224                               PCH_UART_HAL_STB1);
1225         if (ret)
1226                 return ret;
1227
1228         switch (priv->fifo_size) {
1229         case 256:
1230                 fifo_size = PCH_UART_HAL_FIFO256;
1231                 break;
1232         case 64:
1233                 fifo_size = PCH_UART_HAL_FIFO64;
1234                 break;
1235         case 16:
1236                 fifo_size = PCH_UART_HAL_FIFO16;
1237         case 1:
1238         default:
1239                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1240                 break;
1241         }
1242
1243         switch (priv->trigger) {
1244         case PCH_UART_HAL_TRIGGER1:
1245                 trigger_level = 1;
1246                 break;
1247         case PCH_UART_HAL_TRIGGER_L:
1248                 trigger_level = priv->fifo_size / 4;
1249                 break;
1250         case PCH_UART_HAL_TRIGGER_M:
1251                 trigger_level = priv->fifo_size / 2;
1252                 break;
1253         case PCH_UART_HAL_TRIGGER_H:
1254         default:
1255                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1256                 break;
1257         }
1258
1259         priv->trigger_level = trigger_level;
1260         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1261                                     fifo_size, priv->trigger);
1262         if (ret < 0)
1263                 return ret;
1264
1265         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1266                         KBUILD_MODNAME, priv);
1267         if (ret < 0)
1268                 return ret;
1269
1270         if (priv->use_dma)
1271                 pch_request_dma(port);
1272
1273         priv->start_rx = 1;
1274         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1275         uart_update_timeout(port, CS8, default_baud);
1276
1277         return 0;
1278 }
1279
1280 static void pch_uart_shutdown(struct uart_port *port)
1281 {
1282         struct eg20t_port *priv;
1283         int ret;
1284
1285         priv = container_of(port, struct eg20t_port, port);
1286         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1287         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1288         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1289                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1290         if (ret)
1291                 dev_err(priv->port.dev,
1292                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1293
1294         pch_free_dma(port);
1295
1296         free_irq(priv->port.irq, priv);
1297 }
1298
1299 /* Change the port parameters, including word length, parity, stop
1300  *bits.  Update read_status_mask and ignore_status_mask to indicate
1301  *the types of events we are interested in receiving.  */
1302 static void pch_uart_set_termios(struct uart_port *port,
1303                                  struct ktermios *termios, struct ktermios *old)
1304 {
1305         int baud;
1306         int rtn;
1307         unsigned int parity, bits, stb;
1308         struct eg20t_port *priv;
1309         unsigned long flags;
1310
1311         priv = container_of(port, struct eg20t_port, port);
1312         switch (termios->c_cflag & CSIZE) {
1313         case CS5:
1314                 bits = PCH_UART_HAL_5BIT;
1315                 break;
1316         case CS6:
1317                 bits = PCH_UART_HAL_6BIT;
1318                 break;
1319         case CS7:
1320                 bits = PCH_UART_HAL_7BIT;
1321                 break;
1322         default:                /* CS8 */
1323                 bits = PCH_UART_HAL_8BIT;
1324                 break;
1325         }
1326         if (termios->c_cflag & CSTOPB)
1327                 stb = PCH_UART_HAL_STB2;
1328         else
1329                 stb = PCH_UART_HAL_STB1;
1330
1331         if (termios->c_cflag & PARENB) {
1332                 if (!(termios->c_cflag & PARODD))
1333                         parity = PCH_UART_HAL_PARITY_ODD;
1334                 else
1335                         parity = PCH_UART_HAL_PARITY_EVEN;
1336
1337         } else
1338                 parity = PCH_UART_HAL_PARITY_NONE;
1339
1340         /* Only UART0 has auto hardware flow function */
1341         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1342                 priv->mcr |= UART_MCR_AFE;
1343         else
1344                 priv->mcr &= ~UART_MCR_AFE;
1345
1346         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1347
1348         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1349
1350         spin_lock_irqsave(&port->lock, flags);
1351
1352         uart_update_timeout(port, termios->c_cflag, baud);
1353         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1354         if (rtn)
1355                 goto out;
1356
1357         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1358         /* Don't rewrite B0 */
1359         if (tty_termios_baud_rate(termios))
1360                 tty_termios_encode_baud_rate(termios, baud, baud);
1361
1362 out:
1363         spin_unlock_irqrestore(&port->lock, flags);
1364 }
1365
1366 static const char *pch_uart_type(struct uart_port *port)
1367 {
1368         return KBUILD_MODNAME;
1369 }
1370
1371 static void pch_uart_release_port(struct uart_port *port)
1372 {
1373         struct eg20t_port *priv;
1374
1375         priv = container_of(port, struct eg20t_port, port);
1376         pci_iounmap(priv->pdev, priv->membase);
1377         pci_release_regions(priv->pdev);
1378 }
1379
1380 static int pch_uart_request_port(struct uart_port *port)
1381 {
1382         struct eg20t_port *priv;
1383         int ret;
1384         void __iomem *membase;
1385
1386         priv = container_of(port, struct eg20t_port, port);
1387         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1388         if (ret < 0)
1389                 return -EBUSY;
1390
1391         membase = pci_iomap(priv->pdev, 1, 0);
1392         if (!membase) {
1393                 pci_release_regions(priv->pdev);
1394                 return -EBUSY;
1395         }
1396         priv->membase = port->membase = membase;
1397
1398         return 0;
1399 }
1400
1401 static void pch_uart_config_port(struct uart_port *port, int type)
1402 {
1403         struct eg20t_port *priv;
1404
1405         priv = container_of(port, struct eg20t_port, port);
1406         if (type & UART_CONFIG_TYPE) {
1407                 port->type = priv->port_type;
1408                 pch_uart_request_port(port);
1409         }
1410 }
1411
1412 static int pch_uart_verify_port(struct uart_port *port,
1413                                 struct serial_struct *serinfo)
1414 {
1415         struct eg20t_port *priv;
1416
1417         priv = container_of(port, struct eg20t_port, port);
1418         if (serinfo->flags & UPF_LOW_LATENCY) {
1419                 dev_info(priv->port.dev,
1420                         "PCH UART : Use PIO Mode (without DMA)\n");
1421                 priv->use_dma = 0;
1422                 serinfo->flags &= ~UPF_LOW_LATENCY;
1423         } else {
1424 #ifndef CONFIG_PCH_DMA
1425                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1426                         __func__);
1427                 return -EOPNOTSUPP;
1428 #endif
1429                 priv->use_dma = 1;
1430                 priv->use_dma_flag = 1;
1431                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1432         }
1433
1434         return 0;
1435 }
1436
1437 static struct uart_ops pch_uart_ops = {
1438         .tx_empty = pch_uart_tx_empty,
1439         .set_mctrl = pch_uart_set_mctrl,
1440         .get_mctrl = pch_uart_get_mctrl,
1441         .stop_tx = pch_uart_stop_tx,
1442         .start_tx = pch_uart_start_tx,
1443         .stop_rx = pch_uart_stop_rx,
1444         .enable_ms = pch_uart_enable_ms,
1445         .break_ctl = pch_uart_break_ctl,
1446         .startup = pch_uart_startup,
1447         .shutdown = pch_uart_shutdown,
1448         .set_termios = pch_uart_set_termios,
1449 /*      .pm             = pch_uart_pm,          Not supported yet */
1450 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1451         .type = pch_uart_type,
1452         .release_port = pch_uart_release_port,
1453         .request_port = pch_uart_request_port,
1454         .config_port = pch_uart_config_port,
1455         .verify_port = pch_uart_verify_port
1456 };
1457
1458 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1459
1460 /*
1461  *      Wait for transmitter & holding register to empty
1462  */
1463 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1464 {
1465         unsigned int status, tmout = 10000;
1466
1467         /* Wait up to 10ms for the character(s) to be sent. */
1468         for (;;) {
1469                 status = ioread8(up->membase + UART_LSR);
1470
1471                 if ((status & bits) == bits)
1472                         break;
1473                 if (--tmout == 0)
1474                         break;
1475                 udelay(1);
1476         }
1477
1478         /* Wait up to 1s for flow control if necessary */
1479         if (up->port.flags & UPF_CONS_FLOW) {
1480                 unsigned int tmout;
1481                 for (tmout = 1000000; tmout; tmout--) {
1482                         unsigned int msr = ioread8(up->membase + UART_MSR);
1483                         if (msr & UART_MSR_CTS)
1484                                 break;
1485                         udelay(1);
1486                         touch_nmi_watchdog();
1487                 }
1488         }
1489 }
1490
1491 static void pch_console_putchar(struct uart_port *port, int ch)
1492 {
1493         struct eg20t_port *priv =
1494                 container_of(port, struct eg20t_port, port);
1495
1496         wait_for_xmitr(priv, UART_LSR_THRE);
1497         iowrite8(ch, priv->membase + PCH_UART_THR);
1498 }
1499
1500 /*
1501  *      Print a string to the serial port trying not to disturb
1502  *      any possible real use of the port...
1503  *
1504  *      The console_lock must be held when we get here.
1505  */
1506 static void
1507 pch_console_write(struct console *co, const char *s, unsigned int count)
1508 {
1509         struct eg20t_port *priv;
1510         unsigned long flags;
1511         u8 ier;
1512         int locked = 1;
1513
1514         priv = pch_uart_ports[co->index];
1515
1516         touch_nmi_watchdog();
1517
1518         local_irq_save(flags);
1519         if (priv->port.sysrq) {
1520                 /* serial8250_handle_port() already took the lock */
1521                 locked = 0;
1522         } else if (oops_in_progress) {
1523                 locked = spin_trylock(&priv->port.lock);
1524         } else
1525                 spin_lock(&priv->port.lock);
1526
1527         /*
1528          *      First save the IER then disable the interrupts
1529          */
1530         ier = ioread8(priv->membase + UART_IER);
1531
1532         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1533
1534         uart_console_write(&priv->port, s, count, pch_console_putchar);
1535
1536         /*
1537          *      Finally, wait for transmitter to become empty
1538          *      and restore the IER
1539          */
1540         wait_for_xmitr(priv, BOTH_EMPTY);
1541         iowrite8(ier, priv->membase + UART_IER);
1542
1543         if (locked)
1544                 spin_unlock(&priv->port.lock);
1545         local_irq_restore(flags);
1546 }
1547
1548 static int __init pch_console_setup(struct console *co, char *options)
1549 {
1550         struct uart_port *port;
1551         int baud = 9600;
1552         int bits = 8;
1553         int parity = 'n';
1554         int flow = 'n';
1555
1556         /*
1557          * Check whether an invalid uart number has been specified, and
1558          * if so, search for the first available port that does have
1559          * console support.
1560          */
1561         if (co->index >= PCH_UART_NR)
1562                 co->index = 0;
1563         port = &pch_uart_ports[co->index]->port;
1564
1565         if (!port || (!port->iobase && !port->membase))
1566                 return -ENODEV;
1567
1568         /* setup uartclock */
1569         port->uartclk = DEFAULT_BAUD_RATE;
1570
1571         if (options)
1572                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1573
1574         return uart_set_options(port, co, baud, parity, bits, flow);
1575 }
1576
1577 static struct uart_driver pch_uart_driver;
1578
1579 static struct console pch_console = {
1580         .name           = PCH_UART_DRIVER_DEVICE,
1581         .write          = pch_console_write,
1582         .device         = uart_console_device,
1583         .setup          = pch_console_setup,
1584         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1585         .index          = -1,
1586         .data           = &pch_uart_driver,
1587 };
1588
1589 #define PCH_CONSOLE     (&pch_console)
1590 #else
1591 #define PCH_CONSOLE     NULL
1592 #endif
1593
1594 static struct uart_driver pch_uart_driver = {
1595         .owner = THIS_MODULE,
1596         .driver_name = KBUILD_MODNAME,
1597         .dev_name = PCH_UART_DRIVER_DEVICE,
1598         .major = 0,
1599         .minor = 0,
1600         .nr = PCH_UART_NR,
1601         .cons = PCH_CONSOLE,
1602 };
1603
1604 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1605                                              const struct pci_device_id *id)
1606 {
1607         struct eg20t_port *priv;
1608         int ret;
1609         unsigned int iobase;
1610         unsigned int mapbase;
1611         unsigned char *rxbuf;
1612         int fifosize, base_baud;
1613         int port_type;
1614         struct pch_uart_driver_data *board;
1615         const char *board_name;
1616         char name[32];  /* for debugfs file name */
1617
1618         board = &drv_dat[id->driver_data];
1619         port_type = board->port_type;
1620
1621         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1622         if (priv == NULL)
1623                 goto init_port_alloc_err;
1624
1625         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1626         if (!rxbuf)
1627                 goto init_port_free_txbuf;
1628
1629         base_baud = DEFAULT_BAUD_RATE;
1630
1631         /* quirk for CM-iTC board */
1632         board_name = dmi_get_system_info(DMI_BOARD_NAME);
1633         if (board_name && strstr(board_name, "CM-iTC"))
1634                 base_baud = 192000000; /* 192.0MHz */
1635
1636         switch (port_type) {
1637         case PORT_UNKNOWN:
1638                 fifosize = 256; /* EG20T/ML7213: UART0 */
1639                 break;
1640         case PORT_8250:
1641                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1642                 break;
1643         default:
1644                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1645                 goto init_port_hal_free;
1646         }
1647
1648         pci_enable_msi(pdev);
1649
1650         iobase = pci_resource_start(pdev, 0);
1651         mapbase = pci_resource_start(pdev, 1);
1652         priv->mapbase = mapbase;
1653         priv->iobase = iobase;
1654         priv->pdev = pdev;
1655         priv->tx_empty = 1;
1656         priv->rxbuf.buf = rxbuf;
1657         priv->rxbuf.size = PAGE_SIZE;
1658
1659         priv->fifo_size = fifosize;
1660         priv->base_baud = base_baud;
1661         priv->port_type = PORT_MAX_8250 + port_type + 1;
1662         priv->port.dev = &pdev->dev;
1663         priv->port.iobase = iobase;
1664         priv->port.membase = NULL;
1665         priv->port.mapbase = mapbase;
1666         priv->port.irq = pdev->irq;
1667         priv->port.iotype = UPIO_PORT;
1668         priv->port.ops = &pch_uart_ops;
1669         priv->port.flags = UPF_BOOT_AUTOCONF;
1670         priv->port.fifosize = fifosize;
1671         priv->port.line = board->line_no;
1672         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1673
1674         spin_lock_init(&priv->port.lock);
1675
1676         pci_set_drvdata(pdev, priv);
1677         pch_uart_hal_request(pdev, fifosize, base_baud);
1678
1679 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1680         pch_uart_ports[board->line_no] = priv;
1681 #endif
1682         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1683         if (ret < 0)
1684                 goto init_port_hal_free;
1685
1686 #ifdef CONFIG_DEBUG_FS
1687         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1688         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1689                                 NULL, priv, &port_regs_ops);
1690 #endif
1691
1692         return priv;
1693
1694 init_port_hal_free:
1695 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1696         pch_uart_ports[board->line_no] = NULL;
1697 #endif
1698         free_page((unsigned long)rxbuf);
1699 init_port_free_txbuf:
1700         kfree(priv);
1701 init_port_alloc_err:
1702
1703         return NULL;
1704 }
1705
1706 static void pch_uart_exit_port(struct eg20t_port *priv)
1707 {
1708
1709 #ifdef CONFIG_DEBUG_FS
1710         if (priv->debugfs)
1711                 debugfs_remove(priv->debugfs);
1712 #endif
1713         uart_remove_one_port(&pch_uart_driver, &priv->port);
1714         pci_set_drvdata(priv->pdev, NULL);
1715         free_page((unsigned long)priv->rxbuf.buf);
1716 }
1717
1718 static void pch_uart_pci_remove(struct pci_dev *pdev)
1719 {
1720         struct eg20t_port *priv;
1721
1722         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1723
1724         pci_disable_msi(pdev);
1725
1726 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1727         pch_uart_ports[priv->port.line] = NULL;
1728 #endif
1729         pch_uart_exit_port(priv);
1730         pci_disable_device(pdev);
1731         kfree(priv);
1732         return;
1733 }
1734 #ifdef CONFIG_PM
1735 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1736 {
1737         struct eg20t_port *priv = pci_get_drvdata(pdev);
1738
1739         uart_suspend_port(&pch_uart_driver, &priv->port);
1740
1741         pci_save_state(pdev);
1742         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1743         return 0;
1744 }
1745
1746 static int pch_uart_pci_resume(struct pci_dev *pdev)
1747 {
1748         struct eg20t_port *priv = pci_get_drvdata(pdev);
1749         int ret;
1750
1751         pci_set_power_state(pdev, PCI_D0);
1752         pci_restore_state(pdev);
1753
1754         ret = pci_enable_device(pdev);
1755         if (ret) {
1756                 dev_err(&pdev->dev,
1757                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1758                 return ret;
1759         }
1760
1761         uart_resume_port(&pch_uart_driver, &priv->port);
1762
1763         return 0;
1764 }
1765 #else
1766 #define pch_uart_pci_suspend NULL
1767 #define pch_uart_pci_resume NULL
1768 #endif
1769
1770 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1771         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1772          .driver_data = pch_et20t_uart0},
1773         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1774          .driver_data = pch_et20t_uart1},
1775         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1776          .driver_data = pch_et20t_uart2},
1777         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1778          .driver_data = pch_et20t_uart3},
1779         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1780          .driver_data = pch_ml7213_uart0},
1781         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1782          .driver_data = pch_ml7213_uart1},
1783         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1784          .driver_data = pch_ml7213_uart2},
1785         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1786          .driver_data = pch_ml7223_uart0},
1787         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1788          .driver_data = pch_ml7223_uart1},
1789         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1790          .driver_data = pch_ml7831_uart0},
1791         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1792          .driver_data = pch_ml7831_uart1},
1793         {0,},
1794 };
1795
1796 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1797                                         const struct pci_device_id *id)
1798 {
1799         int ret;
1800         struct eg20t_port *priv;
1801
1802         ret = pci_enable_device(pdev);
1803         if (ret < 0)
1804                 goto probe_error;
1805
1806         priv = pch_uart_init_port(pdev, id);
1807         if (!priv) {
1808                 ret = -EBUSY;
1809                 goto probe_disable_device;
1810         }
1811         pci_set_drvdata(pdev, priv);
1812
1813         return ret;
1814
1815 probe_disable_device:
1816         pci_disable_msi(pdev);
1817         pci_disable_device(pdev);
1818 probe_error:
1819         return ret;
1820 }
1821
1822 static struct pci_driver pch_uart_pci_driver = {
1823         .name = "pch_uart",
1824         .id_table = pch_uart_pci_id,
1825         .probe = pch_uart_pci_probe,
1826         .remove = __devexit_p(pch_uart_pci_remove),
1827         .suspend = pch_uart_pci_suspend,
1828         .resume = pch_uart_pci_resume,
1829 };
1830
1831 static int __init pch_uart_module_init(void)
1832 {
1833         int ret;
1834
1835         /* register as UART driver */
1836         ret = uart_register_driver(&pch_uart_driver);
1837         if (ret < 0)
1838                 return ret;
1839
1840         /* register as PCI driver */
1841         ret = pci_register_driver(&pch_uart_pci_driver);
1842         if (ret < 0)
1843                 uart_unregister_driver(&pch_uart_driver);
1844
1845         return ret;
1846 }
1847 module_init(pch_uart_module_init);
1848
1849 static void __exit pch_uart_module_exit(void)
1850 {
1851         pci_unregister_driver(&pch_uart_pci_driver);
1852         uart_unregister_driver(&pch_uart_driver);
1853 }
1854 module_exit(pch_uart_module_exit);
1855
1856 MODULE_LICENSE("GPL v2");
1857 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1858 module_param(default_baud, uint, S_IRUGO);