drivers/tty/serial/owl-uart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Actions Semi Owl family serial console
   4  *
   5  * Copyright 2013 Actions Semi Inc.
   6  * Author: Actions Semi, Inc.
   7  *
   8  * Copyright (c) 2016-2017 Andreas Färber
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/serial.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35
  36 #define OWL_UART_PORT_NUM 7
  37 #define OWL_UART_DEV_NAME "ttyOWL"
  38
  39 #define OWL_UART_CTL    0x000
  40 #define OWL_UART_RXDAT  0x004
  41 #define OWL_UART_TXDAT  0x008
  42 #define OWL_UART_STAT   0x00c
  43
  44 #define OWL_UART_CTL_DWLS_MASK          GENMASK(1, 0)
  45 #define OWL_UART_CTL_DWLS_5BITS         (0x0 << 0)
  46 #define OWL_UART_CTL_DWLS_6BITS         (0x1 << 0)
  47 #define OWL_UART_CTL_DWLS_7BITS         (0x2 << 0)
  48 #define OWL_UART_CTL_DWLS_8BITS         (0x3 << 0)
  49 #define OWL_UART_CTL_STPS_2BITS         BIT(2)
  50 #define OWL_UART_CTL_PRS_MASK           GENMASK(6, 4)
  51 #define OWL_UART_CTL_PRS_NONE           (0x0 << 4)
  52 #define OWL_UART_CTL_PRS_ODD            (0x4 << 4)
  53 #define OWL_UART_CTL_PRS_MARK           (0x5 << 4)
  54 #define OWL_UART_CTL_PRS_EVEN           (0x6 << 4)
  55 #define OWL_UART_CTL_PRS_SPACE          (0x7 << 4)
  56 #define OWL_UART_CTL_AFE                BIT(12)
  57 #define OWL_UART_CTL_TRFS_TX            BIT(14)
  58 #define OWL_UART_CTL_EN                 BIT(15)
  59 #define OWL_UART_CTL_RXDE               BIT(16)
  60 #define OWL_UART_CTL_TXDE               BIT(17)
  61 #define OWL_UART_CTL_RXIE               BIT(18)
  62 #define OWL_UART_CTL_TXIE               BIT(19)
  63 #define OWL_UART_CTL_LBEN               BIT(20)
  64
  65 #define OWL_UART_STAT_RIP               BIT(0)
  66 #define OWL_UART_STAT_TIP               BIT(1)
  67 #define OWL_UART_STAT_RXER              BIT(2)
  68 #define OWL_UART_STAT_TFER              BIT(3)
  69 #define OWL_UART_STAT_RXST              BIT(4)
  70 #define OWL_UART_STAT_RFEM              BIT(5)
  71 #define OWL_UART_STAT_TFFU              BIT(6)
  72 #define OWL_UART_STAT_CTSS              BIT(7)
  73 #define OWL_UART_STAT_RTSS              BIT(8)
  74 #define OWL_UART_STAT_TFES              BIT(10)
  75 #define OWL_UART_STAT_TRFL_MASK         GENMASK(16, 11)
  76 #define OWL_UART_STAT_UTBB              BIT(17)
  77
  78 static struct uart_driver owl_uart_driver;
  79
  80 struct owl_uart_info {
  81         unsigned int tx_fifosize;
  82 };
  83
  84 struct owl_uart_port {
  85         struct uart_port port;
  86         struct clk *clk;
  87 };
  88
  89 #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
  90
  91 static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
  92
  93 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
  94 {
  95         writel(val, port->membase + off);
  96 }
  97
  98 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
  99 {
 100         return readl(port->membase + off);
 101 }
 102
 103 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 104 {
 105         u32 ctl;
 106
 107         ctl = owl_uart_read(port, OWL_UART_CTL);
 108
 109         if (mctrl & TIOCM_LOOP)
 110                 ctl |= OWL_UART_CTL_LBEN;
 111         else
 112                 ctl &= ~OWL_UART_CTL_LBEN;
 113
 114         owl_uart_write(port, ctl, OWL_UART_CTL);
 115 }
 116
 117 static unsigned int owl_uart_get_mctrl(struct uart_port *port)
 118 {
 119         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
 120         u32 stat, ctl;
 121
 122         ctl = owl_uart_read(port, OWL_UART_CTL);
 123         stat = owl_uart_read(port, OWL_UART_STAT);
 124         if (stat & OWL_UART_STAT_RTSS)
 125                 mctrl |= TIOCM_RTS;
 126         if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
 127                 mctrl |= TIOCM_CTS;
 128         return mctrl;
 129 }
 130
 131 static unsigned int owl_uart_tx_empty(struct uart_port *port)
 132 {
 133         unsigned long flags;
 134         u32 val;
 135         unsigned int ret;
 136
 137         spin_lock_irqsave(&port->lock, flags);
 138
 139         val = owl_uart_read(port, OWL_UART_STAT);
 140         ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
 141
 142         spin_unlock_irqrestore(&port->lock, flags);
 143
 144         return ret;
 145 }
 146
 147 static void owl_uart_stop_rx(struct uart_port *port)
 148 {
 149         u32 val;
 150
 151         val = owl_uart_read(port, OWL_UART_CTL);
 152         val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
 153         owl_uart_write(port, val, OWL_UART_CTL);
 154
 155         val = owl_uart_read(port, OWL_UART_STAT);
 156         val |= OWL_UART_STAT_RIP;
 157         owl_uart_write(port, val, OWL_UART_STAT);
 158 }
 159
 160 static void owl_uart_stop_tx(struct uart_port *port)
 161 {
 162         u32 val;
 163
 164         val = owl_uart_read(port, OWL_UART_CTL);
 165         val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
 166         owl_uart_write(port, val, OWL_UART_CTL);
 167
 168         val = owl_uart_read(port, OWL_UART_STAT);
 169         val |= OWL_UART_STAT_TIP;
 170         owl_uart_write(port, val, OWL_UART_STAT);
 171 }
 172
 173 static void owl_uart_start_tx(struct uart_port *port)
 174 {
 175         u32 val;
 176
 177         if (uart_tx_stopped(port)) {
 178                 owl_uart_stop_tx(port);
 179                 return;
 180         }
 181
 182         val = owl_uart_read(port, OWL_UART_STAT);
 183         val |= OWL_UART_STAT_TIP;
 184         owl_uart_write(port, val, OWL_UART_STAT);
 185
 186         val = owl_uart_read(port, OWL_UART_CTL);
 187         val |= OWL_UART_CTL_TXIE;
 188         owl_uart_write(port, val, OWL_UART_CTL);
 189 }
 190
 191 static void owl_uart_send_chars(struct uart_port *port)
 192 {
 193         struct circ_buf *xmit = &port->state->xmit;
 194         unsigned int ch;
 195
 196         if (uart_tx_stopped(port))
 197                 return;
 198
 199         if (port->x_char) {
 200                 while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
 201                         cpu_relax();
 202                 owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
 203                 port->icount.tx++;
 204                 port->x_char = 0;
 205         }
 206
 207         while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
 208                 if (uart_circ_empty(xmit))
 209                         break;
 210
 211                 ch = xmit->buf[xmit->tail];
 212                 owl_uart_write(port, ch, OWL_UART_TXDAT);
 213                 xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
 214                 port->icount.tx++;
 215         }
 216
 217         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 218                 uart_write_wakeup(port);
 219
 220         if (uart_circ_empty(xmit))
 221                 owl_uart_stop_tx(port);
 222 }
 223
 224 static void owl_uart_receive_chars(struct uart_port *port)
 225 {
 226         u32 stat, val;
 227
 228         val = owl_uart_read(port, OWL_UART_CTL);
 229         val &= ~OWL_UART_CTL_TRFS_TX;
 230         owl_uart_write(port, val, OWL_UART_CTL);
 231
 232         stat = owl_uart_read(port, OWL_UART_STAT);
 233         while (!(stat & OWL_UART_STAT_RFEM)) {
 234                 char flag = TTY_NORMAL;
 235
 236                 if (stat & OWL_UART_STAT_RXER)
 237                         port->icount.overrun++;
 238
 239                 if (stat & OWL_UART_STAT_RXST) {
 240                         /* We are not able to distinguish the error type. */
 241                         port->icount.brk++;
 242                         port->icount.frame++;
 243
 244                         stat &= port->read_status_mask;
 245                         if (stat & OWL_UART_STAT_RXST)
 246                                 flag = TTY_PARITY;
 247                 } else
 248                         port->icount.rx++;
 249
 250                 val = owl_uart_read(port, OWL_UART_RXDAT);
 251                 val &= 0xff;
 252
 253                 if ((stat & port->ignore_status_mask) == 0)
 254                         tty_insert_flip_char(&port->state->port, val, flag);
 255
 256                 stat = owl_uart_read(port, OWL_UART_STAT);
 257         }
 258
 259         spin_unlock(&port->lock);
 260         tty_flip_buffer_push(&port->state->port);
 261         spin_lock(&port->lock);
 262 }
 263
 264 static irqreturn_t owl_uart_irq(int irq, void *dev_id)
 265 {
 266         struct uart_port *port = dev_id;
 267         unsigned long flags;
 268         u32 stat;
 269
 270         spin_lock_irqsave(&port->lock, flags);
 271
 272         stat = owl_uart_read(port, OWL_UART_STAT);
 273
 274         if (stat & OWL_UART_STAT_RIP)
 275                 owl_uart_receive_chars(port);
 276
 277         if (stat & OWL_UART_STAT_TIP)
 278                 owl_uart_send_chars(port);
 279
 280         stat = owl_uart_read(port, OWL_UART_STAT);
 281         stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
 282         owl_uart_write(port, stat, OWL_UART_STAT);
 283
 284         spin_unlock_irqrestore(&port->lock, flags);
 285
 286         return IRQ_HANDLED;
 287 }
 288
 289 static void owl_uart_shutdown(struct uart_port *port)
 290 {
 291         u32 val;
 292         unsigned long flags;
 293
 294         spin_lock_irqsave(&port->lock, flags);
 295
 296         val = owl_uart_read(port, OWL_UART_CTL);
 297         val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
 298                 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
 299         owl_uart_write(port, val, OWL_UART_CTL);
 300
 301         spin_unlock_irqrestore(&port->lock, flags);
 302
 303         free_irq(port->irq, port);
 304 }
 305
 306 static int owl_uart_startup(struct uart_port *port)
 307 {
 308         u32 val;
 309         unsigned long flags;
 310         int ret;
 311
 312         ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
 313                         "owl-uart", port);
 314         if (ret)
 315                 return ret;
 316
 317         spin_lock_irqsave(&port->lock, flags);
 318
 319         val = owl_uart_read(port, OWL_UART_STAT);
 320         val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
 321                 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
 322         owl_uart_write(port, val, OWL_UART_STAT);
 323
 324         val = owl_uart_read(port, OWL_UART_CTL);
 325         val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
 326         val |= OWL_UART_CTL_EN;
 327         owl_uart_write(port, val, OWL_UART_CTL);
 328
 329         spin_unlock_irqrestore(&port->lock, flags);
 330
 331         return 0;
 332 }
 333
 334 static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
 335                                      unsigned long baud)
 336 {
 337         clk_set_rate(owl_port->clk, baud * 8);
 338 }
 339
 340 static void owl_uart_set_termios(struct uart_port *port,
 341                                  struct ktermios *termios,
 342                                  struct ktermios *old)
 343 {
 344         struct owl_uart_port *owl_port = to_owl_uart_port(port);
 345         unsigned int baud;
 346         u32 ctl;
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&port->lock, flags);
 350
 351         ctl = owl_uart_read(port, OWL_UART_CTL);
 352
 353         ctl &= ~OWL_UART_CTL_DWLS_MASK;
 354         switch (termios->c_cflag & CSIZE) {
 355         case CS5:
 356                 ctl |= OWL_UART_CTL_DWLS_5BITS;
 357                 break;
 358         case CS6:
 359                 ctl |= OWL_UART_CTL_DWLS_6BITS;
 360                 break;
 361         case CS7:
 362                 ctl |= OWL_UART_CTL_DWLS_7BITS;
 363                 break;
 364         case CS8:
 365         default:
 366                 ctl |= OWL_UART_CTL_DWLS_8BITS;
 367                 break;
 368         }
 369
 370         if (termios->c_cflag & CSTOPB)
 371                 ctl |= OWL_UART_CTL_STPS_2BITS;
 372         else
 373                 ctl &= ~OWL_UART_CTL_STPS_2BITS;
 374
 375         ctl &= ~OWL_UART_CTL_PRS_MASK;
 376         if (termios->c_cflag & PARENB) {
 377                 if (termios->c_cflag & CMSPAR) {
 378                         if (termios->c_cflag & PARODD)
 379                                 ctl |= OWL_UART_CTL_PRS_MARK;
 380                         else
 381                                 ctl |= OWL_UART_CTL_PRS_SPACE;
 382                 } else if (termios->c_cflag & PARODD)
 383                         ctl |= OWL_UART_CTL_PRS_ODD;
 384                 else
 385                         ctl |= OWL_UART_CTL_PRS_EVEN;
 386         } else
 387                 ctl |= OWL_UART_CTL_PRS_NONE;
 388
 389         if (termios->c_cflag & CRTSCTS)
 390                 ctl |= OWL_UART_CTL_AFE;
 391         else
 392                 ctl &= ~OWL_UART_CTL_AFE;
 393
 394         owl_uart_write(port, ctl, OWL_UART_CTL);
 395
 396         baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
 397         owl_uart_change_baudrate(owl_port, baud);
 398
 399         /* Don't rewrite B0 */
 400         if (tty_termios_baud_rate(termios))
 401                 tty_termios_encode_baud_rate(termios, baud, baud);
 402
 403         port->read_status_mask |= OWL_UART_STAT_RXER;
 404         if (termios->c_iflag & INPCK)
 405                 port->read_status_mask |= OWL_UART_STAT_RXST;
 406
 407         uart_update_timeout(port, termios->c_cflag, baud);
 408
 409         spin_unlock_irqrestore(&port->lock, flags);
 410 }
 411
 412 static void owl_uart_release_port(struct uart_port *port)
 413 {
 414         struct platform_device *pdev = to_platform_device(port->dev);
 415         struct resource *res;
 416
 417         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 418         if (!res)
 419                 return;
 420
 421         if (port->flags & UPF_IOREMAP) {
 422                 devm_release_mem_region(port->dev, port->mapbase,
 423                         resource_size(res));
 424                 devm_iounmap(port->dev, port->membase);
 425                 port->membase = NULL;
 426         }
 427 }
 428
 429 static int owl_uart_request_port(struct uart_port *port)
 430 {
 431         struct platform_device *pdev = to_platform_device(port->dev);
 432         struct resource *res;
 433
 434         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 435         if (!res)
 436                 return -ENXIO;
 437
 438         if (!devm_request_mem_region(port->dev, port->mapbase,
 439                         resource_size(res), dev_name(port->dev)))
 440                 return -EBUSY;
 441
 442         if (port->flags & UPF_IOREMAP) {
 443                 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
 444                                 resource_size(res));
 445                 if (!port->membase)
 446                         return -EBUSY;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static const char *owl_uart_type(struct uart_port *port)
 453 {
 454         return (port->type == PORT_OWL) ? "owl-uart" : NULL;
 455 }
 456
 457 static int owl_uart_verify_port(struct uart_port *port,
 458                                 struct serial_struct *ser)
 459 {
 460         if (port->type != PORT_OWL)
 461                 return -EINVAL;
 462
 463         if (port->irq != ser->irq)
 464                 return -EINVAL;
 465
 466         return 0;
 467 }
 468
 469 static void owl_uart_config_port(struct uart_port *port, int flags)
 470 {
 471         if (flags & UART_CONFIG_TYPE) {
 472                 port->type = PORT_OWL;
 473                 owl_uart_request_port(port);
 474         }
 475 }
 476
 477 static const struct uart_ops owl_uart_ops = {
 478         .set_mctrl = owl_uart_set_mctrl,
 479         .get_mctrl = owl_uart_get_mctrl,
 480         .tx_empty = owl_uart_tx_empty,
 481         .start_tx = owl_uart_start_tx,
 482         .stop_rx = owl_uart_stop_rx,
 483         .stop_tx = owl_uart_stop_tx,
 484         .startup = owl_uart_startup,
 485         .shutdown = owl_uart_shutdown,
 486         .set_termios = owl_uart_set_termios,
 487         .type = owl_uart_type,
 488         .config_port = owl_uart_config_port,
 489         .request_port = owl_uart_request_port,
 490         .release_port = owl_uart_release_port,
 491         .verify_port = owl_uart_verify_port,
 492 };
 493
 494 #ifdef CONFIG_SERIAL_OWL_CONSOLE
 495
 496 static void owl_console_putchar(struct uart_port *port, int ch)
 497 {
 498         if (!port->membase)
 499                 return;
 500
 501         while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
 502                 cpu_relax();
 503
 504         owl_uart_write(port, ch, OWL_UART_TXDAT);
 505 }
 506
 507 static void owl_uart_port_write(struct uart_port *port, const char *s,
 508                                 u_int count)
 509 {
 510         u32 old_ctl, val;
 511         unsigned long flags;
 512         int locked;
 513
 514         local_irq_save(flags);
 515
 516         if (port->sysrq)
 517                 locked = 0;
 518         else if (oops_in_progress)
 519                 locked = spin_trylock(&port->lock);
 520         else {
 521                 spin_lock(&port->lock);
 522                 locked = 1;
 523         }
 524
 525         old_ctl = owl_uart_read(port, OWL_UART_CTL);
 526         val = old_ctl | OWL_UART_CTL_TRFS_TX;
 527         /* disable IRQ */
 528         val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
 529         owl_uart_write(port, val, OWL_UART_CTL);
 530
 531         uart_console_write(port, s, count, owl_console_putchar);
 532
 533         /* wait until all contents have been sent out */
 534         while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
 535                 cpu_relax();
 536
 537         /* clear IRQ pending */
 538         val = owl_uart_read(port, OWL_UART_STAT);
 539         val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
 540         owl_uart_write(port, val, OWL_UART_STAT);
 541
 542         owl_uart_write(port, old_ctl, OWL_UART_CTL);
 543
 544         if (locked)
 545                 spin_unlock(&port->lock);
 546
 547         local_irq_restore(flags);
 548 }
 549
 550 static void owl_uart_console_write(struct console *co, const char *s,
 551                                    u_int count)
 552 {
 553         struct owl_uart_port *owl_port;
 554
 555         owl_port = owl_uart_ports[co->index];
 556         if (!owl_port)
 557                 return;
 558
 559         owl_uart_port_write(&owl_port->port, s, count);
 560 }
 561
 562 static int owl_uart_console_setup(struct console *co, char *options)
 563 {
 564         struct owl_uart_port *owl_port;
 565         int baud = 115200;
 566         int bits = 8;
 567         int parity = 'n';
 568         int flow = 'n';
 569
 570         if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
 571                 return -EINVAL;
 572
 573         owl_port = owl_uart_ports[co->index];
 574         if (!owl_port || !owl_port->port.membase)
 575                 return -ENODEV;
 576
 577         if (options)
 578                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 579
 580         return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
 581 }
 582
 583 static struct console owl_uart_console = {
 584         .name = OWL_UART_DEV_NAME,
 585         .write = owl_uart_console_write,
 586         .device = uart_console_device,
 587         .setup = owl_uart_console_setup,
 588         .flags = CON_PRINTBUFFER,
 589         .index = -1,
 590         .data = &owl_uart_driver,
 591 };
 592
 593 static int __init owl_uart_console_init(void)
 594 {
 595         register_console(&owl_uart_console);
 596
 597         return 0;
 598 }
 599 console_initcall(owl_uart_console_init);
 600
 601 static void owl_uart_early_console_write(struct console *co,
 602                                          const char *s,
 603                                          u_int count)
 604 {
 605         struct earlycon_device *dev = co->data;
 606
 607         owl_uart_port_write(&dev->port, s, count);
 608 }
 609
 610 static int __init
 611 owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
 612 {
 613         if (!device->port.membase)
 614                 return -ENODEV;
 615
 616         device->con->write = owl_uart_early_console_write;
 617
 618         return 0;
 619 }
 620 OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
 621                     owl_uart_early_console_setup);
 622
 623 #define OWL_UART_CONSOLE (&owl_uart_console)
 624 #else
 625 #define OWL_UART_CONSOLE NULL
 626 #endif
 627
 628 static struct uart_driver owl_uart_driver = {
 629         .owner = THIS_MODULE,
 630         .driver_name = "owl-uart",
 631         .dev_name = OWL_UART_DEV_NAME,
 632         .nr = OWL_UART_PORT_NUM,
 633         .cons = OWL_UART_CONSOLE,
 634 };
 635
 636 static const struct owl_uart_info owl_s500_info = {
 637         .tx_fifosize = 16,
 638 };
 639
 640 static const struct owl_uart_info owl_s900_info = {
 641         .tx_fifosize = 32,
 642 };
 643
 644 static const struct of_device_id owl_uart_dt_matches[] = {
 645         { .compatible = "actions,s500-uart", .data = &owl_s500_info },
 646         { .compatible = "actions,s900-uart", .data = &owl_s900_info },
 647         { }
 648 };
 649 MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
 650
 651 static int owl_uart_probe(struct platform_device *pdev)
 652 {
 653         const struct of_device_id *match;
 654         const struct owl_uart_info *info = NULL;
 655         struct resource *res_mem;
 656         struct owl_uart_port *owl_port;
 657         int ret, irq;
 658
 659         if (pdev->dev.of_node) {
 660                 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
 661                 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
 662                 if (match)
 663                         info = match->data;
 664         }
 665
 666         if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
 667                 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
 668                 return -EINVAL;
 669         }
 670
 671         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 672         if (!res_mem) {
 673                 dev_err(&pdev->dev, "could not get mem\n");
 674                 return -ENODEV;
 675         }
 676
 677         irq = platform_get_irq(pdev, 0);
 678         if (irq < 0) {
 679                 dev_err(&pdev->dev, "could not get irq\n");
 680                 return irq;
 681         }
 682
 683         if (owl_uart_ports[pdev->id]) {
 684                 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
 685                 return -EBUSY;
 686         }
 687
 688         owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
 689         if (!owl_port)
 690                 return -ENOMEM;
 691
 692         owl_port->clk = devm_clk_get(&pdev->dev, NULL);
 693         if (IS_ERR(owl_port->clk)) {
 694                 dev_err(&pdev->dev, "could not get clk\n");
 695                 return PTR_ERR(owl_port->clk);
 696         }
 697
 698         owl_port->port.dev = &pdev->dev;
 699         owl_port->port.line = pdev->id;
 700         owl_port->port.type = PORT_OWL;
 701         owl_port->port.iotype = UPIO_MEM;
 702         owl_port->port.mapbase = res_mem->start;
 703         owl_port->port.irq = irq;
 704         owl_port->port.uartclk = clk_get_rate(owl_port->clk);
 705         if (owl_port->port.uartclk == 0) {
 706                 dev_err(&pdev->dev, "clock rate is zero\n");
 707                 return -EINVAL;
 708         }
 709         owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
 710         owl_port->port.x_char = 0;
 711         owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
 712         owl_port->port.ops = &owl_uart_ops;
 713
 714         owl_uart_ports[pdev->id] = owl_port;
 715         platform_set_drvdata(pdev, owl_port);
 716
 717         ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
 718         if (ret)
 719                 owl_uart_ports[pdev->id] = NULL;
 720
 721         return ret;
 722 }
 723
 724 static int owl_uart_remove(struct platform_device *pdev)
 725 {
 726         struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
 727
 728         uart_remove_one_port(&owl_uart_driver, &owl_port->port);
 729         owl_uart_ports[pdev->id] = NULL;
 730
 731         return 0;
 732 }
 733
 734 static struct platform_driver owl_uart_platform_driver = {
 735         .probe = owl_uart_probe,
 736         .remove = owl_uart_remove,
 737         .driver = {
 738                 .name = "owl-uart",
 739                 .of_match_table = owl_uart_dt_matches,
 740         },
 741 };
 742
 743 static int __init owl_uart_init(void)
 744 {
 745         int ret;
 746
 747         ret = uart_register_driver(&owl_uart_driver);
 748         if (ret)
 749                 return ret;
 750
 751         ret = platform_driver_register(&owl_uart_platform_driver);
 752         if (ret)
 753                 uart_unregister_driver(&owl_uart_driver);
 754
 755         return ret;
 756 }
 757
 758 static void __init owl_uart_exit(void)
 759 {
 760         platform_driver_unregister(&owl_uart_platform_driver);
 761         uart_unregister_driver(&owl_uart_driver);
 762 }
 763
 764 module_init(owl_uart_init);
 765 module_exit(owl_uart_exit);
 766
 767 MODULE_LICENSE("GPL");