2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/gpio.h>
45 #include <plat/dmtimer.h>
46 #include <plat/omap-serial.h>
48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
50 #define OMAP_UART_REV_42 0x0402
51 #define OMAP_UART_REV_46 0x0406
52 #define OMAP_UART_REV_52 0x0502
53 #define OMAP_UART_REV_63 0x0603
55 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
57 /* SCR register bitmasks */
58 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
60 /* FCR register bitmasks */
61 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
62 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
64 /* MVR register bitmasks */
65 #define OMAP_UART_MVR_SCHEME_SHIFT 30
67 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
68 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
69 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
71 #define OMAP_UART_MVR_MAJ_MASK 0x700
72 #define OMAP_UART_MVR_MAJ_SHIFT 8
73 #define OMAP_UART_MVR_MIN_MASK 0x3f
75 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
77 /* Forward declaration of functions */
78 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
79 static void serial_omap_rxdma_poll(unsigned long uart_no);
80 static int serial_omap_start_rxdma(struct uart_omap_port *up);
81 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
83 static struct workqueue_struct *serial_omap_uart_wq;
85 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
87 offset <<= up->port.regshift;
88 return readw(up->port.membase + offset);
91 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
93 offset <<= up->port.regshift;
94 writew(value, up->port.membase + offset);
97 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
99 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
100 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
101 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
102 serial_out(up, UART_FCR, 0);
106 * serial_omap_get_divisor - calculate divisor value
107 * @port: uart port info
108 * @baud: baudrate for which divisor needs to be calculated.
110 * We have written our own function to get the divisor so as to support
111 * 13x mode. 3Mbps Baudrate as an different divisor.
112 * Reference OMAP TRM Chapter 17:
113 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
114 * referring to oversampling - divisor value
115 * baudrate 460,800 to 3,686,400 all have divisor 13
116 * except 3,000,000 which has divisor value 16
119 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
121 unsigned int divisor;
123 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
127 return port->uartclk/(baud * divisor);
130 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
132 if (up->uart_dma.rx_dma_used) {
133 del_timer(&up->uart_dma.rx_timer);
134 omap_stop_dma(up->uart_dma.rx_dma_channel);
135 omap_free_dma(up->uart_dma.rx_dma_channel);
136 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
137 up->uart_dma.rx_dma_used = false;
138 pm_runtime_mark_last_busy(&up->pdev->dev);
139 pm_runtime_put_autosuspend(&up->pdev->dev);
143 static void serial_omap_enable_ms(struct uart_port *port)
145 struct uart_omap_port *up = (struct uart_omap_port *)port;
147 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
149 pm_runtime_get_sync(&up->pdev->dev);
150 up->ier |= UART_IER_MSI;
151 serial_out(up, UART_IER, up->ier);
152 pm_runtime_put(&up->pdev->dev);
155 static void serial_omap_stop_tx(struct uart_port *port)
157 struct uart_omap_port *up = (struct uart_omap_port *)port;
158 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
161 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
163 * Check if dma is still active. If yes do nothing,
164 * return. Else stop dma
166 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
168 omap_stop_dma(up->uart_dma.tx_dma_channel);
169 omap_free_dma(up->uart_dma.tx_dma_channel);
170 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
171 pm_runtime_mark_last_busy(&up->pdev->dev);
172 pm_runtime_put_autosuspend(&up->pdev->dev);
175 pm_runtime_get_sync(&up->pdev->dev);
176 if (up->ier & UART_IER_THRI) {
177 up->ier &= ~UART_IER_THRI;
178 serial_out(up, UART_IER, up->ier);
181 if (!up->use_dma && pdata && pdata->set_forceidle)
182 pdata->set_forceidle(up->pdev);
184 pm_runtime_mark_last_busy(&up->pdev->dev);
185 pm_runtime_put_autosuspend(&up->pdev->dev);
188 static void serial_omap_stop_rx(struct uart_port *port)
190 struct uart_omap_port *up = (struct uart_omap_port *)port;
192 pm_runtime_get_sync(&up->pdev->dev);
194 serial_omap_stop_rxdma(up);
195 up->ier &= ~UART_IER_RLSI;
196 up->port.read_status_mask &= ~UART_LSR_DR;
197 serial_out(up, UART_IER, up->ier);
198 pm_runtime_mark_last_busy(&up->pdev->dev);
199 pm_runtime_put_autosuspend(&up->pdev->dev);
202 static inline void receive_chars(struct uart_omap_port *up,
203 unsigned int *status)
205 struct tty_struct *tty = up->port.state->port.tty;
206 unsigned int flag, lsr = *status;
207 unsigned char ch = 0;
211 if (likely(lsr & UART_LSR_DR))
212 ch = serial_in(up, UART_RX);
214 up->port.icount.rx++;
216 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
218 * For statistics only
220 if (lsr & UART_LSR_BI) {
221 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
222 up->port.icount.brk++;
224 * We do the SysRQ and SAK checking
225 * here because otherwise the break
226 * may get masked by ignore_status_mask
227 * or read_status_mask.
229 if (uart_handle_break(&up->port))
231 } else if (lsr & UART_LSR_PE) {
232 up->port.icount.parity++;
233 } else if (lsr & UART_LSR_FE) {
234 up->port.icount.frame++;
237 if (lsr & UART_LSR_OE)
238 up->port.icount.overrun++;
241 * Mask off conditions which should be ignored.
243 lsr &= up->port.read_status_mask;
245 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
246 if (up->port.line == up->port.cons->index) {
247 /* Recover the break flag from console xmit */
248 lsr |= up->lsr_break_flag;
251 if (lsr & UART_LSR_BI)
253 else if (lsr & UART_LSR_PE)
255 else if (lsr & UART_LSR_FE)
259 if (uart_handle_sysrq_char(&up->port, ch))
261 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
263 lsr = serial_in(up, UART_LSR);
264 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
265 spin_unlock(&up->port.lock);
266 tty_flip_buffer_push(tty);
267 spin_lock(&up->port.lock);
270 static void transmit_chars(struct uart_omap_port *up)
272 struct circ_buf *xmit = &up->port.state->xmit;
275 if (up->port.x_char) {
276 serial_out(up, UART_TX, up->port.x_char);
277 up->port.icount.tx++;
281 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
282 serial_omap_stop_tx(&up->port);
285 count = up->port.fifosize / 4;
287 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
288 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
289 up->port.icount.tx++;
290 if (uart_circ_empty(xmit))
292 } while (--count > 0);
294 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
295 uart_write_wakeup(&up->port);
297 if (uart_circ_empty(xmit))
298 serial_omap_stop_tx(&up->port);
301 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
303 if (!(up->ier & UART_IER_THRI)) {
304 up->ier |= UART_IER_THRI;
305 serial_out(up, UART_IER, up->ier);
309 static void serial_omap_start_tx(struct uart_port *port)
311 struct uart_omap_port *up = (struct uart_omap_port *)port;
312 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
313 struct circ_buf *xmit;
318 pm_runtime_get_sync(&up->pdev->dev);
319 serial_omap_enable_ier_thri(up);
320 if (pdata && pdata->set_noidle)
321 pdata->set_noidle(up->pdev);
322 pm_runtime_mark_last_busy(&up->pdev->dev);
323 pm_runtime_put_autosuspend(&up->pdev->dev);
327 if (up->uart_dma.tx_dma_used)
330 xmit = &up->port.state->xmit;
332 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
333 pm_runtime_get_sync(&up->pdev->dev);
334 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
336 (void *)uart_tx_dma_callback, up,
337 &(up->uart_dma.tx_dma_channel));
340 serial_omap_enable_ier_thri(up);
344 spin_lock(&(up->uart_dma.tx_lock));
345 up->uart_dma.tx_dma_used = true;
346 spin_unlock(&(up->uart_dma.tx_lock));
348 start = up->uart_dma.tx_buf_dma_phys +
349 (xmit->tail & (UART_XMIT_SIZE - 1));
351 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
353 * It is a circular buffer. See if the buffer has wounded back.
354 * If yes it will have to be transferred in two separate dma
357 if (start + up->uart_dma.tx_buf_size >=
358 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
359 up->uart_dma.tx_buf_size =
360 (up->uart_dma.tx_buf_dma_phys +
361 UART_XMIT_SIZE) - start;
363 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
364 OMAP_DMA_AMODE_CONSTANT,
365 up->uart_dma.uart_base, 0, 0);
366 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
367 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
368 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
369 OMAP_DMA_DATA_TYPE_S8,
370 up->uart_dma.tx_buf_size, 1,
371 OMAP_DMA_SYNC_ELEMENT,
372 up->uart_dma.uart_dma_tx, 0);
373 /* FIXME: Cache maintenance needed here? */
374 omap_start_dma(up->uart_dma.tx_dma_channel);
377 static unsigned int check_modem_status(struct uart_omap_port *up)
381 status = serial_in(up, UART_MSR);
382 status |= up->msr_saved_flags;
383 up->msr_saved_flags = 0;
384 if ((status & UART_MSR_ANY_DELTA) == 0)
387 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
388 up->port.state != NULL) {
389 if (status & UART_MSR_TERI)
390 up->port.icount.rng++;
391 if (status & UART_MSR_DDSR)
392 up->port.icount.dsr++;
393 if (status & UART_MSR_DDCD)
394 uart_handle_dcd_change
395 (&up->port, status & UART_MSR_DCD);
396 if (status & UART_MSR_DCTS)
397 uart_handle_cts_change
398 (&up->port, status & UART_MSR_CTS);
399 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
406 * serial_omap_irq() - This handles the interrupt from one port
407 * @irq: uart port irq number
408 * @dev_id: uart port info
410 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
412 struct uart_omap_port *up = dev_id;
413 unsigned int iir, lsr;
416 pm_runtime_get_sync(&up->pdev->dev);
417 iir = serial_in(up, UART_IIR);
418 if (iir & UART_IIR_NO_INT) {
419 pm_runtime_mark_last_busy(&up->pdev->dev);
420 pm_runtime_put_autosuspend(&up->pdev->dev);
424 spin_lock_irqsave(&up->port.lock, flags);
425 lsr = serial_in(up, UART_LSR);
426 if (iir & UART_IIR_RLSI) {
428 if (lsr & UART_LSR_DR)
429 receive_chars(up, &lsr);
431 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
432 serial_out(up, UART_IER, up->ier);
433 if ((serial_omap_start_rxdma(up) != 0) &&
435 receive_chars(up, &lsr);
439 check_modem_status(up);
440 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
443 spin_unlock_irqrestore(&up->port.lock, flags);
444 pm_runtime_mark_last_busy(&up->pdev->dev);
445 pm_runtime_put_autosuspend(&up->pdev->dev);
447 up->port_activity = jiffies;
451 static unsigned int serial_omap_tx_empty(struct uart_port *port)
453 struct uart_omap_port *up = (struct uart_omap_port *)port;
454 unsigned long flags = 0;
455 unsigned int ret = 0;
457 pm_runtime_get_sync(&up->pdev->dev);
458 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
459 spin_lock_irqsave(&up->port.lock, flags);
460 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
461 spin_unlock_irqrestore(&up->port.lock, flags);
462 pm_runtime_put(&up->pdev->dev);
466 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
468 struct uart_omap_port *up = (struct uart_omap_port *)port;
470 unsigned int ret = 0;
472 pm_runtime_get_sync(&up->pdev->dev);
473 status = check_modem_status(up);
474 pm_runtime_put(&up->pdev->dev);
476 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
478 if (status & UART_MSR_DCD)
480 if (status & UART_MSR_RI)
482 if (status & UART_MSR_DSR)
484 if (status & UART_MSR_CTS)
489 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
491 struct uart_omap_port *up = (struct uart_omap_port *)port;
492 unsigned char mcr = 0;
494 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
495 if (mctrl & TIOCM_RTS)
497 if (mctrl & TIOCM_DTR)
499 if (mctrl & TIOCM_OUT1)
500 mcr |= UART_MCR_OUT1;
501 if (mctrl & TIOCM_OUT2)
502 mcr |= UART_MCR_OUT2;
503 if (mctrl & TIOCM_LOOP)
504 mcr |= UART_MCR_LOOP;
506 pm_runtime_get_sync(&up->pdev->dev);
507 up->mcr = serial_in(up, UART_MCR);
509 serial_out(up, UART_MCR, up->mcr);
510 pm_runtime_put(&up->pdev->dev);
512 if (gpio_is_valid(up->DTR_gpio) &&
513 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
514 up->DTR_active = !up->DTR_active;
515 if (gpio_cansleep(up->DTR_gpio))
516 schedule_work(&up->qos_work);
518 gpio_set_value(up->DTR_gpio,
519 up->DTR_active != up->DTR_inverted);
523 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
525 struct uart_omap_port *up = (struct uart_omap_port *)port;
526 unsigned long flags = 0;
528 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
529 pm_runtime_get_sync(&up->pdev->dev);
530 spin_lock_irqsave(&up->port.lock, flags);
531 if (break_state == -1)
532 up->lcr |= UART_LCR_SBC;
534 up->lcr &= ~UART_LCR_SBC;
535 serial_out(up, UART_LCR, up->lcr);
536 spin_unlock_irqrestore(&up->port.lock, flags);
537 pm_runtime_put(&up->pdev->dev);
540 static int serial_omap_startup(struct uart_port *port)
542 struct uart_omap_port *up = (struct uart_omap_port *)port;
543 unsigned long flags = 0;
549 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
554 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
556 pm_runtime_get_sync(&up->pdev->dev);
558 * Clear the FIFO buffers and disable them.
559 * (they will be reenabled in set_termios())
561 serial_omap_clear_fifos(up);
562 /* For Hardware flow control */
563 serial_out(up, UART_MCR, UART_MCR_RTS);
566 * Clear the interrupt registers.
568 (void) serial_in(up, UART_LSR);
569 if (serial_in(up, UART_LSR) & UART_LSR_DR)
570 (void) serial_in(up, UART_RX);
571 (void) serial_in(up, UART_IIR);
572 (void) serial_in(up, UART_MSR);
575 * Now, initialize the UART
577 serial_out(up, UART_LCR, UART_LCR_WLEN8);
578 spin_lock_irqsave(&up->port.lock, flags);
580 * Most PC uarts need OUT2 raised to enable interrupts.
582 up->port.mctrl |= TIOCM_OUT2;
583 serial_omap_set_mctrl(&up->port, up->port.mctrl);
584 spin_unlock_irqrestore(&up->port.lock, flags);
586 up->msr_saved_flags = 0;
588 free_page((unsigned long)up->port.state->xmit.buf);
589 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
591 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
593 init_timer(&(up->uart_dma.rx_timer));
594 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
595 up->uart_dma.rx_timer.data = up->port.line;
596 /* Currently the buffer size is 4KB. Can increase it */
597 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
598 up->uart_dma.rx_buf_size,
599 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
602 * Finally, enable interrupts. Note: Modem status interrupts
603 * are set via set_termios(), which will be occurring imminently
604 * anyway, so we don't enable them here.
606 up->ier = UART_IER_RLSI | UART_IER_RDI;
607 serial_out(up, UART_IER, up->ier);
609 /* Enable module level wake up */
610 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
612 pm_runtime_mark_last_busy(&up->pdev->dev);
613 pm_runtime_put_autosuspend(&up->pdev->dev);
614 up->port_activity = jiffies;
618 static void serial_omap_shutdown(struct uart_port *port)
620 struct uart_omap_port *up = (struct uart_omap_port *)port;
621 unsigned long flags = 0;
623 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
625 pm_runtime_get_sync(&up->pdev->dev);
627 * Disable interrupts from this port
630 serial_out(up, UART_IER, 0);
632 spin_lock_irqsave(&up->port.lock, flags);
633 up->port.mctrl &= ~TIOCM_OUT2;
634 serial_omap_set_mctrl(&up->port, up->port.mctrl);
635 spin_unlock_irqrestore(&up->port.lock, flags);
638 * Disable break condition and FIFOs
640 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
641 serial_omap_clear_fifos(up);
644 * Read data port to reset things, and then free the irq
646 if (serial_in(up, UART_LSR) & UART_LSR_DR)
647 (void) serial_in(up, UART_RX);
649 dma_free_coherent(up->port.dev,
650 UART_XMIT_SIZE, up->port.state->xmit.buf,
651 up->uart_dma.tx_buf_dma_phys);
652 up->port.state->xmit.buf = NULL;
653 serial_omap_stop_rx(port);
654 dma_free_coherent(up->port.dev,
655 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
656 up->uart_dma.rx_buf_dma_phys);
657 up->uart_dma.rx_buf = NULL;
660 pm_runtime_put(&up->pdev->dev);
661 free_irq(up->port.irq, up);
665 serial_omap_configure_xonxoff
666 (struct uart_omap_port *up, struct ktermios *termios)
668 up->lcr = serial_in(up, UART_LCR);
669 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
670 up->efr = serial_in(up, UART_EFR);
671 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
673 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
674 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
676 /* clear SW control mode bits */
677 up->efr &= OMAP_UART_SW_CLR;
681 * Enable XON/XOFF flow control on output.
682 * Transmit XON1, XOFF1
684 if (termios->c_iflag & IXON)
685 up->efr |= OMAP_UART_SW_TX;
689 * Enable XON/XOFF flow control on input.
690 * Receiver compares XON1, XOFF1.
692 if (termios->c_iflag & IXOFF)
693 up->efr |= OMAP_UART_SW_RX;
695 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
696 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
698 up->mcr = serial_in(up, UART_MCR);
702 * Enable any character to restart output.
703 * Operation resumes after receiving any
704 * character after recognition of the XOFF character
706 if (termios->c_iflag & IXANY)
707 up->mcr |= UART_MCR_XONANY;
709 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
710 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
711 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
712 /* Enable special char function UARTi.EFR_REG[5] and
713 * load the new software flow control mode IXON or IXOFF
714 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
716 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
717 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
719 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
720 serial_out(up, UART_LCR, up->lcr);
723 static void serial_omap_uart_qos_work(struct work_struct *work)
725 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
728 pm_qos_update_request(&up->pm_qos_request, up->latency);
729 if (gpio_is_valid(up->DTR_gpio))
730 gpio_set_value_cansleep(up->DTR_gpio,
731 up->DTR_active != up->DTR_inverted);
735 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
736 struct ktermios *old)
738 struct uart_omap_port *up = (struct uart_omap_port *)port;
739 unsigned char cval = 0;
740 unsigned char efr = 0;
741 unsigned long flags = 0;
742 unsigned int baud, quot;
744 switch (termios->c_cflag & CSIZE) {
746 cval = UART_LCR_WLEN5;
749 cval = UART_LCR_WLEN6;
752 cval = UART_LCR_WLEN7;
756 cval = UART_LCR_WLEN8;
760 if (termios->c_cflag & CSTOPB)
761 cval |= UART_LCR_STOP;
762 if (termios->c_cflag & PARENB)
763 cval |= UART_LCR_PARITY;
764 if (!(termios->c_cflag & PARODD))
765 cval |= UART_LCR_EPAR;
768 * Ask the core to calculate the divisor for us.
771 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
772 quot = serial_omap_get_divisor(port, baud);
774 /* calculate wakeup latency constraint */
775 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
776 up->latency = up->calc_latency;
777 schedule_work(&up->qos_work);
779 up->dll = quot & 0xff;
781 up->mdr1 = UART_OMAP_MDR1_DISABLE;
783 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
784 UART_FCR_ENABLE_FIFO;
786 up->fcr |= UART_FCR_DMA_SELECT;
789 * Ok, we're now changing the port state. Do it with
790 * interrupts disabled.
792 pm_runtime_get_sync(&up->pdev->dev);
793 spin_lock_irqsave(&up->port.lock, flags);
796 * Update the per-port timeout.
798 uart_update_timeout(port, termios->c_cflag, baud);
800 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
801 if (termios->c_iflag & INPCK)
802 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
803 if (termios->c_iflag & (BRKINT | PARMRK))
804 up->port.read_status_mask |= UART_LSR_BI;
807 * Characters to ignore
809 up->port.ignore_status_mask = 0;
810 if (termios->c_iflag & IGNPAR)
811 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
812 if (termios->c_iflag & IGNBRK) {
813 up->port.ignore_status_mask |= UART_LSR_BI;
815 * If we're ignoring parity and break indicators,
816 * ignore overruns too (for real raw support).
818 if (termios->c_iflag & IGNPAR)
819 up->port.ignore_status_mask |= UART_LSR_OE;
823 * ignore all characters if CREAD is not set
825 if ((termios->c_cflag & CREAD) == 0)
826 up->port.ignore_status_mask |= UART_LSR_DR;
829 * Modem status interrupts
831 up->ier &= ~UART_IER_MSI;
832 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
833 up->ier |= UART_IER_MSI;
834 serial_out(up, UART_IER, up->ier);
835 serial_out(up, UART_LCR, cval); /* reset DLAB */
837 up->scr = OMAP_UART_SCR_TX_EMPTY;
839 /* FIFOs and DMA Settings */
841 /* FCR can be changed only when the
842 * baud clock is not running
843 * DLL_REG and DLH_REG set to 0.
845 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
846 serial_out(up, UART_DLL, 0);
847 serial_out(up, UART_DLM, 0);
848 serial_out(up, UART_LCR, 0);
850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
852 up->efr = serial_in(up, UART_EFR);
853 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
856 up->mcr = serial_in(up, UART_MCR);
857 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
858 /* FIFO ENABLE, DMA MODE */
860 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
863 serial_out(up, UART_TI752_TLR, 0);
864 up->scr |= UART_FCR_TRIGGER_4;
866 /* Set receive FIFO threshold to 1 byte */
867 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
868 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
871 serial_out(up, UART_FCR, up->fcr);
872 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874 serial_out(up, UART_OMAP_SCR, up->scr);
876 serial_out(up, UART_EFR, up->efr);
877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
878 serial_out(up, UART_MCR, up->mcr);
880 /* Protocol, Baud Rate, and Interrupt Settings */
882 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
883 serial_omap_mdr1_errataset(up, up->mdr1);
885 serial_out(up, UART_OMAP_MDR1, up->mdr1);
887 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
889 up->efr = serial_in(up, UART_EFR);
890 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
892 serial_out(up, UART_LCR, 0);
893 serial_out(up, UART_IER, 0);
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
896 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
897 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
899 serial_out(up, UART_LCR, 0);
900 serial_out(up, UART_IER, up->ier);
901 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
903 serial_out(up, UART_EFR, up->efr);
904 serial_out(up, UART_LCR, cval);
906 if (baud > 230400 && baud != 3000000)
907 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
909 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
911 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
912 serial_omap_mdr1_errataset(up, up->mdr1);
914 serial_out(up, UART_OMAP_MDR1, up->mdr1);
916 /* Hardware Flow Control Configuration */
918 if (termios->c_cflag & CRTSCTS) {
919 efr |= (UART_EFR_CTS | UART_EFR_RTS);
920 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
922 up->mcr = serial_in(up, UART_MCR);
923 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
925 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
926 up->efr = serial_in(up, UART_EFR);
927 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
929 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
930 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
931 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
932 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
933 serial_out(up, UART_LCR, cval);
936 serial_omap_set_mctrl(&up->port, up->port.mctrl);
937 /* Software Flow Control Configuration */
938 serial_omap_configure_xonxoff(up, termios);
940 spin_unlock_irqrestore(&up->port.lock, flags);
941 pm_runtime_put(&up->pdev->dev);
942 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
946 serial_omap_pm(struct uart_port *port, unsigned int state,
947 unsigned int oldstate)
949 struct uart_omap_port *up = (struct uart_omap_port *)port;
952 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
954 pm_runtime_get_sync(&up->pdev->dev);
955 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
956 efr = serial_in(up, UART_EFR);
957 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
958 serial_out(up, UART_LCR, 0);
960 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
962 serial_out(up, UART_EFR, efr);
963 serial_out(up, UART_LCR, 0);
965 if (!device_may_wakeup(&up->pdev->dev)) {
967 pm_runtime_forbid(&up->pdev->dev);
969 pm_runtime_allow(&up->pdev->dev);
972 pm_runtime_put(&up->pdev->dev);
975 static void serial_omap_release_port(struct uart_port *port)
977 dev_dbg(port->dev, "serial_omap_release_port+\n");
980 static int serial_omap_request_port(struct uart_port *port)
982 dev_dbg(port->dev, "serial_omap_request_port+\n");
986 static void serial_omap_config_port(struct uart_port *port, int flags)
988 struct uart_omap_port *up = (struct uart_omap_port *)port;
990 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
992 up->port.type = PORT_OMAP;
996 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
998 /* we don't want the core code to modify any port params */
999 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1004 serial_omap_type(struct uart_port *port)
1006 struct uart_omap_port *up = (struct uart_omap_port *)port;
1008 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1012 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1014 static inline void wait_for_xmitr(struct uart_omap_port *up)
1016 unsigned int status, tmout = 10000;
1018 /* Wait up to 10ms for the character(s) to be sent. */
1020 status = serial_in(up, UART_LSR);
1022 if (status & UART_LSR_BI)
1023 up->lsr_break_flag = UART_LSR_BI;
1028 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1030 /* Wait up to 1s for flow control if necessary */
1031 if (up->port.flags & UPF_CONS_FLOW) {
1033 for (tmout = 1000000; tmout; tmout--) {
1034 unsigned int msr = serial_in(up, UART_MSR);
1036 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1037 if (msr & UART_MSR_CTS)
1045 #ifdef CONFIG_CONSOLE_POLL
1047 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1049 struct uart_omap_port *up = (struct uart_omap_port *)port;
1051 pm_runtime_get_sync(&up->pdev->dev);
1053 serial_out(up, UART_TX, ch);
1054 pm_runtime_put(&up->pdev->dev);
1057 static int serial_omap_poll_get_char(struct uart_port *port)
1059 struct uart_omap_port *up = (struct uart_omap_port *)port;
1060 unsigned int status;
1062 pm_runtime_get_sync(&up->pdev->dev);
1063 status = serial_in(up, UART_LSR);
1064 if (!(status & UART_LSR_DR))
1065 return NO_POLL_CHAR;
1067 status = serial_in(up, UART_RX);
1068 pm_runtime_put(&up->pdev->dev);
1072 #endif /* CONFIG_CONSOLE_POLL */
1074 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1076 static struct uart_omap_port *serial_omap_console_ports[4];
1078 static struct uart_driver serial_omap_reg;
1080 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1082 struct uart_omap_port *up = (struct uart_omap_port *)port;
1085 serial_out(up, UART_TX, ch);
1089 serial_omap_console_write(struct console *co, const char *s,
1092 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1093 unsigned long flags;
1097 pm_runtime_get_sync(&up->pdev->dev);
1099 local_irq_save(flags);
1102 else if (oops_in_progress)
1103 locked = spin_trylock(&up->port.lock);
1105 spin_lock(&up->port.lock);
1108 * First save the IER then disable the interrupts
1110 ier = serial_in(up, UART_IER);
1111 serial_out(up, UART_IER, 0);
1113 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1116 * Finally, wait for transmitter to become empty
1117 * and restore the IER
1120 serial_out(up, UART_IER, ier);
1122 * The receive handling will happen properly because the
1123 * receive ready bit will still be set; it is not cleared
1124 * on read. However, modem control will not, we must
1125 * call it if we have saved something in the saved flags
1126 * while processing with interrupts off.
1128 if (up->msr_saved_flags)
1129 check_modem_status(up);
1131 pm_runtime_mark_last_busy(&up->pdev->dev);
1132 pm_runtime_put_autosuspend(&up->pdev->dev);
1134 spin_unlock(&up->port.lock);
1135 local_irq_restore(flags);
1139 serial_omap_console_setup(struct console *co, char *options)
1141 struct uart_omap_port *up;
1147 if (serial_omap_console_ports[co->index] == NULL)
1149 up = serial_omap_console_ports[co->index];
1152 uart_parse_options(options, &baud, &parity, &bits, &flow);
1154 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1157 static struct console serial_omap_console = {
1158 .name = OMAP_SERIAL_NAME,
1159 .write = serial_omap_console_write,
1160 .device = uart_console_device,
1161 .setup = serial_omap_console_setup,
1162 .flags = CON_PRINTBUFFER,
1164 .data = &serial_omap_reg,
1167 static void serial_omap_add_console_port(struct uart_omap_port *up)
1169 serial_omap_console_ports[up->port.line] = up;
1172 #define OMAP_CONSOLE (&serial_omap_console)
1176 #define OMAP_CONSOLE NULL
1178 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1183 static struct uart_ops serial_omap_pops = {
1184 .tx_empty = serial_omap_tx_empty,
1185 .set_mctrl = serial_omap_set_mctrl,
1186 .get_mctrl = serial_omap_get_mctrl,
1187 .stop_tx = serial_omap_stop_tx,
1188 .start_tx = serial_omap_start_tx,
1189 .stop_rx = serial_omap_stop_rx,
1190 .enable_ms = serial_omap_enable_ms,
1191 .break_ctl = serial_omap_break_ctl,
1192 .startup = serial_omap_startup,
1193 .shutdown = serial_omap_shutdown,
1194 .set_termios = serial_omap_set_termios,
1195 .pm = serial_omap_pm,
1196 .type = serial_omap_type,
1197 .release_port = serial_omap_release_port,
1198 .request_port = serial_omap_request_port,
1199 .config_port = serial_omap_config_port,
1200 .verify_port = serial_omap_verify_port,
1201 #ifdef CONFIG_CONSOLE_POLL
1202 .poll_put_char = serial_omap_poll_put_char,
1203 .poll_get_char = serial_omap_poll_get_char,
1207 static struct uart_driver serial_omap_reg = {
1208 .owner = THIS_MODULE,
1209 .driver_name = "OMAP-SERIAL",
1210 .dev_name = OMAP_SERIAL_NAME,
1211 .nr = OMAP_MAX_HSUART_PORTS,
1212 .cons = OMAP_CONSOLE,
1215 #ifdef CONFIG_PM_SLEEP
1216 static int serial_omap_suspend(struct device *dev)
1218 struct uart_omap_port *up = dev_get_drvdata(dev);
1221 uart_suspend_port(&serial_omap_reg, &up->port);
1222 flush_work_sync(&up->qos_work);
1228 static int serial_omap_resume(struct device *dev)
1230 struct uart_omap_port *up = dev_get_drvdata(dev);
1233 uart_resume_port(&serial_omap_reg, &up->port);
1238 static void serial_omap_rxdma_poll(unsigned long uart_no)
1240 struct uart_omap_port *up = ui[uart_no];
1241 unsigned int curr_dma_pos, curr_transmitted_size;
1244 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1245 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1246 (curr_dma_pos == 0)) {
1247 if (jiffies_to_msecs(jiffies - up->port_activity) <
1248 up->uart_dma.rx_timeout) {
1249 mod_timer(&up->uart_dma.rx_timer, jiffies +
1250 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1252 serial_omap_stop_rxdma(up);
1253 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1254 serial_out(up, UART_IER, up->ier);
1259 curr_transmitted_size = curr_dma_pos -
1260 up->uart_dma.prev_rx_dma_pos;
1261 up->port.icount.rx += curr_transmitted_size;
1262 tty_insert_flip_string(up->port.state->port.tty,
1263 up->uart_dma.rx_buf +
1264 (up->uart_dma.prev_rx_dma_pos -
1265 up->uart_dma.rx_buf_dma_phys),
1266 curr_transmitted_size);
1267 tty_flip_buffer_push(up->port.state->port.tty);
1268 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1269 if (up->uart_dma.rx_buf_size +
1270 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1271 ret = serial_omap_start_rxdma(up);
1273 serial_omap_stop_rxdma(up);
1274 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1275 serial_out(up, UART_IER, up->ier);
1278 mod_timer(&up->uart_dma.rx_timer, jiffies +
1279 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1281 up->port_activity = jiffies;
1284 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1289 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1293 if (up->uart_dma.rx_dma_channel == -1) {
1294 pm_runtime_get_sync(&up->pdev->dev);
1295 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1297 (void *)uart_rx_dma_callback, up,
1298 &(up->uart_dma.rx_dma_channel));
1302 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1303 OMAP_DMA_AMODE_CONSTANT,
1304 up->uart_dma.uart_base, 0, 0);
1305 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1306 OMAP_DMA_AMODE_POST_INC,
1307 up->uart_dma.rx_buf_dma_phys, 0, 0);
1308 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1309 OMAP_DMA_DATA_TYPE_S8,
1310 up->uart_dma.rx_buf_size, 1,
1311 OMAP_DMA_SYNC_ELEMENT,
1312 up->uart_dma.uart_dma_rx, 0);
1314 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1315 /* FIXME: Cache maintenance needed here? */
1316 omap_start_dma(up->uart_dma.rx_dma_channel);
1317 mod_timer(&up->uart_dma.rx_timer, jiffies +
1318 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1319 up->uart_dma.rx_dma_used = true;
1323 static void serial_omap_continue_tx(struct uart_omap_port *up)
1325 struct circ_buf *xmit = &up->port.state->xmit;
1326 unsigned int start = up->uart_dma.tx_buf_dma_phys
1327 + (xmit->tail & (UART_XMIT_SIZE - 1));
1329 if (uart_circ_empty(xmit))
1332 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1334 * It is a circular buffer. See if the buffer has wounded back.
1335 * If yes it will have to be transferred in two separate dma
1338 if (start + up->uart_dma.tx_buf_size >=
1339 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1340 up->uart_dma.tx_buf_size =
1341 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1342 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1343 OMAP_DMA_AMODE_CONSTANT,
1344 up->uart_dma.uart_base, 0, 0);
1345 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1346 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1347 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1348 OMAP_DMA_DATA_TYPE_S8,
1349 up->uart_dma.tx_buf_size, 1,
1350 OMAP_DMA_SYNC_ELEMENT,
1351 up->uart_dma.uart_dma_tx, 0);
1352 /* FIXME: Cache maintenance needed here? */
1353 omap_start_dma(up->uart_dma.tx_dma_channel);
1356 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1358 struct uart_omap_port *up = (struct uart_omap_port *)data;
1359 struct circ_buf *xmit = &up->port.state->xmit;
1361 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1362 (UART_XMIT_SIZE - 1);
1363 up->port.icount.tx += up->uart_dma.tx_buf_size;
1365 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1366 uart_write_wakeup(&up->port);
1368 if (uart_circ_empty(xmit)) {
1369 spin_lock(&(up->uart_dma.tx_lock));
1370 serial_omap_stop_tx(&up->port);
1371 up->uart_dma.tx_dma_used = false;
1372 spin_unlock(&(up->uart_dma.tx_lock));
1374 omap_stop_dma(up->uart_dma.tx_dma_channel);
1375 serial_omap_continue_tx(up);
1377 up->port_activity = jiffies;
1381 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1384 u16 revision, major, minor;
1386 mvr = serial_in(up, UART_OMAP_MVER);
1388 /* Check revision register scheme */
1389 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1392 case 0: /* Legacy Scheme: OMAP2/3 */
1393 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1394 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1395 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1396 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1399 /* New Scheme: OMAP4+ */
1400 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1401 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1402 OMAP_UART_MVR_MAJ_SHIFT;
1403 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1406 dev_warn(&up->pdev->dev,
1407 "Unknown %s revision, defaulting to highest\n",
1409 /* highest possible revision */
1414 /* normalize revision for the driver */
1415 revision = UART_BUILD_REVISION(major, minor);
1418 case OMAP_UART_REV_46:
1419 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1420 UART_ERRATA_i291_DMA_FORCEIDLE);
1422 case OMAP_UART_REV_52:
1423 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1424 UART_ERRATA_i291_DMA_FORCEIDLE);
1426 case OMAP_UART_REV_63:
1427 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1434 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1436 struct omap_uart_port_info *omap_up_info;
1438 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1440 return NULL; /* out of memory */
1442 of_property_read_u32(dev->of_node, "clock-frequency",
1443 &omap_up_info->uartclk);
1444 return omap_up_info;
1447 static int serial_omap_probe(struct platform_device *pdev)
1449 struct uart_omap_port *up;
1450 struct resource *mem, *irq, *dma_tx, *dma_rx;
1451 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1454 if (pdev->dev.of_node)
1455 omap_up_info = of_get_uart_port_info(&pdev->dev);
1457 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1459 dev_err(&pdev->dev, "no mem resource?\n");
1463 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1465 dev_err(&pdev->dev, "no irq resource?\n");
1469 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1470 pdev->dev.driver->name)) {
1471 dev_err(&pdev->dev, "memory region already claimed\n");
1475 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1479 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1483 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1484 omap_up_info->DTR_present) {
1485 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1488 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1489 omap_up_info->DTR_inverted);
1494 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1498 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1499 omap_up_info->DTR_present) {
1500 up->DTR_gpio = omap_up_info->DTR_gpio;
1501 up->DTR_inverted = omap_up_info->DTR_inverted;
1503 up->DTR_gpio = -EINVAL;
1507 up->port.dev = &pdev->dev;
1508 up->port.type = PORT_OMAP;
1509 up->port.iotype = UPIO_MEM;
1510 up->port.irq = irq->start;
1512 up->port.regshift = 2;
1513 up->port.fifosize = 64;
1514 up->port.ops = &serial_omap_pops;
1516 if (pdev->dev.of_node)
1517 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1519 up->port.line = pdev->id;
1521 if (up->port.line < 0) {
1522 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1528 sprintf(up->name, "OMAP UART%d", up->port.line);
1529 up->port.mapbase = mem->start;
1530 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1531 resource_size(mem));
1532 if (!up->port.membase) {
1533 dev_err(&pdev->dev, "can't ioremap UART\n");
1538 up->port.flags = omap_up_info->flags;
1539 up->port.uartclk = omap_up_info->uartclk;
1540 if (!up->port.uartclk) {
1541 up->port.uartclk = DEFAULT_CLK_SPEED;
1542 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1543 "%d\n", DEFAULT_CLK_SPEED);
1545 up->uart_dma.uart_base = mem->start;
1547 if (omap_up_info->dma_enabled) {
1548 up->uart_dma.uart_dma_tx = dma_tx->start;
1549 up->uart_dma.uart_dma_rx = dma_rx->start;
1551 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1552 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1553 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1554 spin_lock_init(&(up->uart_dma.tx_lock));
1555 spin_lock_init(&(up->uart_dma.rx_lock));
1556 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1557 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1560 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1561 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1562 pm_qos_add_request(&up->pm_qos_request,
1563 PM_QOS_CPU_DMA_LATENCY, up->latency);
1564 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1565 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1567 pm_runtime_use_autosuspend(&pdev->dev);
1568 pm_runtime_set_autosuspend_delay(&pdev->dev,
1569 omap_up_info->autosuspend_timeout);
1571 pm_runtime_irq_safe(&pdev->dev);
1572 pm_runtime_enable(&pdev->dev);
1573 pm_runtime_get_sync(&pdev->dev);
1575 omap_serial_fill_features_erratas(up);
1577 ui[up->port.line] = up;
1578 serial_omap_add_console_port(up);
1580 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1584 pm_runtime_put(&pdev->dev);
1585 platform_set_drvdata(pdev, up);
1589 pm_runtime_put(&pdev->dev);
1590 pm_runtime_disable(&pdev->dev);
1593 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1594 pdev->id, __func__, ret);
1598 static int serial_omap_remove(struct platform_device *dev)
1600 struct uart_omap_port *up = platform_get_drvdata(dev);
1603 pm_runtime_disable(&up->pdev->dev);
1604 uart_remove_one_port(&serial_omap_reg, &up->port);
1605 pm_qos_remove_request(&up->pm_qos_request);
1608 platform_set_drvdata(dev, NULL);
1613 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1614 * The access to uart register after MDR1 Access
1615 * causes UART to corrupt data.
1618 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1619 * give 10 times as much
1621 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1625 serial_out(up, UART_OMAP_MDR1, mdr1);
1627 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1628 UART_FCR_CLEAR_RCVR);
1630 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1631 * TX_FIFO_E bit is 1.
1633 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1634 (UART_LSR_THRE | UART_LSR_DR))) {
1637 /* Should *never* happen. we warn and carry on */
1638 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1639 serial_in(up, UART_LSR));
1646 #ifdef CONFIG_PM_RUNTIME
1647 static void serial_omap_restore_context(struct uart_omap_port *up)
1649 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1650 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1652 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1654 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1655 serial_out(up, UART_EFR, UART_EFR_ECB);
1656 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1657 serial_out(up, UART_IER, 0x0);
1658 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1659 serial_out(up, UART_DLL, up->dll);
1660 serial_out(up, UART_DLM, up->dlh);
1661 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1662 serial_out(up, UART_IER, up->ier);
1663 serial_out(up, UART_FCR, up->fcr);
1664 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1665 serial_out(up, UART_MCR, up->mcr);
1666 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1667 serial_out(up, UART_OMAP_SCR, up->scr);
1668 serial_out(up, UART_EFR, up->efr);
1669 serial_out(up, UART_LCR, up->lcr);
1670 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1671 serial_omap_mdr1_errataset(up, up->mdr1);
1673 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1676 static int serial_omap_runtime_suspend(struct device *dev)
1678 struct uart_omap_port *up = dev_get_drvdata(dev);
1679 struct omap_uart_port_info *pdata = dev->platform_data;
1684 if (!pdata || !pdata->enable_wakeup)
1687 if (pdata->get_context_loss_count)
1688 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1690 if (device_may_wakeup(dev)) {
1691 if (!up->wakeups_enabled) {
1692 pdata->enable_wakeup(up->pdev, true);
1693 up->wakeups_enabled = true;
1696 if (up->wakeups_enabled) {
1697 pdata->enable_wakeup(up->pdev, false);
1698 up->wakeups_enabled = false;
1703 if (up->use_dma && pdata->set_forceidle &&
1704 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1705 pdata->set_forceidle(up->pdev);
1707 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1708 schedule_work(&up->qos_work);
1713 static int serial_omap_runtime_resume(struct device *dev)
1715 struct uart_omap_port *up = dev_get_drvdata(dev);
1716 struct omap_uart_port_info *pdata = dev->platform_data;
1719 if (pdata->get_context_loss_count) {
1720 u32 loss_cnt = pdata->get_context_loss_count(dev);
1722 if (up->context_loss_cnt != loss_cnt)
1723 serial_omap_restore_context(up);
1727 if (up->use_dma && pdata->set_noidle &&
1728 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1729 pdata->set_noidle(up->pdev);
1731 up->latency = up->calc_latency;
1732 schedule_work(&up->qos_work);
1739 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1740 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1741 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1742 serial_omap_runtime_resume, NULL)
1745 #if defined(CONFIG_OF)
1746 static const struct of_device_id omap_serial_of_match[] = {
1747 { .compatible = "ti,omap2-uart" },
1748 { .compatible = "ti,omap3-uart" },
1749 { .compatible = "ti,omap4-uart" },
1752 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1755 static struct platform_driver serial_omap_driver = {
1756 .probe = serial_omap_probe,
1757 .remove = serial_omap_remove,
1759 .name = DRIVER_NAME,
1760 .pm = &serial_omap_dev_pm_ops,
1761 .of_match_table = of_match_ptr(omap_serial_of_match),
1765 static int __init serial_omap_init(void)
1769 ret = uart_register_driver(&serial_omap_reg);
1772 ret = platform_driver_register(&serial_omap_driver);
1774 uart_unregister_driver(&serial_omap_reg);
1778 static void __exit serial_omap_exit(void)
1780 platform_driver_unregister(&serial_omap_driver);
1781 uart_unregister_driver(&serial_omap_reg);
1784 module_init(serial_omap_init);
1785 module_exit(serial_omap_exit);
1787 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1788 MODULE_LICENSE("GPL");
1789 MODULE_AUTHOR("Texas Instruments Inc");