2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
44 #include <plat/dmtimer.h>
45 #include <plat/omap-serial.h>
47 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
49 #define OMAP_UART_REV_42 0x0402
50 #define OMAP_UART_REV_46 0x0406
51 #define OMAP_UART_REV_52 0x0502
52 #define OMAP_UART_REV_63 0x0603
54 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
56 /* SCR register bitmasks */
57 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
59 /* FCR register bitmasks */
60 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
61 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
63 /* MVR register bitmasks */
64 #define OMAP_UART_MVR_SCHEME_SHIFT 30
66 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
67 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
68 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
70 #define OMAP_UART_MVR_MAJ_MASK 0x700
71 #define OMAP_UART_MVR_MAJ_SHIFT 8
72 #define OMAP_UART_MVR_MIN_MASK 0x3f
74 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
76 /* Forward declaration of functions */
77 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
78 static void serial_omap_rxdma_poll(unsigned long uart_no);
79 static int serial_omap_start_rxdma(struct uart_omap_port *up);
80 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
82 static struct workqueue_struct *serial_omap_uart_wq;
84 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
86 offset <<= up->port.regshift;
87 return readw(up->port.membase + offset);
90 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
92 offset <<= up->port.regshift;
93 writew(value, up->port.membase + offset);
96 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
98 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
99 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
100 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
101 serial_out(up, UART_FCR, 0);
105 * serial_omap_get_divisor - calculate divisor value
106 * @port: uart port info
107 * @baud: baudrate for which divisor needs to be calculated.
109 * We have written our own function to get the divisor so as to support
110 * 13x mode. 3Mbps Baudrate as an different divisor.
111 * Reference OMAP TRM Chapter 17:
112 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
113 * referring to oversampling - divisor value
114 * baudrate 460,800 to 3,686,400 all have divisor 13
115 * except 3,000,000 which has divisor value 16
118 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
120 unsigned int divisor;
122 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
126 return port->uartclk/(baud * divisor);
129 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
131 if (up->uart_dma.rx_dma_used) {
132 del_timer(&up->uart_dma.rx_timer);
133 omap_stop_dma(up->uart_dma.rx_dma_channel);
134 omap_free_dma(up->uart_dma.rx_dma_channel);
135 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
136 up->uart_dma.rx_dma_used = false;
137 pm_runtime_mark_last_busy(&up->pdev->dev);
138 pm_runtime_put_autosuspend(&up->pdev->dev);
142 static void serial_omap_enable_ms(struct uart_port *port)
144 struct uart_omap_port *up = (struct uart_omap_port *)port;
146 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
148 pm_runtime_get_sync(&up->pdev->dev);
149 up->ier |= UART_IER_MSI;
150 serial_out(up, UART_IER, up->ier);
151 pm_runtime_put(&up->pdev->dev);
154 static void serial_omap_stop_tx(struct uart_port *port)
156 struct uart_omap_port *up = (struct uart_omap_port *)port;
157 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
160 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
162 * Check if dma is still active. If yes do nothing,
163 * return. Else stop dma
165 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
167 omap_stop_dma(up->uart_dma.tx_dma_channel);
168 omap_free_dma(up->uart_dma.tx_dma_channel);
169 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
170 pm_runtime_mark_last_busy(&up->pdev->dev);
171 pm_runtime_put_autosuspend(&up->pdev->dev);
174 pm_runtime_get_sync(&up->pdev->dev);
175 if (up->ier & UART_IER_THRI) {
176 up->ier &= ~UART_IER_THRI;
177 serial_out(up, UART_IER, up->ier);
180 if (!up->use_dma && pdata && pdata->set_forceidle)
181 pdata->set_forceidle(up->pdev);
183 pm_runtime_mark_last_busy(&up->pdev->dev);
184 pm_runtime_put_autosuspend(&up->pdev->dev);
187 static void serial_omap_stop_rx(struct uart_port *port)
189 struct uart_omap_port *up = (struct uart_omap_port *)port;
191 pm_runtime_get_sync(&up->pdev->dev);
193 serial_omap_stop_rxdma(up);
194 up->ier &= ~UART_IER_RLSI;
195 up->port.read_status_mask &= ~UART_LSR_DR;
196 serial_out(up, UART_IER, up->ier);
197 pm_runtime_mark_last_busy(&up->pdev->dev);
198 pm_runtime_put_autosuspend(&up->pdev->dev);
201 static inline void receive_chars(struct uart_omap_port *up,
202 unsigned int *status)
204 struct tty_struct *tty = up->port.state->port.tty;
205 unsigned int flag, lsr = *status;
206 unsigned char ch = 0;
210 if (likely(lsr & UART_LSR_DR))
211 ch = serial_in(up, UART_RX);
213 up->port.icount.rx++;
215 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
217 * For statistics only
219 if (lsr & UART_LSR_BI) {
220 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
221 up->port.icount.brk++;
223 * We do the SysRQ and SAK checking
224 * here because otherwise the break
225 * may get masked by ignore_status_mask
226 * or read_status_mask.
228 if (uart_handle_break(&up->port))
230 } else if (lsr & UART_LSR_PE) {
231 up->port.icount.parity++;
232 } else if (lsr & UART_LSR_FE) {
233 up->port.icount.frame++;
236 if (lsr & UART_LSR_OE)
237 up->port.icount.overrun++;
240 * Mask off conditions which should be ignored.
242 lsr &= up->port.read_status_mask;
244 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
245 if (up->port.line == up->port.cons->index) {
246 /* Recover the break flag from console xmit */
247 lsr |= up->lsr_break_flag;
250 if (lsr & UART_LSR_BI)
252 else if (lsr & UART_LSR_PE)
254 else if (lsr & UART_LSR_FE)
258 if (uart_handle_sysrq_char(&up->port, ch))
260 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
262 lsr = serial_in(up, UART_LSR);
263 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
264 spin_unlock(&up->port.lock);
265 tty_flip_buffer_push(tty);
266 spin_lock(&up->port.lock);
269 static void transmit_chars(struct uart_omap_port *up)
271 struct circ_buf *xmit = &up->port.state->xmit;
274 if (up->port.x_char) {
275 serial_out(up, UART_TX, up->port.x_char);
276 up->port.icount.tx++;
280 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
281 serial_omap_stop_tx(&up->port);
284 count = up->port.fifosize / 4;
286 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
287 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
288 up->port.icount.tx++;
289 if (uart_circ_empty(xmit))
291 } while (--count > 0);
293 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
294 uart_write_wakeup(&up->port);
296 if (uart_circ_empty(xmit))
297 serial_omap_stop_tx(&up->port);
300 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
302 if (!(up->ier & UART_IER_THRI)) {
303 up->ier |= UART_IER_THRI;
304 serial_out(up, UART_IER, up->ier);
308 static void serial_omap_start_tx(struct uart_port *port)
310 struct uart_omap_port *up = (struct uart_omap_port *)port;
311 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data;
312 struct circ_buf *xmit;
317 pm_runtime_get_sync(&up->pdev->dev);
318 serial_omap_enable_ier_thri(up);
319 if (pdata && pdata->set_noidle)
320 pdata->set_noidle(up->pdev);
321 pm_runtime_mark_last_busy(&up->pdev->dev);
322 pm_runtime_put_autosuspend(&up->pdev->dev);
326 if (up->uart_dma.tx_dma_used)
329 xmit = &up->port.state->xmit;
331 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
332 pm_runtime_get_sync(&up->pdev->dev);
333 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
335 (void *)uart_tx_dma_callback, up,
336 &(up->uart_dma.tx_dma_channel));
339 serial_omap_enable_ier_thri(up);
343 spin_lock(&(up->uart_dma.tx_lock));
344 up->uart_dma.tx_dma_used = true;
345 spin_unlock(&(up->uart_dma.tx_lock));
347 start = up->uart_dma.tx_buf_dma_phys +
348 (xmit->tail & (UART_XMIT_SIZE - 1));
350 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
352 * It is a circular buffer. See if the buffer has wounded back.
353 * If yes it will have to be transferred in two separate dma
356 if (start + up->uart_dma.tx_buf_size >=
357 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
358 up->uart_dma.tx_buf_size =
359 (up->uart_dma.tx_buf_dma_phys +
360 UART_XMIT_SIZE) - start;
362 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
363 OMAP_DMA_AMODE_CONSTANT,
364 up->uart_dma.uart_base, 0, 0);
365 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
366 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
367 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
368 OMAP_DMA_DATA_TYPE_S8,
369 up->uart_dma.tx_buf_size, 1,
370 OMAP_DMA_SYNC_ELEMENT,
371 up->uart_dma.uart_dma_tx, 0);
372 /* FIXME: Cache maintenance needed here? */
373 omap_start_dma(up->uart_dma.tx_dma_channel);
376 static unsigned int check_modem_status(struct uart_omap_port *up)
380 status = serial_in(up, UART_MSR);
381 status |= up->msr_saved_flags;
382 up->msr_saved_flags = 0;
383 if ((status & UART_MSR_ANY_DELTA) == 0)
386 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
387 up->port.state != NULL) {
388 if (status & UART_MSR_TERI)
389 up->port.icount.rng++;
390 if (status & UART_MSR_DDSR)
391 up->port.icount.dsr++;
392 if (status & UART_MSR_DDCD)
393 uart_handle_dcd_change
394 (&up->port, status & UART_MSR_DCD);
395 if (status & UART_MSR_DCTS)
396 uart_handle_cts_change
397 (&up->port, status & UART_MSR_CTS);
398 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
405 * serial_omap_irq() - This handles the interrupt from one port
406 * @irq: uart port irq number
407 * @dev_id: uart port info
409 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
411 struct uart_omap_port *up = dev_id;
412 unsigned int iir, lsr;
415 pm_runtime_get_sync(&up->pdev->dev);
416 iir = serial_in(up, UART_IIR);
417 if (iir & UART_IIR_NO_INT) {
418 pm_runtime_mark_last_busy(&up->pdev->dev);
419 pm_runtime_put_autosuspend(&up->pdev->dev);
423 spin_lock_irqsave(&up->port.lock, flags);
424 lsr = serial_in(up, UART_LSR);
425 if (iir & UART_IIR_RLSI) {
427 if (lsr & UART_LSR_DR)
428 receive_chars(up, &lsr);
430 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
431 serial_out(up, UART_IER, up->ier);
432 if ((serial_omap_start_rxdma(up) != 0) &&
434 receive_chars(up, &lsr);
438 check_modem_status(up);
439 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
442 spin_unlock_irqrestore(&up->port.lock, flags);
443 pm_runtime_mark_last_busy(&up->pdev->dev);
444 pm_runtime_put_autosuspend(&up->pdev->dev);
446 up->port_activity = jiffies;
450 static unsigned int serial_omap_tx_empty(struct uart_port *port)
452 struct uart_omap_port *up = (struct uart_omap_port *)port;
453 unsigned long flags = 0;
454 unsigned int ret = 0;
456 pm_runtime_get_sync(&up->pdev->dev);
457 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
458 spin_lock_irqsave(&up->port.lock, flags);
459 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
460 spin_unlock_irqrestore(&up->port.lock, flags);
461 pm_runtime_put(&up->pdev->dev);
465 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
467 struct uart_omap_port *up = (struct uart_omap_port *)port;
469 unsigned int ret = 0;
471 pm_runtime_get_sync(&up->pdev->dev);
472 status = check_modem_status(up);
473 pm_runtime_put(&up->pdev->dev);
475 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
477 if (status & UART_MSR_DCD)
479 if (status & UART_MSR_RI)
481 if (status & UART_MSR_DSR)
483 if (status & UART_MSR_CTS)
488 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
490 struct uart_omap_port *up = (struct uart_omap_port *)port;
491 unsigned char mcr = 0;
493 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
494 if (mctrl & TIOCM_RTS)
496 if (mctrl & TIOCM_DTR)
498 if (mctrl & TIOCM_OUT1)
499 mcr |= UART_MCR_OUT1;
500 if (mctrl & TIOCM_OUT2)
501 mcr |= UART_MCR_OUT2;
502 if (mctrl & TIOCM_LOOP)
503 mcr |= UART_MCR_LOOP;
505 pm_runtime_get_sync(&up->pdev->dev);
506 up->mcr = serial_in(up, UART_MCR);
508 serial_out(up, UART_MCR, up->mcr);
509 pm_runtime_put(&up->pdev->dev);
512 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
514 struct uart_omap_port *up = (struct uart_omap_port *)port;
515 unsigned long flags = 0;
517 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
518 pm_runtime_get_sync(&up->pdev->dev);
519 spin_lock_irqsave(&up->port.lock, flags);
520 if (break_state == -1)
521 up->lcr |= UART_LCR_SBC;
523 up->lcr &= ~UART_LCR_SBC;
524 serial_out(up, UART_LCR, up->lcr);
525 spin_unlock_irqrestore(&up->port.lock, flags);
526 pm_runtime_put(&up->pdev->dev);
529 static int serial_omap_startup(struct uart_port *port)
531 struct uart_omap_port *up = (struct uart_omap_port *)port;
532 unsigned long flags = 0;
538 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
543 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
545 pm_runtime_get_sync(&up->pdev->dev);
547 * Clear the FIFO buffers and disable them.
548 * (they will be reenabled in set_termios())
550 serial_omap_clear_fifos(up);
551 /* For Hardware flow control */
552 serial_out(up, UART_MCR, UART_MCR_RTS);
555 * Clear the interrupt registers.
557 (void) serial_in(up, UART_LSR);
558 if (serial_in(up, UART_LSR) & UART_LSR_DR)
559 (void) serial_in(up, UART_RX);
560 (void) serial_in(up, UART_IIR);
561 (void) serial_in(up, UART_MSR);
564 * Now, initialize the UART
566 serial_out(up, UART_LCR, UART_LCR_WLEN8);
567 spin_lock_irqsave(&up->port.lock, flags);
569 * Most PC uarts need OUT2 raised to enable interrupts.
571 up->port.mctrl |= TIOCM_OUT2;
572 serial_omap_set_mctrl(&up->port, up->port.mctrl);
573 spin_unlock_irqrestore(&up->port.lock, flags);
575 up->msr_saved_flags = 0;
577 free_page((unsigned long)up->port.state->xmit.buf);
578 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
580 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
582 init_timer(&(up->uart_dma.rx_timer));
583 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
584 up->uart_dma.rx_timer.data = up->port.line;
585 /* Currently the buffer size is 4KB. Can increase it */
586 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
587 up->uart_dma.rx_buf_size,
588 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
591 * Finally, enable interrupts. Note: Modem status interrupts
592 * are set via set_termios(), which will be occurring imminently
593 * anyway, so we don't enable them here.
595 up->ier = UART_IER_RLSI | UART_IER_RDI;
596 serial_out(up, UART_IER, up->ier);
598 /* Enable module level wake up */
599 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
601 pm_runtime_mark_last_busy(&up->pdev->dev);
602 pm_runtime_put_autosuspend(&up->pdev->dev);
603 up->port_activity = jiffies;
607 static void serial_omap_shutdown(struct uart_port *port)
609 struct uart_omap_port *up = (struct uart_omap_port *)port;
610 unsigned long flags = 0;
612 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
614 pm_runtime_get_sync(&up->pdev->dev);
616 * Disable interrupts from this port
619 serial_out(up, UART_IER, 0);
621 spin_lock_irqsave(&up->port.lock, flags);
622 up->port.mctrl &= ~TIOCM_OUT2;
623 serial_omap_set_mctrl(&up->port, up->port.mctrl);
624 spin_unlock_irqrestore(&up->port.lock, flags);
627 * Disable break condition and FIFOs
629 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
630 serial_omap_clear_fifos(up);
633 * Read data port to reset things, and then free the irq
635 if (serial_in(up, UART_LSR) & UART_LSR_DR)
636 (void) serial_in(up, UART_RX);
638 dma_free_coherent(up->port.dev,
639 UART_XMIT_SIZE, up->port.state->xmit.buf,
640 up->uart_dma.tx_buf_dma_phys);
641 up->port.state->xmit.buf = NULL;
642 serial_omap_stop_rx(port);
643 dma_free_coherent(up->port.dev,
644 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
645 up->uart_dma.rx_buf_dma_phys);
646 up->uart_dma.rx_buf = NULL;
649 pm_runtime_put(&up->pdev->dev);
650 free_irq(up->port.irq, up);
654 serial_omap_configure_xonxoff
655 (struct uart_omap_port *up, struct ktermios *termios)
657 up->lcr = serial_in(up, UART_LCR);
658 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
659 up->efr = serial_in(up, UART_EFR);
660 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
662 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
663 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
665 /* clear SW control mode bits */
666 up->efr &= OMAP_UART_SW_CLR;
670 * Enable XON/XOFF flow control on output.
671 * Transmit XON1, XOFF1
673 if (termios->c_iflag & IXON)
674 up->efr |= OMAP_UART_SW_TX;
678 * Enable XON/XOFF flow control on input.
679 * Receiver compares XON1, XOFF1.
681 if (termios->c_iflag & IXOFF)
682 up->efr |= OMAP_UART_SW_RX;
684 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
685 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
687 up->mcr = serial_in(up, UART_MCR);
691 * Enable any character to restart output.
692 * Operation resumes after receiving any
693 * character after recognition of the XOFF character
695 if (termios->c_iflag & IXANY)
696 up->mcr |= UART_MCR_XONANY;
698 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
699 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
700 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
701 /* Enable special char function UARTi.EFR_REG[5] and
702 * load the new software flow control mode IXON or IXOFF
703 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
705 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
706 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
708 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
709 serial_out(up, UART_LCR, up->lcr);
712 static void serial_omap_uart_qos_work(struct work_struct *work)
714 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
717 pm_qos_update_request(&up->pm_qos_request, up->latency);
721 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
722 struct ktermios *old)
724 struct uart_omap_port *up = (struct uart_omap_port *)port;
725 unsigned char cval = 0;
726 unsigned char efr = 0;
727 unsigned long flags = 0;
728 unsigned int baud, quot;
730 switch (termios->c_cflag & CSIZE) {
732 cval = UART_LCR_WLEN5;
735 cval = UART_LCR_WLEN6;
738 cval = UART_LCR_WLEN7;
742 cval = UART_LCR_WLEN8;
746 if (termios->c_cflag & CSTOPB)
747 cval |= UART_LCR_STOP;
748 if (termios->c_cflag & PARENB)
749 cval |= UART_LCR_PARITY;
750 if (!(termios->c_cflag & PARODD))
751 cval |= UART_LCR_EPAR;
754 * Ask the core to calculate the divisor for us.
757 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
758 quot = serial_omap_get_divisor(port, baud);
760 /* calculate wakeup latency constraint */
761 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
762 up->latency = up->calc_latency;
763 schedule_work(&up->qos_work);
765 up->dll = quot & 0xff;
767 up->mdr1 = UART_OMAP_MDR1_DISABLE;
769 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
770 UART_FCR_ENABLE_FIFO;
772 up->fcr |= UART_FCR_DMA_SELECT;
775 * Ok, we're now changing the port state. Do it with
776 * interrupts disabled.
778 pm_runtime_get_sync(&up->pdev->dev);
779 spin_lock_irqsave(&up->port.lock, flags);
782 * Update the per-port timeout.
784 uart_update_timeout(port, termios->c_cflag, baud);
786 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
787 if (termios->c_iflag & INPCK)
788 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
789 if (termios->c_iflag & (BRKINT | PARMRK))
790 up->port.read_status_mask |= UART_LSR_BI;
793 * Characters to ignore
795 up->port.ignore_status_mask = 0;
796 if (termios->c_iflag & IGNPAR)
797 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
798 if (termios->c_iflag & IGNBRK) {
799 up->port.ignore_status_mask |= UART_LSR_BI;
801 * If we're ignoring parity and break indicators,
802 * ignore overruns too (for real raw support).
804 if (termios->c_iflag & IGNPAR)
805 up->port.ignore_status_mask |= UART_LSR_OE;
809 * ignore all characters if CREAD is not set
811 if ((termios->c_cflag & CREAD) == 0)
812 up->port.ignore_status_mask |= UART_LSR_DR;
815 * Modem status interrupts
817 up->ier &= ~UART_IER_MSI;
818 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
819 up->ier |= UART_IER_MSI;
820 serial_out(up, UART_IER, up->ier);
821 serial_out(up, UART_LCR, cval); /* reset DLAB */
823 up->scr = OMAP_UART_SCR_TX_EMPTY;
825 /* FIFOs and DMA Settings */
827 /* FCR can be changed only when the
828 * baud clock is not running
829 * DLL_REG and DLH_REG set to 0.
831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
832 serial_out(up, UART_DLL, 0);
833 serial_out(up, UART_DLM, 0);
834 serial_out(up, UART_LCR, 0);
836 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
838 up->efr = serial_in(up, UART_EFR);
839 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
841 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
842 up->mcr = serial_in(up, UART_MCR);
843 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
844 /* FIFO ENABLE, DMA MODE */
846 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
849 serial_out(up, UART_TI752_TLR, 0);
850 up->scr |= UART_FCR_TRIGGER_4;
852 /* Set receive FIFO threshold to 1 byte */
853 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
854 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
857 serial_out(up, UART_FCR, up->fcr);
858 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
860 serial_out(up, UART_OMAP_SCR, up->scr);
862 serial_out(up, UART_EFR, up->efr);
863 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
864 serial_out(up, UART_MCR, up->mcr);
866 /* Protocol, Baud Rate, and Interrupt Settings */
868 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
869 serial_omap_mdr1_errataset(up, up->mdr1);
871 serial_out(up, UART_OMAP_MDR1, up->mdr1);
873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
875 up->efr = serial_in(up, UART_EFR);
876 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
878 serial_out(up, UART_LCR, 0);
879 serial_out(up, UART_IER, 0);
880 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
882 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
883 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
885 serial_out(up, UART_LCR, 0);
886 serial_out(up, UART_IER, up->ier);
887 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
889 serial_out(up, UART_EFR, up->efr);
890 serial_out(up, UART_LCR, cval);
892 if (baud > 230400 && baud != 3000000)
893 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
895 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
897 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
898 serial_omap_mdr1_errataset(up, up->mdr1);
900 serial_out(up, UART_OMAP_MDR1, up->mdr1);
902 /* Hardware Flow Control Configuration */
904 if (termios->c_cflag & CRTSCTS) {
905 efr |= (UART_EFR_CTS | UART_EFR_RTS);
906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
908 up->mcr = serial_in(up, UART_MCR);
909 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
912 up->efr = serial_in(up, UART_EFR);
913 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
915 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
916 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
917 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
918 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
919 serial_out(up, UART_LCR, cval);
922 serial_omap_set_mctrl(&up->port, up->port.mctrl);
923 /* Software Flow Control Configuration */
924 serial_omap_configure_xonxoff(up, termios);
926 spin_unlock_irqrestore(&up->port.lock, flags);
927 pm_runtime_put(&up->pdev->dev);
928 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
932 serial_omap_pm(struct uart_port *port, unsigned int state,
933 unsigned int oldstate)
935 struct uart_omap_port *up = (struct uart_omap_port *)port;
938 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
940 pm_runtime_get_sync(&up->pdev->dev);
941 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
942 efr = serial_in(up, UART_EFR);
943 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
944 serial_out(up, UART_LCR, 0);
946 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
947 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
948 serial_out(up, UART_EFR, efr);
949 serial_out(up, UART_LCR, 0);
951 if (!device_may_wakeup(&up->pdev->dev)) {
953 pm_runtime_forbid(&up->pdev->dev);
955 pm_runtime_allow(&up->pdev->dev);
958 pm_runtime_put(&up->pdev->dev);
961 static void serial_omap_release_port(struct uart_port *port)
963 dev_dbg(port->dev, "serial_omap_release_port+\n");
966 static int serial_omap_request_port(struct uart_port *port)
968 dev_dbg(port->dev, "serial_omap_request_port+\n");
972 static void serial_omap_config_port(struct uart_port *port, int flags)
974 struct uart_omap_port *up = (struct uart_omap_port *)port;
976 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
978 up->port.type = PORT_OMAP;
982 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
984 /* we don't want the core code to modify any port params */
985 dev_dbg(port->dev, "serial_omap_verify_port+\n");
990 serial_omap_type(struct uart_port *port)
992 struct uart_omap_port *up = (struct uart_omap_port *)port;
994 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
998 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1000 static inline void wait_for_xmitr(struct uart_omap_port *up)
1002 unsigned int status, tmout = 10000;
1004 /* Wait up to 10ms for the character(s) to be sent. */
1006 status = serial_in(up, UART_LSR);
1008 if (status & UART_LSR_BI)
1009 up->lsr_break_flag = UART_LSR_BI;
1014 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1016 /* Wait up to 1s for flow control if necessary */
1017 if (up->port.flags & UPF_CONS_FLOW) {
1019 for (tmout = 1000000; tmout; tmout--) {
1020 unsigned int msr = serial_in(up, UART_MSR);
1022 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1023 if (msr & UART_MSR_CTS)
1031 #ifdef CONFIG_CONSOLE_POLL
1033 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1035 struct uart_omap_port *up = (struct uart_omap_port *)port;
1037 pm_runtime_get_sync(&up->pdev->dev);
1039 serial_out(up, UART_TX, ch);
1040 pm_runtime_put(&up->pdev->dev);
1043 static int serial_omap_poll_get_char(struct uart_port *port)
1045 struct uart_omap_port *up = (struct uart_omap_port *)port;
1046 unsigned int status;
1048 pm_runtime_get_sync(&up->pdev->dev);
1049 status = serial_in(up, UART_LSR);
1050 if (!(status & UART_LSR_DR))
1051 return NO_POLL_CHAR;
1053 status = serial_in(up, UART_RX);
1054 pm_runtime_put(&up->pdev->dev);
1058 #endif /* CONFIG_CONSOLE_POLL */
1060 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1062 static struct uart_omap_port *serial_omap_console_ports[4];
1064 static struct uart_driver serial_omap_reg;
1066 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1068 struct uart_omap_port *up = (struct uart_omap_port *)port;
1071 serial_out(up, UART_TX, ch);
1075 serial_omap_console_write(struct console *co, const char *s,
1078 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1079 unsigned long flags;
1083 pm_runtime_get_sync(&up->pdev->dev);
1085 local_irq_save(flags);
1088 else if (oops_in_progress)
1089 locked = spin_trylock(&up->port.lock);
1091 spin_lock(&up->port.lock);
1094 * First save the IER then disable the interrupts
1096 ier = serial_in(up, UART_IER);
1097 serial_out(up, UART_IER, 0);
1099 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1102 * Finally, wait for transmitter to become empty
1103 * and restore the IER
1106 serial_out(up, UART_IER, ier);
1108 * The receive handling will happen properly because the
1109 * receive ready bit will still be set; it is not cleared
1110 * on read. However, modem control will not, we must
1111 * call it if we have saved something in the saved flags
1112 * while processing with interrupts off.
1114 if (up->msr_saved_flags)
1115 check_modem_status(up);
1117 pm_runtime_mark_last_busy(&up->pdev->dev);
1118 pm_runtime_put_autosuspend(&up->pdev->dev);
1120 spin_unlock(&up->port.lock);
1121 local_irq_restore(flags);
1125 serial_omap_console_setup(struct console *co, char *options)
1127 struct uart_omap_port *up;
1133 if (serial_omap_console_ports[co->index] == NULL)
1135 up = serial_omap_console_ports[co->index];
1138 uart_parse_options(options, &baud, &parity, &bits, &flow);
1140 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1143 static struct console serial_omap_console = {
1144 .name = OMAP_SERIAL_NAME,
1145 .write = serial_omap_console_write,
1146 .device = uart_console_device,
1147 .setup = serial_omap_console_setup,
1148 .flags = CON_PRINTBUFFER,
1150 .data = &serial_omap_reg,
1153 static void serial_omap_add_console_port(struct uart_omap_port *up)
1155 serial_omap_console_ports[up->port.line] = up;
1158 #define OMAP_CONSOLE (&serial_omap_console)
1162 #define OMAP_CONSOLE NULL
1164 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1169 static struct uart_ops serial_omap_pops = {
1170 .tx_empty = serial_omap_tx_empty,
1171 .set_mctrl = serial_omap_set_mctrl,
1172 .get_mctrl = serial_omap_get_mctrl,
1173 .stop_tx = serial_omap_stop_tx,
1174 .start_tx = serial_omap_start_tx,
1175 .stop_rx = serial_omap_stop_rx,
1176 .enable_ms = serial_omap_enable_ms,
1177 .break_ctl = serial_omap_break_ctl,
1178 .startup = serial_omap_startup,
1179 .shutdown = serial_omap_shutdown,
1180 .set_termios = serial_omap_set_termios,
1181 .pm = serial_omap_pm,
1182 .type = serial_omap_type,
1183 .release_port = serial_omap_release_port,
1184 .request_port = serial_omap_request_port,
1185 .config_port = serial_omap_config_port,
1186 .verify_port = serial_omap_verify_port,
1187 #ifdef CONFIG_CONSOLE_POLL
1188 .poll_put_char = serial_omap_poll_put_char,
1189 .poll_get_char = serial_omap_poll_get_char,
1193 static struct uart_driver serial_omap_reg = {
1194 .owner = THIS_MODULE,
1195 .driver_name = "OMAP-SERIAL",
1196 .dev_name = OMAP_SERIAL_NAME,
1197 .nr = OMAP_MAX_HSUART_PORTS,
1198 .cons = OMAP_CONSOLE,
1201 #ifdef CONFIG_PM_SLEEP
1202 static int serial_omap_suspend(struct device *dev)
1204 struct uart_omap_port *up = dev_get_drvdata(dev);
1207 uart_suspend_port(&serial_omap_reg, &up->port);
1208 flush_work(&up->qos_work);
1214 static int serial_omap_resume(struct device *dev)
1216 struct uart_omap_port *up = dev_get_drvdata(dev);
1219 uart_resume_port(&serial_omap_reg, &up->port);
1224 static void serial_omap_rxdma_poll(unsigned long uart_no)
1226 struct uart_omap_port *up = ui[uart_no];
1227 unsigned int curr_dma_pos, curr_transmitted_size;
1230 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1231 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1232 (curr_dma_pos == 0)) {
1233 if (jiffies_to_msecs(jiffies - up->port_activity) <
1234 up->uart_dma.rx_timeout) {
1235 mod_timer(&up->uart_dma.rx_timer, jiffies +
1236 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1238 serial_omap_stop_rxdma(up);
1239 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1240 serial_out(up, UART_IER, up->ier);
1245 curr_transmitted_size = curr_dma_pos -
1246 up->uart_dma.prev_rx_dma_pos;
1247 up->port.icount.rx += curr_transmitted_size;
1248 tty_insert_flip_string(up->port.state->port.tty,
1249 up->uart_dma.rx_buf +
1250 (up->uart_dma.prev_rx_dma_pos -
1251 up->uart_dma.rx_buf_dma_phys),
1252 curr_transmitted_size);
1253 tty_flip_buffer_push(up->port.state->port.tty);
1254 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1255 if (up->uart_dma.rx_buf_size +
1256 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1257 ret = serial_omap_start_rxdma(up);
1259 serial_omap_stop_rxdma(up);
1260 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1261 serial_out(up, UART_IER, up->ier);
1264 mod_timer(&up->uart_dma.rx_timer, jiffies +
1265 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1267 up->port_activity = jiffies;
1270 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1275 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1279 if (up->uart_dma.rx_dma_channel == -1) {
1280 pm_runtime_get_sync(&up->pdev->dev);
1281 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1283 (void *)uart_rx_dma_callback, up,
1284 &(up->uart_dma.rx_dma_channel));
1288 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1289 OMAP_DMA_AMODE_CONSTANT,
1290 up->uart_dma.uart_base, 0, 0);
1291 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1292 OMAP_DMA_AMODE_POST_INC,
1293 up->uart_dma.rx_buf_dma_phys, 0, 0);
1294 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1295 OMAP_DMA_DATA_TYPE_S8,
1296 up->uart_dma.rx_buf_size, 1,
1297 OMAP_DMA_SYNC_ELEMENT,
1298 up->uart_dma.uart_dma_rx, 0);
1300 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1301 /* FIXME: Cache maintenance needed here? */
1302 omap_start_dma(up->uart_dma.rx_dma_channel);
1303 mod_timer(&up->uart_dma.rx_timer, jiffies +
1304 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1305 up->uart_dma.rx_dma_used = true;
1309 static void serial_omap_continue_tx(struct uart_omap_port *up)
1311 struct circ_buf *xmit = &up->port.state->xmit;
1312 unsigned int start = up->uart_dma.tx_buf_dma_phys
1313 + (xmit->tail & (UART_XMIT_SIZE - 1));
1315 if (uart_circ_empty(xmit))
1318 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1320 * It is a circular buffer. See if the buffer has wounded back.
1321 * If yes it will have to be transferred in two separate dma
1324 if (start + up->uart_dma.tx_buf_size >=
1325 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1326 up->uart_dma.tx_buf_size =
1327 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1328 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1329 OMAP_DMA_AMODE_CONSTANT,
1330 up->uart_dma.uart_base, 0, 0);
1331 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1332 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1333 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1334 OMAP_DMA_DATA_TYPE_S8,
1335 up->uart_dma.tx_buf_size, 1,
1336 OMAP_DMA_SYNC_ELEMENT,
1337 up->uart_dma.uart_dma_tx, 0);
1338 /* FIXME: Cache maintenance needed here? */
1339 omap_start_dma(up->uart_dma.tx_dma_channel);
1342 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1344 struct uart_omap_port *up = (struct uart_omap_port *)data;
1345 struct circ_buf *xmit = &up->port.state->xmit;
1347 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1348 (UART_XMIT_SIZE - 1);
1349 up->port.icount.tx += up->uart_dma.tx_buf_size;
1351 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1352 uart_write_wakeup(&up->port);
1354 if (uart_circ_empty(xmit)) {
1355 spin_lock(&(up->uart_dma.tx_lock));
1356 serial_omap_stop_tx(&up->port);
1357 up->uart_dma.tx_dma_used = false;
1358 spin_unlock(&(up->uart_dma.tx_lock));
1360 omap_stop_dma(up->uart_dma.tx_dma_channel);
1361 serial_omap_continue_tx(up);
1363 up->port_activity = jiffies;
1367 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1370 u16 revision, major, minor;
1372 mvr = serial_in(up, UART_OMAP_MVER);
1374 /* Check revision register scheme */
1375 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1378 case 0: /* Legacy Scheme: OMAP2/3 */
1379 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1380 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1381 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1382 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1385 /* New Scheme: OMAP4+ */
1386 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1387 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1388 OMAP_UART_MVR_MAJ_SHIFT;
1389 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1392 dev_warn(&up->pdev->dev,
1393 "Unknown %s revision, defaulting to highest\n",
1395 /* highest possible revision */
1400 /* normalize revision for the driver */
1401 revision = UART_BUILD_REVISION(major, minor);
1404 case OMAP_UART_REV_46:
1405 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1406 UART_ERRATA_i291_DMA_FORCEIDLE);
1408 case OMAP_UART_REV_52:
1409 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1410 UART_ERRATA_i291_DMA_FORCEIDLE);
1412 case OMAP_UART_REV_63:
1413 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1420 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1422 struct omap_uart_port_info *omap_up_info;
1424 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1426 return NULL; /* out of memory */
1428 of_property_read_u32(dev->of_node, "clock-frequency",
1429 &omap_up_info->uartclk);
1430 return omap_up_info;
1433 static int serial_omap_probe(struct platform_device *pdev)
1435 struct uart_omap_port *up;
1436 struct resource *mem, *irq, *dma_tx, *dma_rx;
1437 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1440 if (pdev->dev.of_node)
1441 omap_up_info = of_get_uart_port_info(&pdev->dev);
1443 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1445 dev_err(&pdev->dev, "no mem resource?\n");
1449 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1451 dev_err(&pdev->dev, "no irq resource?\n");
1455 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1456 pdev->dev.driver->name)) {
1457 dev_err(&pdev->dev, "memory region already claimed\n");
1461 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1465 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1469 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1474 up->port.dev = &pdev->dev;
1475 up->port.type = PORT_OMAP;
1476 up->port.iotype = UPIO_MEM;
1477 up->port.irq = irq->start;
1479 up->port.regshift = 2;
1480 up->port.fifosize = 64;
1481 up->port.ops = &serial_omap_pops;
1483 if (pdev->dev.of_node)
1484 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1486 up->port.line = pdev->id;
1488 if (up->port.line < 0) {
1489 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1495 sprintf(up->name, "OMAP UART%d", up->port.line);
1496 up->port.mapbase = mem->start;
1497 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1498 resource_size(mem));
1499 if (!up->port.membase) {
1500 dev_err(&pdev->dev, "can't ioremap UART\n");
1505 up->port.flags = omap_up_info->flags;
1506 up->port.uartclk = omap_up_info->uartclk;
1507 if (!up->port.uartclk) {
1508 up->port.uartclk = DEFAULT_CLK_SPEED;
1509 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1510 "%d\n", DEFAULT_CLK_SPEED);
1512 up->uart_dma.uart_base = mem->start;
1514 if (omap_up_info->dma_enabled) {
1515 up->uart_dma.uart_dma_tx = dma_tx->start;
1516 up->uart_dma.uart_dma_rx = dma_rx->start;
1518 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1519 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1520 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1521 spin_lock_init(&(up->uart_dma.tx_lock));
1522 spin_lock_init(&(up->uart_dma.rx_lock));
1523 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1524 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1527 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1528 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1529 pm_qos_add_request(&up->pm_qos_request,
1530 PM_QOS_CPU_DMA_LATENCY, up->latency);
1531 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1532 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1534 pm_runtime_use_autosuspend(&pdev->dev);
1535 pm_runtime_set_autosuspend_delay(&pdev->dev,
1536 omap_up_info->autosuspend_timeout);
1538 pm_runtime_irq_safe(&pdev->dev);
1539 pm_runtime_enable(&pdev->dev);
1540 pm_runtime_get_sync(&pdev->dev);
1542 omap_serial_fill_features_erratas(up);
1544 ui[up->port.line] = up;
1545 serial_omap_add_console_port(up);
1547 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1551 pm_runtime_put(&pdev->dev);
1552 platform_set_drvdata(pdev, up);
1556 pm_runtime_put(&pdev->dev);
1557 pm_runtime_disable(&pdev->dev);
1560 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1561 pdev->id, __func__, ret);
1565 static int serial_omap_remove(struct platform_device *dev)
1567 struct uart_omap_port *up = platform_get_drvdata(dev);
1570 pm_runtime_disable(&up->pdev->dev);
1571 uart_remove_one_port(&serial_omap_reg, &up->port);
1572 pm_qos_remove_request(&up->pm_qos_request);
1575 platform_set_drvdata(dev, NULL);
1580 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1581 * The access to uart register after MDR1 Access
1582 * causes UART to corrupt data.
1585 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1586 * give 10 times as much
1588 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1592 serial_out(up, UART_OMAP_MDR1, mdr1);
1594 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1595 UART_FCR_CLEAR_RCVR);
1597 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1598 * TX_FIFO_E bit is 1.
1600 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1601 (UART_LSR_THRE | UART_LSR_DR))) {
1604 /* Should *never* happen. we warn and carry on */
1605 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1606 serial_in(up, UART_LSR));
1613 #ifdef CONFIG_PM_RUNTIME
1614 static void serial_omap_restore_context(struct uart_omap_port *up)
1616 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1617 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1619 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1621 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1622 serial_out(up, UART_EFR, UART_EFR_ECB);
1623 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1624 serial_out(up, UART_IER, 0x0);
1625 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1626 serial_out(up, UART_DLL, up->dll);
1627 serial_out(up, UART_DLM, up->dlh);
1628 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1629 serial_out(up, UART_IER, up->ier);
1630 serial_out(up, UART_FCR, up->fcr);
1631 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1632 serial_out(up, UART_MCR, up->mcr);
1633 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1634 serial_out(up, UART_OMAP_SCR, up->scr);
1635 serial_out(up, UART_EFR, up->efr);
1636 serial_out(up, UART_LCR, up->lcr);
1637 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1638 serial_omap_mdr1_errataset(up, up->mdr1);
1640 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1643 static int serial_omap_runtime_suspend(struct device *dev)
1645 struct uart_omap_port *up = dev_get_drvdata(dev);
1646 struct omap_uart_port_info *pdata = dev->platform_data;
1651 if (!pdata || !pdata->enable_wakeup)
1654 if (pdata->get_context_loss_count)
1655 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1657 if (device_may_wakeup(dev)) {
1658 if (!up->wakeups_enabled) {
1659 pdata->enable_wakeup(up->pdev, true);
1660 up->wakeups_enabled = true;
1663 if (up->wakeups_enabled) {
1664 pdata->enable_wakeup(up->pdev, false);
1665 up->wakeups_enabled = false;
1670 if (up->use_dma && pdata->set_forceidle &&
1671 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1672 pdata->set_forceidle(up->pdev);
1674 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1675 schedule_work(&up->qos_work);
1680 static int serial_omap_runtime_resume(struct device *dev)
1682 struct uart_omap_port *up = dev_get_drvdata(dev);
1683 struct omap_uart_port_info *pdata = dev->platform_data;
1686 if (pdata->get_context_loss_count) {
1687 u32 loss_cnt = pdata->get_context_loss_count(dev);
1689 if (up->context_loss_cnt != loss_cnt)
1690 serial_omap_restore_context(up);
1694 if (up->use_dma && pdata->set_noidle &&
1695 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1696 pdata->set_noidle(up->pdev);
1698 up->latency = up->calc_latency;
1699 schedule_work(&up->qos_work);
1706 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1707 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1708 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1709 serial_omap_runtime_resume, NULL)
1712 #if defined(CONFIG_OF)
1713 static const struct of_device_id omap_serial_of_match[] = {
1714 { .compatible = "ti,omap2-uart" },
1715 { .compatible = "ti,omap3-uart" },
1716 { .compatible = "ti,omap4-uart" },
1719 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1722 static struct platform_driver serial_omap_driver = {
1723 .probe = serial_omap_probe,
1724 .remove = serial_omap_remove,
1726 .name = DRIVER_NAME,
1727 .pm = &serial_omap_dev_pm_ops,
1728 .of_match_table = of_match_ptr(omap_serial_of_match),
1732 static int __init serial_omap_init(void)
1736 ret = uart_register_driver(&serial_omap_reg);
1739 ret = platform_driver_register(&serial_omap_driver);
1741 uart_unregister_driver(&serial_omap_reg);
1745 static void __exit serial_omap_exit(void)
1747 platform_driver_unregister(&serial_omap_driver);
1748 uart_unregister_driver(&serial_omap_reg);
1751 module_init(serial_omap_init);
1752 module_exit(serial_omap_exit);
1754 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1755 MODULE_LICENSE("GPL");
1756 MODULE_AUTHOR("Texas Instruments Inc");