2 * ***************************************************************************
3 * Marvell Armada-3700 Serial Driver
4 * Author: Wilson Ding <dingwei@marvell.com>
5 * Copyright (C) 2015 Marvell International Ltd.
6 * ***************************************************************************
7 * This program is free software: you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation, either version 2 of the License, or any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 * ***************************************************************************
21 #include <linux/clk.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/slab.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
41 #define UART_STD_RBR 0x00
43 #define UART_STD_TSH 0x04
45 #define UART_STD_CTRL1 0x08
46 #define CTRL_SOFT_RST BIT(31)
47 #define CTRL_TXFIFO_RST BIT(15)
48 #define CTRL_RXFIFO_RST BIT(14)
49 #define CTRL_SND_BRK_SEQ BIT(11)
50 #define CTRL_BRK_DET_INT BIT(3)
51 #define CTRL_FRM_ERR_INT BIT(2)
52 #define CTRL_PAR_ERR_INT BIT(1)
53 #define CTRL_OVR_ERR_INT BIT(0)
54 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
55 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
57 #define UART_STD_CTRL2 UART_STD_CTRL1
58 #define CTRL_STD_TX_RDY_INT BIT(5)
59 #define CTRL_STD_RX_RDY_INT BIT(4)
61 #define UART_STAT 0x0C
62 #define STAT_TX_FIFO_EMP BIT(13)
63 #define STAT_TX_FIFO_FUL BIT(11)
64 #define STAT_TX_EMP BIT(6)
65 #define STAT_STD_TX_RDY BIT(5)
66 #define STAT_STD_RX_RDY BIT(4)
67 #define STAT_BRK_DET BIT(3)
68 #define STAT_FRM_ERR BIT(2)
69 #define STAT_PAR_ERR BIT(1)
70 #define STAT_OVR_ERR BIT(0)
71 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
72 | STAT_PAR_ERR | STAT_OVR_ERR)
74 #define UART_BRDV 0x10
75 #define BRDV_BAUD_MASK 0x3FF
77 #define MVEBU_NR_UARTS 1
79 #define MVEBU_UART_TYPE "mvebu-uart"
80 #define DRIVER_NAME "mvebu_serial"
82 /* Register offsets, different depending on the UART */
83 struct uart_regs_layout {
92 unsigned int ctrl_tx_rdy_int;
93 unsigned int ctrl_rx_rdy_int;
94 unsigned int stat_tx_rdy;
95 unsigned int stat_rx_rdy;
98 /* Driver data, a structure for each UART port */
99 struct mvebu_uart_driver_data {
101 struct uart_regs_layout regs;
102 struct uart_flags flags;
105 /* MVEBU UART driver structure */
107 struct uart_port *port;
109 struct mvebu_uart_driver_data *data;
112 static struct mvebu_uart *to_mvuart(struct uart_port *port)
114 return (struct mvebu_uart *)port->private_data;
117 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
119 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
120 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
121 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
122 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
124 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
125 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
126 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
127 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
129 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
131 /* Core UART Driver Operations */
132 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
137 spin_lock_irqsave(&port->lock, flags);
138 st = readl(port->membase + UART_STAT);
139 spin_unlock_irqrestore(&port->lock, flags);
141 return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
144 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
146 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
149 static void mvebu_uart_set_mctrl(struct uart_port *port,
153 * Even if we do not support configuring the modem control lines, this
154 * function must be proided to the serial core
158 static void mvebu_uart_stop_tx(struct uart_port *port)
160 unsigned int ctl = readl(port->membase + UART_INTR(port));
162 ctl &= ~CTRL_TX_RDY_INT(port);
163 writel(ctl, port->membase + UART_INTR(port));
166 static void mvebu_uart_start_tx(struct uart_port *port)
169 struct circ_buf *xmit = &port->state->xmit;
171 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
172 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
173 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
177 ctl = readl(port->membase + UART_INTR(port));
178 ctl |= CTRL_TX_RDY_INT(port);
179 writel(ctl, port->membase + UART_INTR(port));
182 static void mvebu_uart_stop_rx(struct uart_port *port)
186 ctl = readl(port->membase + UART_CTRL(port));
187 ctl &= ~CTRL_BRK_INT;
188 writel(ctl, port->membase + UART_CTRL(port));
190 ctl = readl(port->membase + UART_INTR(port));
191 ctl &= ~CTRL_RX_RDY_INT(port);
192 writel(ctl, port->membase + UART_INTR(port));
195 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
200 spin_lock_irqsave(&port->lock, flags);
201 ctl = readl(port->membase + UART_CTRL(port));
203 ctl |= CTRL_SND_BRK_SEQ;
205 ctl &= ~CTRL_SND_BRK_SEQ;
206 writel(ctl, port->membase + UART_CTRL(port));
207 spin_unlock_irqrestore(&port->lock, flags);
210 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
212 struct tty_port *tport = &port->state->port;
213 unsigned char ch = 0;
217 if (status & STAT_RX_RDY(port)) {
218 ch = readl(port->membase + UART_RBR(port));
223 if (status & STAT_PAR_ERR)
224 port->icount.parity++;
227 if (status & STAT_BRK_DET) {
229 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
230 if (uart_handle_break(port))
234 if (status & STAT_OVR_ERR)
235 port->icount.overrun++;
237 if (status & STAT_FRM_ERR)
238 port->icount.frame++;
240 if (uart_handle_sysrq_char(port, ch))
243 if (status & port->ignore_status_mask & STAT_PAR_ERR)
244 status &= ~STAT_RX_RDY(port);
246 status &= port->read_status_mask;
248 if (status & STAT_PAR_ERR)
251 status &= ~port->ignore_status_mask;
253 if (status & STAT_RX_RDY(port))
254 tty_insert_flip_char(tport, ch, flag);
256 if (status & STAT_BRK_DET)
257 tty_insert_flip_char(tport, 0, TTY_BREAK);
259 if (status & STAT_FRM_ERR)
260 tty_insert_flip_char(tport, 0, TTY_FRAME);
262 if (status & STAT_OVR_ERR)
263 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
266 status = readl(port->membase + UART_STAT);
267 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
269 tty_flip_buffer_push(tport);
272 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
274 struct circ_buf *xmit = &port->state->xmit;
279 writel(port->x_char, port->membase + UART_TSH(port));
285 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
286 mvebu_uart_stop_tx(port);
290 for (count = 0; count < port->fifosize; count++) {
291 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
292 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
295 if (uart_circ_empty(xmit))
298 st = readl(port->membase + UART_STAT);
299 if (st & STAT_TX_FIFO_FUL)
303 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
304 uart_write_wakeup(port);
306 if (uart_circ_empty(xmit))
307 mvebu_uart_stop_tx(port);
310 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
312 struct uart_port *port = (struct uart_port *)dev_id;
313 unsigned int st = readl(port->membase + UART_STAT);
315 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
317 mvebu_uart_rx_chars(port, st);
319 if (st & STAT_TX_RDY(port))
320 mvebu_uart_tx_chars(port, st);
325 static int mvebu_uart_startup(struct uart_port *port)
330 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
331 port->membase + UART_CTRL(port));
334 /* Clear the error bits of state register before IRQ request */
335 ret = readl(port->membase + UART_STAT);
337 writel(ret, port->membase + UART_STAT);
339 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
341 ctl = readl(port->membase + UART_INTR(port));
342 ctl |= CTRL_RX_RDY_INT(port);
343 writel(ctl, port->membase + UART_INTR(port));
345 ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags,
348 dev_err(port->dev, "failed to request irq\n");
355 static void mvebu_uart_shutdown(struct uart_port *port)
357 writel(0, port->membase + UART_INTR(port));
359 free_irq(port->irq, port);
362 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
364 struct mvebu_uart *mvuart = to_mvuart(port);
365 unsigned int baud_rate_div;
368 if (IS_ERR(mvuart->clk))
369 return -PTR_ERR(mvuart->clk);
372 * The UART clock is divided by the value of the divisor to generate
373 * UCLK_OUT clock, which is 16 times faster than the baudrate.
374 * This prescaler can achieve all standard baudrates until 230400.
375 * Higher baudrates could be achieved for the extended UART by using the
376 * programmable oversampling stack (also called fractional divisor).
378 baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
379 brdv = readl(port->membase + UART_BRDV);
380 brdv &= ~BRDV_BAUD_MASK;
381 brdv |= baud_rate_div;
382 writel(brdv, port->membase + UART_BRDV);
387 static void mvebu_uart_set_termios(struct uart_port *port,
388 struct ktermios *termios,
389 struct ktermios *old)
394 spin_lock_irqsave(&port->lock, flags);
396 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
397 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
399 if (termios->c_iflag & INPCK)
400 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
402 port->ignore_status_mask = 0;
403 if (termios->c_iflag & IGNPAR)
404 port->ignore_status_mask |=
405 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
407 if ((termios->c_cflag & CREAD) == 0)
408 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
411 * Maximum achievable frequency with simple baudrate divisor is 230400.
412 * Since the error per bit frame would be of more than 15%, achieving
413 * higher frequencies would require to implement the fractional divisor
416 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
417 if (mvebu_uart_baud_rate_set(port, baud)) {
418 /* No clock available, baudrate cannot be changed */
420 baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
422 tty_termios_encode_baud_rate(termios, baud, baud);
423 uart_update_timeout(port, termios->c_cflag, baud);
426 /* Only the following flag changes are supported */
428 termios->c_iflag &= INPCK | IGNPAR;
429 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
430 termios->c_cflag &= CREAD | CBAUD;
431 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
432 termios->c_lflag = old->c_lflag;
435 spin_unlock_irqrestore(&port->lock, flags);
438 static const char *mvebu_uart_type(struct uart_port *port)
440 return MVEBU_UART_TYPE;
443 static void mvebu_uart_release_port(struct uart_port *port)
445 /* Nothing to do here */
448 static int mvebu_uart_request_port(struct uart_port *port)
453 #ifdef CONFIG_CONSOLE_POLL
454 static int mvebu_uart_get_poll_char(struct uart_port *port)
456 unsigned int st = readl(port->membase + UART_STAT);
458 if (!(st & STAT_RX_RDY(port)))
461 return readl(port->membase + UART_RBR(port));
464 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
469 st = readl(port->membase + UART_STAT);
471 if (!(st & STAT_TX_FIFO_FUL))
477 writel(c, port->membase + UART_TSH(port));
481 static const struct uart_ops mvebu_uart_ops = {
482 .tx_empty = mvebu_uart_tx_empty,
483 .set_mctrl = mvebu_uart_set_mctrl,
484 .get_mctrl = mvebu_uart_get_mctrl,
485 .stop_tx = mvebu_uart_stop_tx,
486 .start_tx = mvebu_uart_start_tx,
487 .stop_rx = mvebu_uart_stop_rx,
488 .break_ctl = mvebu_uart_break_ctl,
489 .startup = mvebu_uart_startup,
490 .shutdown = mvebu_uart_shutdown,
491 .set_termios = mvebu_uart_set_termios,
492 .type = mvebu_uart_type,
493 .release_port = mvebu_uart_release_port,
494 .request_port = mvebu_uart_request_port,
495 #ifdef CONFIG_CONSOLE_POLL
496 .poll_get_char = mvebu_uart_get_poll_char,
497 .poll_put_char = mvebu_uart_put_poll_char,
501 /* Console Driver Operations */
503 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
505 static void mvebu_uart_putc(struct uart_port *port, int c)
510 st = readl(port->membase + UART_STAT);
511 if (!(st & STAT_TX_FIFO_FUL))
515 /* At early stage, DT is not parsed yet, only use UART0 */
516 writel(c, port->membase + UART_STD_TSH);
519 st = readl(port->membase + UART_STAT);
520 if (st & STAT_TX_FIFO_EMP)
525 static void mvebu_uart_putc_early_write(struct console *con,
529 struct earlycon_device *dev = con->data;
531 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
535 mvebu_uart_early_console_setup(struct earlycon_device *device,
538 if (!device->port.membase)
541 device->con->write = mvebu_uart_putc_early_write;
546 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
547 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
548 mvebu_uart_early_console_setup);
550 static void wait_for_xmitr(struct uart_port *port)
554 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
555 (val & STAT_TX_EMP), 1, 10000);
558 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
560 wait_for_xmitr(port);
561 writel(ch, port->membase + UART_TSH(port));
564 static void mvebu_uart_console_write(struct console *co, const char *s,
567 struct uart_port *port = &mvebu_uart_ports[co->index];
569 unsigned int ier, intr, ctl;
572 if (oops_in_progress)
573 locked = spin_trylock_irqsave(&port->lock, flags);
575 spin_lock_irqsave(&port->lock, flags);
577 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
578 intr = readl(port->membase + UART_INTR(port)) &
579 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
580 writel(0, port->membase + UART_CTRL(port));
581 writel(0, port->membase + UART_INTR(port));
583 uart_console_write(port, s, count, mvebu_uart_console_putchar);
585 wait_for_xmitr(port);
588 writel(ier, port->membase + UART_CTRL(port));
591 ctl = intr | readl(port->membase + UART_INTR(port));
592 writel(ctl, port->membase + UART_INTR(port));
596 spin_unlock_irqrestore(&port->lock, flags);
599 static int mvebu_uart_console_setup(struct console *co, char *options)
601 struct uart_port *port;
607 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
610 port = &mvebu_uart_ports[co->index];
612 if (!port->mapbase || !port->membase) {
613 pr_debug("console on ttyMV%i not present\n", co->index);
618 uart_parse_options(options, &baud, &parity, &bits, &flow);
620 return uart_set_options(port, co, baud, parity, bits, flow);
623 static struct uart_driver mvebu_uart_driver;
625 static struct console mvebu_uart_console = {
627 .write = mvebu_uart_console_write,
628 .device = uart_console_device,
629 .setup = mvebu_uart_console_setup,
630 .flags = CON_PRINTBUFFER,
632 .data = &mvebu_uart_driver,
635 static int __init mvebu_uart_console_init(void)
637 register_console(&mvebu_uart_console);
641 console_initcall(mvebu_uart_console_init);
644 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
646 static struct uart_driver mvebu_uart_driver = {
647 .owner = THIS_MODULE,
648 .driver_name = DRIVER_NAME,
650 .nr = MVEBU_NR_UARTS,
651 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
652 .cons = &mvebu_uart_console,
656 static const struct of_device_id mvebu_uart_of_match[];
658 /* Counter to keep track of each UART port id when not using CONFIG_OF */
659 static int uart_num_counter;
661 static int mvebu_uart_probe(struct platform_device *pdev)
663 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
665 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
667 struct uart_port *port;
668 struct mvebu_uart *mvuart;
672 dev_err(&pdev->dev, "no registers/irq defined\n");
676 /* Assume that all UART ports have a DT alias or none has */
677 id = of_alias_get_id(pdev->dev.of_node, "serial");
678 if (!pdev->dev.of_node || id < 0)
679 pdev->id = uart_num_counter++;
683 if (pdev->id >= MVEBU_NR_UARTS) {
684 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
689 port = &mvebu_uart_ports[pdev->id];
691 spin_lock_init(&port->lock);
693 port->dev = &pdev->dev;
694 port->type = PORT_MVEBU;
695 port->ops = &mvebu_uart_ops;
699 port->iotype = UPIO_MEM32;
700 port->flags = UPF_FIXED_PORT;
701 port->line = pdev->id;
703 port->irq = irq->start;
705 port->mapbase = reg->start;
707 port->membase = devm_ioremap_resource(&pdev->dev, reg);
708 if (IS_ERR(port->membase))
709 return -PTR_ERR(port->membase);
711 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
716 /* Get controller data depending on the compatible string */
717 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
720 port->private_data = mvuart;
721 platform_set_drvdata(pdev, mvuart);
723 /* Get fixed clock frequency */
724 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
725 if (IS_ERR(mvuart->clk)) {
726 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
727 return PTR_ERR(mvuart->clk);
729 if (IS_EXTENDED(port)) {
730 dev_err(&pdev->dev, "unable to get UART clock\n");
731 return PTR_ERR(mvuart->clk);
734 if (!clk_prepare_enable(mvuart->clk))
735 port->uartclk = clk_get_rate(mvuart->clk);
739 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
741 writel(0, port->membase + UART_CTRL(port));
743 ret = uart_add_one_port(&mvebu_uart_driver, port);
749 static struct mvebu_uart_driver_data uart_std_driver_data = {
751 .regs.rbr = UART_STD_RBR,
752 .regs.tsh = UART_STD_TSH,
753 .regs.ctrl = UART_STD_CTRL1,
754 .regs.intr = UART_STD_CTRL2,
755 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
756 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
757 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
758 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
761 /* Match table for of_platform binding */
762 static const struct of_device_id mvebu_uart_of_match[] = {
764 .compatible = "marvell,armada-3700-uart",
765 .data = (void *)&uart_std_driver_data,
770 static struct platform_driver mvebu_uart_platform_driver = {
771 .probe = mvebu_uart_probe,
773 .name = "mvebu-uart",
774 .of_match_table = of_match_ptr(mvebu_uart_of_match),
775 .suppress_bind_attrs = true,
779 static int __init mvebu_uart_init(void)
783 ret = uart_register_driver(&mvebu_uart_driver);
787 ret = platform_driver_register(&mvebu_uart_platform_driver);
789 uart_unregister_driver(&mvebu_uart_driver);
793 arch_initcall(mvebu_uart_init);