2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/tty_flip.h>
38 #include <linux/serial.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/delay.h>
44 #include <linux/of_platform.h>
45 #include <linux/clk.h>
47 #include <asm/mpc52xx.h>
48 #include <asm/mpc52xx_psc.h>
50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #include <linux/serial_core.h>
57 /* We've been assigned a range on the "Low-density serial ports" major */
58 #define SERIAL_PSC_MAJOR 204
59 #define SERIAL_PSC_MINOR 148
62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
65 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
74 /* lookup table for matching device nodes to index numbers */
75 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
77 static void mpc52xx_uart_of_enumerate(void);
80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83 /* Forward declaration of the interruption handling routine */
84 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
87 /* ======================================================================== */
88 /* PSC fifo operations for isolating differences between 52xx and 512x */
89 /* ======================================================================== */
92 void (*fifo_init)(struct uart_port *port);
93 int (*raw_rx_rdy)(struct uart_port *port);
94 int (*raw_tx_rdy)(struct uart_port *port);
95 int (*rx_rdy)(struct uart_port *port);
96 int (*tx_rdy)(struct uart_port *port);
97 int (*tx_empty)(struct uart_port *port);
98 void (*stop_rx)(struct uart_port *port);
99 void (*start_tx)(struct uart_port *port);
100 void (*stop_tx)(struct uart_port *port);
101 void (*rx_clr_irq)(struct uart_port *port);
102 void (*tx_clr_irq)(struct uart_port *port);
103 void (*write_char)(struct uart_port *port, unsigned char c);
104 unsigned char (*read_char)(struct uart_port *port);
105 void (*cw_disable_ints)(struct uart_port *port);
106 void (*cw_restore_ints)(struct uart_port *port);
107 unsigned int (*set_baudrate)(struct uart_port *port,
108 struct ktermios *new,
109 struct ktermios *old);
110 int (*clock)(struct uart_port *port, int enable);
111 int (*fifoc_init)(void);
112 void (*fifoc_uninit)(void);
113 void (*get_irq)(struct uart_port *, struct device_node *);
114 irqreturn_t (*handle_irq)(struct uart_port *port);
115 u16 (*get_status)(struct uart_port *port);
116 u8 (*get_ipcr)(struct uart_port *port);
117 void (*command)(struct uart_port *port, u8 cmd);
118 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
119 void (*set_rts)(struct uart_port *port, int state);
120 void (*enable_ms)(struct uart_port *port);
121 void (*set_sicr)(struct uart_port *port, u32 val);
122 void (*set_imr)(struct uart_port *port, u16 val);
123 u8 (*get_mr1)(struct uart_port *port);
126 /* setting the prescaler and divisor reg is common for all chips */
127 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
128 u16 prescaler, unsigned int divisor)
130 /* select prescaler */
131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
132 out_8(&psc->ctur, divisor >> 8);
133 out_8(&psc->ctlr, divisor & 0xff);
136 static u16 mpc52xx_psc_get_status(struct uart_port *port)
138 return in_be16(&PSC(port)->mpc52xx_psc_status);
141 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
143 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
146 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
148 out_8(&PSC(port)->command, cmd);
151 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
153 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
154 out_8(&PSC(port)->mode, mr1);
155 out_8(&PSC(port)->mode, mr2);
158 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
161 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
163 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
166 static void mpc52xx_psc_enable_ms(struct uart_port *port)
168 struct mpc52xx_psc __iomem *psc = PSC(port);
170 /* clear D_*-bits by reading them */
171 in_8(&psc->mpc52xx_psc_ipcr);
172 /* enable CTS and DCD as IPC interrupts */
173 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
175 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
176 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
179 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
181 out_be32(&PSC(port)->sicr, val);
184 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
186 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
189 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
191 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
192 return in_8(&PSC(port)->mode);
195 #ifdef CONFIG_PPC_MPC52xx
196 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
197 static void mpc52xx_psc_fifo_init(struct uart_port *port)
199 struct mpc52xx_psc __iomem *psc = PSC(port);
200 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
202 out_8(&fifo->rfcntl, 0x00);
203 out_be16(&fifo->rfalarm, 0x1ff);
204 out_8(&fifo->tfcntl, 0x07);
205 out_be16(&fifo->tfalarm, 0x80);
207 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
208 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
211 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
213 return in_be16(&PSC(port)->mpc52xx_psc_status)
214 & MPC52xx_PSC_SR_RXRDY;
217 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
219 return in_be16(&PSC(port)->mpc52xx_psc_status)
220 & MPC52xx_PSC_SR_TXRDY;
224 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
226 return in_be16(&PSC(port)->mpc52xx_psc_isr)
227 & port->read_status_mask
228 & MPC52xx_PSC_IMR_RXRDY;
231 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
233 return in_be16(&PSC(port)->mpc52xx_psc_isr)
234 & port->read_status_mask
235 & MPC52xx_PSC_IMR_TXRDY;
238 static int mpc52xx_psc_tx_empty(struct uart_port *port)
240 return in_be16(&PSC(port)->mpc52xx_psc_status)
241 & MPC52xx_PSC_SR_TXEMP;
244 static void mpc52xx_psc_start_tx(struct uart_port *port)
246 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
247 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
250 static void mpc52xx_psc_stop_tx(struct uart_port *port)
252 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
253 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
256 static void mpc52xx_psc_stop_rx(struct uart_port *port)
258 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
259 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
262 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
266 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
270 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
272 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
275 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
277 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
280 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
282 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
285 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
287 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
290 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
291 struct ktermios *new,
292 struct ktermios *old)
295 unsigned int divisor;
297 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
298 baud = uart_get_baud_rate(port, new, old,
299 port->uartclk / (32 * 0xffff) + 1,
301 divisor = (port->uartclk + 16 * baud) / (32 * baud);
303 /* enable the /32 prescaler and set the divisor */
304 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
308 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
309 struct ktermios *new,
310 struct ktermios *old)
313 unsigned int divisor;
316 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
318 baud = uart_get_baud_rate(port, new, old,
319 port->uartclk / (32 * 0xffff) + 1,
321 divisor = (port->uartclk + 2 * baud) / (4 * baud);
323 /* select the proper prescaler and set the divisor
324 * prefer high prescaler for more tolerance on low baudrates */
325 if (divisor > 0xffff || baud <= 115200) {
326 divisor = (divisor + 4) / 8;
327 prescaler = 0xdd00; /* /32 */
329 prescaler = 0xff00; /* /4 */
330 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
334 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
337 port->irq = irq_of_parse_and_map(np, 0);
340 /* 52xx specific interrupt handler. The caller holds the port lock */
341 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
343 return mpc5xxx_uart_process_int(port);
346 static struct psc_ops mpc52xx_psc_ops = {
347 .fifo_init = mpc52xx_psc_fifo_init,
348 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
349 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
350 .rx_rdy = mpc52xx_psc_rx_rdy,
351 .tx_rdy = mpc52xx_psc_tx_rdy,
352 .tx_empty = mpc52xx_psc_tx_empty,
353 .stop_rx = mpc52xx_psc_stop_rx,
354 .start_tx = mpc52xx_psc_start_tx,
355 .stop_tx = mpc52xx_psc_stop_tx,
356 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
357 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
358 .write_char = mpc52xx_psc_write_char,
359 .read_char = mpc52xx_psc_read_char,
360 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
361 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
362 .set_baudrate = mpc5200_psc_set_baudrate,
363 .get_irq = mpc52xx_psc_get_irq,
364 .handle_irq = mpc52xx_psc_handle_irq,
365 .get_status = mpc52xx_psc_get_status,
366 .get_ipcr = mpc52xx_psc_get_ipcr,
367 .command = mpc52xx_psc_command,
368 .set_mode = mpc52xx_psc_set_mode,
369 .set_rts = mpc52xx_psc_set_rts,
370 .enable_ms = mpc52xx_psc_enable_ms,
371 .set_sicr = mpc52xx_psc_set_sicr,
372 .set_imr = mpc52xx_psc_set_imr,
373 .get_mr1 = mpc52xx_psc_get_mr1,
376 static struct psc_ops mpc5200b_psc_ops = {
377 .fifo_init = mpc52xx_psc_fifo_init,
378 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
379 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
380 .rx_rdy = mpc52xx_psc_rx_rdy,
381 .tx_rdy = mpc52xx_psc_tx_rdy,
382 .tx_empty = mpc52xx_psc_tx_empty,
383 .stop_rx = mpc52xx_psc_stop_rx,
384 .start_tx = mpc52xx_psc_start_tx,
385 .stop_tx = mpc52xx_psc_stop_tx,
386 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
387 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
388 .write_char = mpc52xx_psc_write_char,
389 .read_char = mpc52xx_psc_read_char,
390 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
391 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
392 .set_baudrate = mpc5200b_psc_set_baudrate,
393 .get_irq = mpc52xx_psc_get_irq,
394 .handle_irq = mpc52xx_psc_handle_irq,
395 .get_status = mpc52xx_psc_get_status,
396 .get_ipcr = mpc52xx_psc_get_ipcr,
397 .command = mpc52xx_psc_command,
398 .set_mode = mpc52xx_psc_set_mode,
399 .set_rts = mpc52xx_psc_set_rts,
400 .enable_ms = mpc52xx_psc_enable_ms,
401 .set_sicr = mpc52xx_psc_set_sicr,
402 .set_imr = mpc52xx_psc_set_imr,
403 .get_mr1 = mpc52xx_psc_get_mr1,
406 #endif /* CONFIG_MPC52xx */
408 #ifdef CONFIG_PPC_MPC512x
409 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
411 /* PSC FIFO Controller for mpc512x */
420 static struct psc_fifoc __iomem *psc_fifoc;
421 static unsigned int psc_fifoc_irq;
423 static void mpc512x_psc_fifo_init(struct uart_port *port)
426 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
428 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
429 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
430 out_be32(&FIFO_512x(port)->txalarm, 1);
431 out_be32(&FIFO_512x(port)->tximr, 0);
433 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
434 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
435 out_be32(&FIFO_512x(port)->rxalarm, 1);
436 out_be32(&FIFO_512x(port)->rximr, 0);
438 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
439 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
442 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
444 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
447 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
449 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
452 static int mpc512x_psc_rx_rdy(struct uart_port *port)
454 return in_be32(&FIFO_512x(port)->rxsr)
455 & in_be32(&FIFO_512x(port)->rximr)
456 & MPC512x_PSC_FIFO_ALARM;
459 static int mpc512x_psc_tx_rdy(struct uart_port *port)
461 return in_be32(&FIFO_512x(port)->txsr)
462 & in_be32(&FIFO_512x(port)->tximr)
463 & MPC512x_PSC_FIFO_ALARM;
466 static int mpc512x_psc_tx_empty(struct uart_port *port)
468 return in_be32(&FIFO_512x(port)->txsr)
469 & MPC512x_PSC_FIFO_EMPTY;
472 static void mpc512x_psc_stop_rx(struct uart_port *port)
474 unsigned long rx_fifo_imr;
476 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
477 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
478 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
481 static void mpc512x_psc_start_tx(struct uart_port *port)
483 unsigned long tx_fifo_imr;
485 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
486 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
487 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
490 static void mpc512x_psc_stop_tx(struct uart_port *port)
492 unsigned long tx_fifo_imr;
494 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
495 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
496 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
499 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
501 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
504 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
506 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
509 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
511 out_8(&FIFO_512x(port)->txdata_8, c);
514 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
516 return in_8(&FIFO_512x(port)->rxdata_8);
519 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
521 port->read_status_mask =
522 in_be32(&FIFO_512x(port)->tximr) << 16 |
523 in_be32(&FIFO_512x(port)->rximr);
524 out_be32(&FIFO_512x(port)->tximr, 0);
525 out_be32(&FIFO_512x(port)->rximr, 0);
528 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
530 out_be32(&FIFO_512x(port)->tximr,
531 (port->read_status_mask >> 16) & 0x7f);
532 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
535 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
536 struct ktermios *new,
537 struct ktermios *old)
540 unsigned int divisor;
543 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
544 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
545 * Furthermore, it states that "After reset, the prescaler by 10
546 * for the UART mode is selected", but the reset register value is
547 * 0x0000 which means a /32 prescaler. This is wrong.
549 * In reality using /32 prescaler doesn't work, as it is not supported!
550 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
551 * Chapter 4.1 PSC in UART Mode.
552 * Calculate with a /16 prescaler here.
555 /* uartclk contains the ips freq */
556 baud = uart_get_baud_rate(port, new, old,
557 port->uartclk / (16 * 0xffff) + 1,
559 divisor = (port->uartclk + 8 * baud) / (16 * baud);
561 /* enable the /16 prescaler and set the divisor */
562 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
566 /* Init PSC FIFO Controller */
567 static int __init mpc512x_psc_fifoc_init(void)
569 struct device_node *np;
571 np = of_find_compatible_node(NULL, NULL,
572 "fsl,mpc5121-psc-fifo");
574 pr_err("%s: Can't find FIFOC node\n", __func__);
578 psc_fifoc = of_iomap(np, 0);
580 pr_err("%s: Can't map FIFOC\n", __func__);
585 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
587 if (psc_fifoc_irq == 0) {
588 pr_err("%s: Can't get FIFOC irq\n", __func__);
596 static void __exit mpc512x_psc_fifoc_uninit(void)
601 /* 512x specific interrupt handler. The caller holds the port lock */
602 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
604 unsigned long fifoc_int;
607 /* Read pending PSC FIFOC interrupts */
608 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
610 /* Check if it is an interrupt for this port */
611 psc_num = (port->mapbase & 0xf00) >> 8;
612 if (test_bit(psc_num, &fifoc_int) ||
613 test_bit(psc_num + 16, &fifoc_int))
614 return mpc5xxx_uart_process_int(port);
619 static int mpc512x_psc_clock(struct uart_port *port, int enable)
625 if (uart_console(port))
628 psc_num = (port->mapbase & 0xf00) >> 8;
629 snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
630 psc_clk = clk_get(port->dev, clk_name);
631 if (IS_ERR(psc_clk)) {
632 dev_err(port->dev, "Failed to get PSC clock entry!\n");
636 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
641 clk_disable(psc_clk);
646 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
648 port->irqflags = IRQF_SHARED;
649 port->irq = psc_fifoc_irq;
653 #ifdef CONFIG_PPC_MPC512x
655 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
656 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
658 static void mpc5125_psc_fifo_init(struct uart_port *port)
661 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
663 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
664 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
665 out_be32(&FIFO_5125(port)->txalarm, 1);
666 out_be32(&FIFO_5125(port)->tximr, 0);
668 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
669 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
670 out_be32(&FIFO_5125(port)->rxalarm, 1);
671 out_be32(&FIFO_5125(port)->rximr, 0);
673 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
674 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
677 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
679 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
682 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
684 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
687 static int mpc5125_psc_rx_rdy(struct uart_port *port)
689 return in_be32(&FIFO_5125(port)->rxsr) &
690 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
693 static int mpc5125_psc_tx_rdy(struct uart_port *port)
695 return in_be32(&FIFO_5125(port)->txsr) &
696 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
699 static int mpc5125_psc_tx_empty(struct uart_port *port)
701 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
704 static void mpc5125_psc_stop_rx(struct uart_port *port)
706 unsigned long rx_fifo_imr;
708 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
709 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
710 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
713 static void mpc5125_psc_start_tx(struct uart_port *port)
715 unsigned long tx_fifo_imr;
717 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
718 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
719 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
722 static void mpc5125_psc_stop_tx(struct uart_port *port)
724 unsigned long tx_fifo_imr;
726 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
727 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
728 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
731 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
733 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
736 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
738 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
741 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
743 out_8(&FIFO_5125(port)->txdata_8, c);
746 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
748 return in_8(&FIFO_5125(port)->rxdata_8);
751 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
753 port->read_status_mask =
754 in_be32(&FIFO_5125(port)->tximr) << 16 |
755 in_be32(&FIFO_5125(port)->rximr);
756 out_be32(&FIFO_5125(port)->tximr, 0);
757 out_be32(&FIFO_5125(port)->rximr, 0);
760 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
762 out_be32(&FIFO_5125(port)->tximr,
763 (port->read_status_mask >> 16) & 0x7f);
764 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
767 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
768 u8 prescaler, unsigned int divisor)
770 /* select prescaler */
771 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
772 out_8(&psc->ctur, divisor >> 8);
773 out_8(&psc->ctlr, divisor & 0xff);
776 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
777 struct ktermios *new,
778 struct ktermios *old)
781 unsigned int divisor;
784 * Calculate with a /16 prescaler here.
787 /* uartclk contains the ips freq */
788 baud = uart_get_baud_rate(port, new, old,
789 port->uartclk / (16 * 0xffff) + 1,
791 divisor = (port->uartclk + 8 * baud) / (16 * baud);
793 /* enable the /16 prescaler and set the divisor */
794 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
799 * MPC5125 have compatible PSC FIFO Controller.
800 * Special init not needed.
802 static u16 mpc5125_psc_get_status(struct uart_port *port)
804 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
807 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
809 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
812 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
814 out_8(&PSC_5125(port)->command, cmd);
817 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
819 out_8(&PSC_5125(port)->mr1, mr1);
820 out_8(&PSC_5125(port)->mr2, mr2);
823 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
825 if (state & TIOCM_RTS)
826 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
828 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
831 static void mpc5125_psc_enable_ms(struct uart_port *port)
833 struct mpc5125_psc __iomem *psc = PSC_5125(port);
835 /* clear D_*-bits by reading them */
836 in_8(&psc->mpc52xx_psc_ipcr);
837 /* enable CTS and DCD as IPC interrupts */
838 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
840 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
841 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
844 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
846 out_be32(&PSC_5125(port)->sicr, val);
849 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
851 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
854 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
856 return in_8(&PSC_5125(port)->mr1);
859 static struct psc_ops mpc5125_psc_ops = {
860 .fifo_init = mpc5125_psc_fifo_init,
861 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
862 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
863 .rx_rdy = mpc5125_psc_rx_rdy,
864 .tx_rdy = mpc5125_psc_tx_rdy,
865 .tx_empty = mpc5125_psc_tx_empty,
866 .stop_rx = mpc5125_psc_stop_rx,
867 .start_tx = mpc5125_psc_start_tx,
868 .stop_tx = mpc5125_psc_stop_tx,
869 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
870 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
871 .write_char = mpc5125_psc_write_char,
872 .read_char = mpc5125_psc_read_char,
873 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
874 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
875 .set_baudrate = mpc5125_psc_set_baudrate,
876 .clock = mpc512x_psc_clock,
877 .fifoc_init = mpc512x_psc_fifoc_init,
878 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
879 .get_irq = mpc512x_psc_get_irq,
880 .handle_irq = mpc512x_psc_handle_irq,
881 .get_status = mpc5125_psc_get_status,
882 .get_ipcr = mpc5125_psc_get_ipcr,
883 .command = mpc5125_psc_command,
884 .set_mode = mpc5125_psc_set_mode,
885 .set_rts = mpc5125_psc_set_rts,
886 .enable_ms = mpc5125_psc_enable_ms,
887 .set_sicr = mpc5125_psc_set_sicr,
888 .set_imr = mpc5125_psc_set_imr,
889 .get_mr1 = mpc5125_psc_get_mr1,
892 static struct psc_ops mpc512x_psc_ops = {
893 .fifo_init = mpc512x_psc_fifo_init,
894 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
895 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
896 .rx_rdy = mpc512x_psc_rx_rdy,
897 .tx_rdy = mpc512x_psc_tx_rdy,
898 .tx_empty = mpc512x_psc_tx_empty,
899 .stop_rx = mpc512x_psc_stop_rx,
900 .start_tx = mpc512x_psc_start_tx,
901 .stop_tx = mpc512x_psc_stop_tx,
902 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
903 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
904 .write_char = mpc512x_psc_write_char,
905 .read_char = mpc512x_psc_read_char,
906 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
907 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
908 .set_baudrate = mpc512x_psc_set_baudrate,
909 .clock = mpc512x_psc_clock,
910 .fifoc_init = mpc512x_psc_fifoc_init,
911 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
912 .get_irq = mpc512x_psc_get_irq,
913 .handle_irq = mpc512x_psc_handle_irq,
914 .get_status = mpc52xx_psc_get_status,
915 .get_ipcr = mpc52xx_psc_get_ipcr,
916 .command = mpc52xx_psc_command,
917 .set_mode = mpc52xx_psc_set_mode,
918 .set_rts = mpc52xx_psc_set_rts,
919 .enable_ms = mpc52xx_psc_enable_ms,
920 .set_sicr = mpc52xx_psc_set_sicr,
921 .set_imr = mpc52xx_psc_set_imr,
922 .get_mr1 = mpc52xx_psc_get_mr1,
924 #endif /* CONFIG_PPC_MPC512x */
927 static const struct psc_ops *psc_ops;
929 /* ======================================================================== */
930 /* UART operations */
931 /* ======================================================================== */
934 mpc52xx_uart_tx_empty(struct uart_port *port)
936 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
940 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
942 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
946 mpc52xx_uart_get_mctrl(struct uart_port *port)
948 unsigned int ret = TIOCM_DSR;
949 u8 status = psc_ops->get_ipcr(port);
951 if (!(status & MPC52xx_PSC_CTS))
953 if (!(status & MPC52xx_PSC_DCD))
960 mpc52xx_uart_stop_tx(struct uart_port *port)
962 /* port->lock taken by caller */
963 psc_ops->stop_tx(port);
967 mpc52xx_uart_start_tx(struct uart_port *port)
969 /* port->lock taken by caller */
970 psc_ops->start_tx(port);
974 mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
977 spin_lock_irqsave(&port->lock, flags);
981 /* Make sure tx interrupts are on */
982 /* Truly necessary ??? They should be anyway */
983 psc_ops->start_tx(port);
986 spin_unlock_irqrestore(&port->lock, flags);
990 mpc52xx_uart_stop_rx(struct uart_port *port)
992 /* port->lock taken by caller */
993 psc_ops->stop_rx(port);
997 mpc52xx_uart_enable_ms(struct uart_port *port)
999 psc_ops->enable_ms(port);
1003 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1005 unsigned long flags;
1006 spin_lock_irqsave(&port->lock, flags);
1009 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1011 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1013 spin_unlock_irqrestore(&port->lock, flags);
1017 mpc52xx_uart_startup(struct uart_port *port)
1021 if (psc_ops->clock) {
1022 ret = psc_ops->clock(port, 1);
1028 ret = request_irq(port->irq, mpc52xx_uart_int,
1029 port->irqflags, "mpc52xx_psc_uart", port);
1033 /* Reset/activate the port, clear and enable interrupts */
1034 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1035 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1037 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1039 psc_ops->fifo_init(port);
1041 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1042 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1048 mpc52xx_uart_shutdown(struct uart_port *port)
1050 /* Shut down the port. Leave TX active if on a console port */
1051 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1052 if (!uart_console(port))
1053 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1055 port->read_status_mask = 0;
1056 psc_ops->set_imr(port, port->read_status_mask);
1059 psc_ops->clock(port, 0);
1061 /* Release interrupt */
1062 free_irq(port->irq, port);
1066 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1067 struct ktermios *old)
1069 unsigned long flags;
1070 unsigned char mr1, mr2;
1074 /* Prepare what we're gonna write */
1077 switch (new->c_cflag & CSIZE) {
1078 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1080 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1082 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1085 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1088 if (new->c_cflag & PARENB) {
1089 if (new->c_cflag & CMSPAR)
1090 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1092 /* With CMSPAR, PARODD also means high parity (same as termios) */
1093 mr1 |= (new->c_cflag & PARODD) ?
1094 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1096 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1101 if (new->c_cflag & CSTOPB)
1102 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1104 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1105 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1106 MPC52xx_PSC_MODE_ONE_STOP;
1108 if (new->c_cflag & CRTSCTS) {
1109 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1110 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1114 spin_lock_irqsave(&port->lock, flags);
1116 /* Do our best to flush TX & RX, so we don't lose anything */
1117 /* But we don't wait indefinitely ! */
1118 j = 5000000; /* Maximum wait */
1119 /* FIXME Can't receive chars since set_termios might be called at early
1120 * boot for the console, all stuff is not yet ready to receive at that
1121 * time and that just makes the kernel oops */
1122 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1123 while (!mpc52xx_uart_tx_empty(port) && --j)
1127 printk(KERN_ERR "mpc52xx_uart.c: "
1128 "Unable to flush RX & TX fifos in-time in set_termios."
1129 "Some chars may have been lost.\n");
1131 /* Reset the TX & RX */
1132 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1133 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1135 /* Send new mode settings */
1136 psc_ops->set_mode(port, mr1, mr2);
1137 baud = psc_ops->set_baudrate(port, new, old);
1139 /* Update the per-port timeout */
1140 uart_update_timeout(port, new->c_cflag, baud);
1142 if (UART_ENABLE_MS(port, new->c_cflag))
1143 mpc52xx_uart_enable_ms(port);
1145 /* Reenable TX & RX */
1146 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1147 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1149 /* We're all set, release the lock */
1150 spin_unlock_irqrestore(&port->lock, flags);
1154 mpc52xx_uart_type(struct uart_port *port)
1157 * We keep using PORT_MPC52xx for historic reasons although it applies
1158 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1160 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1164 mpc52xx_uart_release_port(struct uart_port *port)
1166 /* remapped by us ? */
1167 if (port->flags & UPF_IOREMAP) {
1168 iounmap(port->membase);
1169 port->membase = NULL;
1172 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1176 mpc52xx_uart_request_port(struct uart_port *port)
1180 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1181 port->membase = ioremap(port->mapbase,
1182 sizeof(struct mpc52xx_psc));
1187 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1188 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1190 if (err && (port->flags & UPF_IOREMAP)) {
1191 iounmap(port->membase);
1192 port->membase = NULL;
1199 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1201 if ((flags & UART_CONFIG_TYPE)
1202 && (mpc52xx_uart_request_port(port) == 0))
1203 port->type = PORT_MPC52xx;
1207 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1209 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1212 if ((ser->irq != port->irq) ||
1213 (ser->io_type != UPIO_MEM) ||
1214 (ser->baud_base != port->uartclk) ||
1215 (ser->iomem_base != (void *)port->mapbase) ||
1223 static struct uart_ops mpc52xx_uart_ops = {
1224 .tx_empty = mpc52xx_uart_tx_empty,
1225 .set_mctrl = mpc52xx_uart_set_mctrl,
1226 .get_mctrl = mpc52xx_uart_get_mctrl,
1227 .stop_tx = mpc52xx_uart_stop_tx,
1228 .start_tx = mpc52xx_uart_start_tx,
1229 .send_xchar = mpc52xx_uart_send_xchar,
1230 .stop_rx = mpc52xx_uart_stop_rx,
1231 .enable_ms = mpc52xx_uart_enable_ms,
1232 .break_ctl = mpc52xx_uart_break_ctl,
1233 .startup = mpc52xx_uart_startup,
1234 .shutdown = mpc52xx_uart_shutdown,
1235 .set_termios = mpc52xx_uart_set_termios,
1236 /* .pm = mpc52xx_uart_pm, Not supported yet */
1237 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
1238 .type = mpc52xx_uart_type,
1239 .release_port = mpc52xx_uart_release_port,
1240 .request_port = mpc52xx_uart_request_port,
1241 .config_port = mpc52xx_uart_config_port,
1242 .verify_port = mpc52xx_uart_verify_port
1246 /* ======================================================================== */
1247 /* Interrupt handling */
1248 /* ======================================================================== */
1251 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1253 struct tty_port *tport = &port->state->port;
1254 unsigned char ch, flag;
1255 unsigned short status;
1257 /* While we can read, do so ! */
1258 while (psc_ops->raw_rx_rdy(port)) {
1260 ch = psc_ops->read_char(port);
1262 /* Handle sysreq char */
1263 #ifdef SUPPORT_SYSRQ
1264 if (uart_handle_sysrq_char(port, ch)) {
1275 status = psc_ops->get_status(port);
1277 if (status & (MPC52xx_PSC_SR_PE |
1279 MPC52xx_PSC_SR_RB)) {
1281 if (status & MPC52xx_PSC_SR_RB) {
1283 uart_handle_break(port);
1285 } else if (status & MPC52xx_PSC_SR_PE) {
1287 port->icount.parity++;
1289 else if (status & MPC52xx_PSC_SR_FE) {
1291 port->icount.frame++;
1294 /* Clear error condition */
1295 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1298 tty_insert_flip_char(tport, ch, flag);
1299 if (status & MPC52xx_PSC_SR_OE) {
1301 * Overrun is special, since it's
1302 * reported immediately, and doesn't
1303 * affect the current character
1305 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1306 port->icount.overrun++;
1310 spin_unlock(&port->lock);
1311 tty_flip_buffer_push(tport);
1312 spin_lock(&port->lock);
1314 return psc_ops->raw_rx_rdy(port);
1318 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1320 struct circ_buf *xmit = &port->state->xmit;
1322 /* Process out of band chars */
1324 psc_ops->write_char(port, port->x_char);
1330 /* Nothing to do ? */
1331 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1332 mpc52xx_uart_stop_tx(port);
1337 while (psc_ops->raw_tx_rdy(port)) {
1338 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1341 if (uart_circ_empty(xmit))
1346 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1347 uart_write_wakeup(port);
1349 /* Maybe we're done after all */
1350 if (uart_circ_empty(xmit)) {
1351 mpc52xx_uart_stop_tx(port);
1359 mpc5xxx_uart_process_int(struct uart_port *port)
1361 unsigned long pass = ISR_PASS_LIMIT;
1362 unsigned int keepgoing;
1365 /* While we have stuff to do, we continue */
1367 /* If we don't find anything to do, we stop */
1370 psc_ops->rx_clr_irq(port);
1371 if (psc_ops->rx_rdy(port))
1372 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1374 psc_ops->tx_clr_irq(port);
1375 if (psc_ops->tx_rdy(port))
1376 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1378 status = psc_ops->get_ipcr(port);
1379 if (status & MPC52xx_PSC_D_DCD)
1380 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1382 if (status & MPC52xx_PSC_D_CTS)
1383 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1385 /* Limit number of iteration */
1389 } while (keepgoing);
1395 mpc52xx_uart_int(int irq, void *dev_id)
1397 struct uart_port *port = dev_id;
1400 spin_lock(&port->lock);
1402 ret = psc_ops->handle_irq(port);
1404 spin_unlock(&port->lock);
1409 /* ======================================================================== */
1410 /* Console ( if applicable ) */
1411 /* ======================================================================== */
1413 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1416 mpc52xx_console_get_options(struct uart_port *port,
1417 int *baud, int *parity, int *bits, int *flow)
1421 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1423 /* Read the mode registers */
1424 mr1 = psc_ops->get_mr1(port);
1426 /* CT{U,L}R are write-only ! */
1427 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1430 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1431 case MPC52xx_PSC_MODE_5_BITS:
1434 case MPC52xx_PSC_MODE_6_BITS:
1437 case MPC52xx_PSC_MODE_7_BITS:
1440 case MPC52xx_PSC_MODE_8_BITS:
1445 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1448 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1452 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1454 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1457 /* Disable interrupts */
1458 psc_ops->cw_disable_ints(port);
1460 /* Wait the TX buffer to be empty */
1461 j = 5000000; /* Maximum wait */
1462 while (!mpc52xx_uart_tx_empty(port) && --j)
1465 /* Write all the chars */
1466 for (i = 0; i < count; i++, s++) {
1467 /* Line return handling */
1469 psc_ops->write_char(port, '\r');
1472 psc_ops->write_char(port, *s);
1474 /* Wait the TX buffer to be empty */
1475 j = 20000; /* Maximum wait */
1476 while (!mpc52xx_uart_tx_empty(port) && --j)
1480 /* Restore interrupt state */
1481 psc_ops->cw_restore_ints(port);
1486 mpc52xx_console_setup(struct console *co, char *options)
1488 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1489 struct device_node *np = mpc52xx_uart_nodes[co->index];
1490 unsigned int uartclk;
1491 struct resource res;
1494 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1499 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1500 co, co->index, options);
1502 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1503 pr_debug("PSC%x out of range\n", co->index);
1508 pr_debug("PSC%x not found in device tree\n", co->index);
1512 pr_debug("Console on ttyPSC%x is %s\n",
1513 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1515 /* Fetch register locations */
1516 ret = of_address_to_resource(np, 0, &res);
1518 pr_debug("Could not get resources for PSC%x\n", co->index);
1522 uartclk = mpc5xxx_get_bus_frequency(np);
1524 pr_debug("Could not find uart clock frequency!\n");
1528 /* Basic port init. Needed since we use some uart_??? func before
1529 * real init for early access */
1530 spin_lock_init(&port->lock);
1531 port->uartclk = uartclk;
1532 port->ops = &mpc52xx_uart_ops;
1533 port->mapbase = res.start;
1534 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1535 port->irq = irq_of_parse_and_map(np, 0);
1537 if (port->membase == NULL)
1540 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1541 (void *)port->mapbase, port->membase,
1542 port->irq, port->uartclk);
1544 /* Setup the port parameters accoding to options */
1546 uart_parse_options(options, &baud, &parity, &bits, &flow);
1548 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1550 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1551 baud, bits, parity, flow);
1553 return uart_set_options(port, co, baud, parity, bits, flow);
1557 static struct uart_driver mpc52xx_uart_driver;
1559 static struct console mpc52xx_console = {
1561 .write = mpc52xx_console_write,
1562 .device = uart_console_device,
1563 .setup = mpc52xx_console_setup,
1564 .flags = CON_PRINTBUFFER,
1565 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1566 .data = &mpc52xx_uart_driver,
1571 mpc52xx_console_init(void)
1573 mpc52xx_uart_of_enumerate();
1574 register_console(&mpc52xx_console);
1578 console_initcall(mpc52xx_console_init);
1580 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1582 #define MPC52xx_PSC_CONSOLE NULL
1586 /* ======================================================================== */
1588 /* ======================================================================== */
1590 static struct uart_driver mpc52xx_uart_driver = {
1591 .driver_name = "mpc52xx_psc_uart",
1592 .dev_name = "ttyPSC",
1593 .major = SERIAL_PSC_MAJOR,
1594 .minor = SERIAL_PSC_MINOR,
1595 .nr = MPC52xx_PSC_MAXNUM,
1596 .cons = MPC52xx_PSC_CONSOLE,
1599 /* ======================================================================== */
1600 /* OF Platform Driver */
1601 /* ======================================================================== */
1603 static struct of_device_id mpc52xx_uart_of_match[] = {
1604 #ifdef CONFIG_PPC_MPC52xx
1605 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1606 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1607 /* binding used by old lite5200 device trees: */
1608 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1609 /* binding used by efika: */
1610 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1612 #ifdef CONFIG_PPC_MPC512x
1613 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1614 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1619 static int mpc52xx_uart_of_probe(struct platform_device *op)
1622 unsigned int uartclk;
1623 struct uart_port *port = NULL;
1624 struct resource res;
1627 /* Check validity & presence */
1628 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1629 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1631 if (idx >= MPC52xx_PSC_MAXNUM)
1633 pr_debug("Found %s assigned to ttyPSC%x\n",
1634 mpc52xx_uart_nodes[idx]->full_name, idx);
1636 /* set the uart clock to the input clock of the psc, the different
1637 * prescalers are taken into account in the set_baudrate() methods
1638 * of the respective chip */
1639 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1641 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1645 /* Init the port structure */
1646 port = &mpc52xx_uart_ports[idx];
1648 spin_lock_init(&port->lock);
1649 port->uartclk = uartclk;
1650 port->fifosize = 512;
1651 port->iotype = UPIO_MEM;
1652 port->flags = UPF_BOOT_AUTOCONF |
1653 (uart_console(port) ? 0 : UPF_IOREMAP);
1655 port->ops = &mpc52xx_uart_ops;
1656 port->dev = &op->dev;
1658 /* Search for IRQ and mapbase */
1659 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1663 port->mapbase = res.start;
1664 if (!port->mapbase) {
1665 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1669 psc_ops->get_irq(port, op->dev.of_node);
1670 if (port->irq == 0) {
1671 dev_dbg(&op->dev, "Could not get irq\n");
1675 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1676 (void *)port->mapbase, port->irq, port->uartclk);
1678 /* Add the port to the uart sub-system */
1679 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1683 platform_set_drvdata(op, (void *)port);
1688 mpc52xx_uart_of_remove(struct platform_device *op)
1690 struct uart_port *port = platform_get_drvdata(op);
1693 uart_remove_one_port(&mpc52xx_uart_driver, port);
1700 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1702 struct uart_port *port = (struct uart_port *) platform_get_drvdata(op);
1705 uart_suspend_port(&mpc52xx_uart_driver, port);
1711 mpc52xx_uart_of_resume(struct platform_device *op)
1713 struct uart_port *port = (struct uart_port *) platform_get_drvdata(op);
1716 uart_resume_port(&mpc52xx_uart_driver, port);
1723 mpc52xx_uart_of_assign(struct device_node *np)
1727 /* Find the first free PSC number */
1728 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1729 if (mpc52xx_uart_nodes[i] == NULL) {
1731 mpc52xx_uart_nodes[i] = np;
1738 mpc52xx_uart_of_enumerate(void)
1740 static int enum_done;
1741 struct device_node *np;
1742 const struct of_device_id *match;
1748 /* Assign index to each PSC in device tree */
1749 for_each_matching_node(np, mpc52xx_uart_of_match) {
1750 match = of_match_node(mpc52xx_uart_of_match, np);
1751 psc_ops = match->data;
1752 mpc52xx_uart_of_assign(np);
1757 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1758 if (mpc52xx_uart_nodes[i])
1759 pr_debug("%s assigned to ttyPSC%x\n",
1760 mpc52xx_uart_nodes[i]->full_name, i);
1764 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1766 static struct platform_driver mpc52xx_uart_of_driver = {
1767 .probe = mpc52xx_uart_of_probe,
1768 .remove = mpc52xx_uart_of_remove,
1770 .suspend = mpc52xx_uart_of_suspend,
1771 .resume = mpc52xx_uart_of_resume,
1774 .name = "mpc52xx-psc-uart",
1775 .owner = THIS_MODULE,
1776 .of_match_table = mpc52xx_uart_of_match,
1781 /* ======================================================================== */
1783 /* ======================================================================== */
1786 mpc52xx_uart_init(void)
1790 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1792 ret = uart_register_driver(&mpc52xx_uart_driver);
1794 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1799 mpc52xx_uart_of_enumerate();
1802 * Map the PSC FIFO Controller and init if on MPC512x.
1804 if (psc_ops && psc_ops->fifoc_init) {
1805 ret = psc_ops->fifoc_init();
1810 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1812 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1819 if (psc_ops && psc_ops->fifoc_uninit)
1820 psc_ops->fifoc_uninit();
1822 uart_unregister_driver(&mpc52xx_uart_driver);
1827 mpc52xx_uart_exit(void)
1829 if (psc_ops->fifoc_uninit)
1830 psc_ops->fifoc_uninit();
1832 platform_driver_unregister(&mpc52xx_uart_of_driver);
1833 uart_unregister_driver(&mpc52xx_uart_driver);
1837 module_init(mpc52xx_uart_init);
1838 module_exit(mpc52xx_uart_exit);
1840 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1841 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1842 MODULE_LICENSE("GPL");