drivers/tty/serial/jsm/jsm.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /************************************************************************
   3  * Copyright 2003 Digi International (www.digi.com)
   4  *
   5  * Copyright (C) 2004 IBM Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  14  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  15  * PURPOSE.  See the GNU General Public License for more details.
  16  *
  17  * Contact Information:
  18  * Scott H Kilau <Scott_Kilau@digi.com>
  19  * Wendy Xiong   <wendyx@us.ibm.com>
  20  *
  21  ***********************************************************************/
  22
  23 #ifndef __JSM_DRIVER_H
  24 #define __JSM_DRIVER_H
  25
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>        /* To pick up the varions Linux types */
  28 #include <linux/tty.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/device.h>
  31
  32 /*
  33  * Debugging levels can be set using debug insmod variable
  34  * They can also be compiled out completely.
  35  */
  36 enum {
  37         DBG_INIT        = 0x01,
  38         DBG_BASIC       = 0x02,
  39         DBG_CORE        = 0x04,
  40         DBG_OPEN        = 0x08,
  41         DBG_CLOSE       = 0x10,
  42         DBG_READ        = 0x20,
  43         DBG_WRITE       = 0x40,
  44         DBG_IOCTL       = 0x80,
  45         DBG_PROC        = 0x100,
  46         DBG_PARAM       = 0x200,
  47         DBG_PSCAN       = 0x400,
  48         DBG_EVENT       = 0x800,
  49         DBG_DRAIN       = 0x1000,
  50         DBG_MSIGS       = 0x2000,
  51         DBG_MGMT        = 0x4000,
  52         DBG_INTR        = 0x8000,
  53         DBG_CARR        = 0x10000,
  54 };
  55
  56 #define jsm_dbg(nlevel, pdev, fmt, ...)                         \
  57 do {                                                            \
  58         if (DBG_##nlevel & jsm_debug)                           \
  59                 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__);         \
  60 } while (0)
  61
  62 #define MAXLINES        256
  63 #define MAXPORTS        8
  64 #define MAX_STOPS_SENT  5
  65
  66 /* Board ids */
  67 #define PCI_DEVICE_ID_CLASSIC_4         0x0028
  68 #define PCI_DEVICE_ID_CLASSIC_8         0x0029
  69 #define PCI_DEVICE_ID_CLASSIC_4_422     0x00D0
  70 #define PCI_DEVICE_ID_CLASSIC_8_422     0x00D1
  71 #define PCI_DEVICE_ID_NEO_4             0x00B0
  72 #define PCI_DEVICE_ID_NEO_1_422         0x00CC
  73 #define PCI_DEVICE_ID_NEO_1_422_485     0x00CD
  74 #define PCI_DEVICE_ID_NEO_2_422_485     0x00CE
  75 #define PCIE_DEVICE_ID_NEO_8            0x00F0
  76 #define PCIE_DEVICE_ID_NEO_4            0x00F1
  77 #define PCIE_DEVICE_ID_NEO_4RJ45        0x00F2
  78 #define PCIE_DEVICE_ID_NEO_8RJ45        0x00F3
  79
  80 /* Board type definitions */
  81
  82 #define T_NEO           0000
  83 #define T_CLASSIC       0001
  84 #define T_PCIBUS        0400
  85
  86 /* Board State Definitions */
  87
  88 #define BD_RUNNING      0x0
  89 #define BD_REASON       0x7f
  90 #define BD_NOTFOUND     0x1
  91 #define BD_NOIOPORT     0x2
  92 #define BD_NOMEM        0x3
  93 #define BD_NOBIOS       0x4
  94 #define BD_NOFEP        0x5
  95 #define BD_FAILED       0x6
  96 #define BD_ALLOCATED    0x7
  97 #define BD_TRIBOOT      0x8
  98 #define BD_BADKME       0x80
  99
 100
 101 /* 4 extra for alignment play space */
 102 #define WRITEBUFLEN     ((4096) + 4)
 103
 104 #define JSM_VERSION     "jsm: 1.2-1-INKERNEL"
 105 #define JSM_PARTNUM     "40002438_A-INKERNEL"
 106
 107 struct jsm_board;
 108 struct jsm_channel;
 109
 110 /************************************************************************
 111  * Per board operations structure                                       *
 112  ************************************************************************/
 113 struct board_ops {
 114         irq_handler_t intr;
 115         void (*uart_init)(struct jsm_channel *ch);
 116         void (*uart_off)(struct jsm_channel *ch);
 117         void (*param)(struct jsm_channel *ch);
 118         void (*assert_modem_signals)(struct jsm_channel *ch);
 119         void (*flush_uart_write)(struct jsm_channel *ch);
 120         void (*flush_uart_read)(struct jsm_channel *ch);
 121         void (*disable_receiver)(struct jsm_channel *ch);
 122         void (*enable_receiver)(struct jsm_channel *ch);
 123         void (*send_break)(struct jsm_channel *ch);
 124         void (*clear_break)(struct jsm_channel *ch);
 125         void (*send_start_character)(struct jsm_channel *ch);
 126         void (*send_stop_character)(struct jsm_channel *ch);
 127         void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
 128         u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
 129         void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
 130 };
 131
 132
 133 /*
 134  *      Per-board information
 135  */
 136 struct jsm_board
 137 {
 138         int             boardnum;       /* Board number: 0-32 */
 139
 140         int             type;           /* Type of board */
 141         u8              rev;            /* PCI revision ID */
 142         struct pci_dev  *pci_dev;
 143         u32             maxports;       /* MAX ports this board can handle */
 144
 145         spinlock_t      bd_intr_lock;   /* Used to protect the poller tasklet and
 146                                          * the interrupt routine from each other.
 147                                          */
 148
 149         u32             nasync;         /* Number of ports on card */
 150
 151         u32             irq;            /* Interrupt request number */
 152
 153         u64             membase;        /* Start of base memory of the card */
 154         u64             membase_end;    /* End of base memory of the card */
 155
 156         u8      __iomem *re_map_membase;/* Remapped memory of the card */
 157
 158         u64             iobase;         /* Start of io base of the card */
 159         u64             iobase_end;     /* End of io base of the card */
 160
 161         u32             bd_uart_offset; /* Space between each UART */
 162
 163         struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
 164
 165         u32             bd_dividend;    /* Board/UARTs specific dividend */
 166
 167         struct board_ops *bd_ops;
 168
 169         struct list_head jsm_board_entry;
 170 };
 171
 172 /************************************************************************
 173  * Device flag definitions for ch_flags.
 174  ************************************************************************/
 175 #define CH_PRON         0x0001          /* Printer on string            */
 176 #define CH_STOP         0x0002          /* Output is stopped            */
 177 #define CH_STOPI        0x0004          /* Input is stopped             */
 178 #define CH_CD           0x0008          /* Carrier is present           */
 179 #define CH_FCAR         0x0010          /* Carrier forced on            */
 180 #define CH_HANGUP       0x0020          /* Hangup received              */
 181
 182 #define CH_RECEIVER_OFF 0x0040          /* Receiver is off              */
 183 #define CH_OPENING      0x0080          /* Port in fragile open state   */
 184 #define CH_CLOSING      0x0100          /* Port in fragile close state  */
 185 #define CH_FIFO_ENABLED 0x0200          /* Port has FIFOs enabled       */
 186 #define CH_TX_FIFO_EMPTY 0x0400         /* TX Fifo is completely empty  */
 187 #define CH_TX_FIFO_LWM  0x0800          /* TX Fifo is below Low Water   */
 188 #define CH_BREAK_SENDING 0x1000         /* Break is being sent          */
 189 #define CH_LOOPBACK 0x2000              /* Channel is in lookback mode  */
 190 #define CH_BAUD0        0x08000         /* Used for checking B0 transitions */
 191
 192 /* Our Read/Error queue sizes */
 193 #define RQUEUEMASK      0x1FFF          /* 8 K - 1 */
 194 #define EQUEUEMASK      0x1FFF          /* 8 K - 1 */
 195 #define RQUEUESIZE      (RQUEUEMASK + 1)
 196 #define EQUEUESIZE      RQUEUESIZE
 197
 198
 199 /************************************************************************
 200  * Channel information structure.
 201  ************************************************************************/
 202 struct jsm_channel {
 203         struct uart_port uart_port;
 204         struct jsm_board        *ch_bd;         /* Board structure pointer      */
 205
 206         spinlock_t      ch_lock;        /* provide for serialization */
 207         wait_queue_head_t ch_flags_wait;
 208
 209         u32             ch_portnum;     /* Port number, 0 offset.       */
 210         u32             ch_open_count;  /* open count                   */
 211         u32             ch_flags;       /* Channel flags                */
 212
 213         u64             ch_close_delay; /* How long we should drop RTS/DTR for */
 214
 215         tcflag_t        ch_c_iflag;     /* channel iflags               */
 216         tcflag_t        ch_c_cflag;     /* channel cflags               */
 217         tcflag_t        ch_c_oflag;     /* channel oflags               */
 218         tcflag_t        ch_c_lflag;     /* channel lflags               */
 219         u8              ch_stopc;       /* Stop character               */
 220         u8              ch_startc;      /* Start character              */
 221
 222         u8              ch_mostat;      /* FEP output modem status      */
 223         u8              ch_mistat;      /* FEP input modem status       */
 224
 225         /* Pointers to the "mapped" UART structs */
 226         struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
 227         struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
 228
 229         u8              ch_cached_lsr;  /* Cached value of the LSR register */
 230
 231         u8              *ch_rqueue;     /* Our read queue buffer - malloc'ed */
 232         u16             ch_r_head;      /* Head location of the read queue */
 233         u16             ch_r_tail;      /* Tail location of the read queue */
 234
 235         u8              *ch_equeue;     /* Our error queue buffer - malloc'ed */
 236         u16             ch_e_head;      /* Head location of the error queue */
 237         u16             ch_e_tail;      /* Tail location of the error queue */
 238
 239         u64             ch_rxcount;     /* total of data received so far */
 240         u64             ch_txcount;     /* total of data transmitted so far */
 241
 242         u8              ch_r_tlevel;    /* Receive Trigger level */
 243         u8              ch_t_tlevel;    /* Transmit Trigger level */
 244
 245         u8              ch_r_watermark; /* Receive Watermark */
 246
 247
 248         u32             ch_stops_sent;  /* How many times I have sent a stop character
 249                                          * to try to stop the other guy sending.
 250                                          */
 251         u64             ch_err_parity;  /* Count of parity errors on channel */
 252         u64             ch_err_frame;   /* Count of framing errors on channel */
 253         u64             ch_err_break;   /* Count of breaks on channel */
 254         u64             ch_err_overrun; /* Count of overruns on channel */
 255
 256         u64             ch_xon_sends;   /* Count of xons transmitted */
 257         u64             ch_xoff_sends;  /* Count of xoffs transmitted */
 258 };
 259
 260 /************************************************************************
 261  * Per channel/port Classic UART structures                             *
 262  ************************************************************************
 263  *              Base Structure Entries Usage Meanings to Host           *
 264  *                                                                      *
 265  *      W = read write          R = read only                           *
 266  *                      U = Unused.                                     *
 267  ************************************************************************/
 268
 269 struct cls_uart_struct {
 270         u8 txrx;        /* WR  RHR/THR - Holding Reg */
 271         u8 ier;         /* WR  IER - Interrupt Enable Reg */
 272         u8 isr_fcr;     /* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
 273         u8 lcr;         /* WR  LCR - Line Control Reg */
 274         u8 mcr;         /* WR  MCR - Modem Control Reg */
 275         u8 lsr;         /* WR  LSR - Line Status Reg */
 276         u8 msr;         /* WR  MSR - Modem Status Reg */
 277         u8 spr;         /* WR  SPR - Scratch Pad Reg */
 278 };
 279
 280 /* Where to read the interrupt register (8bits) */
 281 #define UART_CLASSIC_POLL_ADDR_OFFSET   0x40
 282
 283 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
 284
 285 #define UART_16654_FCR_TXTRIGGER_8      0x0
 286 #define UART_16654_FCR_TXTRIGGER_16     0x10
 287 #define UART_16654_FCR_TXTRIGGER_32     0x20
 288 #define UART_16654_FCR_TXTRIGGER_56     0x30
 289
 290 #define UART_16654_FCR_RXTRIGGER_8      0x0
 291 #define UART_16654_FCR_RXTRIGGER_16     0x40
 292 #define UART_16654_FCR_RXTRIGGER_56     0x80
 293 #define UART_16654_FCR_RXTRIGGER_60     0xC0
 294
 295 #define UART_IIR_CTSRTS                 0x20    /* Received CTS/RTS change of state */
 296 #define UART_IIR_RDI_TIMEOUT            0x0C    /* Receiver data TIMEOUT */
 297
 298 /*
 299  * These are the EXTENDED definitions for the Exar 654's Interrupt
 300  * Enable Register.
 301  */
 302 #define UART_EXAR654_EFR_ECB      0x10    /* Enhanced control bit */
 303 #define UART_EXAR654_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
 304 #define UART_EXAR654_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
 305 #define UART_EXAR654_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
 306 #define UART_EXAR654_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
 307
 308 #define UART_EXAR654_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char  */
 309 #define UART_EXAR654_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
 310
 311 #define UART_EXAR654_IER_XOFF     0x20    /* Xoff Interrupt Enable */
 312 #define UART_EXAR654_IER_RTSDTR   0x40    /* Output Interrupt Enable */
 313 #define UART_EXAR654_IER_CTSDSR   0x80    /* Input Interrupt Enable */
 314
 315 /************************************************************************
 316  * Per channel/port NEO UART structure                                  *
 317  ************************************************************************
 318  *              Base Structure Entries Usage Meanings to Host           *
 319  *                                                                      *
 320  *      W = read write          R = read only                           *
 321  *                      U = Unused.                                     *
 322  ************************************************************************/
 323
 324 struct neo_uart_struct {
 325          u8 txrx;               /* WR   RHR/THR - Holding Reg */
 326          u8 ier;                /* WR   IER - Interrupt Enable Reg */
 327          u8 isr_fcr;            /* WR   ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
 328          u8 lcr;                /* WR   LCR - Line Control Reg */
 329          u8 mcr;                /* WR   MCR - Modem Control Reg */
 330          u8 lsr;                /* WR   LSR - Line Status Reg */
 331          u8 msr;                /* WR   MSR - Modem Status Reg */
 332          u8 spr;                /* WR   SPR - Scratch Pad Reg */
 333          u8 fctr;               /* WR   FCTR - Feature Control Reg */
 334          u8 efr;                /* WR   EFR - Enhanced Function Reg */
 335          u8 tfifo;              /* WR   TXCNT/TXTRG - Transmit FIFO Reg */
 336          u8 rfifo;              /* WR   RXCNT/RXTRG - Receive FIFO Reg */
 337          u8 xoffchar1;  /* WR   XOFF 1 - XOff Character 1 Reg */
 338          u8 xoffchar2;  /* WR   XOFF 2 - XOff Character 2 Reg */
 339          u8 xonchar1;   /* WR   XON 1 - Xon Character 1 Reg */
 340          u8 xonchar2;   /* WR   XON 2 - XOn Character 2 Reg */
 341
 342          u8 reserved1[0x2ff - 0x200]; /* U      Reserved by Exar */
 343          u8 txrxburst[64];      /* RW   64 bytes of RX/TX FIFO Data */
 344          u8 reserved2[0x37f - 0x340]; /* U      Reserved by Exar */
 345          u8 rxburst_with_errors[64];    /* R    64 bytes of RX FIFO Data + LSR */
 346 };
 347
 348 /* Where to read the extended interrupt register (32bits instead of 8bits) */
 349 #define UART_17158_POLL_ADDR_OFFSET     0x80
 350
 351 /*
 352  * These are the redefinitions for the FCTR on the XR17C158, since
 353  * Exar made them different than their earlier design. (XR16C854)
 354  */
 355
 356 /* These are only applicable when table D is selected */
 357 #define UART_17158_FCTR_RTS_NODELAY     0x00
 358 #define UART_17158_FCTR_RTS_4DELAY      0x01
 359 #define UART_17158_FCTR_RTS_6DELAY      0x02
 360 #define UART_17158_FCTR_RTS_8DELAY      0x03
 361 #define UART_17158_FCTR_RTS_12DELAY     0x12
 362 #define UART_17158_FCTR_RTS_16DELAY     0x05
 363 #define UART_17158_FCTR_RTS_20DELAY     0x13
 364 #define UART_17158_FCTR_RTS_24DELAY     0x06
 365 #define UART_17158_FCTR_RTS_28DELAY     0x14
 366 #define UART_17158_FCTR_RTS_32DELAY     0x07
 367 #define UART_17158_FCTR_RTS_36DELAY     0x16
 368 #define UART_17158_FCTR_RTS_40DELAY     0x08
 369 #define UART_17158_FCTR_RTS_44DELAY     0x09
 370 #define UART_17158_FCTR_RTS_48DELAY     0x10
 371 #define UART_17158_FCTR_RTS_52DELAY     0x11
 372
 373 #define UART_17158_FCTR_RTS_IRDA        0x10
 374 #define UART_17158_FCTR_RS485           0x20
 375 #define UART_17158_FCTR_TRGA            0x00
 376 #define UART_17158_FCTR_TRGB            0x40
 377 #define UART_17158_FCTR_TRGC            0x80
 378 #define UART_17158_FCTR_TRGD            0xC0
 379
 380 /* 17158 trigger table selects.. */
 381 #define UART_17158_FCTR_BIT6            0x40
 382 #define UART_17158_FCTR_BIT7            0x80
 383
 384 /* 17158 TX/RX memmapped buffer offsets */
 385 #define UART_17158_RX_FIFOSIZE          64
 386 #define UART_17158_TX_FIFOSIZE          64
 387
 388 /* 17158 Extended IIR's */
 389 #define UART_17158_IIR_RDI_TIMEOUT      0x0C    /* Receiver data TIMEOUT */
 390 #define UART_17158_IIR_XONXOFF          0x10    /* Received an XON/XOFF char */
 391 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
 392 #define UART_17158_IIR_FIFO_ENABLED     0xC0    /* 16550 FIFOs are Enabled */
 393
 394 /*
 395  * These are the extended interrupts that get sent
 396  * back to us from the UART's 32bit interrupt register
 397  */
 398 #define UART_17158_RX_LINE_STATUS       0x1     /* RX Ready */
 399 #define UART_17158_RXRDY_TIMEOUT        0x2     /* RX Ready Timeout */
 400 #define UART_17158_TXRDY                0x3     /* TX Ready */
 401 #define UART_17158_MSR                  0x4     /* Modem State Change */
 402 #define UART_17158_TX_AND_FIFO_CLR      0x40    /* Transmitter Holding Reg Empty */
 403 #define UART_17158_RX_FIFO_DATA_ERROR   0x80    /* UART detected an RX FIFO Data error */
 404
 405 /*
 406  * These are the EXTENDED definitions for the 17C158's Interrupt
 407  * Enable Register.
 408  */
 409 #define UART_17158_EFR_ECB      0x10    /* Enhanced control bit */
 410 #define UART_17158_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
 411 #define UART_17158_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
 412 #define UART_17158_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
 413 #define UART_17158_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
 414
 415 #define UART_17158_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char */
 416 #define UART_17158_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
 417
 418 #define UART_17158_IER_RSVD1    0x10    /* Reserved by Exar */
 419 #define UART_17158_IER_XOFF     0x20    /* Xoff Interrupt Enable */
 420 #define UART_17158_IER_RTSDTR   0x40    /* Output Interrupt Enable */
 421 #define UART_17158_IER_CTSDSR   0x80    /* Input Interrupt Enable */
 422
 423 #define PCI_DEVICE_NEO_2DB9_PCI_NAME            "Neo 2 - DB9 Universal PCI"
 424 #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME         "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
 425 #define PCI_DEVICE_NEO_2RJ45_PCI_NAME           "Neo 2 - RJ45 Universal PCI"
 426 #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME        "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
 427 #define PCIE_DEVICE_NEO_IBM_PCI_NAME            "Neo 4 - PCI Express - IBM"
 428
 429 /*
 430  * Our Global Variables.
 431  */
 432 extern struct   uart_driver jsm_uart_driver;
 433 extern struct   board_ops jsm_neo_ops;
 434 extern struct   board_ops jsm_cls_ops;
 435 extern int      jsm_debug;
 436
 437 /*************************************************************************
 438  *
 439  * Prototypes for non-static functions used in more than one module
 440  *
 441  *************************************************************************/
 442 int jsm_tty_init(struct jsm_board *);
 443 int jsm_uart_port_init(struct jsm_board *);
 444 int jsm_remove_uart_port(struct jsm_board *);
 445 void jsm_input(struct jsm_channel *ch);
 446 void jsm_check_queue_flow_control(struct jsm_channel *ch);
 447
 448 #endif