2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
53 #include <asm/ioctls.h>
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
59 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
63 #include <linux/serial_core.h>
65 #include "serial_mctrl_gpio.h"
67 static void atmel_start_rx(struct uart_port *port);
68 static void atmel_stop_rx(struct uart_port *port);
70 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
72 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
73 * should coexist with the 8250 driver, such as if we have an external 16C550
75 #define SERIAL_ATMEL_MAJOR 204
76 #define MINOR_START 154
77 #define ATMEL_DEVICENAME "ttyAT"
81 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
82 * name, but it is legally reserved for the 8250 driver. */
83 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
84 #define MINOR_START 64
85 #define ATMEL_DEVICENAME "ttyS"
89 #define ATMEL_ISR_PASS_LIMIT 256
91 /* UART registers. CR is write-only, hence no GET macro */
92 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
93 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
94 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
95 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
96 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
97 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
98 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
99 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
100 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
101 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
102 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
103 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
104 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR)
105 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME)
106 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION)
109 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
110 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
112 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
113 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
114 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
115 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
116 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
118 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
119 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
120 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
122 struct atmel_dma_buffer {
125 unsigned int dma_size;
129 struct atmel_uart_char {
134 #define ATMEL_SERIAL_RINGSIZE 1024
137 * We wrap our port structure around the generic uart_port.
139 struct atmel_uart_port {
140 struct uart_port uart; /* uart */
141 struct clk *clk; /* uart clock */
142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
143 u32 backup_imr; /* IMR saved during suspend */
144 int break_active; /* break being received */
146 bool use_dma_rx; /* enable DMA receiver */
147 bool use_pdc_rx; /* enable PDC receiver */
148 short pdc_rx_idx; /* current PDC RX buffer */
149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
151 bool use_dma_tx; /* enable DMA transmitter */
152 bool use_pdc_tx; /* enable PDC transmitter */
153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
155 spinlock_t lock_tx; /* port lock */
156 spinlock_t lock_rx; /* port lock */
157 struct dma_chan *chan_tx;
158 struct dma_chan *chan_rx;
159 struct dma_async_tx_descriptor *desc_tx;
160 struct dma_async_tx_descriptor *desc_rx;
161 dma_cookie_t cookie_tx;
162 dma_cookie_t cookie_rx;
163 struct scatterlist sg_tx;
164 struct scatterlist sg_rx;
165 struct tasklet_struct tasklet;
166 unsigned int irq_status;
167 unsigned int irq_status_prev;
169 struct circ_buf rx_ring;
171 struct mctrl_gpios *gpios;
172 int gpio_irq[UART_GPIO_MAX];
173 unsigned int tx_done_mask;
175 bool is_usart; /* usart or uart */
176 struct timer_list uart_timer; /* uart timer */
179 unsigned int pending;
180 unsigned int pending_status;
181 spinlock_t lock_suspended;
183 int (*prepare_rx)(struct uart_port *port);
184 int (*prepare_tx)(struct uart_port *port);
185 void (*schedule_rx)(struct uart_port *port);
186 void (*schedule_tx)(struct uart_port *port);
187 void (*release_rx)(struct uart_port *port);
188 void (*release_tx)(struct uart_port *port);
191 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
192 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
195 static struct console atmel_console;
198 #if defined(CONFIG_OF)
199 static const struct of_device_id atmel_serial_dt_ids[] = {
200 { .compatible = "atmel,at91rm9200-usart" },
201 { .compatible = "atmel,at91sam9260-usart" },
205 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
208 static inline struct atmel_uart_port *
209 to_atmel_uart_port(struct uart_port *uart)
211 return container_of(uart, struct atmel_uart_port, uart);
214 #ifdef CONFIG_SERIAL_ATMEL_PDC
215 static bool atmel_use_pdc_rx(struct uart_port *port)
217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
219 return atmel_port->use_pdc_rx;
222 static bool atmel_use_pdc_tx(struct uart_port *port)
224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
226 return atmel_port->use_pdc_tx;
229 static bool atmel_use_pdc_rx(struct uart_port *port)
234 static bool atmel_use_pdc_tx(struct uart_port *port)
240 static bool atmel_use_dma_tx(struct uart_port *port)
242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
244 return atmel_port->use_dma_tx;
247 static bool atmel_use_dma_rx(struct uart_port *port)
249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
251 return atmel_port->use_dma_rx;
254 static unsigned int atmel_get_lines_status(struct uart_port *port)
256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
257 unsigned int status, ret = 0;
259 status = UART_GET_CSR(port);
261 mctrl_gpio_get(atmel_port->gpios, &ret);
263 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
266 status &= ~ATMEL_US_CTS;
268 status |= ATMEL_US_CTS;
271 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
274 status &= ~ATMEL_US_DSR;
276 status |= ATMEL_US_DSR;
279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
282 status &= ~ATMEL_US_RI;
284 status |= ATMEL_US_RI;
287 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
290 status &= ~ATMEL_US_DCD;
292 status |= ATMEL_US_DCD;
298 /* Enable or disable the rs485 support */
299 static int atmel_config_rs485(struct uart_port *port,
300 struct serial_rs485 *rs485conf)
302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
305 /* Disable interrupts */
306 UART_PUT_IDR(port, atmel_port->tx_done_mask);
308 mode = UART_GET_MR(port);
310 /* Resetting serial mode to RS232 (0x0) */
311 mode &= ~ATMEL_US_USMODE;
313 port->rs485 = *rs485conf;
315 if (rs485conf->flags & SER_RS485_ENABLED) {
316 dev_dbg(port->dev, "Setting UART to RS485\n");
317 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
318 if ((rs485conf->delay_rts_after_send) > 0)
319 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send);
320 mode |= ATMEL_US_USMODE_RS485;
322 dev_dbg(port->dev, "Setting UART to RS232\n");
323 if (atmel_use_pdc_tx(port))
324 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
327 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
329 UART_PUT_MR(port, mode);
331 /* Enable interrupts */
332 UART_PUT_IER(port, atmel_port->tx_done_mask);
338 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
340 static u_int atmel_tx_empty(struct uart_port *port)
342 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
346 * Set state of the modem control output lines
348 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
350 unsigned int control = 0;
351 unsigned int mode = UART_GET_MR(port);
352 unsigned int rts_paused, rts_ready;
353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
355 /* override mode to RS485 if needed, otherwise keep the current mode */
356 if (port->rs485.flags & SER_RS485_ENABLED) {
357 if ((port->rs485.delay_rts_after_send) > 0)
358 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
359 mode &= ~ATMEL_US_USMODE;
360 mode |= ATMEL_US_USMODE_RS485;
363 /* set the RTS line state according to the mode */
364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
365 /* force RTS line to high level */
366 rts_paused = ATMEL_US_RTSEN;
368 /* give the control of the RTS line back to the hardware */
369 rts_ready = ATMEL_US_RTSDIS;
371 /* force RTS line to high level */
372 rts_paused = ATMEL_US_RTSDIS;
374 /* force RTS line to low level */
375 rts_ready = ATMEL_US_RTSEN;
378 if (mctrl & TIOCM_RTS)
379 control |= rts_ready;
381 control |= rts_paused;
383 if (mctrl & TIOCM_DTR)
384 control |= ATMEL_US_DTREN;
386 control |= ATMEL_US_DTRDIS;
388 UART_PUT_CR(port, control);
390 mctrl_gpio_set(atmel_port->gpios, mctrl);
392 /* Local loopback mode? */
393 mode &= ~ATMEL_US_CHMODE;
394 if (mctrl & TIOCM_LOOP)
395 mode |= ATMEL_US_CHMODE_LOC_LOOP;
397 mode |= ATMEL_US_CHMODE_NORMAL;
399 UART_PUT_MR(port, mode);
403 * Get state of the modem control input lines
405 static u_int atmel_get_mctrl(struct uart_port *port)
407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
408 unsigned int ret = 0, status;
410 status = UART_GET_CSR(port);
413 * The control signals are active low.
415 if (!(status & ATMEL_US_DCD))
417 if (!(status & ATMEL_US_CTS))
419 if (!(status & ATMEL_US_DSR))
421 if (!(status & ATMEL_US_RI))
424 return mctrl_gpio_get(atmel_port->gpios, &ret);
430 static void atmel_stop_tx(struct uart_port *port)
432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
434 if (atmel_use_pdc_tx(port)) {
435 /* disable PDC transmit */
436 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
438 /* Disable interrupts */
439 UART_PUT_IDR(port, atmel_port->tx_done_mask);
441 if ((port->rs485.flags & SER_RS485_ENABLED) &&
442 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
443 atmel_start_rx(port);
447 * Start transmitting.
449 static void atmel_start_tx(struct uart_port *port)
451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
453 if (atmel_use_pdc_tx(port)) {
454 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
455 /* The transmitter is already running. Yes, we
459 if ((port->rs485.flags & SER_RS485_ENABLED) &&
460 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
463 /* re-enable PDC transmit */
464 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
466 /* Enable interrupts */
467 UART_PUT_IER(port, atmel_port->tx_done_mask);
471 * start receiving - port is in process of being opened.
473 static void atmel_start_rx(struct uart_port *port)
475 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */
477 UART_PUT_CR(port, ATMEL_US_RXEN);
479 if (atmel_use_pdc_rx(port)) {
480 /* enable PDC controller */
481 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
482 port->read_status_mask);
483 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
485 UART_PUT_IER(port, ATMEL_US_RXRDY);
490 * Stop receiving - port is in process of being closed.
492 static void atmel_stop_rx(struct uart_port *port)
494 UART_PUT_CR(port, ATMEL_US_RXDIS);
496 if (atmel_use_pdc_rx(port)) {
497 /* disable PDC receive */
498 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
499 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
500 port->read_status_mask);
502 UART_PUT_IDR(port, ATMEL_US_RXRDY);
507 * Enable modem status interrupts
509 static void atmel_enable_ms(struct uart_port *port)
511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
515 * Interrupt should not be enabled twice
517 if (atmel_port->ms_irq_enabled)
520 atmel_port->ms_irq_enabled = true;
522 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
523 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
525 ier |= ATMEL_US_CTSIC;
527 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
528 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
530 ier |= ATMEL_US_DSRIC;
532 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
533 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
535 ier |= ATMEL_US_RIIC;
537 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
538 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
540 ier |= ATMEL_US_DCDIC;
542 UART_PUT_IER(port, ier);
546 * Disable modem status interrupts
548 static void atmel_disable_ms(struct uart_port *port)
550 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
554 * Interrupt should not be disabled twice
556 if (!atmel_port->ms_irq_enabled)
559 atmel_port->ms_irq_enabled = false;
561 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
562 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
564 idr |= ATMEL_US_CTSIC;
566 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
567 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
569 idr |= ATMEL_US_DSRIC;
571 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
572 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
574 idr |= ATMEL_US_RIIC;
576 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
577 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
579 idr |= ATMEL_US_DCDIC;
581 UART_PUT_IDR(port, idr);
585 * Control the transmission of a break signal
587 static void atmel_break_ctl(struct uart_port *port, int break_state)
589 if (break_state != 0)
590 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */
592 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
596 * Stores the incoming character in the ring buffer
599 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
603 struct circ_buf *ring = &atmel_port->rx_ring;
604 struct atmel_uart_char *c;
606 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
607 /* Buffer overflow, ignore char */
610 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
614 /* Make sure the character is stored before we update head. */
617 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
621 * Deal with parity, framing and overrun errors.
623 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
626 UART_PUT_CR(port, ATMEL_US_RSTSTA);
628 if (status & ATMEL_US_RXBRK) {
629 /* ignore side-effect */
630 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
633 if (status & ATMEL_US_PARE)
634 port->icount.parity++;
635 if (status & ATMEL_US_FRAME)
636 port->icount.frame++;
637 if (status & ATMEL_US_OVRE)
638 port->icount.overrun++;
642 * Characters received (called from interrupt handler)
644 static void atmel_rx_chars(struct uart_port *port)
646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
647 unsigned int status, ch;
649 status = UART_GET_CSR(port);
650 while (status & ATMEL_US_RXRDY) {
651 ch = UART_GET_CHAR(port);
654 * note that the error handling code is
655 * out of the main execution path
657 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
658 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
659 || atmel_port->break_active)) {
662 UART_PUT_CR(port, ATMEL_US_RSTSTA);
664 if (status & ATMEL_US_RXBRK
665 && !atmel_port->break_active) {
666 atmel_port->break_active = 1;
667 UART_PUT_IER(port, ATMEL_US_RXBRK);
670 * This is either the end-of-break
671 * condition or we've received at
672 * least one character without RXBRK
673 * being set. In both cases, the next
674 * RXBRK will indicate start-of-break.
676 UART_PUT_IDR(port, ATMEL_US_RXBRK);
677 status &= ~ATMEL_US_RXBRK;
678 atmel_port->break_active = 0;
682 atmel_buffer_rx_char(port, status, ch);
683 status = UART_GET_CSR(port);
686 tasklet_schedule(&atmel_port->tasklet);
690 * Transmit characters (called from tasklet with TXRDY interrupt
693 static void atmel_tx_chars(struct uart_port *port)
695 struct circ_buf *xmit = &port->state->xmit;
696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
698 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) {
699 UART_PUT_CHAR(port, port->x_char);
703 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
706 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) {
707 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
708 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
710 if (uart_circ_empty(xmit))
714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
715 uart_write_wakeup(port);
717 if (!uart_circ_empty(xmit))
718 /* Enable interrupts */
719 UART_PUT_IER(port, atmel_port->tx_done_mask);
722 static void atmel_complete_tx_dma(void *arg)
724 struct atmel_uart_port *atmel_port = arg;
725 struct uart_port *port = &atmel_port->uart;
726 struct circ_buf *xmit = &port->state->xmit;
727 struct dma_chan *chan = atmel_port->chan_tx;
730 spin_lock_irqsave(&port->lock, flags);
733 dmaengine_terminate_all(chan);
734 xmit->tail += sg_dma_len(&atmel_port->sg_tx);
735 xmit->tail &= UART_XMIT_SIZE - 1;
737 port->icount.tx += sg_dma_len(&atmel_port->sg_tx);
739 spin_lock_irq(&atmel_port->lock_tx);
740 async_tx_ack(atmel_port->desc_tx);
741 atmel_port->cookie_tx = -EINVAL;
742 atmel_port->desc_tx = NULL;
743 spin_unlock_irq(&atmel_port->lock_tx);
745 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
746 uart_write_wakeup(port);
749 * xmit is a circular buffer so, if we have just send data from
750 * xmit->tail to the end of xmit->buf, now we have to transmit the
751 * remaining data from the beginning of xmit->buf to xmit->head.
753 if (!uart_circ_empty(xmit))
754 tasklet_schedule(&atmel_port->tasklet);
756 spin_unlock_irqrestore(&port->lock, flags);
759 static void atmel_release_tx_dma(struct uart_port *port)
761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
762 struct dma_chan *chan = atmel_port->chan_tx;
765 dmaengine_terminate_all(chan);
766 dma_release_channel(chan);
767 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
771 atmel_port->desc_tx = NULL;
772 atmel_port->chan_tx = NULL;
773 atmel_port->cookie_tx = -EINVAL;
777 * Called from tasklet with TXRDY interrupt is disabled.
779 static void atmel_tx_dma(struct uart_port *port)
781 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
782 struct circ_buf *xmit = &port->state->xmit;
783 struct dma_chan *chan = atmel_port->chan_tx;
784 struct dma_async_tx_descriptor *desc;
785 struct scatterlist *sg = &atmel_port->sg_tx;
787 /* Make sure we have an idle channel */
788 if (atmel_port->desc_tx != NULL)
791 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
794 * Port xmit buffer is already mapped,
795 * and it is one page... Just adjust
796 * offsets and lengths. Since it is a circular buffer,
797 * we have to transmit till the end, and then the rest.
798 * Take the port lock to get a
799 * consistent xmit buffer state.
801 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
802 sg_dma_address(sg) = (sg_dma_address(sg) &
803 ~(UART_XMIT_SIZE - 1))
805 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head,
808 BUG_ON(!sg_dma_len(sg));
810 desc = dmaengine_prep_slave_sg(chan,
817 dev_err(port->dev, "Failed to send via dma!\n");
821 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
823 atmel_port->desc_tx = desc;
824 desc->callback = atmel_complete_tx_dma;
825 desc->callback_param = atmel_port;
826 atmel_port->cookie_tx = dmaengine_submit(desc);
829 if (port->rs485.flags & SER_RS485_ENABLED) {
830 /* DMA done, stop TX, start RX for RS485 */
831 atmel_start_rx(port);
835 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
836 uart_write_wakeup(port);
839 static int atmel_prepare_tx_dma(struct uart_port *port)
841 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
843 struct dma_slave_config config;
847 dma_cap_set(DMA_SLAVE, mask);
849 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
850 if (atmel_port->chan_tx == NULL)
852 dev_info(port->dev, "using %s for tx DMA transfers\n",
853 dma_chan_name(atmel_port->chan_tx));
855 spin_lock_init(&atmel_port->lock_tx);
856 sg_init_table(&atmel_port->sg_tx, 1);
857 /* UART circular tx buffer is an aligned page. */
858 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
859 sg_set_page(&atmel_port->sg_tx,
860 virt_to_page(port->state->xmit.buf),
862 (int)port->state->xmit.buf & ~PAGE_MASK);
863 nent = dma_map_sg(port->dev,
869 dev_dbg(port->dev, "need to release resource of dma\n");
872 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
873 sg_dma_len(&atmel_port->sg_tx),
874 port->state->xmit.buf,
875 sg_dma_address(&atmel_port->sg_tx));
878 /* Configure the slave DMA */
879 memset(&config, 0, sizeof(config));
880 config.direction = DMA_MEM_TO_DEV;
881 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
882 config.dst_addr = port->mapbase + ATMEL_US_THR;
883 config.dst_maxburst = 1;
885 ret = dmaengine_slave_config(atmel_port->chan_tx,
888 dev_err(port->dev, "DMA tx slave configuration failed\n");
895 dev_err(port->dev, "TX channel not available, switch to pio\n");
896 atmel_port->use_dma_tx = 0;
897 if (atmel_port->chan_tx)
898 atmel_release_tx_dma(port);
902 static void atmel_complete_rx_dma(void *arg)
904 struct uart_port *port = arg;
905 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
907 tasklet_schedule(&atmel_port->tasklet);
910 static void atmel_release_rx_dma(struct uart_port *port)
912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
913 struct dma_chan *chan = atmel_port->chan_rx;
916 dmaengine_terminate_all(chan);
917 dma_release_channel(chan);
918 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
922 atmel_port->desc_rx = NULL;
923 atmel_port->chan_rx = NULL;
924 atmel_port->cookie_rx = -EINVAL;
927 static void atmel_rx_from_dma(struct uart_port *port)
929 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
930 struct tty_port *tport = &port->state->port;
931 struct circ_buf *ring = &atmel_port->rx_ring;
932 struct dma_chan *chan = atmel_port->chan_rx;
933 struct dma_tx_state state;
934 enum dma_status dmastat;
938 /* Reset the UART timeout early so that we don't miss one */
939 UART_PUT_CR(port, ATMEL_US_STTTO);
940 dmastat = dmaengine_tx_status(chan,
941 atmel_port->cookie_rx,
943 /* Restart a new tasklet if DMA status is error */
944 if (dmastat == DMA_ERROR) {
945 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
946 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
947 tasklet_schedule(&atmel_port->tasklet);
951 /* CPU claims ownership of RX DMA buffer */
952 dma_sync_sg_for_cpu(port->dev,
958 * ring->head points to the end of data already written by the DMA.
959 * ring->tail points to the beginning of data to be read by the
961 * The current transfer size should not be larger than the dma buffer
964 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
965 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
967 * At this point ring->head may point to the first byte right after the
968 * last byte of the dma buffer:
969 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
971 * However ring->tail must always points inside the dma buffer:
972 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
974 * Since we use a ring buffer, we have to handle the case
975 * where head is lower than tail. In such a case, we first read from
976 * tail to the end of the buffer then reset tail.
978 if (ring->head < ring->tail) {
979 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
981 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
983 port->icount.rx += count;
986 /* Finally we read data from tail to head */
987 if (ring->tail < ring->head) {
988 count = ring->head - ring->tail;
990 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
991 /* Wrap ring->head if needed */
992 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
994 ring->tail = ring->head;
995 port->icount.rx += count;
998 /* USART retreives ownership of RX DMA buffer */
999 dma_sync_sg_for_device(port->dev,
1005 * Drop the lock here since it might end up calling
1006 * uart_start(), which takes the lock.
1008 spin_unlock(&port->lock);
1009 tty_flip_buffer_push(tport);
1010 spin_lock(&port->lock);
1012 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1015 static int atmel_prepare_rx_dma(struct uart_port *port)
1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1018 struct dma_async_tx_descriptor *desc;
1019 dma_cap_mask_t mask;
1020 struct dma_slave_config config;
1021 struct circ_buf *ring;
1024 ring = &atmel_port->rx_ring;
1027 dma_cap_set(DMA_CYCLIC, mask);
1029 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1030 if (atmel_port->chan_rx == NULL)
1032 dev_info(port->dev, "using %s for rx DMA transfers\n",
1033 dma_chan_name(atmel_port->chan_rx));
1035 spin_lock_init(&atmel_port->lock_rx);
1036 sg_init_table(&atmel_port->sg_rx, 1);
1037 /* UART circular rx buffer is an aligned page. */
1038 BUG_ON(!PAGE_ALIGNED(ring->buf));
1039 sg_set_page(&atmel_port->sg_rx,
1040 virt_to_page(ring->buf),
1041 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1042 (int)ring->buf & ~PAGE_MASK);
1043 nent = dma_map_sg(port->dev,
1049 dev_dbg(port->dev, "need to release resource of dma\n");
1052 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1053 sg_dma_len(&atmel_port->sg_rx),
1055 sg_dma_address(&atmel_port->sg_rx));
1058 /* Configure the slave DMA */
1059 memset(&config, 0, sizeof(config));
1060 config.direction = DMA_DEV_TO_MEM;
1061 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1062 config.src_addr = port->mapbase + ATMEL_US_RHR;
1063 config.src_maxburst = 1;
1065 ret = dmaengine_slave_config(atmel_port->chan_rx,
1068 dev_err(port->dev, "DMA rx slave configuration failed\n");
1072 * Prepare a cyclic dma transfer, assign 2 descriptors,
1073 * each one is half ring buffer size
1075 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1076 sg_dma_address(&atmel_port->sg_rx),
1077 sg_dma_len(&atmel_port->sg_rx),
1078 sg_dma_len(&atmel_port->sg_rx)/2,
1080 DMA_PREP_INTERRUPT);
1081 desc->callback = atmel_complete_rx_dma;
1082 desc->callback_param = port;
1083 atmel_port->desc_rx = desc;
1084 atmel_port->cookie_rx = dmaengine_submit(desc);
1089 dev_err(port->dev, "RX channel not available, switch to pio\n");
1090 atmel_port->use_dma_rx = 0;
1091 if (atmel_port->chan_rx)
1092 atmel_release_rx_dma(port);
1096 static void atmel_uart_timer_callback(unsigned long data)
1098 struct uart_port *port = (void *)data;
1099 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1101 tasklet_schedule(&atmel_port->tasklet);
1102 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1106 * receive interrupt handler.
1109 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1111 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1113 if (atmel_use_pdc_rx(port)) {
1115 * PDC receive. Just schedule the tasklet and let it
1116 * figure out the details.
1118 * TODO: We're not handling error flags correctly at
1121 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1122 UART_PUT_IDR(port, (ATMEL_US_ENDRX
1123 | ATMEL_US_TIMEOUT));
1124 tasklet_schedule(&atmel_port->tasklet);
1127 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1128 ATMEL_US_FRAME | ATMEL_US_PARE))
1129 atmel_pdc_rxerr(port, pending);
1132 if (atmel_use_dma_rx(port)) {
1133 if (pending & ATMEL_US_TIMEOUT) {
1134 UART_PUT_IDR(port, ATMEL_US_TIMEOUT);
1135 tasklet_schedule(&atmel_port->tasklet);
1139 /* Interrupt receive */
1140 if (pending & ATMEL_US_RXRDY)
1141 atmel_rx_chars(port);
1142 else if (pending & ATMEL_US_RXBRK) {
1144 * End of break detected. If it came along with a
1145 * character, atmel_rx_chars will handle it.
1147 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1148 UART_PUT_IDR(port, ATMEL_US_RXBRK);
1149 atmel_port->break_active = 0;
1154 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1157 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1159 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1161 if (pending & atmel_port->tx_done_mask) {
1162 /* Either PDC or interrupt transmission */
1163 UART_PUT_IDR(port, atmel_port->tx_done_mask);
1164 tasklet_schedule(&atmel_port->tasklet);
1169 * status flags interrupt handler.
1172 atmel_handle_status(struct uart_port *port, unsigned int pending,
1173 unsigned int status)
1175 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1177 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1178 | ATMEL_US_CTSIC)) {
1179 atmel_port->irq_status = status;
1180 tasklet_schedule(&atmel_port->tasklet);
1187 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1189 struct uart_port *port = dev_id;
1190 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1191 unsigned int status, pending, mask, pass_counter = 0;
1192 bool gpio_handled = false;
1194 spin_lock(&atmel_port->lock_suspended);
1197 status = atmel_get_lines_status(port);
1198 mask = UART_GET_IMR(port);
1199 pending = status & mask;
1200 if (!gpio_handled) {
1202 * Dealing with GPIO interrupt
1204 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1205 pending |= ATMEL_US_CTSIC;
1207 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1208 pending |= ATMEL_US_DSRIC;
1210 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1211 pending |= ATMEL_US_RIIC;
1213 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1214 pending |= ATMEL_US_DCDIC;
1216 gpio_handled = true;
1221 if (atmel_port->suspended) {
1222 atmel_port->pending |= pending;
1223 atmel_port->pending_status = status;
1224 UART_PUT_IDR(port, mask);
1229 atmel_handle_receive(port, pending);
1230 atmel_handle_status(port, pending, status);
1231 atmel_handle_transmit(port, pending);
1232 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1234 spin_unlock(&atmel_port->lock_suspended);
1236 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1239 static void atmel_release_tx_pdc(struct uart_port *port)
1241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1242 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1244 dma_unmap_single(port->dev,
1251 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1253 static void atmel_tx_pdc(struct uart_port *port)
1255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1256 struct circ_buf *xmit = &port->state->xmit;
1257 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1260 /* nothing left to transmit? */
1261 if (UART_GET_TCR(port))
1264 xmit->tail += pdc->ofs;
1265 xmit->tail &= UART_XMIT_SIZE - 1;
1267 port->icount.tx += pdc->ofs;
1270 /* more to transmit - setup next transfer */
1272 /* disable PDC transmit */
1273 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1275 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1276 dma_sync_single_for_device(port->dev,
1281 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1284 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
1285 UART_PUT_TCR(port, count);
1286 /* re-enable PDC transmit */
1287 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1288 /* Enable interrupts */
1289 UART_PUT_IER(port, atmel_port->tx_done_mask);
1291 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1292 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1293 /* DMA done, stop TX, start RX for RS485 */
1294 atmel_start_rx(port);
1298 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1299 uart_write_wakeup(port);
1302 static int atmel_prepare_tx_pdc(struct uart_port *port)
1304 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1305 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1306 struct circ_buf *xmit = &port->state->xmit;
1308 pdc->buf = xmit->buf;
1309 pdc->dma_addr = dma_map_single(port->dev,
1313 pdc->dma_size = UART_XMIT_SIZE;
1319 static void atmel_rx_from_ring(struct uart_port *port)
1321 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1322 struct circ_buf *ring = &atmel_port->rx_ring;
1324 unsigned int status;
1326 while (ring->head != ring->tail) {
1327 struct atmel_uart_char c;
1329 /* Make sure c is loaded after head. */
1332 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1334 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1341 * note that the error handling code is
1342 * out of the main execution path
1344 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1345 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1346 if (status & ATMEL_US_RXBRK) {
1347 /* ignore side-effect */
1348 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1351 if (uart_handle_break(port))
1354 if (status & ATMEL_US_PARE)
1355 port->icount.parity++;
1356 if (status & ATMEL_US_FRAME)
1357 port->icount.frame++;
1358 if (status & ATMEL_US_OVRE)
1359 port->icount.overrun++;
1361 status &= port->read_status_mask;
1363 if (status & ATMEL_US_RXBRK)
1365 else if (status & ATMEL_US_PARE)
1367 else if (status & ATMEL_US_FRAME)
1372 if (uart_handle_sysrq_char(port, c.ch))
1375 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1379 * Drop the lock here since it might end up calling
1380 * uart_start(), which takes the lock.
1382 spin_unlock(&port->lock);
1383 tty_flip_buffer_push(&port->state->port);
1384 spin_lock(&port->lock);
1387 static void atmel_release_rx_pdc(struct uart_port *port)
1389 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1392 for (i = 0; i < 2; i++) {
1393 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1395 dma_unmap_single(port->dev,
1403 static void atmel_rx_from_pdc(struct uart_port *port)
1405 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1406 struct tty_port *tport = &port->state->port;
1407 struct atmel_dma_buffer *pdc;
1408 int rx_idx = atmel_port->pdc_rx_idx;
1414 /* Reset the UART timeout early so that we don't miss one */
1415 UART_PUT_CR(port, ATMEL_US_STTTO);
1417 pdc = &atmel_port->pdc_rx[rx_idx];
1418 head = UART_GET_RPR(port) - pdc->dma_addr;
1421 /* If the PDC has switched buffers, RPR won't contain
1422 * any address within the current buffer. Since head
1423 * is unsigned, we just need a one-way comparison to
1426 * In this case, we just need to consume the entire
1427 * buffer and resubmit it for DMA. This will clear the
1428 * ENDRX bit as well, so that we can safely re-enable
1429 * all interrupts below.
1431 head = min(head, pdc->dma_size);
1433 if (likely(head != tail)) {
1434 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1435 pdc->dma_size, DMA_FROM_DEVICE);
1438 * head will only wrap around when we recycle
1439 * the DMA buffer, and when that happens, we
1440 * explicitly set tail to 0. So head will
1441 * always be greater than tail.
1443 count = head - tail;
1445 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1448 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1449 pdc->dma_size, DMA_FROM_DEVICE);
1451 port->icount.rx += count;
1456 * If the current buffer is full, we need to check if
1457 * the next one contains any additional data.
1459 if (head >= pdc->dma_size) {
1461 UART_PUT_RNPR(port, pdc->dma_addr);
1462 UART_PUT_RNCR(port, pdc->dma_size);
1465 atmel_port->pdc_rx_idx = rx_idx;
1467 } while (head >= pdc->dma_size);
1470 * Drop the lock here since it might end up calling
1471 * uart_start(), which takes the lock.
1473 spin_unlock(&port->lock);
1474 tty_flip_buffer_push(tport);
1475 spin_lock(&port->lock);
1477 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1480 static int atmel_prepare_rx_pdc(struct uart_port *port)
1482 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1485 for (i = 0; i < 2; i++) {
1486 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1488 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1489 if (pdc->buf == NULL) {
1491 dma_unmap_single(port->dev,
1492 atmel_port->pdc_rx[0].dma_addr,
1495 kfree(atmel_port->pdc_rx[0].buf);
1497 atmel_port->use_pdc_rx = 0;
1500 pdc->dma_addr = dma_map_single(port->dev,
1504 pdc->dma_size = PDC_BUFFER_SIZE;
1508 atmel_port->pdc_rx_idx = 0;
1510 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
1511 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
1513 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
1514 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
1520 * tasklet handling tty stuff outside the interrupt handler.
1522 static void atmel_tasklet_func(unsigned long data)
1524 struct uart_port *port = (struct uart_port *)data;
1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1526 unsigned int status;
1527 unsigned int status_change;
1529 /* The interrupt handler does not take the lock */
1530 spin_lock(&port->lock);
1532 atmel_port->schedule_tx(port);
1534 status = atmel_port->irq_status;
1535 status_change = status ^ atmel_port->irq_status_prev;
1537 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1538 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1539 /* TODO: All reads to CSR will clear these interrupts! */
1540 if (status_change & ATMEL_US_RI)
1542 if (status_change & ATMEL_US_DSR)
1544 if (status_change & ATMEL_US_DCD)
1545 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1546 if (status_change & ATMEL_US_CTS)
1547 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1549 wake_up_interruptible(&port->state->port.delta_msr_wait);
1551 atmel_port->irq_status_prev = status;
1554 atmel_port->schedule_rx(port);
1556 spin_unlock(&port->lock);
1559 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1560 struct platform_device *pdev)
1562 struct device_node *np = pdev->dev.of_node;
1563 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1566 /* DMA/PDC usage specification */
1567 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1568 if (of_get_property(np, "dmas", NULL)) {
1569 atmel_port->use_dma_rx = true;
1570 atmel_port->use_pdc_rx = false;
1572 atmel_port->use_dma_rx = false;
1573 atmel_port->use_pdc_rx = true;
1576 atmel_port->use_dma_rx = false;
1577 atmel_port->use_pdc_rx = false;
1580 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1581 if (of_get_property(np, "dmas", NULL)) {
1582 atmel_port->use_dma_tx = true;
1583 atmel_port->use_pdc_tx = false;
1585 atmel_port->use_dma_tx = false;
1586 atmel_port->use_pdc_tx = true;
1589 atmel_port->use_dma_tx = false;
1590 atmel_port->use_pdc_tx = false;
1594 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1595 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1596 atmel_port->use_dma_rx = false;
1597 atmel_port->use_dma_tx = false;
1602 static void atmel_init_rs485(struct uart_port *port,
1603 struct platform_device *pdev)
1605 struct device_node *np = pdev->dev.of_node;
1606 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1610 /* rs485 properties */
1611 if (of_property_read_u32_array(np, "rs485-rts-delay",
1612 rs485_delay, 2) == 0) {
1613 struct serial_rs485 *rs485conf = &port->rs485;
1615 rs485conf->delay_rts_before_send = rs485_delay[0];
1616 rs485conf->delay_rts_after_send = rs485_delay[1];
1617 rs485conf->flags = 0;
1619 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1620 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1622 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1624 rs485conf->flags |= SER_RS485_ENABLED;
1627 port->rs485 = pdata->rs485;
1632 static void atmel_set_ops(struct uart_port *port)
1634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1636 if (atmel_use_dma_rx(port)) {
1637 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1638 atmel_port->schedule_rx = &atmel_rx_from_dma;
1639 atmel_port->release_rx = &atmel_release_rx_dma;
1640 } else if (atmel_use_pdc_rx(port)) {
1641 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1642 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1643 atmel_port->release_rx = &atmel_release_rx_pdc;
1645 atmel_port->prepare_rx = NULL;
1646 atmel_port->schedule_rx = &atmel_rx_from_ring;
1647 atmel_port->release_rx = NULL;
1650 if (atmel_use_dma_tx(port)) {
1651 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1652 atmel_port->schedule_tx = &atmel_tx_dma;
1653 atmel_port->release_tx = &atmel_release_tx_dma;
1654 } else if (atmel_use_pdc_tx(port)) {
1655 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1656 atmel_port->schedule_tx = &atmel_tx_pdc;
1657 atmel_port->release_tx = &atmel_release_tx_pdc;
1659 atmel_port->prepare_tx = NULL;
1660 atmel_port->schedule_tx = &atmel_tx_chars;
1661 atmel_port->release_tx = NULL;
1666 * Get ip name usart or uart
1668 static void atmel_get_ip_name(struct uart_port *port)
1670 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1671 int name = UART_GET_IP_NAME(port);
1674 /* usart and uart ascii */
1678 atmel_port->is_usart = false;
1680 if (name == usart) {
1681 dev_dbg(port->dev, "This is usart\n");
1682 atmel_port->is_usart = true;
1683 } else if (name == uart) {
1684 dev_dbg(port->dev, "This is uart\n");
1685 atmel_port->is_usart = false;
1687 /* fallback for older SoCs: use version field */
1688 version = UART_GET_IP_VERSION(port);
1692 dev_dbg(port->dev, "This version is usart\n");
1693 atmel_port->is_usart = true;
1697 dev_dbg(port->dev, "This version is uart\n");
1698 atmel_port->is_usart = false;
1701 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1706 static void atmel_free_gpio_irq(struct uart_port *port)
1708 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1709 enum mctrl_gpio_idx i;
1711 for (i = 0; i < UART_GPIO_MAX; i++)
1712 if (atmel_port->gpio_irq[i] >= 0)
1713 free_irq(atmel_port->gpio_irq[i], port);
1716 static int atmel_request_gpio_irq(struct uart_port *port)
1718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1719 int *irq = atmel_port->gpio_irq;
1720 enum mctrl_gpio_idx i;
1723 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1727 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1728 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1729 "atmel_serial", port);
1731 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1736 * If something went wrong, rollback.
1738 while (err && (--i >= 0))
1740 free_irq(irq[i], port);
1746 * Perform initialization and enable port for reception
1748 static int atmel_startup(struct uart_port *port)
1750 struct platform_device *pdev = to_platform_device(port->dev);
1751 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1752 struct tty_struct *tty = port->state->port.tty;
1756 * Ensure that no interrupts are enabled otherwise when
1757 * request_irq() is called we could get stuck trying to
1758 * handle an unexpected interrupt
1760 UART_PUT_IDR(port, -1);
1761 atmel_port->ms_irq_enabled = false;
1766 retval = request_irq(port->irq, atmel_interrupt,
1767 IRQF_SHARED | IRQF_COND_SUSPEND,
1768 tty ? tty->name : "atmel_serial", port);
1770 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1775 * Get the GPIO lines IRQ
1777 retval = atmel_request_gpio_irq(port);
1781 tasklet_enable(&atmel_port->tasklet);
1784 * Initialize DMA (if necessary)
1786 atmel_init_property(atmel_port, pdev);
1787 atmel_set_ops(port);
1789 if (atmel_port->prepare_rx) {
1790 retval = atmel_port->prepare_rx(port);
1792 atmel_set_ops(port);
1795 if (atmel_port->prepare_tx) {
1796 retval = atmel_port->prepare_tx(port);
1798 atmel_set_ops(port);
1801 /* Save current CSR for comparison in atmel_tasklet_func() */
1802 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1803 atmel_port->irq_status = atmel_port->irq_status_prev;
1806 * Finally, enable the serial port
1808 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1809 /* enable xmit & rcvr */
1810 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1812 setup_timer(&atmel_port->uart_timer,
1813 atmel_uart_timer_callback,
1814 (unsigned long)port);
1816 if (atmel_use_pdc_rx(port)) {
1817 /* set UART timeout */
1818 if (!atmel_port->is_usart) {
1819 mod_timer(&atmel_port->uart_timer,
1820 jiffies + uart_poll_timeout(port));
1821 /* set USART timeout */
1823 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1824 UART_PUT_CR(port, ATMEL_US_STTTO);
1826 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1828 /* enable PDC controller */
1829 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
1830 } else if (atmel_use_dma_rx(port)) {
1831 /* set UART timeout */
1832 if (!atmel_port->is_usart) {
1833 mod_timer(&atmel_port->uart_timer,
1834 jiffies + uart_poll_timeout(port));
1835 /* set USART timeout */
1837 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
1838 UART_PUT_CR(port, ATMEL_US_STTTO);
1840 UART_PUT_IER(port, ATMEL_US_TIMEOUT);
1843 /* enable receive only */
1844 UART_PUT_IER(port, ATMEL_US_RXRDY);
1850 free_irq(port->irq, port);
1856 * Flush any TX data submitted for DMA. Called when the TX circular
1859 static void atmel_flush_buffer(struct uart_port *port)
1861 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1863 if (atmel_use_pdc_tx(port)) {
1864 UART_PUT_TCR(port, 0);
1865 atmel_port->pdc_tx.ofs = 0;
1872 static void atmel_shutdown(struct uart_port *port)
1874 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1877 * Prevent any tasklets being scheduled during
1880 del_timer_sync(&atmel_port->uart_timer);
1883 * Clear out any scheduled tasklets before
1884 * we destroy the buffers
1886 tasklet_disable(&atmel_port->tasklet);
1887 tasklet_kill(&atmel_port->tasklet);
1890 * Ensure everything is stopped and
1891 * disable all interrupts, port and break condition.
1893 atmel_stop_rx(port);
1894 atmel_stop_tx(port);
1896 UART_PUT_CR(port, ATMEL_US_RSTSTA);
1897 UART_PUT_IDR(port, -1);
1901 * Shut-down the DMA.
1903 if (atmel_port->release_rx)
1904 atmel_port->release_rx(port);
1905 if (atmel_port->release_tx)
1906 atmel_port->release_tx(port);
1909 * Reset ring buffer pointers
1911 atmel_port->rx_ring.head = 0;
1912 atmel_port->rx_ring.tail = 0;
1915 * Free the interrupts
1917 free_irq(port->irq, port);
1918 atmel_free_gpio_irq(port);
1920 atmel_port->ms_irq_enabled = false;
1922 atmel_flush_buffer(port);
1926 * Power / Clock management.
1928 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1929 unsigned int oldstate)
1931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1936 * Enable the peripheral clock for this serial port.
1937 * This is called on uart_open() or a resume event.
1939 clk_prepare_enable(atmel_port->clk);
1941 /* re-enable interrupts if we disabled some on suspend */
1942 UART_PUT_IER(port, atmel_port->backup_imr);
1945 /* Back up the interrupt mask and disable all interrupts */
1946 atmel_port->backup_imr = UART_GET_IMR(port);
1947 UART_PUT_IDR(port, -1);
1950 * Disable the peripheral clock for this serial port.
1951 * This is called on uart_close() or a suspend event.
1953 clk_disable_unprepare(atmel_port->clk);
1956 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1961 * Change the port parameters
1963 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1964 struct ktermios *old)
1966 unsigned long flags;
1967 unsigned int old_mode, mode, imr, quot, baud;
1969 /* save the current mode register */
1970 mode = old_mode = UART_GET_MR(port);
1972 /* reset the mode, clock divisor, parity, stop bits and data size */
1973 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
1974 ATMEL_US_PAR | ATMEL_US_USMODE);
1976 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1977 quot = uart_get_divisor(port, baud);
1979 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
1981 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1985 switch (termios->c_cflag & CSIZE) {
1987 mode |= ATMEL_US_CHRL_5;
1990 mode |= ATMEL_US_CHRL_6;
1993 mode |= ATMEL_US_CHRL_7;
1996 mode |= ATMEL_US_CHRL_8;
2001 if (termios->c_cflag & CSTOPB)
2002 mode |= ATMEL_US_NBSTOP_2;
2005 if (termios->c_cflag & PARENB) {
2006 /* Mark or Space parity */
2007 if (termios->c_cflag & CMSPAR) {
2008 if (termios->c_cflag & PARODD)
2009 mode |= ATMEL_US_PAR_MARK;
2011 mode |= ATMEL_US_PAR_SPACE;
2012 } else if (termios->c_cflag & PARODD)
2013 mode |= ATMEL_US_PAR_ODD;
2015 mode |= ATMEL_US_PAR_EVEN;
2017 mode |= ATMEL_US_PAR_NONE;
2019 spin_lock_irqsave(&port->lock, flags);
2021 port->read_status_mask = ATMEL_US_OVRE;
2022 if (termios->c_iflag & INPCK)
2023 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2024 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2025 port->read_status_mask |= ATMEL_US_RXBRK;
2027 if (atmel_use_pdc_rx(port))
2028 /* need to enable error interrupts */
2029 UART_PUT_IER(port, port->read_status_mask);
2032 * Characters to ignore
2034 port->ignore_status_mask = 0;
2035 if (termios->c_iflag & IGNPAR)
2036 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2037 if (termios->c_iflag & IGNBRK) {
2038 port->ignore_status_mask |= ATMEL_US_RXBRK;
2040 * If we're ignoring parity and break indicators,
2041 * ignore overruns too (for real raw support).
2043 if (termios->c_iflag & IGNPAR)
2044 port->ignore_status_mask |= ATMEL_US_OVRE;
2046 /* TODO: Ignore all characters if CREAD is set.*/
2048 /* update the per-port timeout */
2049 uart_update_timeout(port, termios->c_cflag, baud);
2052 * save/disable interrupts. The tty layer will ensure that the
2053 * transmitter is empty if requested by the caller, so there's
2054 * no need to wait for it here.
2056 imr = UART_GET_IMR(port);
2057 UART_PUT_IDR(port, -1);
2059 /* disable receiver and transmitter */
2060 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2063 if (port->rs485.flags & SER_RS485_ENABLED) {
2064 if ((port->rs485.delay_rts_after_send) > 0)
2065 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send);
2066 mode |= ATMEL_US_USMODE_RS485;
2067 } else if (termios->c_cflag & CRTSCTS) {
2068 /* RS232 with hardware handshake (RTS/CTS) */
2069 mode |= ATMEL_US_USMODE_HWHS;
2071 /* RS232 without hadware handshake */
2072 mode |= ATMEL_US_USMODE_NORMAL;
2075 /* set the mode, clock divisor, parity, stop bits and data size */
2076 UART_PUT_MR(port, mode);
2079 * when switching the mode, set the RTS line state according to the
2080 * new mode, otherwise keep the former state
2082 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2083 unsigned int rts_state;
2085 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2086 /* let the hardware control the RTS line */
2087 rts_state = ATMEL_US_RTSDIS;
2089 /* force RTS line to low level */
2090 rts_state = ATMEL_US_RTSEN;
2093 UART_PUT_CR(port, rts_state);
2096 /* set the baud rate */
2097 UART_PUT_BRGR(port, quot);
2098 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2099 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2101 /* restore interrupts */
2102 UART_PUT_IER(port, imr);
2104 /* CTS flow-control and modem-status interrupts */
2105 if (UART_ENABLE_MS(port, termios->c_cflag))
2106 atmel_enable_ms(port);
2108 atmel_disable_ms(port);
2110 spin_unlock_irqrestore(&port->lock, flags);
2113 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2115 if (termios->c_line == N_PPS) {
2116 port->flags |= UPF_HARDPPS_CD;
2117 spin_lock_irq(&port->lock);
2118 atmel_enable_ms(port);
2119 spin_unlock_irq(&port->lock);
2121 port->flags &= ~UPF_HARDPPS_CD;
2122 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2123 spin_lock_irq(&port->lock);
2124 atmel_disable_ms(port);
2125 spin_unlock_irq(&port->lock);
2131 * Return string describing the specified port
2133 static const char *atmel_type(struct uart_port *port)
2135 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2139 * Release the memory region(s) being used by 'port'.
2141 static void atmel_release_port(struct uart_port *port)
2143 struct platform_device *pdev = to_platform_device(port->dev);
2144 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2146 release_mem_region(port->mapbase, size);
2148 if (port->flags & UPF_IOREMAP) {
2149 iounmap(port->membase);
2150 port->membase = NULL;
2155 * Request the memory region(s) being used by 'port'.
2157 static int atmel_request_port(struct uart_port *port)
2159 struct platform_device *pdev = to_platform_device(port->dev);
2160 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2162 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2165 if (port->flags & UPF_IOREMAP) {
2166 port->membase = ioremap(port->mapbase, size);
2167 if (port->membase == NULL) {
2168 release_mem_region(port->mapbase, size);
2177 * Configure/autoconfigure the port.
2179 static void atmel_config_port(struct uart_port *port, int flags)
2181 if (flags & UART_CONFIG_TYPE) {
2182 port->type = PORT_ATMEL;
2183 atmel_request_port(port);
2188 * Verify the new serial_struct (for TIOCSSERIAL).
2190 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2193 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2195 if (port->irq != ser->irq)
2197 if (ser->io_type != SERIAL_IO_MEM)
2199 if (port->uartclk / 16 != ser->baud_base)
2201 if ((void *)port->mapbase != ser->iomem_base)
2203 if (port->iobase != ser->port)
2210 #ifdef CONFIG_CONSOLE_POLL
2211 static int atmel_poll_get_char(struct uart_port *port)
2213 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY))
2216 return UART_GET_CHAR(port);
2219 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2221 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2224 UART_PUT_CHAR(port, ch);
2228 static struct uart_ops atmel_pops = {
2229 .tx_empty = atmel_tx_empty,
2230 .set_mctrl = atmel_set_mctrl,
2231 .get_mctrl = atmel_get_mctrl,
2232 .stop_tx = atmel_stop_tx,
2233 .start_tx = atmel_start_tx,
2234 .stop_rx = atmel_stop_rx,
2235 .enable_ms = atmel_enable_ms,
2236 .break_ctl = atmel_break_ctl,
2237 .startup = atmel_startup,
2238 .shutdown = atmel_shutdown,
2239 .flush_buffer = atmel_flush_buffer,
2240 .set_termios = atmel_set_termios,
2241 .set_ldisc = atmel_set_ldisc,
2243 .release_port = atmel_release_port,
2244 .request_port = atmel_request_port,
2245 .config_port = atmel_config_port,
2246 .verify_port = atmel_verify_port,
2247 .pm = atmel_serial_pm,
2248 #ifdef CONFIG_CONSOLE_POLL
2249 .poll_get_char = atmel_poll_get_char,
2250 .poll_put_char = atmel_poll_put_char,
2255 * Configure the port from the platform device resource info.
2257 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2258 struct platform_device *pdev)
2261 struct uart_port *port = &atmel_port->uart;
2262 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2264 atmel_init_property(atmel_port, pdev);
2265 atmel_set_ops(port);
2267 atmel_init_rs485(port, pdev);
2269 port->iotype = UPIO_MEM;
2270 port->flags = UPF_BOOT_AUTOCONF;
2271 port->ops = &atmel_pops;
2273 port->dev = &pdev->dev;
2274 port->mapbase = pdev->resource[0].start;
2275 port->irq = pdev->resource[1].start;
2276 port->rs485_config = atmel_config_rs485;
2278 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2279 (unsigned long)port);
2280 tasklet_disable(&atmel_port->tasklet);
2282 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2284 if (pdata && pdata->regs) {
2285 /* Already mapped by setup code */
2286 port->membase = pdata->regs;
2288 port->flags |= UPF_IOREMAP;
2289 port->membase = NULL;
2292 /* for console, the clock could already be configured */
2293 if (!atmel_port->clk) {
2294 atmel_port->clk = clk_get(&pdev->dev, "usart");
2295 if (IS_ERR(atmel_port->clk)) {
2296 ret = PTR_ERR(atmel_port->clk);
2297 atmel_port->clk = NULL;
2300 ret = clk_prepare_enable(atmel_port->clk);
2302 clk_put(atmel_port->clk);
2303 atmel_port->clk = NULL;
2306 port->uartclk = clk_get_rate(atmel_port->clk);
2307 clk_disable_unprepare(atmel_port->clk);
2308 /* only enable clock when USART is in use */
2311 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2312 if (port->rs485.flags & SER_RS485_ENABLED)
2313 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2314 else if (atmel_use_pdc_tx(port)) {
2315 port->fifosize = PDC_BUFFER_SIZE;
2316 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2318 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2324 struct platform_device *atmel_default_console_device; /* the serial console device */
2326 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2327 static void atmel_console_putchar(struct uart_port *port, int ch)
2329 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
2331 UART_PUT_CHAR(port, ch);
2335 * Interrupts are disabled on entering
2337 static void atmel_console_write(struct console *co, const char *s, u_int count)
2339 struct uart_port *port = &atmel_ports[co->index].uart;
2340 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2341 unsigned int status, imr;
2342 unsigned int pdc_tx;
2345 * First, save IMR and then disable interrupts
2347 imr = UART_GET_IMR(port);
2348 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2350 /* Store PDC transmit status and disable it */
2351 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
2352 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
2354 uart_console_write(port, s, count, atmel_console_putchar);
2357 * Finally, wait for transmitter to become empty
2361 status = UART_GET_CSR(port);
2362 } while (!(status & ATMEL_US_TXRDY));
2364 /* Restore PDC transmit status */
2366 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
2368 /* set interrupts back the way they were */
2369 UART_PUT_IER(port, imr);
2373 * If the port was already initialised (eg, by a boot loader),
2374 * try to determine the current setup.
2376 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2377 int *parity, int *bits)
2379 unsigned int mr, quot;
2382 * If the baud rate generator isn't running, the port wasn't
2383 * initialized by the boot loader.
2385 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
2389 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
2390 if (mr == ATMEL_US_CHRL_8)
2395 mr = UART_GET_MR(port) & ATMEL_US_PAR;
2396 if (mr == ATMEL_US_PAR_EVEN)
2398 else if (mr == ATMEL_US_PAR_ODD)
2402 * The serial core only rounds down when matching this to a
2403 * supported baud rate. Make sure we don't end up slightly
2404 * lower than one of those, as it would make us fall through
2405 * to a much lower baud rate than we really want.
2407 *baud = port->uartclk / (16 * (quot - 1));
2410 static int __init atmel_console_setup(struct console *co, char *options)
2413 struct uart_port *port = &atmel_ports[co->index].uart;
2419 if (port->membase == NULL) {
2420 /* Port not initialized yet - delay setup */
2424 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2428 UART_PUT_IDR(port, -1);
2429 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2430 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
2433 uart_parse_options(options, &baud, &parity, &bits, &flow);
2435 atmel_console_get_options(port, &baud, &parity, &bits);
2437 return uart_set_options(port, co, baud, parity, bits, flow);
2440 static struct uart_driver atmel_uart;
2442 static struct console atmel_console = {
2443 .name = ATMEL_DEVICENAME,
2444 .write = atmel_console_write,
2445 .device = uart_console_device,
2446 .setup = atmel_console_setup,
2447 .flags = CON_PRINTBUFFER,
2449 .data = &atmel_uart,
2452 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2455 * Early console initialization (before VM subsystem initialized).
2457 static int __init atmel_console_init(void)
2460 if (atmel_default_console_device) {
2461 struct atmel_uart_data *pdata =
2462 dev_get_platdata(&atmel_default_console_device->dev);
2463 int id = pdata->num;
2464 struct atmel_uart_port *port = &atmel_ports[id];
2466 port->backup_imr = 0;
2467 port->uart.line = id;
2469 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2470 ret = atmel_init_port(port, atmel_default_console_device);
2473 register_console(&atmel_console);
2479 console_initcall(atmel_console_init);
2482 * Late console initialization.
2484 static int __init atmel_late_console_init(void)
2486 if (atmel_default_console_device
2487 && !(atmel_console.flags & CON_ENABLED))
2488 register_console(&atmel_console);
2493 core_initcall(atmel_late_console_init);
2495 static inline bool atmel_is_console_port(struct uart_port *port)
2497 return port->cons && port->cons->index == port->line;
2501 #define ATMEL_CONSOLE_DEVICE NULL
2503 static inline bool atmel_is_console_port(struct uart_port *port)
2509 static struct uart_driver atmel_uart = {
2510 .owner = THIS_MODULE,
2511 .driver_name = "atmel_serial",
2512 .dev_name = ATMEL_DEVICENAME,
2513 .major = SERIAL_ATMEL_MAJOR,
2514 .minor = MINOR_START,
2515 .nr = ATMEL_MAX_UART,
2516 .cons = ATMEL_CONSOLE_DEVICE,
2520 static bool atmel_serial_clk_will_stop(void)
2522 #ifdef CONFIG_ARCH_AT91
2523 return at91_suspend_entering_slow_clock();
2529 static int atmel_serial_suspend(struct platform_device *pdev,
2532 struct uart_port *port = platform_get_drvdata(pdev);
2533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2535 if (atmel_is_console_port(port) && console_suspend_enabled) {
2536 /* Drain the TX shifter */
2537 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
2541 /* we can not wake up if we're running on slow clock */
2542 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2543 if (atmel_serial_clk_will_stop()) {
2544 unsigned long flags;
2546 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2547 atmel_port->suspended = true;
2548 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2549 device_set_wakeup_enable(&pdev->dev, 0);
2552 uart_suspend_port(&atmel_uart, port);
2557 static int atmel_serial_resume(struct platform_device *pdev)
2559 struct uart_port *port = platform_get_drvdata(pdev);
2560 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2561 unsigned long flags;
2563 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2564 if (atmel_port->pending) {
2565 atmel_handle_receive(port, atmel_port->pending);
2566 atmel_handle_status(port, atmel_port->pending,
2567 atmel_port->pending_status);
2568 atmel_handle_transmit(port, atmel_port->pending);
2569 atmel_port->pending = 0;
2571 atmel_port->suspended = false;
2572 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2574 uart_resume_port(&atmel_uart, port);
2575 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2580 #define atmel_serial_suspend NULL
2581 #define atmel_serial_resume NULL
2584 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2586 enum mctrl_gpio_idx i;
2587 struct gpio_desc *gpiod;
2589 p->gpios = mctrl_gpio_init(dev, 0);
2590 if (IS_ERR(p->gpios))
2591 return PTR_ERR(p->gpios);
2593 for (i = 0; i < UART_GPIO_MAX; i++) {
2594 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2595 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2596 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2598 p->gpio_irq[i] = -EINVAL;
2604 static int atmel_serial_probe(struct platform_device *pdev)
2606 struct atmel_uart_port *port;
2607 struct device_node *np = pdev->dev.of_node;
2608 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2613 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2616 ret = of_alias_get_id(np, "serial");
2622 /* port id not found in platform data nor device-tree aliases:
2623 * auto-enumerate it */
2624 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2626 if (ret >= ATMEL_MAX_UART) {
2631 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2632 /* port already in use */
2637 port = &atmel_ports[ret];
2638 port->backup_imr = 0;
2639 port->uart.line = ret;
2641 spin_lock_init(&port->lock_suspended);
2643 ret = atmel_init_gpios(port, &pdev->dev);
2645 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2649 ret = atmel_init_port(port, pdev);
2653 if (!atmel_use_pdc_rx(&port->uart)) {
2655 data = kmalloc(sizeof(struct atmel_uart_char)
2656 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2658 goto err_alloc_ring;
2659 port->rx_ring.buf = data;
2662 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2664 ret = uart_add_one_port(&atmel_uart, &port->uart);
2668 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2669 if (atmel_is_console_port(&port->uart)
2670 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2672 * The serial core enabled the clock for us, so undo
2673 * the clk_prepare_enable() in atmel_console_setup()
2675 clk_disable_unprepare(port->clk);
2679 device_init_wakeup(&pdev->dev, 1);
2680 platform_set_drvdata(pdev, port);
2683 * The peripheral clock has been disabled by atmel_init_port():
2684 * enable it before accessing I/O registers
2686 clk_prepare_enable(port->clk);
2688 if (rs485_enabled) {
2689 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL);
2690 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN);
2694 * Get port name of usart or uart
2696 atmel_get_ip_name(&port->uart);
2699 * The peripheral clock can now safely be disabled till the port
2702 clk_disable_unprepare(port->clk);
2707 kfree(port->rx_ring.buf);
2708 port->rx_ring.buf = NULL;
2710 if (!atmel_is_console_port(&port->uart)) {
2715 clear_bit(port->uart.line, atmel_ports_in_use);
2720 static int atmel_serial_remove(struct platform_device *pdev)
2722 struct uart_port *port = platform_get_drvdata(pdev);
2723 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2726 tasklet_kill(&atmel_port->tasklet);
2728 device_init_wakeup(&pdev->dev, 0);
2730 ret = uart_remove_one_port(&atmel_uart, port);
2732 kfree(atmel_port->rx_ring.buf);
2734 /* "port" is allocated statically, so we shouldn't free it */
2736 clear_bit(port->line, atmel_ports_in_use);
2738 clk_put(atmel_port->clk);
2743 static struct platform_driver atmel_serial_driver = {
2744 .probe = atmel_serial_probe,
2745 .remove = atmel_serial_remove,
2746 .suspend = atmel_serial_suspend,
2747 .resume = atmel_serial_resume,
2749 .name = "atmel_usart",
2750 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2754 static int __init atmel_serial_init(void)
2758 ret = uart_register_driver(&atmel_uart);
2762 ret = platform_driver_register(&atmel_serial_driver);
2764 uart_unregister_driver(&atmel_uart);
2769 static void __exit atmel_serial_exit(void)
2771 platform_driver_unregister(&atmel_serial_driver);
2772 uart_unregister_driver(&atmel_uart);
2775 module_init(atmel_serial_init);
2776 module_exit(atmel_serial_exit);
2778 MODULE_AUTHOR("Rick Bronson");
2779 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2780 MODULE_LICENSE("GPL");
2781 MODULE_ALIAS("platform:atmel_usart");