2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
64 #define SERIAL_AMBA_MAJOR 204
65 #define SERIAL_AMBA_MINOR 64
66 #define SERIAL_AMBA_NR UART_NR
68 #define AMBA_ISR_PASS_LIMIT 256
70 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71 #define UART_DUMMY_DR_RX (1 << 16)
73 /* There is by now at least one vendor with differing details, so handle it */
80 bool cts_event_workaround;
82 unsigned int (*get_fifosize)(unsigned int periphid);
85 static unsigned int get_fifosize_arm(unsigned int periphid)
87 unsigned int rev = (periphid >> 20) & 0xf;
88 return rev < 3 ? 16 : 32;
91 static struct vendor_data vendor_arm = {
92 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
93 .lcrh_tx = UART011_LCRH,
94 .lcrh_rx = UART011_LCRH,
95 .oversampling = false,
96 .dma_threshold = false,
97 .cts_event_workaround = false,
98 .get_fifosize = get_fifosize_arm,
101 static unsigned int get_fifosize_st(unsigned int periphid)
106 static struct vendor_data vendor_st = {
107 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
108 .lcrh_tx = ST_UART011_LCRH_TX,
109 .lcrh_rx = ST_UART011_LCRH_RX,
110 .oversampling = true,
111 .dma_threshold = true,
112 .cts_event_workaround = true,
113 .get_fifosize = get_fifosize_st,
116 static struct uart_amba_port *amba_ports[UART_NR];
118 /* Deals with DMA transactions */
121 struct scatterlist sg;
125 struct pl011_dmarx_data {
126 struct dma_chan *chan;
127 struct completion complete;
129 struct pl011_sgbuf sgbuf_a;
130 struct pl011_sgbuf sgbuf_b;
133 struct timer_list timer;
134 unsigned int last_residue;
135 unsigned long last_jiffies;
137 unsigned int poll_rate;
138 unsigned int poll_timeout;
141 struct pl011_dmatx_data {
142 struct dma_chan *chan;
143 struct scatterlist sg;
149 * We wrap our port structure around the generic uart_port.
151 struct uart_amba_port {
152 struct uart_port port;
154 /* Two optional pin states - default & sleep */
155 struct pinctrl *pinctrl;
156 struct pinctrl_state *pins_default;
157 struct pinctrl_state *pins_sleep;
158 const struct vendor_data *vendor;
159 unsigned int dmacr; /* dma control reg */
160 unsigned int im; /* interrupt mask */
161 unsigned int old_status;
162 unsigned int fifosize; /* vendor-specific */
163 unsigned int lcrh_tx; /* vendor-specific */
164 unsigned int lcrh_rx; /* vendor-specific */
165 unsigned int old_cr; /* state during shutdown */
168 #ifdef CONFIG_DMA_ENGINE
172 struct pl011_dmarx_data dmarx;
173 struct pl011_dmatx_data dmatx;
178 * Reads up to 256 characters from the FIFO or until it's empty and
179 * inserts them into the TTY layer. Returns the number of characters
180 * read from the FIFO.
182 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
185 unsigned int flag, max_count = 256;
188 while (max_count--) {
189 status = readw(uap->port.membase + UART01x_FR);
190 if (status & UART01x_FR_RXFE)
193 /* Take chars from the FIFO and update status */
194 ch = readw(uap->port.membase + UART01x_DR) |
197 uap->port.icount.rx++;
200 if (unlikely(ch & UART_DR_ERROR)) {
201 if (ch & UART011_DR_BE) {
202 ch &= ~(UART011_DR_FE | UART011_DR_PE);
203 uap->port.icount.brk++;
204 if (uart_handle_break(&uap->port))
206 } else if (ch & UART011_DR_PE)
207 uap->port.icount.parity++;
208 else if (ch & UART011_DR_FE)
209 uap->port.icount.frame++;
210 if (ch & UART011_DR_OE)
211 uap->port.icount.overrun++;
213 ch &= uap->port.read_status_mask;
215 if (ch & UART011_DR_BE)
217 else if (ch & UART011_DR_PE)
219 else if (ch & UART011_DR_FE)
223 if (uart_handle_sysrq_char(&uap->port, ch & 255))
226 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
234 * All the DMA operation mode stuff goes inside this ifdef.
235 * This assumes that you have a generic DMA device interface,
236 * no custom DMA interfaces are supported.
238 #ifdef CONFIG_DMA_ENGINE
240 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
242 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
243 enum dma_data_direction dir)
247 sg->buf = dma_alloc_coherent(chan->device->dev,
248 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
252 sg_init_table(&sg->sg, 1);
253 sg_set_page(&sg->sg, phys_to_page(dma_addr),
254 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
255 sg_dma_address(&sg->sg) = dma_addr;
260 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
261 enum dma_data_direction dir)
264 dma_free_coherent(chan->device->dev,
265 PL011_DMA_BUFFER_SIZE, sg->buf,
266 sg_dma_address(&sg->sg));
270 static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
272 /* DMA is the sole user of the platform data right now */
273 struct amba_pl011_data *plat = uap->port.dev->platform_data;
274 struct dma_slave_config tx_conf = {
275 .dst_addr = uap->port.mapbase + UART01x_DR,
276 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
277 .direction = DMA_MEM_TO_DEV,
278 .dst_maxburst = uap->fifosize >> 1,
281 struct dma_chan *chan;
284 /* We need platform data */
285 if (!plat || !plat->dma_filter) {
286 dev_info(uap->port.dev, "no DMA platform data\n");
290 /* Try to acquire a generic DMA engine slave TX channel */
292 dma_cap_set(DMA_SLAVE, mask);
294 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
296 dev_err(uap->port.dev, "no TX DMA channel!\n");
300 dmaengine_slave_config(chan, &tx_conf);
301 uap->dmatx.chan = chan;
303 dev_info(uap->port.dev, "DMA channel TX %s\n",
304 dma_chan_name(uap->dmatx.chan));
306 /* Optionally make use of an RX channel as well */
307 if (plat->dma_rx_param) {
308 struct dma_slave_config rx_conf = {
309 .src_addr = uap->port.mapbase + UART01x_DR,
310 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
311 .direction = DMA_DEV_TO_MEM,
312 .src_maxburst = uap->fifosize >> 1,
316 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
318 dev_err(uap->port.dev, "no RX DMA channel!\n");
322 dmaengine_slave_config(chan, &rx_conf);
323 uap->dmarx.chan = chan;
325 if (plat->dma_rx_poll_enable) {
326 /* Set poll rate if specified. */
327 if (plat->dma_rx_poll_rate) {
328 uap->dmarx.auto_poll_rate = false;
329 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
332 * 100 ms defaults to poll rate if not
333 * specified. This will be adjusted with
334 * the baud rate at set_termios.
336 uap->dmarx.auto_poll_rate = true;
337 uap->dmarx.poll_rate = 100;
339 /* 3 secs defaults poll_timeout if not specified. */
340 if (plat->dma_rx_poll_timeout)
341 uap->dmarx.poll_timeout =
342 plat->dma_rx_poll_timeout;
344 uap->dmarx.poll_timeout = 3000;
346 uap->dmarx.auto_poll_rate = false;
348 dev_info(uap->port.dev, "DMA channel RX %s\n",
349 dma_chan_name(uap->dmarx.chan));
355 * Stack up the UARTs and let the above initcall be done at device
356 * initcall time, because the serial driver is called as an arch
357 * initcall, and at this time the DMA subsystem is not yet registered.
358 * At this point the driver will switch over to using DMA where desired.
361 struct list_head node;
362 struct uart_amba_port *uap;
365 static LIST_HEAD(pl011_dma_uarts);
367 static int __init pl011_dma_initcall(void)
369 struct list_head *node, *tmp;
371 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
372 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
373 pl011_dma_probe_initcall(dmau->uap);
380 device_initcall(pl011_dma_initcall);
382 static void pl011_dma_probe(struct uart_amba_port *uap)
384 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
387 list_add_tail(&dmau->node, &pl011_dma_uarts);
391 static void pl011_dma_probe(struct uart_amba_port *uap)
393 pl011_dma_probe_initcall(uap);
397 static void pl011_dma_remove(struct uart_amba_port *uap)
399 /* TODO: remove the initcall if it has not yet executed */
401 dma_release_channel(uap->dmatx.chan);
403 dma_release_channel(uap->dmarx.chan);
406 /* Forward declare this for the refill routine */
407 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
410 * The current DMA TX buffer has been sent.
411 * Try to queue up another DMA buffer.
413 static void pl011_dma_tx_callback(void *data)
415 struct uart_amba_port *uap = data;
416 struct pl011_dmatx_data *dmatx = &uap->dmatx;
420 spin_lock_irqsave(&uap->port.lock, flags);
421 if (uap->dmatx.queued)
422 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
426 uap->dmacr = dmacr & ~UART011_TXDMAE;
427 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
430 * If TX DMA was disabled, it means that we've stopped the DMA for
431 * some reason (eg, XOFF received, or we want to send an X-char.)
433 * Note: we need to be careful here of a potential race between DMA
434 * and the rest of the driver - if the driver disables TX DMA while
435 * a TX buffer completing, we must update the tx queued status to
436 * get further refills (hence we check dmacr).
438 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
439 uart_circ_empty(&uap->port.state->xmit)) {
440 uap->dmatx.queued = false;
441 spin_unlock_irqrestore(&uap->port.lock, flags);
445 if (pl011_dma_tx_refill(uap) <= 0) {
447 * We didn't queue a DMA buffer for some reason, but we
448 * have data pending to be sent. Re-enable the TX IRQ.
450 uap->im |= UART011_TXIM;
451 writew(uap->im, uap->port.membase + UART011_IMSC);
453 spin_unlock_irqrestore(&uap->port.lock, flags);
457 * Try to refill the TX DMA buffer.
458 * Locking: called with port lock held and IRQs disabled.
460 * 1 if we queued up a TX DMA buffer.
461 * 0 if we didn't want to handle this by DMA
464 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
466 struct pl011_dmatx_data *dmatx = &uap->dmatx;
467 struct dma_chan *chan = dmatx->chan;
468 struct dma_device *dma_dev = chan->device;
469 struct dma_async_tx_descriptor *desc;
470 struct circ_buf *xmit = &uap->port.state->xmit;
474 * Try to avoid the overhead involved in using DMA if the
475 * transaction fits in the first half of the FIFO, by using
476 * the standard interrupt handling. This ensures that we
477 * issue a uart_write_wakeup() at the appropriate time.
479 count = uart_circ_chars_pending(xmit);
480 if (count < (uap->fifosize >> 1)) {
481 uap->dmatx.queued = false;
486 * Bodge: don't send the last character by DMA, as this
487 * will prevent XON from notifying us to restart DMA.
491 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
492 if (count > PL011_DMA_BUFFER_SIZE)
493 count = PL011_DMA_BUFFER_SIZE;
495 if (xmit->tail < xmit->head)
496 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
498 size_t first = UART_XMIT_SIZE - xmit->tail;
499 size_t second = xmit->head;
501 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
503 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
506 dmatx->sg.length = count;
508 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
509 uap->dmatx.queued = false;
510 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
514 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
515 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
517 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
518 uap->dmatx.queued = false;
520 * If DMA cannot be used right now, we complete this
521 * transaction via IRQ and let the TTY layer retry.
523 dev_dbg(uap->port.dev, "TX DMA busy\n");
527 /* Some data to go along to the callback */
528 desc->callback = pl011_dma_tx_callback;
529 desc->callback_param = uap;
531 /* All errors should happen at prepare time */
532 dmaengine_submit(desc);
534 /* Fire the DMA transaction */
535 dma_dev->device_issue_pending(chan);
537 uap->dmacr |= UART011_TXDMAE;
538 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
539 uap->dmatx.queued = true;
542 * Now we know that DMA will fire, so advance the ring buffer
543 * with the stuff we just dispatched.
545 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
546 uap->port.icount.tx += count;
548 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
549 uart_write_wakeup(&uap->port);
555 * We received a transmit interrupt without a pending X-char but with
556 * pending characters.
557 * Locking: called with port lock held and IRQs disabled.
559 * false if we want to use PIO to transmit
560 * true if we queued a DMA buffer
562 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
564 if (!uap->using_tx_dma)
568 * If we already have a TX buffer queued, but received a
569 * TX interrupt, it will be because we've just sent an X-char.
570 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
572 if (uap->dmatx.queued) {
573 uap->dmacr |= UART011_TXDMAE;
574 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
575 uap->im &= ~UART011_TXIM;
576 writew(uap->im, uap->port.membase + UART011_IMSC);
581 * We don't have a TX buffer queued, so try to queue one.
582 * If we successfully queued a buffer, mask the TX IRQ.
584 if (pl011_dma_tx_refill(uap) > 0) {
585 uap->im &= ~UART011_TXIM;
586 writew(uap->im, uap->port.membase + UART011_IMSC);
593 * Stop the DMA transmit (eg, due to received XOFF).
594 * Locking: called with port lock held and IRQs disabled.
596 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
598 if (uap->dmatx.queued) {
599 uap->dmacr &= ~UART011_TXDMAE;
600 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
605 * Try to start a DMA transmit, or in the case of an XON/OFF
606 * character queued for send, try to get that character out ASAP.
607 * Locking: called with port lock held and IRQs disabled.
609 * false if we want the TX IRQ to be enabled
610 * true if we have a buffer queued
612 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
616 if (!uap->using_tx_dma)
619 if (!uap->port.x_char) {
620 /* no X-char, try to push chars out in DMA mode */
623 if (!uap->dmatx.queued) {
624 if (pl011_dma_tx_refill(uap) > 0) {
625 uap->im &= ~UART011_TXIM;
628 uap->im |= UART011_TXIM;
631 writew(uap->im, uap->port.membase + UART011_IMSC);
632 } else if (!(uap->dmacr & UART011_TXDMAE)) {
633 uap->dmacr |= UART011_TXDMAE;
635 uap->port.membase + UART011_DMACR);
641 * We have an X-char to send. Disable DMA to prevent it loading
642 * the TX fifo, and then see if we can stuff it into the FIFO.
645 uap->dmacr &= ~UART011_TXDMAE;
646 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
648 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
650 * No space in the FIFO, so enable the transmit interrupt
651 * so we know when there is space. Note that once we've
652 * loaded the character, we should just re-enable DMA.
657 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
658 uap->port.icount.tx++;
659 uap->port.x_char = 0;
661 /* Success - restore the DMA state */
663 writew(dmacr, uap->port.membase + UART011_DMACR);
669 * Flush the transmit buffer.
670 * Locking: called with port lock held and IRQs disabled.
672 static void pl011_dma_flush_buffer(struct uart_port *port)
674 struct uart_amba_port *uap = (struct uart_amba_port *)port;
676 if (!uap->using_tx_dma)
679 /* Avoid deadlock with the DMA engine callback */
680 spin_unlock(&uap->port.lock);
681 dmaengine_terminate_all(uap->dmatx.chan);
682 spin_lock(&uap->port.lock);
683 if (uap->dmatx.queued) {
684 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
686 uap->dmatx.queued = false;
687 uap->dmacr &= ~UART011_TXDMAE;
688 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
692 static void pl011_dma_rx_callback(void *data);
694 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
696 struct dma_chan *rxchan = uap->dmarx.chan;
697 struct pl011_dmarx_data *dmarx = &uap->dmarx;
698 struct dma_async_tx_descriptor *desc;
699 struct pl011_sgbuf *sgbuf;
704 /* Start the RX DMA job */
705 sgbuf = uap->dmarx.use_buf_b ?
706 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
707 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
709 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
711 * If the DMA engine is busy and cannot prepare a
712 * channel, no big deal, the driver will fall back
713 * to interrupt mode as a result of this error code.
716 uap->dmarx.running = false;
717 dmaengine_terminate_all(rxchan);
721 /* Some data to go along to the callback */
722 desc->callback = pl011_dma_rx_callback;
723 desc->callback_param = uap;
724 dmarx->cookie = dmaengine_submit(desc);
725 dma_async_issue_pending(rxchan);
727 uap->dmacr |= UART011_RXDMAE;
728 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
729 uap->dmarx.running = true;
731 uap->im &= ~UART011_RXIM;
732 writew(uap->im, uap->port.membase + UART011_IMSC);
738 * This is called when either the DMA job is complete, or
739 * the FIFO timeout interrupt occurred. This must be called
740 * with the port spinlock uap->port.lock held.
742 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
743 u32 pending, bool use_buf_b,
746 struct tty_port *port = &uap->port.state->port;
747 struct pl011_sgbuf *sgbuf = use_buf_b ?
748 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
750 u32 fifotaken = 0; /* only used for vdbg() */
752 struct pl011_dmarx_data *dmarx = &uap->dmarx;
755 if (uap->dmarx.poll_rate) {
756 /* The data can be taken by polling */
757 dmataken = sgbuf->sg.length - dmarx->last_residue;
758 /* Recalculate the pending size */
759 if (pending >= dmataken)
763 /* Pick the remain data from the DMA */
767 * First take all chars in the DMA pipe, then look in the FIFO.
768 * Note that tty_insert_flip_buf() tries to take as many chars
771 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
774 uap->port.icount.rx += dma_count;
775 if (dma_count < pending)
776 dev_warn(uap->port.dev,
777 "couldn't insert all characters (TTY is full?)\n");
780 /* Reset the last_residue for Rx DMA poll */
781 if (uap->dmarx.poll_rate)
782 dmarx->last_residue = sgbuf->sg.length;
785 * Only continue with trying to read the FIFO if all DMA chars have
788 if (dma_count == pending && readfifo) {
789 /* Clear any error flags */
790 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
791 uap->port.membase + UART011_ICR);
794 * If we read all the DMA'd characters, and we had an
795 * incomplete buffer, that could be due to an rx error, or
796 * maybe we just timed out. Read any pending chars and check
799 * Error conditions will only occur in the FIFO, these will
800 * trigger an immediate interrupt and stop the DMA job, so we
801 * will always find the error in the FIFO, never in the DMA
804 fifotaken = pl011_fifo_to_tty(uap);
807 spin_unlock(&uap->port.lock);
808 dev_vdbg(uap->port.dev,
809 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
810 dma_count, fifotaken);
811 tty_flip_buffer_push(port);
812 spin_lock(&uap->port.lock);
815 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
817 struct pl011_dmarx_data *dmarx = &uap->dmarx;
818 struct dma_chan *rxchan = dmarx->chan;
819 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
820 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
822 struct dma_tx_state state;
823 enum dma_status dmastat;
826 * Pause the transfer so we can trust the current counter,
827 * do this before we pause the PL011 block, else we may
830 if (dmaengine_pause(rxchan))
831 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
832 dmastat = rxchan->device->device_tx_status(rxchan,
833 dmarx->cookie, &state);
834 if (dmastat != DMA_PAUSED)
835 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
837 /* Disable RX DMA - incoming data will wait in the FIFO */
838 uap->dmacr &= ~UART011_RXDMAE;
839 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
840 uap->dmarx.running = false;
842 pending = sgbuf->sg.length - state.residue;
843 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
844 /* Then we terminate the transfer - we now know our residue */
845 dmaengine_terminate_all(rxchan);
848 * This will take the chars we have so far and insert
849 * into the framework.
851 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
853 /* Switch buffer & re-trigger DMA job */
854 dmarx->use_buf_b = !dmarx->use_buf_b;
855 if (pl011_dma_rx_trigger_dma(uap)) {
856 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
857 "fall back to interrupt mode\n");
858 uap->im |= UART011_RXIM;
859 writew(uap->im, uap->port.membase + UART011_IMSC);
863 static void pl011_dma_rx_callback(void *data)
865 struct uart_amba_port *uap = data;
866 struct pl011_dmarx_data *dmarx = &uap->dmarx;
867 struct dma_chan *rxchan = dmarx->chan;
868 bool lastbuf = dmarx->use_buf_b;
869 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
870 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
872 struct dma_tx_state state;
876 * This completion interrupt occurs typically when the
877 * RX buffer is totally stuffed but no timeout has yet
878 * occurred. When that happens, we just want the RX
879 * routine to flush out the secondary DMA buffer while
880 * we immediately trigger the next DMA job.
882 spin_lock_irq(&uap->port.lock);
884 * Rx data can be taken by the UART interrupts during
885 * the DMA irq handler. So we check the residue here.
887 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
888 pending = sgbuf->sg.length - state.residue;
889 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
890 /* Then we terminate the transfer - we now know our residue */
891 dmaengine_terminate_all(rxchan);
893 uap->dmarx.running = false;
894 dmarx->use_buf_b = !lastbuf;
895 ret = pl011_dma_rx_trigger_dma(uap);
897 pl011_dma_rx_chars(uap, pending, lastbuf, false);
898 spin_unlock_irq(&uap->port.lock);
900 * Do this check after we picked the DMA chars so we don't
901 * get some IRQ immediately from RX.
904 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
905 "fall back to interrupt mode\n");
906 uap->im |= UART011_RXIM;
907 writew(uap->im, uap->port.membase + UART011_IMSC);
912 * Stop accepting received characters, when we're shutting down or
913 * suspending this port.
914 * Locking: called with port lock held and IRQs disabled.
916 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
918 /* FIXME. Just disable the DMA enable */
919 uap->dmacr &= ~UART011_RXDMAE;
920 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
924 * Timer handler for Rx DMA polling.
925 * Every polling, It checks the residue in the dma buffer and transfer
926 * data to the tty. Also, last_residue is updated for the next polling.
928 static void pl011_dma_rx_poll(unsigned long args)
930 struct uart_amba_port *uap = (struct uart_amba_port *)args;
931 struct tty_port *port = &uap->port.state->port;
932 struct pl011_dmarx_data *dmarx = &uap->dmarx;
933 struct dma_chan *rxchan = uap->dmarx.chan;
934 unsigned long flags = 0;
935 unsigned int dmataken = 0;
936 unsigned int size = 0;
937 struct pl011_sgbuf *sgbuf;
939 struct dma_tx_state state;
941 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
942 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
943 if (likely(state.residue < dmarx->last_residue)) {
944 dmataken = sgbuf->sg.length - dmarx->last_residue;
945 size = dmarx->last_residue - state.residue;
946 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
948 if (dma_count == size)
949 dmarx->last_residue = state.residue;
950 dmarx->last_jiffies = jiffies;
952 tty_flip_buffer_push(port);
955 * If no data is received in poll_timeout, the driver will fall back
956 * to interrupt mode. We will retrigger DMA at the first interrupt.
958 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
959 > uap->dmarx.poll_timeout) {
961 spin_lock_irqsave(&uap->port.lock, flags);
962 pl011_dma_rx_stop(uap);
963 spin_unlock_irqrestore(&uap->port.lock, flags);
965 uap->dmarx.running = false;
966 dmaengine_terminate_all(rxchan);
967 del_timer(&uap->dmarx.timer);
969 mod_timer(&uap->dmarx.timer,
970 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
974 static void pl011_dma_startup(struct uart_amba_port *uap)
978 if (!uap->dmatx.chan)
981 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
982 if (!uap->dmatx.buf) {
983 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
984 uap->port.fifosize = uap->fifosize;
988 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
990 /* The DMA buffer is now the FIFO the TTY subsystem can use */
991 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
992 uap->using_tx_dma = true;
994 if (!uap->dmarx.chan)
997 /* Allocate and map DMA RX buffers */
998 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1001 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1002 "RX buffer A", ret);
1006 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1009 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1010 "RX buffer B", ret);
1011 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1016 uap->using_rx_dma = true;
1019 /* Turn on DMA error (RX/TX will be enabled on demand) */
1020 uap->dmacr |= UART011_DMAONERR;
1021 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1024 * ST Micro variants has some specific dma burst threshold
1025 * compensation. Set this to 16 bytes, so burst will only
1026 * be issued above/below 16 bytes.
1028 if (uap->vendor->dma_threshold)
1029 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1030 uap->port.membase + ST_UART011_DMAWM);
1032 if (uap->using_rx_dma) {
1033 if (pl011_dma_rx_trigger_dma(uap))
1034 dev_dbg(uap->port.dev, "could not trigger initial "
1035 "RX DMA job, fall back to interrupt mode\n");
1036 if (uap->dmarx.poll_rate) {
1037 init_timer(&(uap->dmarx.timer));
1038 uap->dmarx.timer.function = pl011_dma_rx_poll;
1039 uap->dmarx.timer.data = (unsigned long)uap;
1040 mod_timer(&uap->dmarx.timer,
1042 msecs_to_jiffies(uap->dmarx.poll_rate));
1043 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1044 uap->dmarx.last_jiffies = jiffies;
1049 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1051 if (!(uap->using_tx_dma || uap->using_rx_dma))
1054 /* Disable RX and TX DMA */
1055 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1058 spin_lock_irq(&uap->port.lock);
1059 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1060 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1061 spin_unlock_irq(&uap->port.lock);
1063 if (uap->using_tx_dma) {
1064 /* In theory, this should already be done by pl011_dma_flush_buffer */
1065 dmaengine_terminate_all(uap->dmatx.chan);
1066 if (uap->dmatx.queued) {
1067 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1069 uap->dmatx.queued = false;
1072 kfree(uap->dmatx.buf);
1073 uap->using_tx_dma = false;
1076 if (uap->using_rx_dma) {
1077 dmaengine_terminate_all(uap->dmarx.chan);
1078 /* Clean up the RX DMA */
1079 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1080 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1081 if (uap->dmarx.poll_rate)
1082 del_timer_sync(&uap->dmarx.timer);
1083 uap->using_rx_dma = false;
1087 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1089 return uap->using_rx_dma;
1092 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1094 return uap->using_rx_dma && uap->dmarx.running;
1098 /* Blank functions if the DMA engine is not available */
1099 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1103 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1107 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1111 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1115 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1120 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1124 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1129 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1133 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1137 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1142 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1147 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1152 #define pl011_dma_flush_buffer NULL
1155 static void pl011_stop_tx(struct uart_port *port)
1157 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1159 uap->im &= ~UART011_TXIM;
1160 writew(uap->im, uap->port.membase + UART011_IMSC);
1161 pl011_dma_tx_stop(uap);
1164 static void pl011_start_tx(struct uart_port *port)
1166 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1168 if (!pl011_dma_tx_start(uap)) {
1169 uap->im |= UART011_TXIM;
1170 writew(uap->im, uap->port.membase + UART011_IMSC);
1174 static void pl011_stop_rx(struct uart_port *port)
1176 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1178 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1179 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1180 writew(uap->im, uap->port.membase + UART011_IMSC);
1182 pl011_dma_rx_stop(uap);
1185 static void pl011_enable_ms(struct uart_port *port)
1187 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1189 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1190 writew(uap->im, uap->port.membase + UART011_IMSC);
1193 static void pl011_rx_chars(struct uart_amba_port *uap)
1195 pl011_fifo_to_tty(uap);
1197 spin_unlock(&uap->port.lock);
1198 tty_flip_buffer_push(&uap->port.state->port);
1200 * If we were temporarily out of DMA mode for a while,
1201 * attempt to switch back to DMA mode again.
1203 if (pl011_dma_rx_available(uap)) {
1204 if (pl011_dma_rx_trigger_dma(uap)) {
1205 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1206 "fall back to interrupt mode again\n");
1207 uap->im |= UART011_RXIM;
1209 uap->im &= ~UART011_RXIM;
1210 #ifdef CONFIG_DMA_ENGINE
1211 /* Start Rx DMA poll */
1212 if (uap->dmarx.poll_rate) {
1213 uap->dmarx.last_jiffies = jiffies;
1214 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1215 mod_timer(&uap->dmarx.timer,
1217 msecs_to_jiffies(uap->dmarx.poll_rate));
1222 writew(uap->im, uap->port.membase + UART011_IMSC);
1224 spin_lock(&uap->port.lock);
1227 static void pl011_tx_chars(struct uart_amba_port *uap)
1229 struct circ_buf *xmit = &uap->port.state->xmit;
1232 if (uap->port.x_char) {
1233 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1234 uap->port.icount.tx++;
1235 uap->port.x_char = 0;
1238 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1239 pl011_stop_tx(&uap->port);
1243 /* If we are using DMA mode, try to send some characters. */
1244 if (pl011_dma_tx_irq(uap))
1247 count = uap->fifosize >> 1;
1249 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1250 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1251 uap->port.icount.tx++;
1252 if (uart_circ_empty(xmit))
1254 } while (--count > 0);
1256 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1257 uart_write_wakeup(&uap->port);
1259 if (uart_circ_empty(xmit))
1260 pl011_stop_tx(&uap->port);
1263 static void pl011_modem_status(struct uart_amba_port *uap)
1265 unsigned int status, delta;
1267 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1269 delta = status ^ uap->old_status;
1270 uap->old_status = status;
1275 if (delta & UART01x_FR_DCD)
1276 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1278 if (delta & UART01x_FR_DSR)
1279 uap->port.icount.dsr++;
1281 if (delta & UART01x_FR_CTS)
1282 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1284 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1287 static irqreturn_t pl011_int(int irq, void *dev_id)
1289 struct uart_amba_port *uap = dev_id;
1290 unsigned long flags;
1291 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1293 unsigned int dummy_read;
1295 spin_lock_irqsave(&uap->port.lock, flags);
1296 status = readw(uap->port.membase + UART011_MIS);
1299 if (uap->vendor->cts_event_workaround) {
1300 /* workaround to make sure that all bits are unlocked.. */
1301 writew(0x00, uap->port.membase + UART011_ICR);
1304 * WA: introduce 26ns(1 uart clk) delay before W1C;
1305 * single apb access will incur 2 pclk(133.12Mhz) delay,
1306 * so add 2 dummy reads
1308 dummy_read = readw(uap->port.membase + UART011_ICR);
1309 dummy_read = readw(uap->port.membase + UART011_ICR);
1312 writew(status & ~(UART011_TXIS|UART011_RTIS|
1314 uap->port.membase + UART011_ICR);
1316 if (status & (UART011_RTIS|UART011_RXIS)) {
1317 if (pl011_dma_rx_running(uap))
1318 pl011_dma_rx_irq(uap);
1320 pl011_rx_chars(uap);
1322 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1323 UART011_CTSMIS|UART011_RIMIS))
1324 pl011_modem_status(uap);
1325 if (status & UART011_TXIS)
1326 pl011_tx_chars(uap);
1328 if (pass_counter-- == 0)
1331 status = readw(uap->port.membase + UART011_MIS);
1332 } while (status != 0);
1336 spin_unlock_irqrestore(&uap->port.lock, flags);
1338 return IRQ_RETVAL(handled);
1341 static unsigned int pl011_tx_empty(struct uart_port *port)
1343 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1344 unsigned int status = readw(uap->port.membase + UART01x_FR);
1345 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1348 static unsigned int pl011_get_mctrl(struct uart_port *port)
1350 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1351 unsigned int result = 0;
1352 unsigned int status = readw(uap->port.membase + UART01x_FR);
1354 #define TIOCMBIT(uartbit, tiocmbit) \
1355 if (status & uartbit) \
1358 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1359 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1360 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1361 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1366 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1368 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1371 cr = readw(uap->port.membase + UART011_CR);
1373 #define TIOCMBIT(tiocmbit, uartbit) \
1374 if (mctrl & tiocmbit) \
1379 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1380 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1381 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1382 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1383 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1386 /* We need to disable auto-RTS if we want to turn RTS off */
1387 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1391 writew(cr, uap->port.membase + UART011_CR);
1394 static void pl011_break_ctl(struct uart_port *port, int break_state)
1396 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1397 unsigned long flags;
1400 spin_lock_irqsave(&uap->port.lock, flags);
1401 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1402 if (break_state == -1)
1403 lcr_h |= UART01x_LCRH_BRK;
1405 lcr_h &= ~UART01x_LCRH_BRK;
1406 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1407 spin_unlock_irqrestore(&uap->port.lock, flags);
1410 #ifdef CONFIG_CONSOLE_POLL
1412 static void pl011_quiesce_irqs(struct uart_port *port)
1414 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1415 unsigned char __iomem *regs = uap->port.membase;
1417 writew(readw(regs + UART011_MIS), regs + UART011_ICR);
1419 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1420 * we simply mask it. start_tx() will unmask it.
1422 * Note we can race with start_tx(), and if the race happens, the
1423 * polling user might get another interrupt just after we clear it.
1424 * But it should be OK and can happen even w/o the race, e.g.
1425 * controller immediately got some new data and raised the IRQ.
1427 * And whoever uses polling routines assumes that it manages the device
1428 * (including tx queue), so we're also fine with start_tx()'s caller
1431 writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
1434 static int pl011_get_poll_char(struct uart_port *port)
1436 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1437 unsigned int status;
1440 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1443 pl011_quiesce_irqs(port);
1445 status = readw(uap->port.membase + UART01x_FR);
1446 if (status & UART01x_FR_RXFE)
1447 return NO_POLL_CHAR;
1449 return readw(uap->port.membase + UART01x_DR);
1452 static void pl011_put_poll_char(struct uart_port *port,
1455 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1457 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1460 writew(ch, uap->port.membase + UART01x_DR);
1463 #endif /* CONFIG_CONSOLE_POLL */
1465 static int pl011_hwinit(struct uart_port *port)
1467 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1470 /* Optionaly enable pins to be muxed in and configured */
1471 if (!IS_ERR(uap->pins_default)) {
1472 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1475 "could not set default pins\n");
1479 * Try to enable the clock producer.
1481 retval = clk_prepare_enable(uap->clk);
1485 uap->port.uartclk = clk_get_rate(uap->clk);
1487 /* Clear pending error and receive interrupts */
1488 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1489 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1492 * Save interrupts enable mask, and enable RX interrupts in case if
1493 * the interrupt is used for NMI entry.
1495 uap->im = readw(uap->port.membase + UART011_IMSC);
1496 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1498 if (uap->port.dev->platform_data) {
1499 struct amba_pl011_data *plat;
1501 plat = uap->port.dev->platform_data;
1510 static int pl011_startup(struct uart_port *port)
1512 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1516 retval = pl011_hwinit(port);
1520 writew(uap->im, uap->port.membase + UART011_IMSC);
1525 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1529 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1532 * Provoke TX FIFO interrupt into asserting.
1534 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1535 writew(cr, uap->port.membase + UART011_CR);
1536 writew(0, uap->port.membase + UART011_FBRD);
1537 writew(1, uap->port.membase + UART011_IBRD);
1538 writew(0, uap->port.membase + uap->lcrh_rx);
1539 if (uap->lcrh_tx != uap->lcrh_rx) {
1542 * Wait 10 PCLKs before writing LCRH_TX register,
1543 * to get this delay write read only register 10 times
1545 for (i = 0; i < 10; ++i)
1546 writew(0xff, uap->port.membase + UART011_MIS);
1547 writew(0, uap->port.membase + uap->lcrh_tx);
1549 writew(0, uap->port.membase + UART01x_DR);
1550 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1553 /* restore RTS and DTR */
1554 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1555 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1556 writew(cr, uap->port.membase + UART011_CR);
1559 * initialise the old status of the modem signals
1561 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1564 pl011_dma_startup(uap);
1567 * Finally, enable interrupts, only timeouts when using DMA
1568 * if initial RX DMA job failed, start in interrupt mode
1571 spin_lock_irq(&uap->port.lock);
1572 /* Clear out any spuriously appearing RX interrupts */
1573 writew(UART011_RTIS | UART011_RXIS,
1574 uap->port.membase + UART011_ICR);
1575 uap->im = UART011_RTIM;
1576 if (!pl011_dma_rx_running(uap))
1577 uap->im |= UART011_RXIM;
1578 writew(uap->im, uap->port.membase + UART011_IMSC);
1579 spin_unlock_irq(&uap->port.lock);
1584 clk_disable_unprepare(uap->clk);
1588 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1593 val = readw(uap->port.membase + lcrh);
1594 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1595 writew(val, uap->port.membase + lcrh);
1598 static void pl011_shutdown(struct uart_port *port)
1600 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1605 * disable all interrupts
1607 spin_lock_irq(&uap->port.lock);
1609 writew(uap->im, uap->port.membase + UART011_IMSC);
1610 writew(0xffff, uap->port.membase + UART011_ICR);
1611 spin_unlock_irq(&uap->port.lock);
1613 pl011_dma_shutdown(uap);
1616 * Free the interrupt
1618 free_irq(uap->port.irq, uap);
1622 * disable the port. It should not disable RTS and DTR.
1623 * Also RTS and DTR state should be preserved to restore
1624 * it during startup().
1626 uap->autorts = false;
1627 cr = readw(uap->port.membase + UART011_CR);
1629 cr &= UART011_CR_RTS | UART011_CR_DTR;
1630 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1631 writew(cr, uap->port.membase + UART011_CR);
1634 * disable break condition and fifos
1636 pl011_shutdown_channel(uap, uap->lcrh_rx);
1637 if (uap->lcrh_rx != uap->lcrh_tx)
1638 pl011_shutdown_channel(uap, uap->lcrh_tx);
1641 * Shut down the clock producer
1643 clk_disable_unprepare(uap->clk);
1644 /* Optionally let pins go into sleep states */
1645 if (!IS_ERR(uap->pins_sleep)) {
1646 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1649 "could not set pins to sleep state\n");
1653 if (uap->port.dev->platform_data) {
1654 struct amba_pl011_data *plat;
1656 plat = uap->port.dev->platform_data;
1664 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1665 struct ktermios *old)
1667 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1668 unsigned int lcr_h, old_cr;
1669 unsigned long flags;
1670 unsigned int baud, quot, clkdiv;
1672 if (uap->vendor->oversampling)
1678 * Ask the core to calculate the divisor for us.
1680 baud = uart_get_baud_rate(port, termios, old, 0,
1681 port->uartclk / clkdiv);
1682 #ifdef CONFIG_DMA_ENGINE
1684 * Adjust RX DMA polling rate with baud rate if not specified.
1686 if (uap->dmarx.auto_poll_rate)
1687 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1690 if (baud > port->uartclk/16)
1691 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1693 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1695 switch (termios->c_cflag & CSIZE) {
1697 lcr_h = UART01x_LCRH_WLEN_5;
1700 lcr_h = UART01x_LCRH_WLEN_6;
1703 lcr_h = UART01x_LCRH_WLEN_7;
1706 lcr_h = UART01x_LCRH_WLEN_8;
1709 if (termios->c_cflag & CSTOPB)
1710 lcr_h |= UART01x_LCRH_STP2;
1711 if (termios->c_cflag & PARENB) {
1712 lcr_h |= UART01x_LCRH_PEN;
1713 if (!(termios->c_cflag & PARODD))
1714 lcr_h |= UART01x_LCRH_EPS;
1716 if (uap->fifosize > 1)
1717 lcr_h |= UART01x_LCRH_FEN;
1719 spin_lock_irqsave(&port->lock, flags);
1722 * Update the per-port timeout.
1724 uart_update_timeout(port, termios->c_cflag, baud);
1726 port->read_status_mask = UART011_DR_OE | 255;
1727 if (termios->c_iflag & INPCK)
1728 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1729 if (termios->c_iflag & (BRKINT | PARMRK))
1730 port->read_status_mask |= UART011_DR_BE;
1733 * Characters to ignore
1735 port->ignore_status_mask = 0;
1736 if (termios->c_iflag & IGNPAR)
1737 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1738 if (termios->c_iflag & IGNBRK) {
1739 port->ignore_status_mask |= UART011_DR_BE;
1741 * If we're ignoring parity and break indicators,
1742 * ignore overruns too (for real raw support).
1744 if (termios->c_iflag & IGNPAR)
1745 port->ignore_status_mask |= UART011_DR_OE;
1749 * Ignore all characters if CREAD is not set.
1751 if ((termios->c_cflag & CREAD) == 0)
1752 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1754 if (UART_ENABLE_MS(port, termios->c_cflag))
1755 pl011_enable_ms(port);
1757 /* first, disable everything */
1758 old_cr = readw(port->membase + UART011_CR);
1759 writew(0, port->membase + UART011_CR);
1761 if (termios->c_cflag & CRTSCTS) {
1762 if (old_cr & UART011_CR_RTS)
1763 old_cr |= UART011_CR_RTSEN;
1765 old_cr |= UART011_CR_CTSEN;
1766 uap->autorts = true;
1768 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1769 uap->autorts = false;
1772 if (uap->vendor->oversampling) {
1773 if (baud > port->uartclk / 16)
1774 old_cr |= ST_UART011_CR_OVSFACT;
1776 old_cr &= ~ST_UART011_CR_OVSFACT;
1780 * Workaround for the ST Micro oversampling variants to
1781 * increase the bitrate slightly, by lowering the divisor,
1782 * to avoid delayed sampling of start bit at high speeds,
1783 * else we see data corruption.
1785 if (uap->vendor->oversampling) {
1786 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1788 else if ((baud > 3250000) && (quot > 2))
1792 writew(quot & 0x3f, port->membase + UART011_FBRD);
1793 writew(quot >> 6, port->membase + UART011_IBRD);
1796 * ----------v----------v----------v----------v-----
1797 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1798 * UART011_FBRD & UART011_IBRD.
1799 * ----------^----------^----------^----------^-----
1801 writew(lcr_h, port->membase + uap->lcrh_rx);
1802 if (uap->lcrh_rx != uap->lcrh_tx) {
1805 * Wait 10 PCLKs before writing LCRH_TX register,
1806 * to get this delay write read only register 10 times
1808 for (i = 0; i < 10; ++i)
1809 writew(0xff, uap->port.membase + UART011_MIS);
1810 writew(lcr_h, port->membase + uap->lcrh_tx);
1812 writew(old_cr, port->membase + UART011_CR);
1814 spin_unlock_irqrestore(&port->lock, flags);
1817 static const char *pl011_type(struct uart_port *port)
1819 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1820 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1824 * Release the memory region(s) being used by 'port'
1826 static void pl011_release_port(struct uart_port *port)
1828 release_mem_region(port->mapbase, SZ_4K);
1832 * Request the memory region(s) being used by 'port'
1834 static int pl011_request_port(struct uart_port *port)
1836 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1837 != NULL ? 0 : -EBUSY;
1841 * Configure/autoconfigure the port.
1843 static void pl011_config_port(struct uart_port *port, int flags)
1845 if (flags & UART_CONFIG_TYPE) {
1846 port->type = PORT_AMBA;
1847 pl011_request_port(port);
1852 * verify the new serial_struct (for TIOCSSERIAL).
1854 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1857 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1859 if (ser->irq < 0 || ser->irq >= nr_irqs)
1861 if (ser->baud_base < 9600)
1866 static struct uart_ops amba_pl011_pops = {
1867 .tx_empty = pl011_tx_empty,
1868 .set_mctrl = pl011_set_mctrl,
1869 .get_mctrl = pl011_get_mctrl,
1870 .stop_tx = pl011_stop_tx,
1871 .start_tx = pl011_start_tx,
1872 .stop_rx = pl011_stop_rx,
1873 .enable_ms = pl011_enable_ms,
1874 .break_ctl = pl011_break_ctl,
1875 .startup = pl011_startup,
1876 .shutdown = pl011_shutdown,
1877 .flush_buffer = pl011_dma_flush_buffer,
1878 .set_termios = pl011_set_termios,
1880 .release_port = pl011_release_port,
1881 .request_port = pl011_request_port,
1882 .config_port = pl011_config_port,
1883 .verify_port = pl011_verify_port,
1884 #ifdef CONFIG_CONSOLE_POLL
1885 .poll_init = pl011_hwinit,
1886 .poll_get_char = pl011_get_poll_char,
1887 .poll_put_char = pl011_put_poll_char,
1891 static struct uart_amba_port *amba_ports[UART_NR];
1893 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1895 static void pl011_console_putchar(struct uart_port *port, int ch)
1897 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1899 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1901 writew(ch, uap->port.membase + UART01x_DR);
1905 pl011_console_write(struct console *co, const char *s, unsigned int count)
1907 struct uart_amba_port *uap = amba_ports[co->index];
1908 unsigned int status, old_cr, new_cr;
1909 unsigned long flags;
1912 clk_enable(uap->clk);
1914 local_irq_save(flags);
1915 if (uap->port.sysrq)
1917 else if (oops_in_progress)
1918 locked = spin_trylock(&uap->port.lock);
1920 spin_lock(&uap->port.lock);
1923 * First save the CR then disable the interrupts
1925 old_cr = readw(uap->port.membase + UART011_CR);
1926 new_cr = old_cr & ~UART011_CR_CTSEN;
1927 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1928 writew(new_cr, uap->port.membase + UART011_CR);
1930 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1933 * Finally, wait for transmitter to become empty
1934 * and restore the TCR
1937 status = readw(uap->port.membase + UART01x_FR);
1938 } while (status & UART01x_FR_BUSY);
1939 writew(old_cr, uap->port.membase + UART011_CR);
1942 spin_unlock(&uap->port.lock);
1943 local_irq_restore(flags);
1945 clk_disable(uap->clk);
1949 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1950 int *parity, int *bits)
1952 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1953 unsigned int lcr_h, ibrd, fbrd;
1955 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1958 if (lcr_h & UART01x_LCRH_PEN) {
1959 if (lcr_h & UART01x_LCRH_EPS)
1965 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1970 ibrd = readw(uap->port.membase + UART011_IBRD);
1971 fbrd = readw(uap->port.membase + UART011_FBRD);
1973 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1975 if (uap->vendor->oversampling) {
1976 if (readw(uap->port.membase + UART011_CR)
1977 & ST_UART011_CR_OVSFACT)
1983 static int __init pl011_console_setup(struct console *co, char *options)
1985 struct uart_amba_port *uap;
1993 * Check whether an invalid uart number has been specified, and
1994 * if so, search for the first available port that does have
1997 if (co->index >= UART_NR)
1999 uap = amba_ports[co->index];
2003 /* Allow pins to be muxed in and configured */
2004 if (!IS_ERR(uap->pins_default)) {
2005 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
2007 dev_err(uap->port.dev,
2008 "could not set default pins\n");
2011 ret = clk_prepare(uap->clk);
2015 if (uap->port.dev->platform_data) {
2016 struct amba_pl011_data *plat;
2018 plat = uap->port.dev->platform_data;
2023 uap->port.uartclk = clk_get_rate(uap->clk);
2026 uart_parse_options(options, &baud, &parity, &bits, &flow);
2028 pl011_console_get_options(uap, &baud, &parity, &bits);
2030 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2033 static struct uart_driver amba_reg;
2034 static struct console amba_console = {
2036 .write = pl011_console_write,
2037 .device = uart_console_device,
2038 .setup = pl011_console_setup,
2039 .flags = CON_PRINTBUFFER,
2044 #define AMBA_CONSOLE (&amba_console)
2046 #define AMBA_CONSOLE NULL
2049 static struct uart_driver amba_reg = {
2050 .owner = THIS_MODULE,
2051 .driver_name = "ttyAMA",
2052 .dev_name = "ttyAMA",
2053 .major = SERIAL_AMBA_MAJOR,
2054 .minor = SERIAL_AMBA_MINOR,
2056 .cons = AMBA_CONSOLE,
2059 static int pl011_probe_dt_alias(int index, struct device *dev)
2061 struct device_node *np;
2062 static bool seen_dev_with_alias = false;
2063 static bool seen_dev_without_alias = false;
2066 if (!IS_ENABLED(CONFIG_OF))
2073 ret = of_alias_get_id(np, "serial");
2074 if (IS_ERR_VALUE(ret)) {
2075 seen_dev_without_alias = true;
2078 seen_dev_with_alias = true;
2079 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2080 dev_warn(dev, "requested serial port %d not available.\n", ret);
2085 if (seen_dev_with_alias && seen_dev_without_alias)
2086 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2091 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2093 struct uart_amba_port *uap;
2094 struct vendor_data *vendor = id->data;
2098 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2099 if (amba_ports[i] == NULL)
2102 if (i == ARRAY_SIZE(amba_ports)) {
2107 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2114 i = pl011_probe_dt_alias(i, &dev->dev);
2116 base = devm_ioremap(&dev->dev, dev->res.start,
2117 resource_size(&dev->res));
2123 uap->pinctrl = devm_pinctrl_get(&dev->dev);
2124 if (IS_ERR(uap->pinctrl)) {
2125 ret = PTR_ERR(uap->pinctrl);
2128 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
2129 PINCTRL_STATE_DEFAULT);
2130 if (IS_ERR(uap->pins_default))
2131 dev_err(&dev->dev, "could not get default pinstate\n");
2133 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
2134 PINCTRL_STATE_SLEEP);
2135 if (IS_ERR(uap->pins_sleep))
2136 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
2138 uap->clk = devm_clk_get(&dev->dev, NULL);
2139 if (IS_ERR(uap->clk)) {
2140 ret = PTR_ERR(uap->clk);
2144 uap->vendor = vendor;
2145 uap->lcrh_rx = vendor->lcrh_rx;
2146 uap->lcrh_tx = vendor->lcrh_tx;
2148 uap->fifosize = vendor->get_fifosize(dev->periphid);
2149 uap->port.dev = &dev->dev;
2150 uap->port.mapbase = dev->res.start;
2151 uap->port.membase = base;
2152 uap->port.iotype = UPIO_MEM;
2153 uap->port.irq = dev->irq[0];
2154 uap->port.fifosize = uap->fifosize;
2155 uap->port.ops = &amba_pl011_pops;
2156 uap->port.flags = UPF_BOOT_AUTOCONF;
2158 pl011_dma_probe(uap);
2160 /* Ensure interrupts from this UART are masked and cleared */
2161 writew(0, uap->port.membase + UART011_IMSC);
2162 writew(0xffff, uap->port.membase + UART011_ICR);
2164 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2166 amba_ports[i] = uap;
2168 amba_set_drvdata(dev, uap);
2169 ret = uart_add_one_port(&amba_reg, &uap->port);
2171 amba_set_drvdata(dev, NULL);
2172 amba_ports[i] = NULL;
2173 pl011_dma_remove(uap);
2179 static int pl011_remove(struct amba_device *dev)
2181 struct uart_amba_port *uap = amba_get_drvdata(dev);
2184 amba_set_drvdata(dev, NULL);
2186 uart_remove_one_port(&amba_reg, &uap->port);
2188 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2189 if (amba_ports[i] == uap)
2190 amba_ports[i] = NULL;
2192 pl011_dma_remove(uap);
2197 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2199 struct uart_amba_port *uap = amba_get_drvdata(dev);
2204 return uart_suspend_port(&amba_reg, &uap->port);
2207 static int pl011_resume(struct amba_device *dev)
2209 struct uart_amba_port *uap = amba_get_drvdata(dev);
2214 return uart_resume_port(&amba_reg, &uap->port);
2218 static struct amba_id pl011_ids[] = {
2222 .data = &vendor_arm,
2232 MODULE_DEVICE_TABLE(amba, pl011_ids);
2234 static struct amba_driver pl011_driver = {
2236 .name = "uart-pl011",
2238 .id_table = pl011_ids,
2239 .probe = pl011_probe,
2240 .remove = pl011_remove,
2242 .suspend = pl011_suspend,
2243 .resume = pl011_resume,
2247 static int __init pl011_init(void)
2250 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2252 ret = uart_register_driver(&amba_reg);
2254 ret = amba_driver_register(&pl011_driver);
2256 uart_unregister_driver(&amba_reg);
2261 static void __exit pl011_exit(void)
2263 amba_driver_unregister(&pl011_driver);
2264 uart_unregister_driver(&amba_reg);
2268 * While this can be a module, if builtin it's most likely the console
2269 * So let's leave module_exit but move module_init to an earlier place
2271 arch_initcall(pl011_init);
2272 module_exit(pl011_exit);
2274 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2275 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2276 MODULE_LICENSE("GPL");