1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/console.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/sysrq.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/tty.h>
25 #include <linux/ratelimit.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/nmi.h>
30 #include <linux/mutex.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/ktime.h>
41 /* Nuvoton NPCM timeout register */
42 #define UART_NPCM_TOR 7
43 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
49 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
51 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 * Here we define the default xmit fifo size used for each type of UART.
57 static const struct serial8250_config uart_config[] = {
82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 .rxtrig_bytes = {1, 4, 8, 14},
84 .flags = UART_CAP_FIFO,
95 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 .rxtrig_bytes = {8, 16, 24, 28},
104 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 .rxtrig_bytes = {1, 16, 32, 56},
113 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
121 .name = "16C950/954",
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
125 .rxtrig_bytes = {16, 32, 112, 120},
126 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
133 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
135 .rxtrig_bytes = {8, 16, 56, 60},
136 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
142 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 .flags = UART_CAP_FIFO,
156 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 .flags = UART_CAP_FIFO | UART_NATSEMI,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 .flags = UART_CAP_FIFO,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 .flags = UART_CAP_FIFO | UART_CAP_AFE,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 .rxtrig_bytes = {1, 4, 8, 14},
194 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
208 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
210 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
217 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO,
221 [PORT_BRCM_TRUMANAGE] = {
225 .flags = UART_CAP_HFIFO,
230 [PORT_ALTR_16550_F32] = {
231 .name = "Altera 16550 FIFO32",
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 .rxtrig_bytes = {1, 8, 16, 30},
236 .flags = UART_CAP_FIFO | UART_CAP_AFE,
238 [PORT_ALTR_16550_F64] = {
239 .name = "Altera 16550 FIFO64",
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .rxtrig_bytes = {1, 16, 32, 62},
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .rxtrig_bytes = {1, 32, 64, 126},
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
268 .name = "Palmchip BK-3103",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
276 .name = "TI DA8xx/66AK2x",
279 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
281 .rxtrig_bytes = {1, 4, 8, 14},
282 .flags = UART_CAP_FIFO | UART_CAP_AFE,
285 .name = "MediaTek BTIF",
288 .fcr = UART_FCR_ENABLE_FIFO |
289 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 .flags = UART_CAP_FIFO,
293 .name = "Nuvoton 16550",
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 .rxtrig_bytes = {1, 4, 8, 14},
299 .flags = UART_CAP_FIFO,
305 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 .rxtrig_bytes = {1, 32, 64, 112},
307 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
309 [PORT_ASPEED_VUART] = {
310 .name = "ASPEED VUART",
313 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
314 .rxtrig_bytes = {1, 4, 8, 14},
315 .flags = UART_CAP_FIFO,
317 [PORT_MCHP16550A] = {
318 .name = "MCHP16550A",
321 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
322 .rxtrig_bytes = {2, 66, 130, 194},
323 .flags = UART_CAP_FIFO,
326 .name = "Broadcom BCM7271 UART",
329 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
330 .rxtrig_bytes = {1, 8, 16, 30},
331 .flags = UART_CAP_FIFO | UART_CAP_AFE,
335 /* Uart divisor latch read */
336 static u32 default_serial_dl_read(struct uart_8250_port *up)
338 /* Assign these in pieces to truncate any bits above 7. */
339 unsigned char dll = serial_in(up, UART_DLL);
340 unsigned char dlm = serial_in(up, UART_DLM);
342 return dll | dlm << 8;
345 /* Uart divisor latch write */
346 static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
348 serial_out(up, UART_DLL, value & 0xff);
349 serial_out(up, UART_DLM, value >> 8 & 0xff);
352 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
354 offset = offset << p->regshift;
355 outb(p->hub6 - 1 + offset, p->iobase);
356 return inb(p->iobase + 1);
359 static void hub6_serial_out(struct uart_port *p, int offset, int value)
361 offset = offset << p->regshift;
362 outb(p->hub6 - 1 + offset, p->iobase);
363 outb(value, p->iobase + 1);
366 static unsigned int mem_serial_in(struct uart_port *p, int offset)
368 offset = offset << p->regshift;
369 return readb(p->membase + offset);
372 static void mem_serial_out(struct uart_port *p, int offset, int value)
374 offset = offset << p->regshift;
375 writeb(value, p->membase + offset);
378 static void mem16_serial_out(struct uart_port *p, int offset, int value)
380 offset = offset << p->regshift;
381 writew(value, p->membase + offset);
384 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
386 offset = offset << p->regshift;
387 return readw(p->membase + offset);
390 static void mem32_serial_out(struct uart_port *p, int offset, int value)
392 offset = offset << p->regshift;
393 writel(value, p->membase + offset);
396 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
398 offset = offset << p->regshift;
399 return readl(p->membase + offset);
402 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 iowrite32be(value, p->membase + offset);
408 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
410 offset = offset << p->regshift;
411 return ioread32be(p->membase + offset);
414 static unsigned int io_serial_in(struct uart_port *p, int offset)
416 offset = offset << p->regshift;
417 return inb(p->iobase + offset);
420 static void io_serial_out(struct uart_port *p, int offset, int value)
422 offset = offset << p->regshift;
423 outb(value, p->iobase + offset);
426 static int serial8250_default_handle_irq(struct uart_port *port);
428 static void set_io_from_upio(struct uart_port *p)
430 struct uart_8250_port *up = up_to_u8250p(p);
432 up->dl_read = default_serial_dl_read;
433 up->dl_write = default_serial_dl_write;
437 p->serial_in = hub6_serial_in;
438 p->serial_out = hub6_serial_out;
442 p->serial_in = mem_serial_in;
443 p->serial_out = mem_serial_out;
447 p->serial_in = mem16_serial_in;
448 p->serial_out = mem16_serial_out;
452 p->serial_in = mem32_serial_in;
453 p->serial_out = mem32_serial_out;
457 p->serial_in = mem32be_serial_in;
458 p->serial_out = mem32be_serial_out;
462 p->serial_in = io_serial_in;
463 p->serial_out = io_serial_out;
466 /* Remember loaded iotype */
467 up->cur_iotype = p->iotype;
468 p->handle_irq = serial8250_default_handle_irq;
472 serial_port_out_sync(struct uart_port *p, int offset, int value)
480 p->serial_out(p, offset, value);
481 p->serial_in(p, UART_LCR); /* safe, no side-effects */
484 p->serial_out(p, offset, value);
491 static void serial8250_clear_fifos(struct uart_8250_port *p)
493 if (p->capabilities & UART_CAP_FIFO) {
494 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
495 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
496 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
497 serial_out(p, UART_FCR, 0);
501 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
502 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
504 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
506 serial8250_clear_fifos(p);
507 serial_out(p, UART_FCR, p->fcr);
509 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
511 void serial8250_rpm_get(struct uart_8250_port *p)
513 if (!(p->capabilities & UART_CAP_RPM))
515 pm_runtime_get_sync(p->port.dev);
517 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
519 void serial8250_rpm_put(struct uart_8250_port *p)
521 if (!(p->capabilities & UART_CAP_RPM))
523 pm_runtime_mark_last_busy(p->port.dev);
524 pm_runtime_put_autosuspend(p->port.dev);
526 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
529 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
530 * @p: uart_8250_port port instance
532 * The function is used to start rs485 software emulating on the
533 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
534 * transmission. The function is idempotent, so it is safe to call it
537 * The caller MUST enable interrupt on empty shift register before
538 * calling serial8250_em485_init(). This interrupt is not a part of
539 * 8250 standard, but implementation defined.
541 * The function is supposed to be called from .rs485_config callback
542 * or from any other callback protected with p->port.lock spinlock.
544 * See also serial8250_em485_destroy()
546 * Return 0 - success, -errno - otherwise
548 static int serial8250_em485_init(struct uart_8250_port *p)
550 /* Port locked to synchronize UART_IER access against the console. */
551 lockdep_assert_held_once(&p->port.lock);
556 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
560 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
562 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
564 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
565 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
567 p->em485->active_timer = NULL;
568 p->em485->tx_stopped = true;
571 if (p->em485->tx_stopped)
578 * serial8250_em485_destroy() - put uart_8250_port into normal state
579 * @p: uart_8250_port port instance
581 * The function is used to stop rs485 software emulating on the
582 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
583 * call it multiple times.
585 * The function is supposed to be called from .rs485_config callback
586 * or from any other callback protected with p->port.lock spinlock.
588 * See also serial8250_em485_init()
590 void serial8250_em485_destroy(struct uart_8250_port *p)
595 hrtimer_cancel(&p->em485->start_tx_timer);
596 hrtimer_cancel(&p->em485->stop_tx_timer);
601 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
603 struct serial_rs485 serial8250_em485_supported = {
604 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
605 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
606 .delay_rts_before_send = 1,
607 .delay_rts_after_send = 1,
609 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
612 * serial8250_em485_config() - generic ->rs485_config() callback
614 * @termios: termios structure
615 * @rs485: rs485 settings
617 * Generic callback usable by 8250 uart drivers to activate rs485 settings
618 * if the uart is incapable of driving RTS as a Transmit Enable signal in
619 * hardware, relying on software emulation instead.
621 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
622 struct serial_rs485 *rs485)
624 struct uart_8250_port *up = up_to_u8250p(port);
626 /* pick sane settings if the user hasn't */
627 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
628 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
629 rs485->flags |= SER_RS485_RTS_ON_SEND;
630 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
634 * Both serial8250_em485_init() and serial8250_em485_destroy()
637 if (rs485->flags & SER_RS485_ENABLED)
638 return serial8250_em485_init(up);
640 serial8250_em485_destroy(up);
643 EXPORT_SYMBOL_GPL(serial8250_em485_config);
646 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
647 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
648 * empty and the HW can idle again.
650 void serial8250_rpm_get_tx(struct uart_8250_port *p)
652 unsigned char rpm_active;
654 if (!(p->capabilities & UART_CAP_RPM))
657 rpm_active = xchg(&p->rpm_tx_active, 1);
660 pm_runtime_get_sync(p->port.dev);
662 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
664 void serial8250_rpm_put_tx(struct uart_8250_port *p)
666 unsigned char rpm_active;
668 if (!(p->capabilities & UART_CAP_RPM))
671 rpm_active = xchg(&p->rpm_tx_active, 0);
674 pm_runtime_mark_last_busy(p->port.dev);
675 pm_runtime_put_autosuspend(p->port.dev);
677 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
680 * IER sleep support. UARTs which have EFRs need the "extended
681 * capability" bit enabled. Note that on XR16C850s, we need to
682 * reset LCR to write to IER.
684 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
686 unsigned char lcr = 0, efr = 0;
688 serial8250_rpm_get(p);
690 if (p->capabilities & UART_CAP_SLEEP) {
691 /* Synchronize UART_IER access against the console. */
692 spin_lock_irq(&p->port.lock);
693 if (p->capabilities & UART_CAP_EFR) {
694 lcr = serial_in(p, UART_LCR);
695 efr = serial_in(p, UART_EFR);
696 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 serial_out(p, UART_EFR, UART_EFR_ECB);
698 serial_out(p, UART_LCR, 0);
700 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
701 if (p->capabilities & UART_CAP_EFR) {
702 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
703 serial_out(p, UART_EFR, efr);
704 serial_out(p, UART_LCR, lcr);
706 spin_unlock_irq(&p->port.lock);
709 serial8250_rpm_put(p);
712 static void serial8250_clear_IER(struct uart_8250_port *up)
714 if (up->capabilities & UART_CAP_UUE)
715 serial_out(up, UART_IER, UART_IER_UUE);
717 serial_out(up, UART_IER, 0);
720 #ifdef CONFIG_SERIAL_8250_RSA
722 * Attempts to turn on the RSA FIFO. Returns zero on failure.
723 * We set the port uart clock rate if we succeed.
725 static int __enable_rsa(struct uart_8250_port *up)
730 mode = serial_in(up, UART_RSA_MSR);
731 result = mode & UART_RSA_MSR_FIFO;
734 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
735 mode = serial_in(up, UART_RSA_MSR);
736 result = mode & UART_RSA_MSR_FIFO;
740 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
745 static void enable_rsa(struct uart_8250_port *up)
747 if (up->port.type == PORT_RSA) {
748 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
749 spin_lock_irq(&up->port.lock);
751 spin_unlock_irq(&up->port.lock);
753 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
754 serial_out(up, UART_RSA_FRR, 0);
759 * Attempts to turn off the RSA FIFO. Returns zero on failure.
760 * It is unknown why interrupts were disabled in here. However,
761 * the caller is expected to preserve this behaviour by grabbing
762 * the spinlock before calling this function.
764 static void disable_rsa(struct uart_8250_port *up)
769 if (up->port.type == PORT_RSA &&
770 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
771 spin_lock_irq(&up->port.lock);
773 mode = serial_in(up, UART_RSA_MSR);
774 result = !(mode & UART_RSA_MSR_FIFO);
777 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
778 mode = serial_in(up, UART_RSA_MSR);
779 result = !(mode & UART_RSA_MSR_FIFO);
783 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
784 spin_unlock_irq(&up->port.lock);
787 #endif /* CONFIG_SERIAL_8250_RSA */
790 * This is a quickie test to see how big the FIFO is.
791 * It doesn't work at all the time, more's the pity.
793 static int size_fifo(struct uart_8250_port *up)
795 unsigned char old_fcr, old_mcr, old_lcr;
799 old_lcr = serial_in(up, UART_LCR);
800 serial_out(up, UART_LCR, 0);
801 old_fcr = serial_in(up, UART_FCR);
802 old_mcr = serial8250_in_MCR(up);
803 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
804 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
805 serial8250_out_MCR(up, UART_MCR_LOOP);
806 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
807 old_dl = serial_dl_read(up);
808 serial_dl_write(up, 0x0001);
809 serial_out(up, UART_LCR, UART_LCR_WLEN8);
810 for (count = 0; count < 256; count++)
811 serial_out(up, UART_TX, count);
812 mdelay(20);/* FIXME - schedule_timeout */
813 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
814 (count < 256); count++)
815 serial_in(up, UART_RX);
816 serial_out(up, UART_FCR, old_fcr);
817 serial8250_out_MCR(up, old_mcr);
818 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
819 serial_dl_write(up, old_dl);
820 serial_out(up, UART_LCR, old_lcr);
826 * Read UART ID using the divisor method - set DLL and DLM to zero
827 * and the revision will be in DLL and device type in DLM. We
828 * preserve the device state across this.
830 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
832 unsigned char old_lcr;
833 unsigned int id, old_dl;
835 old_lcr = serial_in(p, UART_LCR);
836 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
837 old_dl = serial_dl_read(p);
838 serial_dl_write(p, 0);
839 id = serial_dl_read(p);
840 serial_dl_write(p, old_dl);
842 serial_out(p, UART_LCR, old_lcr);
848 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
849 * When this function is called we know it is at least a StarTech
850 * 16650 V2, but it might be one of several StarTech UARTs, or one of
851 * its clones. (We treat the broken original StarTech 16650 V1 as a
852 * 16550, and why not? Startech doesn't seem to even acknowledge its
855 * What evil have men's minds wrought...
857 static void autoconfig_has_efr(struct uart_8250_port *up)
859 unsigned int id1, id2, id3, rev;
862 * Everything with an EFR has SLEEP
864 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
867 * First we check to see if it's an Oxford Semiconductor UART.
869 * If we have to do this here because some non-National
870 * Semiconductor clone chips lock up if you try writing to the
871 * LSR register (which serial_icr_read does)
875 * Check for Oxford Semiconductor 16C950.
877 * EFR [4] must be set else this test fails.
879 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
880 * claims that it's needed for 952 dual UART's (which are not
881 * recommended for new designs).
884 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
885 serial_out(up, UART_EFR, UART_EFR_ECB);
886 serial_out(up, UART_LCR, 0x00);
887 id1 = serial_icr_read(up, UART_ID1);
888 id2 = serial_icr_read(up, UART_ID2);
889 id3 = serial_icr_read(up, UART_ID3);
890 rev = serial_icr_read(up, UART_REV);
892 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
894 if (id1 == 0x16 && id2 == 0xC9 &&
895 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
896 up->port.type = PORT_16C950;
899 * Enable work around for the Oxford Semiconductor 952 rev B
900 * chip which causes it to seriously miscalculate baud rates
903 if (id3 == 0x52 && rev == 0x01)
904 up->bugs |= UART_BUG_QUOT;
909 * We check for a XR16C850 by setting DLL and DLM to 0, and then
910 * reading back DLL and DLM. The chip type depends on the DLM
912 * 0x10 - XR16C850 and the DLL contains the chip revision.
916 id1 = autoconfig_read_divisor_id(up);
917 DEBUG_AUTOCONF("850id=%04x ", id1);
920 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
921 up->port.type = PORT_16850;
926 * It wasn't an XR16C850.
928 * We distinguish between the '654 and the '650 by counting
929 * how many bytes are in the FIFO. I'm using this for now,
930 * since that's the technique that was sent to me in the
931 * serial driver update, but I'm not convinced this works.
932 * I've had problems doing this in the past. -TYT
934 if (size_fifo(up) == 64)
935 up->port.type = PORT_16654;
937 up->port.type = PORT_16650V2;
941 * We detected a chip without a FIFO. Only two fall into
942 * this category - the original 8250 and the 16450. The
943 * 16450 has a scratch register (accessible with LCR=0)
945 static void autoconfig_8250(struct uart_8250_port *up)
947 unsigned char scratch, status1, status2;
949 up->port.type = PORT_8250;
951 scratch = serial_in(up, UART_SCR);
952 serial_out(up, UART_SCR, 0xa5);
953 status1 = serial_in(up, UART_SCR);
954 serial_out(up, UART_SCR, 0x5a);
955 status2 = serial_in(up, UART_SCR);
956 serial_out(up, UART_SCR, scratch);
958 if (status1 == 0xa5 && status2 == 0x5a)
959 up->port.type = PORT_16450;
962 static int broken_efr(struct uart_8250_port *up)
965 * Exar ST16C2550 "A2" devices incorrectly detect as
966 * having an EFR, and report an ID of 0x0201. See
967 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
969 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
976 * We know that the chip has FIFOs. Does it have an EFR? The
977 * EFR is located in the same register position as the IIR and
978 * we know the top two bits of the IIR are currently set. The
979 * EFR should contain zero. Try to read the EFR.
981 static void autoconfig_16550a(struct uart_8250_port *up)
983 unsigned char status1, status2;
984 unsigned int iersave;
986 /* Port locked to synchronize UART_IER access against the console. */
987 lockdep_assert_held_once(&up->port.lock);
989 up->port.type = PORT_16550A;
990 up->capabilities |= UART_CAP_FIFO;
992 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
993 !(up->port.flags & UPF_FULL_PROBE))
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (serial_in(up, UART_EFR) == 0) {
1002 serial_out(up, UART_EFR, 0xA8);
1003 if (serial_in(up, UART_EFR) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up->port.type = PORT_16650;
1006 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1008 serial_out(up, UART_LCR, 0);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1011 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
1012 UART_IIR_FIFO_ENABLED);
1013 serial_out(up, UART_FCR, 0);
1014 serial_out(up, UART_LCR, 0);
1016 if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
1017 up->port.type = PORT_16550A_FSL64;
1019 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1021 serial_out(up, UART_EFR, 0);
1026 * Maybe it requires 0xbf to be written to the LCR.
1027 * (other ST16C650V2 UARTs, TI16C752A, etc)
1029 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1031 DEBUG_AUTOCONF("EFRv2 ");
1032 autoconfig_has_efr(up);
1037 * Check for a National Semiconductor SuperIO chip.
1038 * Attempt to switch to bank 2, read the value of the LOOP bit
1039 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1040 * switch back to bank 2, read it from EXCR1 again and check
1041 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1043 serial_out(up, UART_LCR, 0);
1044 status1 = serial8250_in_MCR(up);
1045 serial_out(up, UART_LCR, 0xE0);
1046 status2 = serial_in(up, 0x02); /* EXCR1 */
1048 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1049 serial_out(up, UART_LCR, 0);
1050 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1051 serial_out(up, UART_LCR, 0xE0);
1052 status2 = serial_in(up, 0x02); /* EXCR1 */
1053 serial_out(up, UART_LCR, 0);
1054 serial8250_out_MCR(up, status1);
1056 if ((status2 ^ status1) & UART_MCR_LOOP) {
1057 unsigned short quot;
1059 serial_out(up, UART_LCR, 0xE0);
1061 quot = serial_dl_read(up);
1064 if (ns16550a_goto_highspeed(up))
1065 serial_dl_write(up, quot);
1067 serial_out(up, UART_LCR, 0);
1069 up->port.uartclk = 921600*16;
1070 up->port.type = PORT_NS16550A;
1071 up->capabilities |= UART_NATSEMI;
1077 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1078 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1079 * Try setting it with and without DLAB set. Cheap clones
1080 * set bit 5 without DLAB set.
1082 serial_out(up, UART_LCR, 0);
1083 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1084 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1085 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1087 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1089 status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1090 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1092 serial_out(up, UART_LCR, 0);
1094 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1096 if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1097 status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
1098 up->port.type = PORT_16750;
1099 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1104 * Try writing and reading the UART_IER_UUE bit (b6).
1105 * If it works, this is probably one of the Xscale platform's
1107 * We're going to explicitly set the UUE bit to 0 before
1108 * trying to write and read a 1 just to make sure it's not
1109 * already a 1 and maybe locked there before we even start.
1111 iersave = serial_in(up, UART_IER);
1112 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1113 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1115 * OK it's in a known zero state, try writing and reading
1116 * without disturbing the current state of the other bits.
1118 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1119 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1122 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1124 DEBUG_AUTOCONF("Xscale ");
1125 up->port.type = PORT_XSCALE;
1126 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1131 * If we got here we couldn't force the IER_UUE bit to 0.
1132 * Log it and continue.
1134 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1136 serial_out(up, UART_IER, iersave);
1139 * We distinguish between 16550A and U6 16550A by counting
1140 * how many bytes are in the FIFO.
1142 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1143 up->port.type = PORT_U6_16550A;
1144 up->capabilities |= UART_CAP_AFE;
1149 * This routine is called by rs_init() to initialize a specific serial
1150 * port. It determines what type of UART chip this serial port is
1151 * using: 8250, 16450, 16550, 16550A. The important question is
1152 * whether or not this UART is a 16550A or not, since this will
1153 * determine whether or not we can use its FIFO features or not.
1155 static void autoconfig(struct uart_8250_port *up)
1157 unsigned char status1, scratch, scratch2, scratch3;
1158 unsigned char save_lcr, save_mcr;
1159 struct uart_port *port = &up->port;
1160 unsigned long flags;
1161 unsigned int old_capabilities;
1163 if (!port->iobase && !port->mapbase && !port->membase)
1166 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1167 port->name, port->iobase, port->membase);
1170 * We really do need global IRQs disabled here - we're going to
1171 * be frobbing the chips IRQ enable register to see if it exists.
1173 * Synchronize UART_IER access against the console.
1175 spin_lock_irqsave(&port->lock, flags);
1177 up->capabilities = 0;
1180 if (!(port->flags & UPF_BUGGY_UART)) {
1182 * Do a simple existence test first; if we fail this,
1183 * there's no point trying anything else.
1185 * 0x80 is used as a nonsense port to prevent against
1186 * false positives due to ISA bus float. The
1187 * assumption is that 0x80 is a non-existent port;
1188 * which should be safe since include/asm/io.h also
1189 * makes this assumption.
1191 * Note: this is safe as long as MCR bit 4 is clear
1192 * and the device is in "PC" mode.
1194 scratch = serial_in(up, UART_IER);
1195 serial_out(up, UART_IER, 0);
1200 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1201 * 16C754B) allow only to modify them if an EFR bit is set.
1203 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1204 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1208 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1209 serial_out(up, UART_IER, scratch);
1210 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1212 * We failed; there's nothing here
1214 spin_unlock_irqrestore(&port->lock, flags);
1215 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1216 scratch2, scratch3);
1221 save_mcr = serial8250_in_MCR(up);
1222 save_lcr = serial_in(up, UART_LCR);
1225 * Check to see if a UART is really there. Certain broken
1226 * internal modems based on the Rockwell chipset fail this
1227 * test, because they apparently don't implement the loopback
1228 * test mode. So this test is skipped on the COM 1 through
1229 * COM 4 ports. This *should* be safe, since no board
1230 * manufacturer would be stupid enough to design a board
1231 * that conflicts with COM 1-4 --- we hope!
1233 if (!(port->flags & UPF_SKIP_TEST)) {
1234 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1235 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1236 serial8250_out_MCR(up, save_mcr);
1237 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1238 spin_unlock_irqrestore(&port->lock, flags);
1239 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1246 * We're pretty sure there's a port here. Lets find out what
1247 * type of port it is. The IIR top two bits allows us to find
1248 * out if it's 8250 or 16450, 16550, 16550A or later. This
1249 * determines what we test for next.
1251 * We also initialise the EFR (if any) to zero for later. The
1252 * EFR occupies the same register location as the FCR and IIR.
1254 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1255 serial_out(up, UART_EFR, 0);
1256 serial_out(up, UART_LCR, 0);
1258 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1260 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1261 case UART_IIR_FIFO_ENABLED_8250:
1262 autoconfig_8250(up);
1264 case UART_IIR_FIFO_ENABLED_16550:
1265 port->type = PORT_16550;
1267 case UART_IIR_FIFO_ENABLED_16550A:
1268 autoconfig_16550a(up);
1271 port->type = PORT_UNKNOWN;
1275 #ifdef CONFIG_SERIAL_8250_RSA
1277 * Only probe for RSA ports if we got the region.
1279 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1281 port->type = PORT_RSA;
1284 serial_out(up, UART_LCR, save_lcr);
1286 port->fifosize = uart_config[up->port.type].fifo_size;
1287 old_capabilities = up->capabilities;
1288 up->capabilities = uart_config[port->type].flags;
1289 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1291 if (port->type == PORT_UNKNOWN)
1297 #ifdef CONFIG_SERIAL_8250_RSA
1298 if (port->type == PORT_RSA)
1299 serial_out(up, UART_RSA_FRR, 0);
1301 serial8250_out_MCR(up, save_mcr);
1302 serial8250_clear_fifos(up);
1303 serial_in(up, UART_RX);
1304 serial8250_clear_IER(up);
1307 spin_unlock_irqrestore(&port->lock, flags);
1310 * Check if the device is a Fintek F81216A
1312 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1313 fintek_8250_probe(up);
1315 if (up->capabilities != old_capabilities) {
1316 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1317 old_capabilities, up->capabilities);
1320 DEBUG_AUTOCONF("iir=%d ", scratch);
1321 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1324 static void autoconfig_irq(struct uart_8250_port *up)
1326 struct uart_port *port = &up->port;
1327 unsigned char save_mcr, save_ier;
1328 unsigned char save_ICP = 0;
1329 unsigned int ICP = 0;
1333 if (port->flags & UPF_FOURPORT) {
1334 ICP = (port->iobase & 0xfe0) | 0x1f;
1335 save_ICP = inb_p(ICP);
1340 if (uart_console(port))
1343 /* forget possible initially masked and pending IRQ */
1344 probe_irq_off(probe_irq_on());
1345 save_mcr = serial8250_in_MCR(up);
1346 /* Synchronize UART_IER access against the console. */
1347 spin_lock_irq(&port->lock);
1348 save_ier = serial_in(up, UART_IER);
1349 spin_unlock_irq(&port->lock);
1350 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1352 irqs = probe_irq_on();
1353 serial8250_out_MCR(up, 0);
1355 if (port->flags & UPF_FOURPORT) {
1356 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1358 serial8250_out_MCR(up,
1359 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1361 /* Synchronize UART_IER access against the console. */
1362 spin_lock_irq(&port->lock);
1363 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1364 spin_unlock_irq(&port->lock);
1365 serial_in(up, UART_LSR);
1366 serial_in(up, UART_RX);
1367 serial_in(up, UART_IIR);
1368 serial_in(up, UART_MSR);
1369 serial_out(up, UART_TX, 0xFF);
1371 irq = probe_irq_off(irqs);
1373 serial8250_out_MCR(up, save_mcr);
1374 /* Synchronize UART_IER access against the console. */
1375 spin_lock_irq(&port->lock);
1376 serial_out(up, UART_IER, save_ier);
1377 spin_unlock_irq(&port->lock);
1379 if (port->flags & UPF_FOURPORT)
1380 outb_p(save_ICP, ICP);
1382 if (uart_console(port))
1385 port->irq = (irq > 0) ? irq : 0;
1388 static void serial8250_stop_rx(struct uart_port *port)
1390 struct uart_8250_port *up = up_to_u8250p(port);
1392 /* Port locked to synchronize UART_IER access against the console. */
1393 lockdep_assert_held_once(&port->lock);
1395 serial8250_rpm_get(up);
1397 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1398 up->port.read_status_mask &= ~UART_LSR_DR;
1399 serial_port_out(port, UART_IER, up->ier);
1401 serial8250_rpm_put(up);
1405 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1406 * @p: uart 8250 port
1408 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1410 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1412 unsigned char mcr = serial8250_in_MCR(p);
1414 /* Port locked to synchronize UART_IER access against the console. */
1415 lockdep_assert_held_once(&p->port.lock);
1417 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1418 mcr |= UART_MCR_RTS;
1420 mcr &= ~UART_MCR_RTS;
1421 serial8250_out_MCR(p, mcr);
1424 * Empty the RX FIFO, we are not interested in anything
1425 * received during the half-duplex transmission.
1426 * Enable previously disabled RX interrupts.
1428 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1429 serial8250_clear_and_reinit_fifos(p);
1431 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1432 serial_port_out(&p->port, UART_IER, p->ier);
1435 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1437 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1439 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1441 struct uart_8250_port *p = em485->port;
1442 unsigned long flags;
1444 serial8250_rpm_get(p);
1445 spin_lock_irqsave(&p->port.lock, flags);
1446 if (em485->active_timer == &em485->stop_tx_timer) {
1447 p->rs485_stop_tx(p);
1448 em485->active_timer = NULL;
1449 em485->tx_stopped = true;
1451 spin_unlock_irqrestore(&p->port.lock, flags);
1452 serial8250_rpm_put(p);
1454 return HRTIMER_NORESTART;
1457 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1459 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1462 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1464 struct uart_8250_em485 *em485 = p->em485;
1466 /* Port locked to synchronize UART_IER access against the console. */
1467 lockdep_assert_held_once(&p->port.lock);
1469 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1472 * rs485_stop_tx() is going to set RTS according to config
1473 * AND flush RX FIFO if required.
1475 if (stop_delay > 0) {
1476 em485->active_timer = &em485->stop_tx_timer;
1477 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1479 p->rs485_stop_tx(p);
1480 em485->active_timer = NULL;
1481 em485->tx_stopped = true;
1485 static inline void __stop_tx(struct uart_8250_port *p)
1487 struct uart_8250_em485 *em485 = p->em485;
1490 u16 lsr = serial_lsr_in(p);
1493 if (!(lsr & UART_LSR_THRE))
1496 * To provide required timing and allow FIFO transfer,
1497 * __stop_tx_rs485() must be called only when both FIFO and
1498 * shift register are empty. The device driver should either
1499 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1500 * enlarge stop_tx_timer by the tx time of one frame to cover
1501 * for emptying of the shift register.
1503 if (!(lsr & UART_LSR_TEMT)) {
1504 if (!(p->capabilities & UART_CAP_NOTEMT))
1507 * RTS might get deasserted too early with the normal
1508 * frame timing formula. It seems to suggest THRE might
1509 * get asserted already during tx of the stop bit
1510 * rather than after it is fully sent.
1511 * Roughly estimate 1 extra bit here with / 7.
1513 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1516 __stop_tx_rs485(p, stop_delay);
1519 if (serial8250_clear_THRI(p))
1520 serial8250_rpm_put_tx(p);
1523 static void serial8250_stop_tx(struct uart_port *port)
1525 struct uart_8250_port *up = up_to_u8250p(port);
1527 serial8250_rpm_get(up);
1531 * We really want to stop the transmitter from sending.
1533 if (port->type == PORT_16C950) {
1534 up->acr |= UART_ACR_TXDIS;
1535 serial_icr_write(up, UART_ACR, up->acr);
1537 serial8250_rpm_put(up);
1540 static inline void __start_tx(struct uart_port *port)
1542 struct uart_8250_port *up = up_to_u8250p(port);
1544 if (up->dma && !up->dma->tx_dma(up))
1547 if (serial8250_set_THRI(up)) {
1548 if (up->bugs & UART_BUG_TXEN) {
1549 u16 lsr = serial_lsr_in(up);
1551 if (lsr & UART_LSR_THRE)
1552 serial8250_tx_chars(up);
1557 * Re-enable the transmitter if we disabled it.
1559 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1560 up->acr &= ~UART_ACR_TXDIS;
1561 serial_icr_write(up, UART_ACR, up->acr);
1566 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1567 * @up: uart 8250 port
1569 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1570 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1571 * (Some chips use inverse semantics.) Further assumes that reception is
1572 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1573 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1575 void serial8250_em485_start_tx(struct uart_8250_port *up)
1577 unsigned char mcr = serial8250_in_MCR(up);
1579 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1580 serial8250_stop_rx(&up->port);
1582 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1583 mcr |= UART_MCR_RTS;
1585 mcr &= ~UART_MCR_RTS;
1586 serial8250_out_MCR(up, mcr);
1588 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1590 /* Returns false, if start_tx_timer was setup to defer TX start */
1591 static bool start_tx_rs485(struct uart_port *port)
1593 struct uart_8250_port *up = up_to_u8250p(port);
1594 struct uart_8250_em485 *em485 = up->em485;
1597 * While serial8250_em485_handle_stop_tx() is a noop if
1598 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1599 * the timer is still armed and triggers only after the current bunch of
1600 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1601 * So cancel the timer. There is still a theoretical race condition if
1602 * the timer is already running and only comes around to check for
1603 * em485->active_timer when &em485->stop_tx_timer is armed again.
1605 if (em485->active_timer == &em485->stop_tx_timer)
1606 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1608 em485->active_timer = NULL;
1610 if (em485->tx_stopped) {
1611 em485->tx_stopped = false;
1613 up->rs485_start_tx(up);
1615 if (up->port.rs485.delay_rts_before_send > 0) {
1616 em485->active_timer = &em485->start_tx_timer;
1617 start_hrtimer_ms(&em485->start_tx_timer,
1618 up->port.rs485.delay_rts_before_send);
1626 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1628 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1630 struct uart_8250_port *p = em485->port;
1631 unsigned long flags;
1633 spin_lock_irqsave(&p->port.lock, flags);
1634 if (em485->active_timer == &em485->start_tx_timer) {
1635 __start_tx(&p->port);
1636 em485->active_timer = NULL;
1638 spin_unlock_irqrestore(&p->port.lock, flags);
1640 return HRTIMER_NORESTART;
1643 static void serial8250_start_tx(struct uart_port *port)
1645 struct uart_8250_port *up = up_to_u8250p(port);
1646 struct uart_8250_em485 *em485 = up->em485;
1648 /* Port locked to synchronize UART_IER access against the console. */
1649 lockdep_assert_held_once(&port->lock);
1651 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1654 serial8250_rpm_get_tx(up);
1657 if ((em485->active_timer == &em485->start_tx_timer) ||
1658 !start_tx_rs485(port))
1664 static void serial8250_throttle(struct uart_port *port)
1666 port->throttle(port);
1669 static void serial8250_unthrottle(struct uart_port *port)
1671 port->unthrottle(port);
1674 static void serial8250_disable_ms(struct uart_port *port)
1676 struct uart_8250_port *up = up_to_u8250p(port);
1678 /* Port locked to synchronize UART_IER access against the console. */
1679 lockdep_assert_held_once(&port->lock);
1681 /* no MSR capabilities */
1682 if (up->bugs & UART_BUG_NOMSR)
1685 mctrl_gpio_disable_ms(up->gpios);
1687 up->ier &= ~UART_IER_MSI;
1688 serial_port_out(port, UART_IER, up->ier);
1691 static void serial8250_enable_ms(struct uart_port *port)
1693 struct uart_8250_port *up = up_to_u8250p(port);
1695 /* Port locked to synchronize UART_IER access against the console. */
1696 lockdep_assert_held_once(&port->lock);
1698 /* no MSR capabilities */
1699 if (up->bugs & UART_BUG_NOMSR)
1702 mctrl_gpio_enable_ms(up->gpios);
1704 up->ier |= UART_IER_MSI;
1706 serial8250_rpm_get(up);
1707 serial_port_out(port, UART_IER, up->ier);
1708 serial8250_rpm_put(up);
1711 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1713 struct uart_port *port = &up->port;
1714 u8 ch, flag = TTY_NORMAL;
1716 if (likely(lsr & UART_LSR_DR))
1717 ch = serial_in(up, UART_RX);
1720 * Intel 82571 has a Serial Over Lan device that will
1721 * set UART_LSR_BI without setting UART_LSR_DR when
1722 * it receives a break. To avoid reading from the
1723 * receive buffer without UART_LSR_DR bit set, we
1724 * just force the read character to be 0
1730 lsr |= up->lsr_saved_flags;
1731 up->lsr_saved_flags = 0;
1733 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1734 if (lsr & UART_LSR_BI) {
1735 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1738 * We do the SysRQ and SAK checking
1739 * here because otherwise the break
1740 * may get masked by ignore_status_mask
1741 * or read_status_mask.
1743 if (uart_handle_break(port))
1745 } else if (lsr & UART_LSR_PE)
1746 port->icount.parity++;
1747 else if (lsr & UART_LSR_FE)
1748 port->icount.frame++;
1749 if (lsr & UART_LSR_OE)
1750 port->icount.overrun++;
1753 * Mask off conditions which should be ignored.
1755 lsr &= port->read_status_mask;
1757 if (lsr & UART_LSR_BI) {
1758 dev_dbg(port->dev, "handling break\n");
1760 } else if (lsr & UART_LSR_PE)
1762 else if (lsr & UART_LSR_FE)
1765 if (uart_prepare_sysrq_char(port, ch))
1768 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1770 EXPORT_SYMBOL_GPL(serial8250_read_char);
1773 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1775 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1776 * (such as THRE) because the LSR value might come from an already consumed
1779 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1781 struct uart_port *port = &up->port;
1782 int max_count = 256;
1785 serial8250_read_char(up, lsr);
1786 if (--max_count == 0)
1788 lsr = serial_in(up, UART_LSR);
1789 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1791 tty_flip_buffer_push(&port->state->port);
1794 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1796 void serial8250_tx_chars(struct uart_8250_port *up)
1798 struct uart_port *port = &up->port;
1799 struct circ_buf *xmit = &port->state->xmit;
1803 uart_xchar_out(port, UART_TX);
1806 if (uart_tx_stopped(port)) {
1807 serial8250_stop_tx(port);
1810 if (uart_circ_empty(xmit)) {
1815 count = up->tx_loadsz;
1817 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1818 if (up->bugs & UART_BUG_TXRACE) {
1820 * The Aspeed BMC virtual UARTs have a bug where data
1821 * may get stuck in the BMC's Tx FIFO from bursts of
1822 * writes on the APB interface.
1824 * Delay back-to-back writes by a read cycle to avoid
1825 * stalling the VUART. Read a register that won't have
1826 * side-effects and discard the result.
1828 serial_in(up, UART_SCR);
1830 uart_xmit_advance(port, 1);
1831 if (uart_circ_empty(xmit))
1833 if ((up->capabilities & UART_CAP_HFIFO) &&
1834 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1836 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1837 if ((up->capabilities & UART_CAP_MINI) &&
1838 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1840 } while (--count > 0);
1842 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1843 uart_write_wakeup(port);
1846 * With RPM enabled, we have to wait until the FIFO is empty before the
1847 * HW can go idle. So we get here once again with empty FIFO and disable
1848 * the interrupt and RPM in __stop_tx()
1850 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1853 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1855 /* Caller holds uart port lock */
1856 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1858 struct uart_port *port = &up->port;
1859 unsigned int status = serial_in(up, UART_MSR);
1861 status |= up->msr_saved_flags;
1862 up->msr_saved_flags = 0;
1863 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1864 port->state != NULL) {
1865 if (status & UART_MSR_TERI)
1867 if (status & UART_MSR_DDSR)
1869 if (status & UART_MSR_DDCD)
1870 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1871 if (status & UART_MSR_DCTS)
1872 uart_handle_cts_change(port, status & UART_MSR_CTS);
1874 wake_up_interruptible(&port->state->port.delta_msr_wait);
1879 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1881 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1883 switch (iir & 0x3f) {
1886 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1887 * because it's impossible to do an informed decision about
1888 * that with IIR_THRI.
1890 * This also fixes one known DMA Rx corruption issue where
1891 * DR is asserted but DMA Rx only gets a corrupted zero byte
1896 if (!up->dma->rx_running)
1900 case UART_IIR_RX_TIMEOUT:
1901 serial8250_rx_dma_flush(up);
1904 return up->dma->rx_dma(up);
1908 * This handles the interrupt from one port.
1910 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1912 struct uart_8250_port *up = up_to_u8250p(port);
1913 struct tty_port *tport = &port->state->port;
1914 bool skip_rx = false;
1915 unsigned long flags;
1918 if (iir & UART_IIR_NO_INT)
1921 spin_lock_irqsave(&port->lock, flags);
1923 status = serial_lsr_in(up);
1926 * If port is stopped and there are no error conditions in the
1927 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1928 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1929 * control when FIFO occupancy reaches preset threshold, thus
1930 * halting RX. This only works when auto HW flow control is
1933 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1934 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1935 !(port->read_status_mask & UART_LSR_DR))
1938 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1939 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
1940 pm_wakeup_event(tport->tty->dev, 0);
1941 if (!up->dma || handle_rx_dma(up, iir))
1942 status = serial8250_rx_chars(up, status);
1944 serial8250_modem_status(up);
1945 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1946 if (!up->dma || up->dma->tx_err)
1947 serial8250_tx_chars(up);
1948 else if (!up->dma->tx_running)
1952 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1956 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1958 static int serial8250_default_handle_irq(struct uart_port *port)
1960 struct uart_8250_port *up = up_to_u8250p(port);
1964 serial8250_rpm_get(up);
1966 iir = serial_port_in(port, UART_IIR);
1967 ret = serial8250_handle_irq(port, iir);
1969 serial8250_rpm_put(up);
1974 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1975 * have a programmable TX threshold that triggers the THRE interrupt in
1976 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1977 * has space available. Load it up with tx_loadsz bytes.
1979 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1981 unsigned long flags;
1982 unsigned int iir = serial_port_in(port, UART_IIR);
1984 /* TX Threshold IRQ triggered so load up FIFO */
1985 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1986 struct uart_8250_port *up = up_to_u8250p(port);
1988 spin_lock_irqsave(&port->lock, flags);
1989 serial8250_tx_chars(up);
1990 spin_unlock_irqrestore(&port->lock, flags);
1993 iir = serial_port_in(port, UART_IIR);
1994 return serial8250_handle_irq(port, iir);
1997 static unsigned int serial8250_tx_empty(struct uart_port *port)
1999 struct uart_8250_port *up = up_to_u8250p(port);
2000 unsigned int result = 0;
2001 unsigned long flags;
2003 serial8250_rpm_get(up);
2005 spin_lock_irqsave(&port->lock, flags);
2006 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
2007 result = TIOCSER_TEMT;
2008 spin_unlock_irqrestore(&port->lock, flags);
2010 serial8250_rpm_put(up);
2015 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2017 struct uart_8250_port *up = up_to_u8250p(port);
2018 unsigned int status;
2021 serial8250_rpm_get(up);
2022 status = serial8250_modem_status(up);
2023 serial8250_rpm_put(up);
2025 val = serial8250_MSR_to_TIOCM(status);
2027 return mctrl_gpio_get(up->gpios, &val);
2031 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2033 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2035 if (port->get_mctrl)
2036 return port->get_mctrl(port);
2037 return serial8250_do_get_mctrl(port);
2040 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2042 struct uart_8250_port *up = up_to_u8250p(port);
2045 mcr = serial8250_TIOCM_to_MCR(mctrl);
2049 serial8250_out_MCR(up, mcr);
2051 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2053 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2055 if (port->rs485.flags & SER_RS485_ENABLED)
2058 if (port->set_mctrl)
2059 port->set_mctrl(port, mctrl);
2061 serial8250_do_set_mctrl(port, mctrl);
2064 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2066 struct uart_8250_port *up = up_to_u8250p(port);
2067 unsigned long flags;
2069 serial8250_rpm_get(up);
2070 spin_lock_irqsave(&port->lock, flags);
2071 if (break_state == -1)
2072 up->lcr |= UART_LCR_SBC;
2074 up->lcr &= ~UART_LCR_SBC;
2075 serial_port_out(port, UART_LCR, up->lcr);
2076 spin_unlock_irqrestore(&port->lock, flags);
2077 serial8250_rpm_put(up);
2080 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2082 unsigned int status, tmout = 10000;
2084 /* Wait up to 10ms for the character(s) to be sent. */
2086 status = serial_lsr_in(up);
2088 if ((status & bits) == bits)
2093 touch_nmi_watchdog();
2098 * Wait for transmitter & holding register to empty
2100 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2104 wait_for_lsr(up, bits);
2106 /* Wait up to 1s for flow control if necessary */
2107 if (up->port.flags & UPF_CONS_FLOW) {
2108 for (tmout = 1000000; tmout; tmout--) {
2109 unsigned int msr = serial_in(up, UART_MSR);
2110 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2111 if (msr & UART_MSR_CTS)
2114 touch_nmi_watchdog();
2119 #ifdef CONFIG_CONSOLE_POLL
2121 * Console polling routines for writing and reading from the uart while
2122 * in an interrupt or debug context.
2125 static int serial8250_get_poll_char(struct uart_port *port)
2127 struct uart_8250_port *up = up_to_u8250p(port);
2131 serial8250_rpm_get(up);
2133 lsr = serial_port_in(port, UART_LSR);
2135 if (!(lsr & UART_LSR_DR)) {
2136 status = NO_POLL_CHAR;
2140 status = serial_port_in(port, UART_RX);
2142 serial8250_rpm_put(up);
2147 static void serial8250_put_poll_char(struct uart_port *port,
2151 struct uart_8250_port *up = up_to_u8250p(port);
2154 * Normally the port is locked to synchronize UART_IER access
2155 * against the console. However, this function is only used by
2156 * KDB/KGDB, where it may not be possible to acquire the port
2157 * lock because all other CPUs are quiesced. The quiescence
2158 * should allow safe lockless usage here.
2161 serial8250_rpm_get(up);
2163 * First save the IER then disable the interrupts
2165 ier = serial_port_in(port, UART_IER);
2166 serial8250_clear_IER(up);
2168 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2170 * Send the character out.
2172 serial_port_out(port, UART_TX, c);
2175 * Finally, wait for transmitter to become empty
2176 * and restore the IER
2178 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2179 serial_port_out(port, UART_IER, ier);
2180 serial8250_rpm_put(up);
2183 #endif /* CONFIG_CONSOLE_POLL */
2185 int serial8250_do_startup(struct uart_port *port)
2187 struct uart_8250_port *up = up_to_u8250p(port);
2188 unsigned long flags;
2193 if (!port->fifosize)
2194 port->fifosize = uart_config[port->type].fifo_size;
2196 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2197 if (!up->capabilities)
2198 up->capabilities = uart_config[port->type].flags;
2201 if (port->iotype != up->cur_iotype)
2202 set_io_from_upio(port);
2204 serial8250_rpm_get(up);
2205 if (port->type == PORT_16C950) {
2207 * Wake up and initialize UART
2209 * Synchronize UART_IER access against the console.
2211 spin_lock_irqsave(&port->lock, flags);
2213 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2214 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2215 serial_port_out(port, UART_IER, 0);
2216 serial_port_out(port, UART_LCR, 0);
2217 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2218 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2219 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2220 serial_port_out(port, UART_LCR, 0);
2221 spin_unlock_irqrestore(&port->lock, flags);
2224 if (port->type == PORT_DA830) {
2228 * Synchronize UART_IER access against the console.
2230 spin_lock_irqsave(&port->lock, flags);
2231 serial_port_out(port, UART_IER, 0);
2232 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2233 spin_unlock_irqrestore(&port->lock, flags);
2236 /* Enable Tx, Rx and free run mode */
2237 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2238 UART_DA830_PWREMU_MGMT_UTRST |
2239 UART_DA830_PWREMU_MGMT_URRST |
2240 UART_DA830_PWREMU_MGMT_FREE);
2243 if (port->type == PORT_NPCM) {
2245 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2246 * register). Enable it, and set TIOC (timeout interrupt
2247 * comparator) to be 0x20 for correct operation.
2249 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2252 #ifdef CONFIG_SERIAL_8250_RSA
2254 * If this is an RSA port, see if we can kick it up to the
2255 * higher speed clock.
2261 * Clear the FIFO buffers and disable them.
2262 * (they will be reenabled in set_termios())
2264 serial8250_clear_fifos(up);
2267 * Clear the interrupt registers.
2269 serial_port_in(port, UART_LSR);
2270 serial_port_in(port, UART_RX);
2271 serial_port_in(port, UART_IIR);
2272 serial_port_in(port, UART_MSR);
2275 * At this point, there's no way the LSR could still be 0xff;
2276 * if it is, then bail out, because there's likely no UART
2279 if (!(port->flags & UPF_BUGGY_UART) &&
2280 (serial_port_in(port, UART_LSR) == 0xff)) {
2281 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2287 * For a XR16C850, we need to set the trigger levels
2289 if (port->type == PORT_16850) {
2292 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2294 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2295 serial_port_out(port, UART_FCTR,
2296 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2297 serial_port_out(port, UART_TRG, UART_TRG_96);
2298 serial_port_out(port, UART_FCTR,
2299 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2300 serial_port_out(port, UART_TRG, UART_TRG_96);
2302 serial_port_out(port, UART_LCR, 0);
2306 * For the Altera 16550 variants, set TX threshold trigger level.
2308 if (((port->type == PORT_ALTR_16550_F32) ||
2309 (port->type == PORT_ALTR_16550_F64) ||
2310 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2311 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2312 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2313 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2315 serial_port_out(port, UART_ALTR_AFR,
2316 UART_ALTR_EN_TXFIFO_LW);
2317 serial_port_out(port, UART_ALTR_TX_LOW,
2318 port->fifosize - up->tx_loadsz);
2319 port->handle_irq = serial8250_tx_threshold_handle_irq;
2323 /* Check if we need to have shared IRQs */
2324 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2325 up->port.irqflags |= IRQF_SHARED;
2327 retval = up->ops->setup_irq(up);
2331 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2334 if (port->irqflags & IRQF_SHARED)
2335 disable_irq_nosync(port->irq);
2338 * Test for UARTs that do not reassert THRE when the
2339 * transmitter is idle and the interrupt has already
2340 * been cleared. Real 16550s should always reassert
2341 * this interrupt whenever the transmitter is idle and
2342 * the interrupt is enabled. Delays are necessary to
2343 * allow register changes to become visible.
2345 * Synchronize UART_IER access against the console.
2347 spin_lock_irqsave(&port->lock, flags);
2349 wait_for_xmitr(up, UART_LSR_THRE);
2350 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2351 udelay(1); /* allow THRE to set */
2352 iir1 = serial_port_in(port, UART_IIR);
2353 serial_port_out(port, UART_IER, 0);
2354 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2355 udelay(1); /* allow a working UART time to re-assert THRE */
2356 iir = serial_port_in(port, UART_IIR);
2357 serial_port_out(port, UART_IER, 0);
2359 spin_unlock_irqrestore(&port->lock, flags);
2361 if (port->irqflags & IRQF_SHARED)
2362 enable_irq(port->irq);
2365 * If the interrupt is not reasserted, or we otherwise
2366 * don't trust the iir, setup a timer to kick the UART
2367 * on a regular basis.
2369 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2370 up->port.flags & UPF_BUG_THRE) {
2371 up->bugs |= UART_BUG_THRE;
2375 up->ops->setup_timer(up);
2378 * Now, initialize the UART
2380 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2382 spin_lock_irqsave(&port->lock, flags);
2383 if (up->port.flags & UPF_FOURPORT) {
2385 up->port.mctrl |= TIOCM_OUT1;
2388 * Most PC uarts need OUT2 raised to enable interrupts.
2391 up->port.mctrl |= TIOCM_OUT2;
2393 serial8250_set_mctrl(port, port->mctrl);
2396 * Serial over Lan (SoL) hack:
2397 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2398 * used for Serial Over Lan. Those chips take a longer time than a
2399 * normal serial device to signalize that a transmission data was
2400 * queued. Due to that, the above test generally fails. One solution
2401 * would be to delay the reading of iir. However, this is not
2402 * reliable, since the timeout is variable. So, let's just don't
2403 * test if we receive TX irq. This way, we'll never enable
2406 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2407 goto dont_test_tx_en;
2410 * Do a quick test to see if we receive an interrupt when we enable
2413 serial_port_out(port, UART_IER, UART_IER_THRI);
2414 lsr = serial_port_in(port, UART_LSR);
2415 iir = serial_port_in(port, UART_IIR);
2416 serial_port_out(port, UART_IER, 0);
2418 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2419 if (!(up->bugs & UART_BUG_TXEN)) {
2420 up->bugs |= UART_BUG_TXEN;
2421 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2424 up->bugs &= ~UART_BUG_TXEN;
2428 spin_unlock_irqrestore(&port->lock, flags);
2431 * Clear the interrupt registers again for luck, and clear the
2432 * saved flags to avoid getting false values from polling
2433 * routines or the previous session.
2435 serial_port_in(port, UART_LSR);
2436 serial_port_in(port, UART_RX);
2437 serial_port_in(port, UART_IIR);
2438 serial_port_in(port, UART_MSR);
2439 up->lsr_saved_flags = 0;
2440 up->msr_saved_flags = 0;
2443 * Request DMA channels for both RX and TX.
2446 const char *msg = NULL;
2448 if (uart_console(port))
2449 msg = "forbid DMA for kernel console";
2450 else if (serial8250_request_dma(up))
2451 msg = "failed to request DMA";
2453 dev_warn_ratelimited(port->dev, "%s\n", msg);
2459 * Set the IER shadow for rx interrupts but defer actual interrupt
2460 * enable until after the FIFOs are enabled; otherwise, an already-
2461 * active sender can swamp the interrupt handler with "too much work".
2463 up->ier = UART_IER_RLSI | UART_IER_RDI;
2465 if (port->flags & UPF_FOURPORT) {
2468 * Enable interrupts on the AST Fourport board
2470 icp = (port->iobase & 0xfe0) | 0x01f;
2476 serial8250_rpm_put(up);
2479 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2481 static int serial8250_startup(struct uart_port *port)
2484 return port->startup(port);
2485 return serial8250_do_startup(port);
2488 void serial8250_do_shutdown(struct uart_port *port)
2490 struct uart_8250_port *up = up_to_u8250p(port);
2491 unsigned long flags;
2493 serial8250_rpm_get(up);
2495 * Disable interrupts from this port
2497 * Synchronize UART_IER access against the console.
2499 spin_lock_irqsave(&port->lock, flags);
2501 serial_port_out(port, UART_IER, 0);
2502 spin_unlock_irqrestore(&port->lock, flags);
2504 synchronize_irq(port->irq);
2507 serial8250_release_dma(up);
2509 spin_lock_irqsave(&port->lock, flags);
2510 if (port->flags & UPF_FOURPORT) {
2511 /* reset interrupts on the AST Fourport board */
2512 inb((port->iobase & 0xfe0) | 0x1f);
2513 port->mctrl |= TIOCM_OUT1;
2515 port->mctrl &= ~TIOCM_OUT2;
2517 serial8250_set_mctrl(port, port->mctrl);
2518 spin_unlock_irqrestore(&port->lock, flags);
2521 * Disable break condition and FIFOs
2523 serial_port_out(port, UART_LCR,
2524 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2525 serial8250_clear_fifos(up);
2527 #ifdef CONFIG_SERIAL_8250_RSA
2529 * Reset the RSA board back to 115kbps compat mode.
2535 * Read data port to reset things, and then unlink from
2538 serial_port_in(port, UART_RX);
2539 serial8250_rpm_put(up);
2541 up->ops->release_irq(up);
2543 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2545 static void serial8250_shutdown(struct uart_port *port)
2548 port->shutdown(port);
2550 serial8250_do_shutdown(port);
2553 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2554 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2557 struct uart_port *port = &up->port;
2559 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2562 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2566 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2567 struct uart_8250_port *up = up_to_u8250p(port);
2571 * Handle magic divisors for baud rates above baud_base on SMSC
2572 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2573 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2574 * magic divisors actually reprogram the baud rate generator's
2575 * reference clock derived from chips's 14.318MHz clock input.
2577 * Documentation claims that with these magic divisors the base
2578 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2579 * for the extra baud rates of 460800bps and 230400bps rather
2580 * than the usual base frequency of 1.8462MHz. However empirical
2581 * evidence contradicts that.
2583 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2584 * effectively used as a clock prescaler selection bit for the
2585 * base frequency of 7.3728MHz, always used. If set to 0, then
2586 * the base frequency is divided by 4 for use by the Baud Rate
2587 * Generator, for the usual arrangement where the value of 1 of
2588 * the divisor produces the baud rate of 115200bps. Conversely,
2589 * if set to 1 and high-speed operation has been enabled with the
2590 * Serial Port Mode Register in the Device Configuration Space,
2591 * then the base frequency is supplied directly to the Baud Rate
2592 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2593 * 0x8004, etc. the respective baud rates produced are 460800bps,
2594 * 230400bps, 153600bps, 115200bps, etc.
2596 * In all cases only low 15 bits of the divisor are used to divide
2597 * the baud base and therefore 32767 is the maximum divisor value
2598 * possible, even though documentation says that the programmable
2599 * Baud Rate Generator is capable of dividing the internal PLL
2600 * clock by any divisor from 1 to 65535.
2602 if (magic_multiplier && baud >= port->uartclk / 6)
2604 else if (magic_multiplier && baud >= port->uartclk / 12)
2606 else if (up->port.type == PORT_NPCM)
2607 quot = npcm_get_divisor(up, baud);
2609 quot = uart_get_divisor(port, baud);
2612 * Oxford Semi 952 rev B workaround
2614 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2620 static unsigned int serial8250_get_divisor(struct uart_port *port,
2624 if (port->get_divisor)
2625 return port->get_divisor(port, baud, frac);
2627 return serial8250_do_get_divisor(port, baud, frac);
2630 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2635 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2637 if (c_cflag & CSTOPB)
2638 cval |= UART_LCR_STOP;
2639 if (c_cflag & PARENB)
2640 cval |= UART_LCR_PARITY;
2641 if (!(c_cflag & PARODD))
2642 cval |= UART_LCR_EPAR;
2643 if (c_cflag & CMSPAR)
2644 cval |= UART_LCR_SPAR;
2649 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2650 unsigned int quot, unsigned int quot_frac)
2652 struct uart_8250_port *up = up_to_u8250p(port);
2654 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2655 if (is_omap1510_8250(up)) {
2656 if (baud == 115200) {
2658 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2660 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2664 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2665 * otherwise just set DLAB
2667 if (up->capabilities & UART_NATSEMI)
2668 serial_port_out(port, UART_LCR, 0xe0);
2670 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2672 serial_dl_write(up, quot);
2674 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2676 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2677 unsigned int quot, unsigned int quot_frac)
2679 if (port->set_divisor)
2680 port->set_divisor(port, baud, quot, quot_frac);
2682 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2685 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2686 struct ktermios *termios,
2687 const struct ktermios *old)
2689 unsigned int tolerance = port->uartclk / 100;
2694 * Handle magic divisors for baud rates above baud_base on SMSC
2695 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2696 * disable divisor values beyond 32767, which are unavailable.
2698 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2699 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2700 max = (port->uartclk + tolerance) / 4;
2702 min = port->uartclk / 16 / UART_DIV_MAX;
2703 max = (port->uartclk + tolerance) / 16;
2707 * Ask the core to calculate the divisor for us.
2708 * Allow 1% tolerance at the upper limit so uart clks marginally
2709 * slower than nominal still match standard baud rates without
2710 * causing transmission errors.
2712 return uart_get_baud_rate(port, termios, old, min, max);
2716 * Note in order to avoid the tty port mutex deadlock don't use the next method
2717 * within the uart port callbacks. Primarily it's supposed to be utilized to
2718 * handle a sudden reference clock rate change.
2720 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2722 struct uart_8250_port *up = up_to_u8250p(port);
2723 struct tty_port *tport = &port->state->port;
2724 unsigned int baud, quot, frac = 0;
2725 struct ktermios *termios;
2726 struct tty_struct *tty;
2727 unsigned long flags;
2729 tty = tty_port_tty_get(tport);
2731 mutex_lock(&tport->mutex);
2732 port->uartclk = uartclk;
2733 mutex_unlock(&tport->mutex);
2737 down_write(&tty->termios_rwsem);
2738 mutex_lock(&tport->mutex);
2740 if (port->uartclk == uartclk)
2743 port->uartclk = uartclk;
2745 if (!tty_port_initialized(tport))
2748 termios = &tty->termios;
2750 baud = serial8250_get_baud_rate(port, termios, NULL);
2751 quot = serial8250_get_divisor(port, baud, &frac);
2753 serial8250_rpm_get(up);
2754 spin_lock_irqsave(&port->lock, flags);
2756 uart_update_timeout(port, termios->c_cflag, baud);
2758 serial8250_set_divisor(port, baud, quot, frac);
2759 serial_port_out(port, UART_LCR, up->lcr);
2761 spin_unlock_irqrestore(&port->lock, flags);
2762 serial8250_rpm_put(up);
2765 mutex_unlock(&tport->mutex);
2766 up_write(&tty->termios_rwsem);
2769 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2772 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2773 const struct ktermios *old)
2775 struct uart_8250_port *up = up_to_u8250p(port);
2777 unsigned long flags;
2778 unsigned int baud, quot, frac = 0;
2780 if (up->capabilities & UART_CAP_MINI) {
2781 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2782 if ((termios->c_cflag & CSIZE) == CS5 ||
2783 (termios->c_cflag & CSIZE) == CS6)
2784 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2786 cval = serial8250_compute_lcr(up, termios->c_cflag);
2788 baud = serial8250_get_baud_rate(port, termios, old);
2789 quot = serial8250_get_divisor(port, baud, &frac);
2792 * Ok, we're now changing the port state. Do it with
2793 * interrupts disabled.
2795 * Synchronize UART_IER access against the console.
2797 serial8250_rpm_get(up);
2798 spin_lock_irqsave(&port->lock, flags);
2800 up->lcr = cval; /* Save computed LCR */
2802 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2803 if (baud < 2400 && !up->dma) {
2804 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2805 up->fcr |= UART_FCR_TRIGGER_1;
2810 * MCR-based auto flow control. When AFE is enabled, RTS will be
2811 * deasserted when the receive FIFO contains more characters than
2812 * the trigger, or the MCR RTS bit is cleared.
2814 if (up->capabilities & UART_CAP_AFE) {
2815 up->mcr &= ~UART_MCR_AFE;
2816 if (termios->c_cflag & CRTSCTS)
2817 up->mcr |= UART_MCR_AFE;
2821 * Update the per-port timeout.
2823 uart_update_timeout(port, termios->c_cflag, baud);
2825 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2826 if (termios->c_iflag & INPCK)
2827 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2828 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2829 port->read_status_mask |= UART_LSR_BI;
2832 * Characters to ignore
2834 port->ignore_status_mask = 0;
2835 if (termios->c_iflag & IGNPAR)
2836 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2837 if (termios->c_iflag & IGNBRK) {
2838 port->ignore_status_mask |= UART_LSR_BI;
2840 * If we're ignoring parity and break indicators,
2841 * ignore overruns too (for real raw support).
2843 if (termios->c_iflag & IGNPAR)
2844 port->ignore_status_mask |= UART_LSR_OE;
2848 * ignore all characters if CREAD is not set
2850 if ((termios->c_cflag & CREAD) == 0)
2851 port->ignore_status_mask |= UART_LSR_DR;
2854 * CTS flow control flag and modem status interrupts
2856 up->ier &= ~UART_IER_MSI;
2857 if (!(up->bugs & UART_BUG_NOMSR) &&
2858 UART_ENABLE_MS(&up->port, termios->c_cflag))
2859 up->ier |= UART_IER_MSI;
2860 if (up->capabilities & UART_CAP_UUE)
2861 up->ier |= UART_IER_UUE;
2862 if (up->capabilities & UART_CAP_RTOIE)
2863 up->ier |= UART_IER_RTOIE;
2865 serial_port_out(port, UART_IER, up->ier);
2867 if (up->capabilities & UART_CAP_EFR) {
2868 unsigned char efr = 0;
2870 * TI16C752/Startech hardware flow control. FIXME:
2871 * - TI16C752 requires control thresholds to be set.
2872 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2874 if (termios->c_cflag & CRTSCTS)
2875 efr |= UART_EFR_CTS;
2877 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2878 if (port->flags & UPF_EXAR_EFR)
2879 serial_port_out(port, UART_XR_EFR, efr);
2881 serial_port_out(port, UART_EFR, efr);
2884 serial8250_set_divisor(port, baud, quot, frac);
2887 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2888 * is written without DLAB set, this mode will be disabled.
2890 if (port->type == PORT_16750)
2891 serial_port_out(port, UART_FCR, up->fcr);
2893 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2894 if (port->type != PORT_16750) {
2895 /* emulated UARTs (Lucent Venus 167x) need two steps */
2896 if (up->fcr & UART_FCR_ENABLE_FIFO)
2897 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2898 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2900 serial8250_set_mctrl(port, port->mctrl);
2901 spin_unlock_irqrestore(&port->lock, flags);
2902 serial8250_rpm_put(up);
2904 /* Don't rewrite B0 */
2905 if (tty_termios_baud_rate(termios))
2906 tty_termios_encode_baud_rate(termios, baud, baud);
2908 EXPORT_SYMBOL(serial8250_do_set_termios);
2911 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2912 const struct ktermios *old)
2914 if (port->set_termios)
2915 port->set_termios(port, termios, old);
2917 serial8250_do_set_termios(port, termios, old);
2920 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2922 if (termios->c_line == N_PPS) {
2923 port->flags |= UPF_HARDPPS_CD;
2924 spin_lock_irq(&port->lock);
2925 serial8250_enable_ms(port);
2926 spin_unlock_irq(&port->lock);
2928 port->flags &= ~UPF_HARDPPS_CD;
2929 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2930 spin_lock_irq(&port->lock);
2931 serial8250_disable_ms(port);
2932 spin_unlock_irq(&port->lock);
2936 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2939 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2941 if (port->set_ldisc)
2942 port->set_ldisc(port, termios);
2944 serial8250_do_set_ldisc(port, termios);
2947 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2948 unsigned int oldstate)
2950 struct uart_8250_port *p = up_to_u8250p(port);
2952 serial8250_set_sleep(p, state != 0);
2954 EXPORT_SYMBOL(serial8250_do_pm);
2957 serial8250_pm(struct uart_port *port, unsigned int state,
2958 unsigned int oldstate)
2961 port->pm(port, state, oldstate);
2963 serial8250_do_pm(port, state, oldstate);
2966 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2968 if (pt->port.mapsize)
2969 return pt->port.mapsize;
2970 if (is_omap1_8250(pt))
2971 return 0x16 << pt->port.regshift;
2973 return 8 << pt->port.regshift;
2977 * Resource handling.
2979 static int serial8250_request_std_resource(struct uart_8250_port *up)
2981 unsigned int size = serial8250_port_size(up);
2982 struct uart_port *port = &up->port;
2985 switch (port->iotype) {
2992 if (!port->mapbase) {
2997 if (!request_mem_region(port->mapbase, size, "serial")) {
3002 if (port->flags & UPF_IOREMAP) {
3003 port->membase = ioremap(port->mapbase, size);
3004 if (!port->membase) {
3005 release_mem_region(port->mapbase, size);
3013 if (!request_region(port->iobase, size, "serial"))
3020 static void serial8250_release_std_resource(struct uart_8250_port *up)
3022 unsigned int size = serial8250_port_size(up);
3023 struct uart_port *port = &up->port;
3025 switch (port->iotype) {
3035 if (port->flags & UPF_IOREMAP) {
3036 iounmap(port->membase);
3037 port->membase = NULL;
3040 release_mem_region(port->mapbase, size);
3045 release_region(port->iobase, size);
3050 static void serial8250_release_port(struct uart_port *port)
3052 struct uart_8250_port *up = up_to_u8250p(port);
3054 serial8250_release_std_resource(up);
3057 static int serial8250_request_port(struct uart_port *port)
3059 struct uart_8250_port *up = up_to_u8250p(port);
3061 return serial8250_request_std_resource(up);
3064 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3066 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3067 unsigned char bytes;
3069 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3071 return bytes ? bytes : -EOPNOTSUPP;
3074 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3076 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3079 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3082 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3083 if (bytes < conf_type->rxtrig_bytes[i])
3084 /* Use the nearest lower value */
3085 return (--i) << UART_FCR_R_TRIG_SHIFT;
3088 return UART_FCR_R_TRIG_11;
3091 static int do_get_rxtrig(struct tty_port *port)
3093 struct uart_state *state = container_of(port, struct uart_state, port);
3094 struct uart_port *uport = state->uart_port;
3095 struct uart_8250_port *up = up_to_u8250p(uport);
3097 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3100 return fcr_get_rxtrig_bytes(up);
3103 static int do_serial8250_get_rxtrig(struct tty_port *port)
3107 mutex_lock(&port->mutex);
3108 rxtrig_bytes = do_get_rxtrig(port);
3109 mutex_unlock(&port->mutex);
3111 return rxtrig_bytes;
3114 static ssize_t rx_trig_bytes_show(struct device *dev,
3115 struct device_attribute *attr, char *buf)
3117 struct tty_port *port = dev_get_drvdata(dev);
3120 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3121 if (rxtrig_bytes < 0)
3122 return rxtrig_bytes;
3124 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3127 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3129 struct uart_state *state = container_of(port, struct uart_state, port);
3130 struct uart_port *uport = state->uart_port;
3131 struct uart_8250_port *up = up_to_u8250p(uport);
3134 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3137 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3141 serial8250_clear_fifos(up);
3142 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3143 up->fcr |= (unsigned char)rxtrig;
3144 serial_out(up, UART_FCR, up->fcr);
3148 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3152 mutex_lock(&port->mutex);
3153 ret = do_set_rxtrig(port, bytes);
3154 mutex_unlock(&port->mutex);
3159 static ssize_t rx_trig_bytes_store(struct device *dev,
3160 struct device_attribute *attr, const char *buf, size_t count)
3162 struct tty_port *port = dev_get_drvdata(dev);
3163 unsigned char bytes;
3169 ret = kstrtou8(buf, 10, &bytes);
3173 ret = do_serial8250_set_rxtrig(port, bytes);
3180 static DEVICE_ATTR_RW(rx_trig_bytes);
3182 static struct attribute *serial8250_dev_attrs[] = {
3183 &dev_attr_rx_trig_bytes.attr,
3187 static struct attribute_group serial8250_dev_attr_group = {
3188 .attrs = serial8250_dev_attrs,
3191 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3193 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3195 if (conf_type->rxtrig_bytes[0])
3196 up->port.attr_group = &serial8250_dev_attr_group;
3199 static void serial8250_config_port(struct uart_port *port, int flags)
3201 struct uart_8250_port *up = up_to_u8250p(port);
3205 * Find the region that we can probe for. This in turn
3206 * tells us whether we can probe for the type of port.
3208 ret = serial8250_request_std_resource(up);
3212 if (port->iotype != up->cur_iotype)
3213 set_io_from_upio(port);
3215 if (flags & UART_CONFIG_TYPE)
3218 /* HW bugs may trigger IRQ while IIR == NO_INT */
3219 if (port->type == PORT_TEGRA)
3220 up->bugs |= UART_BUG_NOMSR;
3222 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3225 if (port->type == PORT_UNKNOWN)
3226 serial8250_release_std_resource(up);
3228 register_dev_spec_attr_grp(up);
3229 up->fcr = uart_config[up->port.type].fcr;
3233 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3235 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3236 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3237 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3238 ser->type == PORT_STARTECH)
3243 static const char *serial8250_type(struct uart_port *port)
3245 int type = port->type;
3247 if (type >= ARRAY_SIZE(uart_config))
3249 return uart_config[type].name;
3252 static const struct uart_ops serial8250_pops = {
3253 .tx_empty = serial8250_tx_empty,
3254 .set_mctrl = serial8250_set_mctrl,
3255 .get_mctrl = serial8250_get_mctrl,
3256 .stop_tx = serial8250_stop_tx,
3257 .start_tx = serial8250_start_tx,
3258 .throttle = serial8250_throttle,
3259 .unthrottle = serial8250_unthrottle,
3260 .stop_rx = serial8250_stop_rx,
3261 .enable_ms = serial8250_enable_ms,
3262 .break_ctl = serial8250_break_ctl,
3263 .startup = serial8250_startup,
3264 .shutdown = serial8250_shutdown,
3265 .set_termios = serial8250_set_termios,
3266 .set_ldisc = serial8250_set_ldisc,
3267 .pm = serial8250_pm,
3268 .type = serial8250_type,
3269 .release_port = serial8250_release_port,
3270 .request_port = serial8250_request_port,
3271 .config_port = serial8250_config_port,
3272 .verify_port = serial8250_verify_port,
3273 #ifdef CONFIG_CONSOLE_POLL
3274 .poll_get_char = serial8250_get_poll_char,
3275 .poll_put_char = serial8250_put_poll_char,
3279 void serial8250_init_port(struct uart_8250_port *up)
3281 struct uart_port *port = &up->port;
3283 spin_lock_init(&port->lock);
3286 port->ops = &serial8250_pops;
3287 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3289 up->cur_iotype = 0xFF;
3291 EXPORT_SYMBOL_GPL(serial8250_init_port);
3293 void serial8250_set_defaults(struct uart_8250_port *up)
3295 struct uart_port *port = &up->port;
3297 if (up->port.flags & UPF_FIXED_TYPE) {
3298 unsigned int type = up->port.type;
3300 if (!up->port.fifosize)
3301 up->port.fifosize = uart_config[type].fifo_size;
3303 up->tx_loadsz = uart_config[type].tx_loadsz;
3304 if (!up->capabilities)
3305 up->capabilities = uart_config[type].flags;
3308 set_io_from_upio(port);
3310 /* default dma handlers */
3312 if (!up->dma->tx_dma)
3313 up->dma->tx_dma = serial8250_tx_dma;
3314 if (!up->dma->rx_dma)
3315 up->dma->rx_dma = serial8250_rx_dma;
3318 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3320 #ifdef CONFIG_SERIAL_8250_CONSOLE
3322 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3324 struct uart_8250_port *up = up_to_u8250p(port);
3326 wait_for_xmitr(up, UART_LSR_THRE);
3327 serial_port_out(port, UART_TX, ch);
3331 * Restore serial console when h/w power-off detected
3333 static void serial8250_console_restore(struct uart_8250_port *up)
3335 struct uart_port *port = &up->port;
3336 struct ktermios termios;
3337 unsigned int baud, quot, frac = 0;
3339 termios.c_cflag = port->cons->cflag;
3340 termios.c_ispeed = port->cons->ispeed;
3341 termios.c_ospeed = port->cons->ospeed;
3342 if (port->state->port.tty && termios.c_cflag == 0) {
3343 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3344 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3345 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3348 baud = serial8250_get_baud_rate(port, &termios, NULL);
3349 quot = serial8250_get_divisor(port, baud, &frac);
3351 serial8250_set_divisor(port, baud, quot, frac);
3352 serial_port_out(port, UART_LCR, up->lcr);
3353 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3357 * Print a string to the serial port using the device FIFO
3359 * It sends fifosize bytes and then waits for the fifo
3362 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3363 const char *s, unsigned int count)
3366 const char *end = s + count;
3367 unsigned int fifosize = up->tx_loadsz;
3368 bool cr_sent = false;
3371 wait_for_lsr(up, UART_LSR_THRE);
3373 for (i = 0; i < fifosize && s != end; ++i) {
3374 if (*s == '\n' && !cr_sent) {
3375 serial_out(up, UART_TX, '\r');
3378 serial_out(up, UART_TX, *s++);
3386 * Print a string to the serial port trying not to disturb
3387 * any possible real use of the port...
3389 * The console_lock must be held when we get here.
3391 * Doing runtime PM is really a bad idea for the kernel console.
3392 * Thus, we assume the function is called when device is powered up.
3394 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3397 struct uart_8250_em485 *em485 = up->em485;
3398 struct uart_port *port = &up->port;
3399 unsigned long flags;
3400 unsigned int ier, use_fifo;
3403 touch_nmi_watchdog();
3405 if (oops_in_progress)
3406 locked = spin_trylock_irqsave(&port->lock, flags);
3408 spin_lock_irqsave(&port->lock, flags);
3411 * First save the IER then disable the interrupts
3413 ier = serial_port_in(port, UART_IER);
3414 serial8250_clear_IER(up);
3416 /* check scratch reg to see if port powered off during system sleep */
3417 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3418 serial8250_console_restore(up);
3423 if (em485->tx_stopped)
3424 up->rs485_start_tx(up);
3425 mdelay(port->rs485.delay_rts_before_send);
3428 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3430 * BCM283x requires to check the fifo
3433 !(up->capabilities & UART_CAP_MINI) &&
3435 * tx_loadsz contains the transmit fifo size
3437 up->tx_loadsz > 1 &&
3438 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3440 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3442 * After we put a data in the fifo, the controller will send
3443 * it regardless of the CTS state. Therefore, only use fifo
3444 * if we don't use control flow.
3446 !(up->port.flags & UPF_CONS_FLOW);
3448 if (likely(use_fifo))
3449 serial8250_console_fifo_write(up, s, count);
3451 uart_console_write(port, s, count, serial8250_console_putchar);
3454 * Finally, wait for transmitter to become empty
3455 * and restore the IER
3457 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3460 mdelay(port->rs485.delay_rts_after_send);
3461 if (em485->tx_stopped)
3462 up->rs485_stop_tx(up);
3465 serial_port_out(port, UART_IER, ier);
3468 * The receive handling will happen properly because the
3469 * receive ready bit will still be set; it is not cleared
3470 * on read. However, modem control will not, we must
3471 * call it if we have saved something in the saved flags
3472 * while processing with interrupts off.
3474 if (up->msr_saved_flags)
3475 serial8250_modem_status(up);
3478 spin_unlock_irqrestore(&port->lock, flags);
3481 static unsigned int probe_baud(struct uart_port *port)
3483 unsigned char lcr, dll, dlm;
3486 lcr = serial_port_in(port, UART_LCR);
3487 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3488 dll = serial_port_in(port, UART_DLL);
3489 dlm = serial_port_in(port, UART_DLM);
3490 serial_port_out(port, UART_LCR, lcr);
3492 quot = (dlm << 8) | dll;
3493 return (port->uartclk / 16) / quot;
3496 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3504 if (!port->iobase && !port->membase)
3508 uart_parse_options(options, &baud, &parity, &bits, &flow);
3510 baud = probe_baud(port);
3512 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3517 pm_runtime_get_sync(port->dev);
3522 int serial8250_console_exit(struct uart_port *port)
3525 pm_runtime_put_sync(port->dev);
3530 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3532 MODULE_LICENSE("GPL");