2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 #include <linux/rational.h>
26 #include <asm/byteorder.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_data/dma-dw.h>
35 * init function returns:
36 * > 0 - number of ports
37 * = 0 - use board->num_ports
40 struct pci_serial_quirk {
45 int (*probe)(struct pci_dev *dev);
46 int (*init)(struct pci_dev *dev);
47 int (*setup)(struct serial_private *,
48 const struct pciserial_board *,
49 struct uart_8250_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static int pci_default_setup(struct serial_private*,
64 const struct pciserial_board*, struct uart_8250_port *, int);
66 static void moan_device(const char *str, struct pci_dev *dev)
70 "Please send the output of lspci -vv, this\n"
71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
72 "manufacturer and name of serial board or\n"
73 "modem board to <linux-serial@vger.kernel.org>.\n",
74 pci_name(dev), str, dev->vendor, dev->device,
75 dev->subsystem_vendor, dev->subsystem_device);
79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
80 int bar, int offset, int regshift)
82 struct pci_dev *dev = priv->dev;
84 if (bar >= PCI_NUM_BAR_RESOURCES)
87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
90 if (!priv->remapped_bar[bar])
93 port->port.iotype = UPIO_MEM;
94 port->port.iobase = 0;
95 port->port.mapbase = pci_resource_start(dev, bar) + offset;
96 port->port.membase = priv->remapped_bar[bar] + offset;
97 port->port.regshift = regshift;
99 port->port.iotype = UPIO_PORT;
100 port->port.iobase = pci_resource_start(dev, bar) + offset;
101 port->port.mapbase = 0;
102 port->port.membase = NULL;
103 port->port.regshift = 0;
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_8250_port *port, int idx)
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
128 offset += ((idx - 6) * board->uart_offset);
131 return setup_port(priv, port, bar, offset, board->reg_shift);
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_8250_port *port, int idx)
142 unsigned int bar, offset = board->first_offset;
144 bar = FL_GET_BASE(board->flags);
149 offset += (idx - 4) * board->uart_offset;
152 return setup_port(priv, port, bar, offset, board->reg_shift);
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
162 static int pci_hp_diva_init(struct pci_dev *dev)
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_8250_port *port, int idx)
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
215 offset += idx * board->uart_offset;
217 return setup_port(priv, port, bar, offset, board->reg_shift);
221 * Added for EKF Intel i960 serial boards
223 static int pci_inteli960ni_init(struct pci_dev *dev)
227 if (!(dev->subsystem_device & 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, &oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int pci_plx9050_init(struct pci_dev *dev)
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
272 * enable/disable interrupts
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277 writel(irq_config, p + 0x4c);
280 * Read the register back to ensure that it took effect.
288 static void pci_plx9050_exit(struct pci_dev *dev)
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
303 * Read the register back to ensure that it took effect.
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
313 static void pci_ni8420_exit(struct pci_dev *dev)
316 unsigned int bar = 0;
318 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
319 moan_device("no memory in bar", dev);
323 p = pci_ioremap_bar(dev, bar);
327 /* Disable the CPU Interrupt */
328 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
329 p + NI8420_INT_ENABLE_REG);
335 #define MITE_IOWBSR1 0xc4
336 #define MITE_IOWCR1 0xf4
337 #define MITE_LCIMR1 0x08
338 #define MITE_LCIMR2 0x10
340 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342 static void pci_ni8430_exit(struct pci_dev *dev)
345 unsigned int bar = 0;
347 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
348 moan_device("no memory in bar", dev);
352 p = pci_ioremap_bar(dev, bar);
356 /* Disable the CPU Interrupt */
357 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
361 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
364 struct uart_8250_port *port, int idx)
366 unsigned int bar, offset = board->first_offset;
371 /* first four channels map to 0, 0x100, 0x200, 0x300 */
372 offset += idx * board->uart_offset;
373 } else if (idx < 8) {
374 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
375 offset += idx * board->uart_offset + 0xC00;
376 } else /* we have only 8 ports on PMC-OCTALPRO */
379 return setup_port(priv, port, bar, offset, board->reg_shift);
383 * This does initialization for PMC OCTALPRO cards:
384 * maps the device memory, resets the UARTs (needed, bc
385 * if the module is removed and inserted again, the card
386 * is in the sleep mode) and enables global interrupt.
389 /* global control register offset for SBS PMC-OctalPro */
390 #define OCT_REG_CR_OFF 0x500
392 static int sbs_init(struct pci_dev *dev)
396 p = pci_ioremap_bar(dev, 0);
400 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
401 writeb(0x10, p + OCT_REG_CR_OFF);
403 writeb(0x0, p + OCT_REG_CR_OFF);
405 /* Set bit-2 (INTENABLE) of Control Register */
406 writeb(0x4, p + OCT_REG_CR_OFF);
413 * Disables the global interrupt of PMC-OctalPro
416 static void sbs_exit(struct pci_dev *dev)
420 p = pci_ioremap_bar(dev, 0);
421 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 writeb(0, p + OCT_REG_CR_OFF);
428 * SIIG serial cards have an PCI interface chip which also controls
429 * the UART clocking frequency. Each UART can be clocked independently
430 * (except cards equipped with 4 UARTs) and initial clocking settings
431 * are stored in the EEPROM chip. It can cause problems because this
432 * version of serial driver doesn't support differently clocked UART's
433 * on single PCI card. To prevent this, initialization functions set
434 * high frequency clocking for all UART's on given card. It is safe (I
435 * hope) because it doesn't touch EEPROM settings to prevent conflicts
436 * with other OSes (like M$ DOS).
438 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
440 * There is two family of SIIG serial cards with different PCI
441 * interface chip and different configuration methods:
442 * - 10x cards have control registers in IO and/or memory space;
443 * - 20x cards have control registers in standard PCI configuration space.
445 * Note: all 10x cards have PCI device ids 0x10..
446 * all 20x cards have PCI device ids 0x20..
448 * There are also Quartet Serial cards which use Oxford Semiconductor
449 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 * Note: some SIIG cards are probed by the parport_serial object.
454 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
455 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457 static int pci_siig10x_init(struct pci_dev *dev)
462 switch (dev->device & 0xfff8) {
463 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
466 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
469 default: /* 1S1P, 4S */
474 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
478 writew(readw(p + 0x28) & data, p + 0x28);
484 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
485 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487 static int pci_siig20x_init(struct pci_dev *dev)
491 /* Change clock frequency for the first UART. */
492 pci_read_config_byte(dev, 0x6f, &data);
493 pci_write_config_byte(dev, 0x6f, data & 0xef);
495 /* If this card has 2 UART, we have to do the same with second UART. */
496 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
497 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
498 pci_read_config_byte(dev, 0x73, &data);
499 pci_write_config_byte(dev, 0x73, data & 0xef);
504 static int pci_siig_init(struct pci_dev *dev)
506 unsigned int type = dev->device & 0xff00;
509 return pci_siig10x_init(dev);
510 else if (type == 0x2000)
511 return pci_siig20x_init(dev);
513 moan_device("Unknown SIIG card", dev);
517 static int pci_siig_setup(struct serial_private *priv,
518 const struct pciserial_board *board,
519 struct uart_8250_port *port, int idx)
521 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
525 offset = (idx - 4) * 8;
528 return setup_port(priv, port, bar, offset, 0);
532 * Timedia has an explosion of boards, and to avoid the PCI table from
533 * growing *huge*, we use this function to collapse some 70 entries
534 * in the PCI table into one, for sanity's and compactness's sake.
536 static const unsigned short timedia_single_port[] = {
537 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
540 static const unsigned short timedia_dual_port[] = {
541 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
542 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
543 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
544 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
548 static const unsigned short timedia_quad_port[] = {
549 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
550 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
551 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
555 static const unsigned short timedia_eight_port[] = {
556 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
557 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
560 static const struct timedia_struct {
562 const unsigned short *ids;
564 { 1, timedia_single_port },
565 { 2, timedia_dual_port },
566 { 4, timedia_quad_port },
567 { 8, timedia_eight_port }
571 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
572 * listing them individually, this driver merely grabs them all with
573 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
574 * and should be left free to be claimed by parport_serial instead.
576 static int pci_timedia_probe(struct pci_dev *dev)
579 * Check the third digit of the subdevice ID
580 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 "ignoring Timedia subdevice %04x for parport_serial\n",
585 dev->subsystem_device);
592 static int pci_timedia_init(struct pci_dev *dev)
594 const unsigned short *ids;
597 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
598 ids = timedia_data[i].ids;
599 for (j = 0; ids[j]; j++)
600 if (dev->subsystem_device == ids[j])
601 return timedia_data[i].num;
607 * Timedia/SUNIX uses a mixture of BARs and offsets
608 * Ugh, this is ugly as all hell --- TYT
611 pci_timedia_setup(struct serial_private *priv,
612 const struct pciserial_board *board,
613 struct uart_8250_port *port, int idx)
615 unsigned int bar = 0, offset = board->first_offset;
622 offset = board->uart_offset;
629 offset = board->uart_offset;
638 return setup_port(priv, port, bar, offset, board->reg_shift);
642 * Some Titan cards are also a little weird
645 titan_400l_800l_setup(struct serial_private *priv,
646 const struct pciserial_board *board,
647 struct uart_8250_port *port, int idx)
649 unsigned int bar, offset = board->first_offset;
660 offset = (idx - 2) * board->uart_offset;
663 return setup_port(priv, port, bar, offset, board->reg_shift);
666 static int pci_xircom_init(struct pci_dev *dev)
672 static int pci_ni8420_init(struct pci_dev *dev)
675 unsigned int bar = 0;
677 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
678 moan_device("no memory in bar", dev);
682 p = pci_ioremap_bar(dev, bar);
686 /* Enable CPU Interrupt */
687 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
688 p + NI8420_INT_ENABLE_REG);
694 #define MITE_IOWBSR1_WSIZE 0xa
695 #define MITE_IOWBSR1_WIN_OFFSET 0x800
696 #define MITE_IOWBSR1_WENAB (1 << 7)
697 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
698 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
699 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701 static int pci_ni8430_init(struct pci_dev *dev)
704 struct pci_bus_region region;
706 unsigned int bar = 0;
708 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
709 moan_device("no memory in bar", dev);
713 p = pci_ioremap_bar(dev, bar);
718 * Set device window address and size in BAR0, while acknowledging that
719 * the resource structure may contain a translated address that differs
720 * from the address the device responds to.
722 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
723 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
724 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
725 writel(device_window, p + MITE_IOWBSR1);
727 /* Set window access to go to RAMSEL IO address space */
728 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
731 /* Enable IO Bus Interrupt 0 */
732 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734 /* Enable CPU Interrupt */
735 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
741 /* UART Port Control Register */
742 #define NI8430_PORTCON 0x0f
743 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
746 pci_ni8430_setup(struct serial_private *priv,
747 const struct pciserial_board *board,
748 struct uart_8250_port *port, int idx)
750 struct pci_dev *dev = priv->dev;
752 unsigned int bar, offset = board->first_offset;
754 if (idx >= board->num_ports)
757 bar = FL_GET_BASE(board->flags);
758 offset += idx * board->uart_offset;
760 p = pci_ioremap_bar(dev, bar);
764 /* enable the transceiver */
765 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
766 p + offset + NI8430_PORTCON);
770 return setup_port(priv, port, bar, offset, board->reg_shift);
773 static int pci_netmos_9900_setup(struct serial_private *priv,
774 const struct pciserial_board *board,
775 struct uart_8250_port *port, int idx)
779 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
780 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
781 /* netmos apparently orders BARs by datasheet layout, so serial
782 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
786 return setup_port(priv, port, bar, 0, board->reg_shift);
788 return pci_default_setup(priv, board, port, idx);
792 /* the 99xx series comes with a range of device IDs and a variety
795 * 9900 has varying capabilities and can cascade to sub-controllers
796 * (cascading should be purely internal)
797 * 9904 is hardwired with 4 serial ports
798 * 9912 and 9922 are hardwired with 2 serial ports
800 static int pci_netmos_9900_numports(struct pci_dev *dev)
802 unsigned int c = dev->class;
804 unsigned short sub_serports;
810 } else if ((pi == 0) &&
811 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
812 /* two possibilities: 0x30ps encodes number of parallel and
813 * serial ports, or 0x1000 indicates *something*. This is not
814 * immediately obvious, since the 2s1p+4s configuration seems
815 * to offer all functionality on functions 0..2, while still
816 * advertising the same function 3 as the 4s+2s1p config.
818 sub_serports = dev->subsystem_device & 0xf;
819 if (sub_serports > 0) {
822 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
827 moan_device("unknown NetMos/Mostech program interface", dev);
831 static int pci_netmos_init(struct pci_dev *dev)
833 /* subdevice 0x00PS means <P> parallel, <S> serial */
834 unsigned int num_serial = dev->subsystem_device & 0xf;
836 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
837 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
840 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
841 dev->subsystem_device == 0x0299)
844 switch (dev->device) { /* FALLTHROUGH on all */
845 case PCI_DEVICE_ID_NETMOS_9904:
846 case PCI_DEVICE_ID_NETMOS_9912:
847 case PCI_DEVICE_ID_NETMOS_9922:
848 case PCI_DEVICE_ID_NETMOS_9900:
849 num_serial = pci_netmos_9900_numports(dev);
853 if (num_serial == 0 ) {
854 moan_device("unknown NetMos/Mostech device", dev);
865 * These chips are available with optionally one parallel port and up to
866 * two serial ports. Unfortunately they all have the same product id.
868 * Basic configuration is done over a region of 32 I/O ports. The base
869 * ioport is called INTA or INTC, depending on docs/other drivers.
871 * The region of the 32 I/O ports is configured in POSIO0R...
875 #define ITE_887x_MISCR 0x9c
876 #define ITE_887x_INTCBAR 0x78
877 #define ITE_887x_UARTBAR 0x7c
878 #define ITE_887x_PS0BAR 0x10
879 #define ITE_887x_POSIO0 0x60
882 #define ITE_887x_IOSIZE 32
883 /* I/O space size (bits 26-24; 8 bytes = 011b) */
884 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
885 /* I/O space size (bits 26-24; 32 bytes = 101b) */
886 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
887 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
888 #define ITE_887x_POSIO_SPEED (3 << 29)
889 /* enable IO_Space bit */
890 #define ITE_887x_POSIO_ENABLE (1 << 31)
892 static int pci_ite887x_init(struct pci_dev *dev)
894 /* inta_addr are the configuration addresses of the ITE */
895 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
898 struct resource *iobase = NULL;
899 u32 miscr, uartbar, ioport;
901 /* search for the base-ioport */
903 while (inta_addr[i] && iobase == NULL) {
904 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 if (iobase != NULL) {
907 /* write POSIO0R - speed | size | ioport */
908 pci_write_config_dword(dev, ITE_887x_POSIO0,
909 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
910 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
911 /* write INTCBAR - ioport */
912 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 ret = inb(inta_addr[i]);
916 /* ioport connected */
919 release_region(iobase->start, ITE_887x_IOSIZE);
926 dev_err(&dev->dev, "ite887x: could not find iobase\n");
930 /* start of undocumented type checking (see parport_pc.c) */
931 type = inb(iobase->start + 0x18) & 0x0f;
934 case 0x2: /* ITE8871 (1P) */
935 case 0xa: /* ITE8875 (1P) */
938 case 0xe: /* ITE8872 (2S1P) */
941 case 0x6: /* ITE8873 (1S) */
944 case 0x8: /* ITE8874 (2S) */
948 moan_device("Unknown ITE887x", dev);
952 /* configure all serial ports */
953 for (i = 0; i < ret; i++) {
954 /* read the I/O port from the device */
955 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 ioport &= 0x0000FF00; /* the actual base address */
958 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
959 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
960 ITE_887x_POSIO_IOSIZE_8 | ioport);
962 /* write the ioport to the UARTBAR */
963 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
964 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
965 uartbar |= (ioport << (16 * i)); /* set the ioport */
966 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968 /* get current config */
969 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
970 /* disable interrupts (UARTx_Routing[3:0]) */
971 miscr &= ~(0xf << (12 - 4 * i));
972 /* activate the UART (UARTx_En) */
973 miscr |= 1 << (23 - i);
974 /* write new config with activated UART */
975 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
979 /* the device has no UARTs if we get here */
980 release_region(iobase->start, ITE_887x_IOSIZE);
986 static void pci_ite887x_exit(struct pci_dev *dev)
989 /* the ioport is bit 0-15 in POSIO0R */
990 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 release_region(ioport, ITE_887x_IOSIZE);
996 * EndRun Technologies.
997 * Determine the number of ports available on the device.
999 #define PCI_VENDOR_ID_ENDRUN 0x7401
1000 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002 static int pci_endrun_init(struct pci_dev *dev)
1005 unsigned long deviceID;
1006 unsigned int number_uarts = 0;
1008 /* EndRun device is all 0xexxx */
1009 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1010 (dev->device & 0xf000) != 0xe000)
1013 p = pci_iomap(dev, 0, 5);
1017 deviceID = ioread32(p);
1019 if (deviceID == 0x07000200) {
1020 number_uarts = ioread8(p + 4);
1022 "%d ports detected on EndRun PCI Express device\n",
1025 pci_iounmap(dev, p);
1026 return number_uarts;
1030 * Oxford Semiconductor Inc.
1031 * Check that device is part of the Tornado range of devices, then determine
1032 * the number of ports available on the device.
1034 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1037 unsigned long deviceID;
1038 unsigned int number_uarts = 0;
1040 /* OxSemi Tornado devices are all 0xCxxx */
1041 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1042 (dev->device & 0xF000) != 0xC000)
1045 p = pci_iomap(dev, 0, 5);
1049 deviceID = ioread32(p);
1050 /* Tornado device */
1051 if (deviceID == 0x07000200) {
1052 number_uarts = ioread8(p + 4);
1054 "%d ports detected on Oxford PCI Express device\n",
1057 pci_iounmap(dev, p);
1058 return number_uarts;
1061 static int pci_asix_setup(struct serial_private *priv,
1062 const struct pciserial_board *board,
1063 struct uart_8250_port *port, int idx)
1065 port->bugs |= UART_BUG_PARITY;
1066 return pci_default_setup(priv, board, port, idx);
1069 /* Quatech devices have their own extra interface features */
1071 struct quatech_feature {
1076 #define QPCR_TEST_FOR1 0x3F
1077 #define QPCR_TEST_GET1 0x00
1078 #define QPCR_TEST_FOR2 0x40
1079 #define QPCR_TEST_GET2 0x40
1080 #define QPCR_TEST_FOR3 0x80
1081 #define QPCR_TEST_GET3 0x40
1082 #define QPCR_TEST_FOR4 0xC0
1083 #define QPCR_TEST_GET4 0x80
1085 #define QOPR_CLOCK_X1 0x0000
1086 #define QOPR_CLOCK_X2 0x0001
1087 #define QOPR_CLOCK_X4 0x0002
1088 #define QOPR_CLOCK_X8 0x0003
1089 #define QOPR_CLOCK_RATE_MASK 0x0003
1092 static struct quatech_feature quatech_cards[] = {
1093 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1100 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1115 static int pci_quatech_amcc(u16 devid)
1117 struct quatech_feature *qf = &quatech_cards[0];
1119 if (qf->devid == devid)
1123 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1127 static int pci_quatech_rqopr(struct uart_8250_port *port)
1129 unsigned long base = port->port.iobase;
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1139 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141 unsigned long base = port->port.iobase;
1144 LCR = inb(base + UART_LCR);
1145 outb(0xBF, base + UART_LCR);
1146 val = inb(base + UART_SCR);
1147 outb(qopr, base + UART_SCR);
1148 outb(LCR, base + UART_LCR);
1151 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153 unsigned long base = port->port.iobase;
1156 LCR = inb(base + UART_LCR);
1157 outb(0xBF, base + UART_LCR);
1158 val = inb(base + UART_SCR);
1159 outb(val | 0x10, base + UART_SCR);
1160 qmcr = inb(base + UART_MCR);
1161 outb(val, base + UART_SCR);
1162 outb(LCR, base + UART_LCR);
1167 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169 unsigned long base = port->port.iobase;
1172 LCR = inb(base + UART_LCR);
1173 outb(0xBF, base + UART_LCR);
1174 val = inb(base + UART_SCR);
1175 outb(val | 0x10, base + UART_SCR);
1176 outb(qmcr, base + UART_MCR);
1177 outb(val, base + UART_SCR);
1178 outb(LCR, base + UART_LCR);
1181 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183 unsigned long base = port->port.iobase;
1186 LCR = inb(base + UART_LCR);
1187 outb(0xBF, base + UART_LCR);
1188 val = inb(base + UART_SCR);
1190 outb(0x80, UART_LCR);
1191 if (!(inb(UART_SCR) & 0x20)) {
1192 outb(LCR, base + UART_LCR);
1199 static int pci_quatech_test(struct uart_8250_port *port)
1202 u8 qopr = pci_quatech_rqopr(port);
1203 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET1)
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET2)
1211 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1212 reg = pci_quatech_rqopr(port) & 0xC0;
1213 if (reg != QPCR_TEST_GET3)
1215 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1216 reg = pci_quatech_rqopr(port) & 0xC0;
1217 if (reg != QPCR_TEST_GET4)
1220 pci_quatech_wqopr(port, qopr);
1224 static int pci_quatech_clock(struct uart_8250_port *port)
1227 unsigned long clock;
1229 if (pci_quatech_test(port) < 0)
1232 qopr = pci_quatech_rqopr(port);
1234 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1235 reg = pci_quatech_rqopr(port);
1236 if (reg & QOPR_CLOCK_X8) {
1240 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1241 reg = pci_quatech_rqopr(port);
1242 if (!(reg & QOPR_CLOCK_X8)) {
1246 reg &= QOPR_CLOCK_X8;
1247 if (reg == QOPR_CLOCK_X2) {
1249 set = QOPR_CLOCK_X2;
1250 } else if (reg == QOPR_CLOCK_X4) {
1252 set = QOPR_CLOCK_X4;
1253 } else if (reg == QOPR_CLOCK_X8) {
1255 set = QOPR_CLOCK_X8;
1258 set = QOPR_CLOCK_X1;
1260 qopr &= ~QOPR_CLOCK_RATE_MASK;
1264 pci_quatech_wqopr(port, qopr);
1268 static int pci_quatech_rs422(struct uart_8250_port *port)
1273 if (!pci_quatech_has_qmcr(port))
1275 qmcr = pci_quatech_rqmcr(port);
1276 pci_quatech_wqmcr(port, 0xFF);
1277 if (pci_quatech_rqmcr(port))
1279 pci_quatech_wqmcr(port, qmcr);
1283 static int pci_quatech_init(struct pci_dev *dev)
1285 if (pci_quatech_amcc(dev->device)) {
1286 unsigned long base = pci_resource_start(dev, 0);
1289 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1290 tmp = inl(base + 0x3c);
1291 outl(tmp | 0x01000000, base + 0x3c);
1292 outl(tmp &= ~0x01000000, base + 0x3c);
1298 static int pci_quatech_setup(struct serial_private *priv,
1299 const struct pciserial_board *board,
1300 struct uart_8250_port *port, int idx)
1302 /* Needed by pci_quatech calls below */
1303 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1304 /* Set up the clocking */
1305 port->port.uartclk = pci_quatech_clock(port);
1306 /* For now just warn about RS422 */
1307 if (pci_quatech_rs422(port))
1308 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1309 return pci_default_setup(priv, board, port, idx);
1312 static void pci_quatech_exit(struct pci_dev *dev)
1316 static int pci_default_setup(struct serial_private *priv,
1317 const struct pciserial_board *board,
1318 struct uart_8250_port *port, int idx)
1320 unsigned int bar, offset = board->first_offset, maxnr;
1322 bar = FL_GET_BASE(board->flags);
1323 if (board->flags & FL_BASE_BARS)
1326 offset += idx * board->uart_offset;
1328 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1329 (board->reg_shift + 3);
1331 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1334 return setup_port(priv, port, bar, offset, board->reg_shift);
1337 static int pci_pericom_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1341 unsigned int bar, offset = board->first_offset, maxnr;
1343 bar = FL_GET_BASE(board->flags);
1344 if (board->flags & FL_BASE_BARS)
1347 offset += idx * board->uart_offset;
1349 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1350 (board->reg_shift + 3);
1352 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1355 port->port.uartclk = 14745600;
1357 return setup_port(priv, port, bar, offset, board->reg_shift);
1361 ce4100_serial_setup(struct serial_private *priv,
1362 const struct pciserial_board *board,
1363 struct uart_8250_port *port, int idx)
1367 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1368 port->port.iotype = UPIO_MEM32;
1369 port->port.type = PORT_XSCALE;
1370 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1371 port->port.regshift = 2;
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1377 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1380 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1383 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1385 #define BYT_PRV_CLK 0x800
1386 #define BYT_PRV_CLK_EN (1 << 0)
1387 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1388 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1389 #define BYT_PRV_CLK_UPDATE (1 << 31)
1391 #define BYT_TX_OVF_INT 0x820
1392 #define BYT_TX_OVF_INT_MASK (1 << 1)
1395 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1396 struct ktermios *old)
1398 unsigned int baud = tty_termios_baud_rate(termios);
1399 unsigned long fref = 100000000, fuart = baud * 16;
1400 unsigned long w = BIT(15) - 1;
1404 /* Get Fuart closer to Fref */
1405 fuart *= rounddown_pow_of_two(fref / fuart);
1408 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1409 * dividers must be adjusted.
1411 * uartclk = (m / n) * 100 MHz, where m <= n
1413 rational_best_approximation(fuart, fref, w, w, &m, &n);
1416 /* Reset the clock */
1417 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1420 writel(reg, p->membase + BYT_PRV_CLK);
1422 p->status &= ~UPSTAT_AUTOCTS;
1423 if (termios->c_cflag & CRTSCTS)
1424 p->status |= UPSTAT_AUTOCTS;
1426 serial8250_do_set_termios(p, termios, old);
1429 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1431 struct dw_dma_slave *dws = param;
1433 if (dws->dma_dev != chan->device->dev)
1436 chan->private = dws;
1441 byt_serial_setup(struct serial_private *priv,
1442 const struct pciserial_board *board,
1443 struct uart_8250_port *port, int idx)
1445 struct pci_dev *pdev = priv->dev;
1446 struct device *dev = port->port.dev;
1447 struct uart_8250_dma *dma;
1448 struct dw_dma_slave *tx_param, *rx_param;
1449 struct pci_dev *dma_dev;
1452 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1456 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1460 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1464 switch (pdev->device) {
1465 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1466 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1467 case PCI_DEVICE_ID_INTEL_BDW_UART1:
1468 rx_param->src_id = 3;
1469 tx_param->dst_id = 2;
1471 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1472 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1473 case PCI_DEVICE_ID_INTEL_BDW_UART2:
1474 rx_param->src_id = 5;
1475 tx_param->dst_id = 4;
1481 rx_param->src_master = 1;
1482 rx_param->dst_master = 0;
1484 dma->rxconf.src_maxburst = 16;
1486 tx_param->src_master = 1;
1487 tx_param->dst_master = 0;
1489 dma->txconf.dst_maxburst = 16;
1491 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1492 rx_param->dma_dev = &dma_dev->dev;
1493 tx_param->dma_dev = &dma_dev->dev;
1495 dma->fn = byt_dma_filter;
1496 dma->rx_param = rx_param;
1497 dma->tx_param = tx_param;
1499 ret = pci_default_setup(priv, board, port, idx);
1500 port->port.iotype = UPIO_MEM;
1501 port->port.type = PORT_16550A;
1502 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1503 port->port.set_termios = byt_set_termios;
1504 port->port.fifosize = 64;
1505 port->tx_loadsz = 64;
1507 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1509 /* Disable Tx counter interrupts */
1510 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1516 pci_omegapci_setup(struct serial_private *priv,
1517 const struct pciserial_board *board,
1518 struct uart_8250_port *port, int idx)
1520 return setup_port(priv, port, 2, idx * 8, 0);
1524 pci_brcm_trumanage_setup(struct serial_private *priv,
1525 const struct pciserial_board *board,
1526 struct uart_8250_port *port, int idx)
1528 int ret = pci_default_setup(priv, board, port, idx);
1530 port->port.type = PORT_BRCM_TRUMANAGE;
1531 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1535 /* RTS will control by MCR if this bit is 0 */
1536 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1537 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1538 #define FINTEK_RTS_INVERT BIT(5)
1540 /* We should do proper H/W transceiver setting before change to RS485 mode */
1541 static int pci_fintek_rs485_config(struct uart_port *port,
1542 struct serial_rs485 *rs485)
1545 u8 *index = (u8 *) port->private_data;
1546 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1549 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1552 rs485 = &port->rs485;
1553 else if (rs485->flags & SER_RS485_ENABLED)
1554 memset(rs485->padding, 0, sizeof(rs485->padding));
1556 memset(rs485, 0, sizeof(*rs485));
1558 /* F81504/508/512 not support RTS delay before or after send */
1559 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1561 if (rs485->flags & SER_RS485_ENABLED) {
1562 /* Enable RTS H/W control mode */
1563 setting |= FINTEK_RTS_CONTROL_BY_HW;
1565 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1566 /* RTS driving high on TX */
1567 setting &= ~FINTEK_RTS_INVERT;
1569 /* RTS driving low on TX */
1570 setting |= FINTEK_RTS_INVERT;
1573 rs485->delay_rts_after_send = 0;
1574 rs485->delay_rts_before_send = 0;
1576 /* Disable RTS H/W control mode */
1577 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1580 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1582 if (rs485 != &port->rs485)
1583 port->rs485 = *rs485;
1588 static int pci_fintek_setup(struct serial_private *priv,
1589 const struct pciserial_board *board,
1590 struct uart_8250_port *port, int idx)
1592 struct pci_dev *pdev = priv->dev;
1597 config_base = 0x40 + 0x08 * idx;
1599 /* Get the io address from configuration space */
1600 pci_read_config_word(pdev, config_base + 4, &iobase);
1602 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1604 port->port.iotype = UPIO_PORT;
1605 port->port.iobase = iobase;
1606 port->port.rs485_config = pci_fintek_rs485_config;
1608 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1612 /* preserve index in PCI configuration space */
1614 port->port.private_data = data;
1619 static int pci_fintek_init(struct pci_dev *dev)
1621 unsigned long iobase;
1625 struct serial_private *priv = pci_get_drvdata(dev);
1626 struct uart_8250_port *port;
1628 switch (dev->device) {
1629 case 0x1104: /* 4 ports */
1630 case 0x1108: /* 8 ports */
1631 max_port = dev->device & 0xff;
1633 case 0x1112: /* 12 ports */
1640 /* Get the io address dispatch from the BIOS */
1641 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1642 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1643 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1645 for (i = 0; i < max_port; ++i) {
1646 /* UART0 configuration offset start from 0x40 */
1647 config_base = 0x40 + 0x08 * i;
1649 /* Calculate Real IO Port */
1650 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1652 /* Enable UART I/O port */
1653 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1655 /* Select 128-byte FIFO and 8x FIFO threshold */
1656 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1659 pci_write_config_byte(dev, config_base + 0x04,
1660 (u8)(iobase & 0xff));
1663 pci_write_config_byte(dev, config_base + 0x05,
1664 (u8)((iobase & 0xff00) >> 8));
1666 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1669 /* re-apply RS232/485 mode when
1670 * pciserial_resume_ports()
1672 port = serial8250_get_port(priv->line[i]);
1673 pci_fintek_rs485_config(&port->port, NULL);
1675 /* First init without port data
1676 * force init to RS232 Mode
1678 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1685 static int skip_tx_en_setup(struct serial_private *priv,
1686 const struct pciserial_board *board,
1687 struct uart_8250_port *port, int idx)
1689 port->port.flags |= UPF_NO_TXEN_TEST;
1690 dev_dbg(&priv->dev->dev,
1691 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1692 priv->dev->vendor, priv->dev->device,
1693 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1695 return pci_default_setup(priv, board, port, idx);
1698 static void kt_handle_break(struct uart_port *p)
1700 struct uart_8250_port *up = up_to_u8250p(p);
1702 * On receipt of a BI, serial device in Intel ME (Intel
1703 * management engine) needs to have its fifos cleared for sane
1704 * SOL (Serial Over Lan) output.
1706 serial8250_clear_and_reinit_fifos(up);
1709 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1711 struct uart_8250_port *up = up_to_u8250p(p);
1715 * When the Intel ME (management engine) gets reset its serial
1716 * port registers could return 0 momentarily. Functions like
1717 * serial8250_console_write, read and save the IER, perform
1718 * some operation and then restore it. In order to avoid
1719 * setting IER register inadvertently to 0, if the value read
1720 * is 0, double check with ier value in uart_8250_port and use
1721 * that instead. up->ier should be the same value as what is
1722 * currently configured.
1724 val = inb(p->iobase + offset);
1725 if (offset == UART_IER) {
1732 static int kt_serial_setup(struct serial_private *priv,
1733 const struct pciserial_board *board,
1734 struct uart_8250_port *port, int idx)
1736 port->port.flags |= UPF_BUG_THRE;
1737 port->port.serial_in = kt_serial_in;
1738 port->port.handle_break = kt_handle_break;
1739 return skip_tx_en_setup(priv, board, port, idx);
1742 static int pci_eg20t_init(struct pci_dev *dev)
1744 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1751 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1752 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1755 pci_xr17c154_setup(struct serial_private *priv,
1756 const struct pciserial_board *board,
1757 struct uart_8250_port *port, int idx)
1759 port->port.flags |= UPF_EXAR_EFR;
1760 return pci_default_setup(priv, board, port, idx);
1764 xr17v35x_has_slave(struct serial_private *priv)
1766 const int dev_id = priv->dev->device;
1768 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1769 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1773 pci_xr17v35x_setup(struct serial_private *priv,
1774 const struct pciserial_board *board,
1775 struct uart_8250_port *port, int idx)
1779 p = pci_ioremap_bar(priv->dev, 0);
1783 port->port.flags |= UPF_EXAR_EFR;
1786 * Setup the uart clock for the devices on expansion slot to
1787 * half the clock speed of the main chip (which is 125MHz)
1789 if (xr17v35x_has_slave(priv) && idx >= 8)
1790 port->port.uartclk = (7812500 * 16 / 2);
1793 * Setup Multipurpose Input/Output pins.
1796 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1797 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1798 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1799 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1800 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1801 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1802 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1803 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1804 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1805 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1806 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1807 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1809 writeb(0x00, p + UART_EXAR_8XMODE);
1810 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1811 writeb(128, p + UART_EXAR_TXTRG);
1812 writeb(128, p + UART_EXAR_RXTRG);
1815 return pci_default_setup(priv, board, port, idx);
1818 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1819 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1820 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1821 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1824 pci_fastcom335_setup(struct serial_private *priv,
1825 const struct pciserial_board *board,
1826 struct uart_8250_port *port, int idx)
1830 p = pci_ioremap_bar(priv->dev, 0);
1834 port->port.flags |= UPF_EXAR_EFR;
1837 * Setup Multipurpose Input/Output pins.
1840 switch (priv->dev->device) {
1841 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1842 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1843 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1844 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1845 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1847 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1848 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1849 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1850 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1851 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1854 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1855 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1856 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1858 writeb(0x00, p + UART_EXAR_8XMODE);
1859 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1860 writeb(32, p + UART_EXAR_TXTRG);
1861 writeb(32, p + UART_EXAR_RXTRG);
1864 return pci_default_setup(priv, board, port, idx);
1868 pci_wch_ch353_setup(struct serial_private *priv,
1869 const struct pciserial_board *board,
1870 struct uart_8250_port *port, int idx)
1872 port->port.flags |= UPF_FIXED_TYPE;
1873 port->port.type = PORT_16550A;
1874 return pci_default_setup(priv, board, port, idx);
1878 pci_wch_ch38x_setup(struct serial_private *priv,
1879 const struct pciserial_board *board,
1880 struct uart_8250_port *port, int idx)
1882 port->port.flags |= UPF_FIXED_TYPE;
1883 port->port.type = PORT_16850;
1884 return pci_default_setup(priv, board, port, idx);
1887 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1888 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1889 #define PCI_DEVICE_ID_OCTPRO 0x0001
1890 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1891 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1892 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1893 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1894 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1895 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1896 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1897 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1898 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1899 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1900 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1901 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1902 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1903 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1904 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1905 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1906 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1907 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1908 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1909 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1910 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1911 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1912 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1913 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1914 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1915 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1916 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1917 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1918 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1919 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1920 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1921 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1922 #define PCI_VENDOR_ID_WCH 0x4348
1923 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1924 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1925 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1926 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1927 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1928 #define PCI_VENDOR_ID_AGESTAR 0x5372
1929 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1930 #define PCI_VENDOR_ID_ASIX 0x9710
1931 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1932 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1933 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1934 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1935 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1936 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1938 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1939 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1941 #define PCIE_VENDOR_ID_WCH 0x1c00
1942 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1943 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1945 #define PCI_VENDOR_ID_PERICOM 0x12D8
1946 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1947 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1948 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1949 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1951 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1952 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1953 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1956 * Master list of serial port init/setup/exit quirks.
1957 * This does not describe the general nature of the port.
1958 * (ie, baud base, number and location of ports, etc)
1960 * This list is ordered alphabetically by vendor then device.
1961 * Specific entries must come before more generic entries.
1963 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1965 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1968 .vendor = PCI_VENDOR_ID_AMCC,
1969 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1970 .subvendor = PCI_ANY_ID,
1971 .subdevice = PCI_ANY_ID,
1972 .setup = addidata_apci7800_setup,
1975 * AFAVLAB cards - these may be called via parport_serial
1976 * It is not clear whether this applies to all products.
1979 .vendor = PCI_VENDOR_ID_AFAVLAB,
1980 .device = PCI_ANY_ID,
1981 .subvendor = PCI_ANY_ID,
1982 .subdevice = PCI_ANY_ID,
1983 .setup = afavlab_setup,
1989 .vendor = PCI_VENDOR_ID_HP,
1990 .device = PCI_DEVICE_ID_HP_DIVA,
1991 .subvendor = PCI_ANY_ID,
1992 .subdevice = PCI_ANY_ID,
1993 .init = pci_hp_diva_init,
1994 .setup = pci_hp_diva_setup,
2000 .vendor = PCI_VENDOR_ID_INTEL,
2001 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2002 .subvendor = 0xe4bf,
2003 .subdevice = PCI_ANY_ID,
2004 .init = pci_inteli960ni_init,
2005 .setup = pci_default_setup,
2008 .vendor = PCI_VENDOR_ID_INTEL,
2009 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = skip_tx_en_setup,
2015 .vendor = PCI_VENDOR_ID_INTEL,
2016 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = skip_tx_en_setup,
2022 .vendor = PCI_VENDOR_ID_INTEL,
2023 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = skip_tx_en_setup,
2029 .vendor = PCI_VENDOR_ID_INTEL,
2030 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .setup = ce4100_serial_setup,
2036 .vendor = PCI_VENDOR_ID_INTEL,
2037 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2038 .subvendor = PCI_ANY_ID,
2039 .subdevice = PCI_ANY_ID,
2040 .setup = kt_serial_setup,
2043 .vendor = PCI_VENDOR_ID_INTEL,
2044 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2045 .subvendor = PCI_ANY_ID,
2046 .subdevice = PCI_ANY_ID,
2047 .setup = byt_serial_setup,
2050 .vendor = PCI_VENDOR_ID_INTEL,
2051 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2052 .subvendor = PCI_ANY_ID,
2053 .subdevice = PCI_ANY_ID,
2054 .setup = byt_serial_setup,
2057 .vendor = PCI_VENDOR_ID_INTEL,
2058 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2059 .subvendor = PCI_ANY_ID,
2060 .subdevice = PCI_ANY_ID,
2061 .setup = byt_serial_setup,
2064 .vendor = PCI_VENDOR_ID_INTEL,
2065 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2066 .subvendor = PCI_ANY_ID,
2067 .subdevice = PCI_ANY_ID,
2068 .setup = byt_serial_setup,
2071 .vendor = PCI_VENDOR_ID_INTEL,
2072 .device = PCI_DEVICE_ID_INTEL_BDW_UART1,
2073 .subvendor = PCI_ANY_ID,
2074 .subdevice = PCI_ANY_ID,
2075 .setup = byt_serial_setup,
2078 .vendor = PCI_VENDOR_ID_INTEL,
2079 .device = PCI_DEVICE_ID_INTEL_BDW_UART2,
2080 .subvendor = PCI_ANY_ID,
2081 .subdevice = PCI_ANY_ID,
2082 .setup = byt_serial_setup,
2088 .vendor = PCI_VENDOR_ID_ITE,
2089 .device = PCI_DEVICE_ID_ITE_8872,
2090 .subvendor = PCI_ANY_ID,
2091 .subdevice = PCI_ANY_ID,
2092 .init = pci_ite887x_init,
2093 .setup = pci_default_setup,
2094 .exit = pci_ite887x_exit,
2097 * National Instruments
2100 .vendor = PCI_VENDOR_ID_NI,
2101 .device = PCI_DEVICE_ID_NI_PCI23216,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .init = pci_ni8420_init,
2105 .setup = pci_default_setup,
2106 .exit = pci_ni8420_exit,
2109 .vendor = PCI_VENDOR_ID_NI,
2110 .device = PCI_DEVICE_ID_NI_PCI2328,
2111 .subvendor = PCI_ANY_ID,
2112 .subdevice = PCI_ANY_ID,
2113 .init = pci_ni8420_init,
2114 .setup = pci_default_setup,
2115 .exit = pci_ni8420_exit,
2118 .vendor = PCI_VENDOR_ID_NI,
2119 .device = PCI_DEVICE_ID_NI_PCI2324,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .init = pci_ni8420_init,
2123 .setup = pci_default_setup,
2124 .exit = pci_ni8420_exit,
2127 .vendor = PCI_VENDOR_ID_NI,
2128 .device = PCI_DEVICE_ID_NI_PCI2322,
2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
2131 .init = pci_ni8420_init,
2132 .setup = pci_default_setup,
2133 .exit = pci_ni8420_exit,
2136 .vendor = PCI_VENDOR_ID_NI,
2137 .device = PCI_DEVICE_ID_NI_PCI2324I,
2138 .subvendor = PCI_ANY_ID,
2139 .subdevice = PCI_ANY_ID,
2140 .init = pci_ni8420_init,
2141 .setup = pci_default_setup,
2142 .exit = pci_ni8420_exit,
2145 .vendor = PCI_VENDOR_ID_NI,
2146 .device = PCI_DEVICE_ID_NI_PCI2322I,
2147 .subvendor = PCI_ANY_ID,
2148 .subdevice = PCI_ANY_ID,
2149 .init = pci_ni8420_init,
2150 .setup = pci_default_setup,
2151 .exit = pci_ni8420_exit,
2154 .vendor = PCI_VENDOR_ID_NI,
2155 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2156 .subvendor = PCI_ANY_ID,
2157 .subdevice = PCI_ANY_ID,
2158 .init = pci_ni8420_init,
2159 .setup = pci_default_setup,
2160 .exit = pci_ni8420_exit,
2163 .vendor = PCI_VENDOR_ID_NI,
2164 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2165 .subvendor = PCI_ANY_ID,
2166 .subdevice = PCI_ANY_ID,
2167 .init = pci_ni8420_init,
2168 .setup = pci_default_setup,
2169 .exit = pci_ni8420_exit,
2172 .vendor = PCI_VENDOR_ID_NI,
2173 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2174 .subvendor = PCI_ANY_ID,
2175 .subdevice = PCI_ANY_ID,
2176 .init = pci_ni8420_init,
2177 .setup = pci_default_setup,
2178 .exit = pci_ni8420_exit,
2181 .vendor = PCI_VENDOR_ID_NI,
2182 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_ni8420_init,
2186 .setup = pci_default_setup,
2187 .exit = pci_ni8420_exit,
2190 .vendor = PCI_VENDOR_ID_NI,
2191 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_ni8420_init,
2195 .setup = pci_default_setup,
2196 .exit = pci_ni8420_exit,
2199 .vendor = PCI_VENDOR_ID_NI,
2200 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .init = pci_ni8420_init,
2204 .setup = pci_default_setup,
2205 .exit = pci_ni8420_exit,
2208 .vendor = PCI_VENDOR_ID_NI,
2209 .device = PCI_ANY_ID,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .init = pci_ni8430_init,
2213 .setup = pci_ni8430_setup,
2214 .exit = pci_ni8430_exit,
2218 .vendor = PCI_VENDOR_ID_QUATECH,
2219 .device = PCI_ANY_ID,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .init = pci_quatech_init,
2223 .setup = pci_quatech_setup,
2224 .exit = pci_quatech_exit,
2230 .vendor = PCI_VENDOR_ID_PANACOM,
2231 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .init = pci_plx9050_init,
2235 .setup = pci_default_setup,
2236 .exit = pci_plx9050_exit,
2239 .vendor = PCI_VENDOR_ID_PANACOM,
2240 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2241 .subvendor = PCI_ANY_ID,
2242 .subdevice = PCI_ANY_ID,
2243 .init = pci_plx9050_init,
2244 .setup = pci_default_setup,
2245 .exit = pci_plx9050_exit,
2251 .vendor = PCI_VENDOR_ID_PERICOM,
2252 .device = PCI_ANY_ID,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_pericom_setup,
2261 .vendor = PCI_VENDOR_ID_PLX,
2262 .device = PCI_DEVICE_ID_PLX_9050,
2263 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2264 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2265 .init = pci_plx9050_init,
2266 .setup = pci_default_setup,
2267 .exit = pci_plx9050_exit,
2270 .vendor = PCI_VENDOR_ID_PLX,
2271 .device = PCI_DEVICE_ID_PLX_9050,
2272 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2273 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2274 .init = pci_plx9050_init,
2275 .setup = pci_default_setup,
2276 .exit = pci_plx9050_exit,
2279 .vendor = PCI_VENDOR_ID_PLX,
2280 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2281 .subvendor = PCI_VENDOR_ID_PLX,
2282 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2283 .init = pci_plx9050_init,
2284 .setup = pci_default_setup,
2285 .exit = pci_plx9050_exit,
2288 * SBS Technologies, Inc., PMC-OCTALPRO 232
2291 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2292 .device = PCI_DEVICE_ID_OCTPRO,
2293 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2294 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2300 * SBS Technologies, Inc., PMC-OCTALPRO 422
2303 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2304 .device = PCI_DEVICE_ID_OCTPRO,
2305 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2306 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2312 * SBS Technologies, Inc., P-Octal 232
2315 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2316 .device = PCI_DEVICE_ID_OCTPRO,
2317 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2318 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2324 * SBS Technologies, Inc., P-Octal 422
2327 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2328 .device = PCI_DEVICE_ID_OCTPRO,
2329 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2330 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2336 * SIIG cards - these may be called via parport_serial
2339 .vendor = PCI_VENDOR_ID_SIIG,
2340 .device = PCI_ANY_ID,
2341 .subvendor = PCI_ANY_ID,
2342 .subdevice = PCI_ANY_ID,
2343 .init = pci_siig_init,
2344 .setup = pci_siig_setup,
2350 .vendor = PCI_VENDOR_ID_TITAN,
2351 .device = PCI_DEVICE_ID_TITAN_400L,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .setup = titan_400l_800l_setup,
2357 .vendor = PCI_VENDOR_ID_TITAN,
2358 .device = PCI_DEVICE_ID_TITAN_800L,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .setup = titan_400l_800l_setup,
2367 .vendor = PCI_VENDOR_ID_TIMEDIA,
2368 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2369 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2370 .subdevice = PCI_ANY_ID,
2371 .probe = pci_timedia_probe,
2372 .init = pci_timedia_init,
2373 .setup = pci_timedia_setup,
2376 .vendor = PCI_VENDOR_ID_TIMEDIA,
2377 .device = PCI_ANY_ID,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .setup = pci_timedia_setup,
2383 * SUNIX (Timedia) cards
2384 * Do not "probe" for these cards as there is at least one combination
2385 * card that should be handled by parport_pc that doesn't match the
2386 * rule in pci_timedia_probe.
2387 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2388 * There are some boards with part number SER5037AL that report
2389 * subdevice ID 0x0002.
2392 .vendor = PCI_VENDOR_ID_SUNIX,
2393 .device = PCI_DEVICE_ID_SUNIX_1999,
2394 .subvendor = PCI_VENDOR_ID_SUNIX,
2395 .subdevice = PCI_ANY_ID,
2396 .init = pci_timedia_init,
2397 .setup = pci_timedia_setup,
2403 .vendor = PCI_VENDOR_ID_EXAR,
2404 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2405 .subvendor = PCI_ANY_ID,
2406 .subdevice = PCI_ANY_ID,
2407 .setup = pci_xr17c154_setup,
2410 .vendor = PCI_VENDOR_ID_EXAR,
2411 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
2414 .setup = pci_xr17c154_setup,
2417 .vendor = PCI_VENDOR_ID_EXAR,
2418 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .setup = pci_xr17c154_setup,
2424 .vendor = PCI_VENDOR_ID_EXAR,
2425 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2426 .subvendor = PCI_ANY_ID,
2427 .subdevice = PCI_ANY_ID,
2428 .setup = pci_xr17v35x_setup,
2431 .vendor = PCI_VENDOR_ID_EXAR,
2432 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2433 .subvendor = PCI_ANY_ID,
2434 .subdevice = PCI_ANY_ID,
2435 .setup = pci_xr17v35x_setup,
2438 .vendor = PCI_VENDOR_ID_EXAR,
2439 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2440 .subvendor = PCI_ANY_ID,
2441 .subdevice = PCI_ANY_ID,
2442 .setup = pci_xr17v35x_setup,
2445 .vendor = PCI_VENDOR_ID_EXAR,
2446 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_xr17v35x_setup,
2452 .vendor = PCI_VENDOR_ID_EXAR,
2453 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2454 .subvendor = PCI_ANY_ID,
2455 .subdevice = PCI_ANY_ID,
2456 .setup = pci_xr17v35x_setup,
2462 .vendor = PCI_VENDOR_ID_XIRCOM,
2463 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2464 .subvendor = PCI_ANY_ID,
2465 .subdevice = PCI_ANY_ID,
2466 .init = pci_xircom_init,
2467 .setup = pci_default_setup,
2470 * Netmos cards - these may be called via parport_serial
2473 .vendor = PCI_VENDOR_ID_NETMOS,
2474 .device = PCI_ANY_ID,
2475 .subvendor = PCI_ANY_ID,
2476 .subdevice = PCI_ANY_ID,
2477 .init = pci_netmos_init,
2478 .setup = pci_netmos_9900_setup,
2481 * EndRun Technologies
2484 .vendor = PCI_VENDOR_ID_ENDRUN,
2485 .device = PCI_ANY_ID,
2486 .subvendor = PCI_ANY_ID,
2487 .subdevice = PCI_ANY_ID,
2488 .init = pci_endrun_init,
2489 .setup = pci_default_setup,
2492 * For Oxford Semiconductor Tornado based devices
2495 .vendor = PCI_VENDOR_ID_OXSEMI,
2496 .device = PCI_ANY_ID,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .init = pci_oxsemi_tornado_init,
2500 .setup = pci_default_setup,
2503 .vendor = PCI_VENDOR_ID_MAINPINE,
2504 .device = PCI_ANY_ID,
2505 .subvendor = PCI_ANY_ID,
2506 .subdevice = PCI_ANY_ID,
2507 .init = pci_oxsemi_tornado_init,
2508 .setup = pci_default_setup,
2511 .vendor = PCI_VENDOR_ID_DIGI,
2512 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2513 .subvendor = PCI_SUBVENDOR_ID_IBM,
2514 .subdevice = PCI_ANY_ID,
2515 .init = pci_oxsemi_tornado_init,
2516 .setup = pci_default_setup,
2519 .vendor = PCI_VENDOR_ID_INTEL,
2521 .subvendor = PCI_ANY_ID,
2522 .subdevice = PCI_ANY_ID,
2523 .init = pci_eg20t_init,
2524 .setup = pci_default_setup,
2527 .vendor = PCI_VENDOR_ID_INTEL,
2529 .subvendor = PCI_ANY_ID,
2530 .subdevice = PCI_ANY_ID,
2531 .init = pci_eg20t_init,
2532 .setup = pci_default_setup,
2535 .vendor = PCI_VENDOR_ID_INTEL,
2537 .subvendor = PCI_ANY_ID,
2538 .subdevice = PCI_ANY_ID,
2539 .init = pci_eg20t_init,
2540 .setup = pci_default_setup,
2543 .vendor = PCI_VENDOR_ID_INTEL,
2545 .subvendor = PCI_ANY_ID,
2546 .subdevice = PCI_ANY_ID,
2547 .init = pci_eg20t_init,
2548 .setup = pci_default_setup,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_eg20t_init,
2556 .setup = pci_default_setup,
2561 .subvendor = PCI_ANY_ID,
2562 .subdevice = PCI_ANY_ID,
2563 .init = pci_eg20t_init,
2564 .setup = pci_default_setup,
2569 .subvendor = PCI_ANY_ID,
2570 .subdevice = PCI_ANY_ID,
2571 .init = pci_eg20t_init,
2572 .setup = pci_default_setup,
2577 .subvendor = PCI_ANY_ID,
2578 .subdevice = PCI_ANY_ID,
2579 .init = pci_eg20t_init,
2580 .setup = pci_default_setup,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .init = pci_eg20t_init,
2588 .setup = pci_default_setup,
2591 * Cronyx Omega PCI (PLX-chip based)
2594 .vendor = PCI_VENDOR_ID_PLX,
2595 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2596 .subvendor = PCI_ANY_ID,
2597 .subdevice = PCI_ANY_ID,
2598 .setup = pci_omegapci_setup,
2600 /* WCH CH353 1S1P card (16550 clone) */
2602 .vendor = PCI_VENDOR_ID_WCH,
2603 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2604 .subvendor = PCI_ANY_ID,
2605 .subdevice = PCI_ANY_ID,
2606 .setup = pci_wch_ch353_setup,
2608 /* WCH CH353 2S1P card (16550 clone) */
2610 .vendor = PCI_VENDOR_ID_WCH,
2611 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2612 .subvendor = PCI_ANY_ID,
2613 .subdevice = PCI_ANY_ID,
2614 .setup = pci_wch_ch353_setup,
2616 /* WCH CH353 4S card (16550 clone) */
2618 .vendor = PCI_VENDOR_ID_WCH,
2619 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2620 .subvendor = PCI_ANY_ID,
2621 .subdevice = PCI_ANY_ID,
2622 .setup = pci_wch_ch353_setup,
2624 /* WCH CH353 2S1PF card (16550 clone) */
2626 .vendor = PCI_VENDOR_ID_WCH,
2627 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2628 .subvendor = PCI_ANY_ID,
2629 .subdevice = PCI_ANY_ID,
2630 .setup = pci_wch_ch353_setup,
2632 /* WCH CH352 2S card (16550 clone) */
2634 .vendor = PCI_VENDOR_ID_WCH,
2635 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_wch_ch353_setup,
2640 /* WCH CH382 2S1P card (16850 clone) */
2642 .vendor = PCIE_VENDOR_ID_WCH,
2643 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2644 .subvendor = PCI_ANY_ID,
2645 .subdevice = PCI_ANY_ID,
2646 .setup = pci_wch_ch38x_setup,
2648 /* WCH CH384 4S card (16850 clone) */
2650 .vendor = PCIE_VENDOR_ID_WCH,
2651 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2652 .subvendor = PCI_ANY_ID,
2653 .subdevice = PCI_ANY_ID,
2654 .setup = pci_wch_ch38x_setup,
2657 * ASIX devices with FIFO bug
2660 .vendor = PCI_VENDOR_ID_ASIX,
2661 .device = PCI_ANY_ID,
2662 .subvendor = PCI_ANY_ID,
2663 .subdevice = PCI_ANY_ID,
2664 .setup = pci_asix_setup,
2667 * Commtech, Inc. Fastcom adapters
2671 .vendor = PCI_VENDOR_ID_COMMTECH,
2672 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2673 .subvendor = PCI_ANY_ID,
2674 .subdevice = PCI_ANY_ID,
2675 .setup = pci_fastcom335_setup,
2678 .vendor = PCI_VENDOR_ID_COMMTECH,
2679 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2680 .subvendor = PCI_ANY_ID,
2681 .subdevice = PCI_ANY_ID,
2682 .setup = pci_fastcom335_setup,
2685 .vendor = PCI_VENDOR_ID_COMMTECH,
2686 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2687 .subvendor = PCI_ANY_ID,
2688 .subdevice = PCI_ANY_ID,
2689 .setup = pci_fastcom335_setup,
2692 .vendor = PCI_VENDOR_ID_COMMTECH,
2693 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2694 .subvendor = PCI_ANY_ID,
2695 .subdevice = PCI_ANY_ID,
2696 .setup = pci_fastcom335_setup,
2699 .vendor = PCI_VENDOR_ID_COMMTECH,
2700 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2701 .subvendor = PCI_ANY_ID,
2702 .subdevice = PCI_ANY_ID,
2703 .setup = pci_xr17v35x_setup,
2706 .vendor = PCI_VENDOR_ID_COMMTECH,
2707 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2708 .subvendor = PCI_ANY_ID,
2709 .subdevice = PCI_ANY_ID,
2710 .setup = pci_xr17v35x_setup,
2713 .vendor = PCI_VENDOR_ID_COMMTECH,
2714 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2715 .subvendor = PCI_ANY_ID,
2716 .subdevice = PCI_ANY_ID,
2717 .setup = pci_xr17v35x_setup,
2720 * Broadcom TruManage (NetXtreme)
2723 .vendor = PCI_VENDOR_ID_BROADCOM,
2724 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2725 .subvendor = PCI_ANY_ID,
2726 .subdevice = PCI_ANY_ID,
2727 .setup = pci_brcm_trumanage_setup,
2732 .subvendor = PCI_ANY_ID,
2733 .subdevice = PCI_ANY_ID,
2734 .setup = pci_fintek_setup,
2735 .init = pci_fintek_init,
2740 .subvendor = PCI_ANY_ID,
2741 .subdevice = PCI_ANY_ID,
2742 .setup = pci_fintek_setup,
2743 .init = pci_fintek_init,
2748 .subvendor = PCI_ANY_ID,
2749 .subdevice = PCI_ANY_ID,
2750 .setup = pci_fintek_setup,
2751 .init = pci_fintek_init,
2755 * Default "match everything" terminator entry
2758 .vendor = PCI_ANY_ID,
2759 .device = PCI_ANY_ID,
2760 .subvendor = PCI_ANY_ID,
2761 .subdevice = PCI_ANY_ID,
2762 .setup = pci_default_setup,
2766 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2768 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2771 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2773 struct pci_serial_quirk *quirk;
2775 for (quirk = pci_serial_quirks; ; quirk++)
2776 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2777 quirk_id_matches(quirk->device, dev->device) &&
2778 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2779 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2784 static inline int get_pci_irq(struct pci_dev *dev,
2785 const struct pciserial_board *board)
2787 if (board->flags & FL_NOIRQ)
2794 * This is the configuration table for all of the PCI serial boards
2795 * which we support. It is directly indexed by the pci_board_num_t enum
2796 * value, which is encoded in the pci_device_id PCI probe table's
2797 * driver_data member.
2799 * The makeup of these names are:
2800 * pbn_bn{_bt}_n_baud{_offsetinhex}
2802 * bn = PCI BAR number
2803 * bt = Index using PCI BARs
2804 * n = number of serial ports
2806 * offsetinhex = offset for each sequential port (in hex)
2808 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2810 * Please note: in theory if n = 1, _bt infix should make no difference.
2811 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2813 enum pci_board_num_t {
2830 pbn_b0_2_1152000_200,
2831 pbn_b0_4_1152000_200,
2832 pbn_b0_8_1152000_200,
2837 pbn_b0_2_1843200_200,
2838 pbn_b0_4_1843200_200,
2839 pbn_b0_8_1843200_200,
2913 * Board-specific versions.
2919 pbn_endrun_2_4000000,
2921 pbn_oxsemi_1_4000000,
2922 pbn_oxsemi_2_4000000,
2923 pbn_oxsemi_4_4000000,
2924 pbn_oxsemi_8_4000000,
2939 pbn_exar_ibm_saturn,
2945 pbn_ADDIDATA_PCIe_1_3906250,
2946 pbn_ADDIDATA_PCIe_2_3906250,
2947 pbn_ADDIDATA_PCIe_4_3906250,
2948 pbn_ADDIDATA_PCIe_8_3906250,
2949 pbn_ce4100_1_115200,
2953 pbn_NETMOS9900_2s_115200,
2959 pbn_pericom_PI7C9X7951,
2960 pbn_pericom_PI7C9X7952,
2961 pbn_pericom_PI7C9X7954,
2962 pbn_pericom_PI7C9X7958,
2966 * uart_offset - the space between channels
2967 * reg_shift - describes how the UART registers are mapped
2968 * to PCI memory by the card.
2969 * For example IER register on SBS, Inc. PMC-OctPro is located at
2970 * offset 0x10 from the UART base, while UART_IER is defined as 1
2971 * in include/linux/serial_reg.h,
2972 * see first lines of serial_in() and serial_out() in 8250.c
2975 static struct pciserial_board pci_boards[] = {
2979 .base_baud = 115200,
2982 [pbn_b0_1_115200] = {
2985 .base_baud = 115200,
2988 [pbn_b0_2_115200] = {
2991 .base_baud = 115200,
2994 [pbn_b0_4_115200] = {
2997 .base_baud = 115200,
3000 [pbn_b0_5_115200] = {
3003 .base_baud = 115200,
3006 [pbn_b0_8_115200] = {
3009 .base_baud = 115200,
3012 [pbn_b0_1_921600] = {
3015 .base_baud = 921600,
3018 [pbn_b0_2_921600] = {
3021 .base_baud = 921600,
3024 [pbn_b0_4_921600] = {
3027 .base_baud = 921600,
3031 [pbn_b0_2_1130000] = {
3034 .base_baud = 1130000,
3038 [pbn_b0_4_1152000] = {
3041 .base_baud = 1152000,
3045 [pbn_b0_2_1152000_200] = {
3048 .base_baud = 1152000,
3049 .uart_offset = 0x200,
3052 [pbn_b0_4_1152000_200] = {
3055 .base_baud = 1152000,
3056 .uart_offset = 0x200,
3059 [pbn_b0_8_1152000_200] = {
3062 .base_baud = 1152000,
3063 .uart_offset = 0x200,
3066 [pbn_b0_2_1843200] = {
3069 .base_baud = 1843200,
3072 [pbn_b0_4_1843200] = {
3075 .base_baud = 1843200,
3079 [pbn_b0_2_1843200_200] = {
3082 .base_baud = 1843200,
3083 .uart_offset = 0x200,
3085 [pbn_b0_4_1843200_200] = {
3088 .base_baud = 1843200,
3089 .uart_offset = 0x200,
3091 [pbn_b0_8_1843200_200] = {
3094 .base_baud = 1843200,
3095 .uart_offset = 0x200,
3097 [pbn_b0_1_4000000] = {
3100 .base_baud = 4000000,
3104 [pbn_b0_bt_1_115200] = {
3105 .flags = FL_BASE0|FL_BASE_BARS,
3107 .base_baud = 115200,
3110 [pbn_b0_bt_2_115200] = {
3111 .flags = FL_BASE0|FL_BASE_BARS,
3113 .base_baud = 115200,
3116 [pbn_b0_bt_4_115200] = {
3117 .flags = FL_BASE0|FL_BASE_BARS,
3119 .base_baud = 115200,
3122 [pbn_b0_bt_8_115200] = {
3123 .flags = FL_BASE0|FL_BASE_BARS,
3125 .base_baud = 115200,
3129 [pbn_b0_bt_1_460800] = {
3130 .flags = FL_BASE0|FL_BASE_BARS,
3132 .base_baud = 460800,
3135 [pbn_b0_bt_2_460800] = {
3136 .flags = FL_BASE0|FL_BASE_BARS,
3138 .base_baud = 460800,
3141 [pbn_b0_bt_4_460800] = {
3142 .flags = FL_BASE0|FL_BASE_BARS,
3144 .base_baud = 460800,
3148 [pbn_b0_bt_1_921600] = {
3149 .flags = FL_BASE0|FL_BASE_BARS,
3151 .base_baud = 921600,
3154 [pbn_b0_bt_2_921600] = {
3155 .flags = FL_BASE0|FL_BASE_BARS,
3157 .base_baud = 921600,
3160 [pbn_b0_bt_4_921600] = {
3161 .flags = FL_BASE0|FL_BASE_BARS,
3163 .base_baud = 921600,
3166 [pbn_b0_bt_8_921600] = {
3167 .flags = FL_BASE0|FL_BASE_BARS,
3169 .base_baud = 921600,
3173 [pbn_b1_1_115200] = {
3176 .base_baud = 115200,
3179 [pbn_b1_2_115200] = {
3182 .base_baud = 115200,
3185 [pbn_b1_4_115200] = {
3188 .base_baud = 115200,
3191 [pbn_b1_8_115200] = {
3194 .base_baud = 115200,
3197 [pbn_b1_16_115200] = {
3200 .base_baud = 115200,
3204 [pbn_b1_1_921600] = {
3207 .base_baud = 921600,
3210 [pbn_b1_2_921600] = {
3213 .base_baud = 921600,
3216 [pbn_b1_4_921600] = {
3219 .base_baud = 921600,
3222 [pbn_b1_8_921600] = {
3225 .base_baud = 921600,
3228 [pbn_b1_2_1250000] = {
3231 .base_baud = 1250000,
3235 [pbn_b1_bt_1_115200] = {
3236 .flags = FL_BASE1|FL_BASE_BARS,
3238 .base_baud = 115200,
3241 [pbn_b1_bt_2_115200] = {
3242 .flags = FL_BASE1|FL_BASE_BARS,
3244 .base_baud = 115200,
3247 [pbn_b1_bt_4_115200] = {
3248 .flags = FL_BASE1|FL_BASE_BARS,
3250 .base_baud = 115200,
3254 [pbn_b1_bt_2_921600] = {
3255 .flags = FL_BASE1|FL_BASE_BARS,
3257 .base_baud = 921600,
3261 [pbn_b1_1_1382400] = {
3264 .base_baud = 1382400,
3267 [pbn_b1_2_1382400] = {
3270 .base_baud = 1382400,
3273 [pbn_b1_4_1382400] = {
3276 .base_baud = 1382400,
3279 [pbn_b1_8_1382400] = {
3282 .base_baud = 1382400,
3286 [pbn_b2_1_115200] = {
3289 .base_baud = 115200,
3292 [pbn_b2_2_115200] = {
3295 .base_baud = 115200,
3298 [pbn_b2_4_115200] = {
3301 .base_baud = 115200,
3304 [pbn_b2_8_115200] = {
3307 .base_baud = 115200,
3311 [pbn_b2_1_460800] = {
3314 .base_baud = 460800,
3317 [pbn_b2_4_460800] = {
3320 .base_baud = 460800,
3323 [pbn_b2_8_460800] = {
3326 .base_baud = 460800,
3329 [pbn_b2_16_460800] = {
3332 .base_baud = 460800,
3336 [pbn_b2_1_921600] = {
3339 .base_baud = 921600,
3342 [pbn_b2_4_921600] = {
3345 .base_baud = 921600,
3348 [pbn_b2_8_921600] = {
3351 .base_baud = 921600,
3355 [pbn_b2_8_1152000] = {
3358 .base_baud = 1152000,
3362 [pbn_b2_bt_1_115200] = {
3363 .flags = FL_BASE2|FL_BASE_BARS,
3365 .base_baud = 115200,
3368 [pbn_b2_bt_2_115200] = {
3369 .flags = FL_BASE2|FL_BASE_BARS,
3371 .base_baud = 115200,
3374 [pbn_b2_bt_4_115200] = {
3375 .flags = FL_BASE2|FL_BASE_BARS,
3377 .base_baud = 115200,
3381 [pbn_b2_bt_2_921600] = {
3382 .flags = FL_BASE2|FL_BASE_BARS,
3384 .base_baud = 921600,
3387 [pbn_b2_bt_4_921600] = {
3388 .flags = FL_BASE2|FL_BASE_BARS,
3390 .base_baud = 921600,
3394 [pbn_b3_2_115200] = {
3397 .base_baud = 115200,
3400 [pbn_b3_4_115200] = {
3403 .base_baud = 115200,
3406 [pbn_b3_8_115200] = {
3409 .base_baud = 115200,
3413 [pbn_b4_bt_2_921600] = {
3416 .base_baud = 921600,
3419 [pbn_b4_bt_4_921600] = {
3422 .base_baud = 921600,
3425 [pbn_b4_bt_8_921600] = {
3428 .base_baud = 921600,
3433 * Entries following this are board-specific.
3442 .base_baud = 921600,
3443 .uart_offset = 0x400,
3447 .flags = FL_BASE2|FL_BASE_BARS,
3449 .base_baud = 921600,
3450 .uart_offset = 0x400,
3454 .flags = FL_BASE2|FL_BASE_BARS,
3456 .base_baud = 921600,
3457 .uart_offset = 0x400,
3461 /* I think this entry is broken - the first_offset looks wrong --rmk */
3462 [pbn_plx_romulus] = {
3465 .base_baud = 921600,
3466 .uart_offset = 8 << 2,
3468 .first_offset = 0x03,
3472 * EndRun Technologies
3473 * Uses the size of PCI Base region 0 to
3474 * signal now many ports are available
3475 * 2 port 952 Uart support
3477 [pbn_endrun_2_4000000] = {
3480 .base_baud = 4000000,
3481 .uart_offset = 0x200,
3482 .first_offset = 0x1000,
3486 * This board uses the size of PCI Base region 0 to
3487 * signal now many ports are available
3490 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3492 .base_baud = 115200,
3495 [pbn_oxsemi_1_4000000] = {
3498 .base_baud = 4000000,
3499 .uart_offset = 0x200,
3500 .first_offset = 0x1000,
3502 [pbn_oxsemi_2_4000000] = {
3505 .base_baud = 4000000,
3506 .uart_offset = 0x200,
3507 .first_offset = 0x1000,
3509 [pbn_oxsemi_4_4000000] = {
3512 .base_baud = 4000000,
3513 .uart_offset = 0x200,
3514 .first_offset = 0x1000,
3516 [pbn_oxsemi_8_4000000] = {
3519 .base_baud = 4000000,
3520 .uart_offset = 0x200,
3521 .first_offset = 0x1000,
3526 * EKF addition for i960 Boards form EKF with serial port.
3529 [pbn_intel_i960] = {
3532 .base_baud = 921600,
3533 .uart_offset = 8 << 2,
3535 .first_offset = 0x10000,
3538 .flags = FL_BASE0|FL_NOIRQ,
3540 .base_baud = 458333,
3543 .first_offset = 0x20178,
3547 * Computone - uses IOMEM.
3549 [pbn_computone_4] = {
3552 .base_baud = 921600,
3553 .uart_offset = 0x40,
3555 .first_offset = 0x200,
3557 [pbn_computone_6] = {
3560 .base_baud = 921600,
3561 .uart_offset = 0x40,
3563 .first_offset = 0x200,
3565 [pbn_computone_8] = {
3568 .base_baud = 921600,
3569 .uart_offset = 0x40,
3571 .first_offset = 0x200,
3576 .base_baud = 460800,
3581 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3582 * Only basic 16550A support.
3583 * XR17C15[24] are not tested, but they should work.
3585 [pbn_exar_XR17C152] = {
3588 .base_baud = 921600,
3589 .uart_offset = 0x200,
3591 [pbn_exar_XR17C154] = {
3594 .base_baud = 921600,
3595 .uart_offset = 0x200,
3597 [pbn_exar_XR17C158] = {
3600 .base_baud = 921600,
3601 .uart_offset = 0x200,
3603 [pbn_exar_XR17V352] = {
3606 .base_baud = 7812500,
3607 .uart_offset = 0x400,
3611 [pbn_exar_XR17V354] = {
3614 .base_baud = 7812500,
3615 .uart_offset = 0x400,
3619 [pbn_exar_XR17V358] = {
3622 .base_baud = 7812500,
3623 .uart_offset = 0x400,
3627 [pbn_exar_XR17V4358] = {
3630 .base_baud = 7812500,
3631 .uart_offset = 0x400,
3635 [pbn_exar_XR17V8358] = {
3638 .base_baud = 7812500,
3639 .uart_offset = 0x400,
3643 [pbn_exar_ibm_saturn] = {
3646 .base_baud = 921600,
3647 .uart_offset = 0x200,
3651 * PA Semi PWRficient PA6T-1682M on-chip UART
3653 [pbn_pasemi_1682M] = {
3656 .base_baud = 8333333,
3659 * National Instruments 843x
3664 .base_baud = 3686400,
3665 .uart_offset = 0x10,
3666 .first_offset = 0x800,
3671 .base_baud = 3686400,
3672 .uart_offset = 0x10,
3673 .first_offset = 0x800,
3678 .base_baud = 3686400,
3679 .uart_offset = 0x10,
3680 .first_offset = 0x800,
3685 .base_baud = 3686400,
3686 .uart_offset = 0x10,
3687 .first_offset = 0x800,
3690 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3692 [pbn_ADDIDATA_PCIe_1_3906250] = {
3695 .base_baud = 3906250,
3696 .uart_offset = 0x200,
3697 .first_offset = 0x1000,
3699 [pbn_ADDIDATA_PCIe_2_3906250] = {
3702 .base_baud = 3906250,
3703 .uart_offset = 0x200,
3704 .first_offset = 0x1000,
3706 [pbn_ADDIDATA_PCIe_4_3906250] = {
3709 .base_baud = 3906250,
3710 .uart_offset = 0x200,
3711 .first_offset = 0x1000,
3713 [pbn_ADDIDATA_PCIe_8_3906250] = {
3716 .base_baud = 3906250,
3717 .uart_offset = 0x200,
3718 .first_offset = 0x1000,
3720 [pbn_ce4100_1_115200] = {
3721 .flags = FL_BASE_BARS,
3723 .base_baud = 921600,
3727 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3728 * but is overridden by byt_set_termios.
3733 .base_baud = 2764800,
3734 .uart_offset = 0x80,
3740 .base_baud = 2764800,
3746 .base_baud = 115200,
3747 .uart_offset = 0x200,
3749 [pbn_NETMOS9900_2s_115200] = {
3752 .base_baud = 115200,
3754 [pbn_brcm_trumanage] = {
3758 .base_baud = 115200,
3763 .base_baud = 115200,
3764 .first_offset = 0x40,
3769 .base_baud = 115200,
3770 .first_offset = 0x40,
3775 .base_baud = 115200,
3776 .first_offset = 0x40,
3781 .base_baud = 115200,
3783 .first_offset = 0xC0,
3786 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3788 [pbn_pericom_PI7C9X7951] = {
3791 .base_baud = 921600,
3794 [pbn_pericom_PI7C9X7952] = {
3797 .base_baud = 921600,
3800 [pbn_pericom_PI7C9X7954] = {
3803 .base_baud = 921600,
3806 [pbn_pericom_PI7C9X7958] = {
3809 .base_baud = 921600,
3814 static const struct pci_device_id blacklist[] = {
3816 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3817 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3818 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3820 /* multi-io cards handled by parport_serial */
3821 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3822 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3823 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3824 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3826 /* Intel platforms with MID UART */
3827 { PCI_VDEVICE(INTEL, 0x081b), },
3828 { PCI_VDEVICE(INTEL, 0x081c), },
3829 { PCI_VDEVICE(INTEL, 0x081d), },
3830 { PCI_VDEVICE(INTEL, 0x1191), },
3831 { PCI_VDEVICE(INTEL, 0x19d8), },
3835 * Given a complete unknown PCI device, try to use some heuristics to
3836 * guess what the configuration might be, based on the pitiful PCI
3837 * serial specs. Returns 0 on success, 1 on failure.
3840 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3842 const struct pci_device_id *bldev;
3843 int num_iomem, num_port, first_port = -1, i;
3846 * If it is not a communications device or the programming
3847 * interface is greater than 6, give up.
3849 * (Should we try to make guesses for multiport serial devices
3852 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3853 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3854 (dev->class & 0xff) > 6)
3858 * Do not access blacklisted devices that are known not to
3859 * feature serial ports or are handled by other modules.
3861 for (bldev = blacklist;
3862 bldev < blacklist + ARRAY_SIZE(blacklist);
3864 if (dev->vendor == bldev->vendor &&
3865 dev->device == bldev->device)
3869 num_iomem = num_port = 0;
3870 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3871 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3873 if (first_port == -1)
3876 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3881 * If there is 1 or 0 iomem regions, and exactly one port,
3882 * use it. We guess the number of ports based on the IO
3885 if (num_iomem <= 1 && num_port == 1) {
3886 board->flags = first_port;
3887 board->num_ports = pci_resource_len(dev, first_port) / 8;
3892 * Now guess if we've got a board which indexes by BARs.
3893 * Each IO BAR should be 8 bytes, and they should follow
3898 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3899 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3900 pci_resource_len(dev, i) == 8 &&
3901 (first_port == -1 || (first_port + num_port) == i)) {
3903 if (first_port == -1)
3909 board->flags = first_port | FL_BASE_BARS;
3910 board->num_ports = num_port;
3918 serial_pci_matches(const struct pciserial_board *board,
3919 const struct pciserial_board *guessed)
3922 board->num_ports == guessed->num_ports &&
3923 board->base_baud == guessed->base_baud &&
3924 board->uart_offset == guessed->uart_offset &&
3925 board->reg_shift == guessed->reg_shift &&
3926 board->first_offset == guessed->first_offset;
3929 struct serial_private *
3930 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3932 struct uart_8250_port uart;
3933 struct serial_private *priv;
3934 struct pci_serial_quirk *quirk;
3935 int rc, nr_ports, i;
3937 nr_ports = board->num_ports;
3940 * Find an init and setup quirks.
3942 quirk = find_quirk(dev);
3945 * Run the new-style initialization function.
3946 * The initialization function returns:
3948 * 0 - use board->num_ports
3949 * >0 - number of ports
3952 rc = quirk->init(dev);
3961 priv = kzalloc(sizeof(struct serial_private) +
3962 sizeof(unsigned int) * nr_ports,
3965 priv = ERR_PTR(-ENOMEM);
3970 priv->quirk = quirk;
3972 memset(&uart, 0, sizeof(uart));
3973 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3974 uart.port.uartclk = board->base_baud * 16;
3975 uart.port.irq = get_pci_irq(dev, board);
3976 uart.port.dev = &dev->dev;
3978 for (i = 0; i < nr_ports; i++) {
3979 if (quirk->setup(priv, board, &uart, i))
3982 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3983 uart.port.iobase, uart.port.irq, uart.port.iotype);
3985 priv->line[i] = serial8250_register_8250_port(&uart);
3986 if (priv->line[i] < 0) {
3988 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3989 uart.port.iobase, uart.port.irq,
3990 uart.port.iotype, priv->line[i]);
4003 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4005 void pciserial_remove_ports(struct serial_private *priv)
4007 struct pci_serial_quirk *quirk;
4010 for (i = 0; i < priv->nr; i++)
4011 serial8250_unregister_port(priv->line[i]);
4013 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4014 if (priv->remapped_bar[i])
4015 iounmap(priv->remapped_bar[i]);
4016 priv->remapped_bar[i] = NULL;
4020 * Find the exit quirks.
4022 quirk = find_quirk(priv->dev);
4024 quirk->exit(priv->dev);
4028 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4030 void pciserial_suspend_ports(struct serial_private *priv)
4034 for (i = 0; i < priv->nr; i++)
4035 if (priv->line[i] >= 0)
4036 serial8250_suspend_port(priv->line[i]);
4039 * Ensure that every init quirk is properly torn down
4041 if (priv->quirk->exit)
4042 priv->quirk->exit(priv->dev);
4044 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4046 void pciserial_resume_ports(struct serial_private *priv)
4051 * Ensure that the board is correctly configured.
4053 if (priv->quirk->init)
4054 priv->quirk->init(priv->dev);
4056 for (i = 0; i < priv->nr; i++)
4057 if (priv->line[i] >= 0)
4058 serial8250_resume_port(priv->line[i]);
4060 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4063 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4064 * to the arrangement of serial ports on a PCI card.
4067 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4069 struct pci_serial_quirk *quirk;
4070 struct serial_private *priv;
4071 const struct pciserial_board *board;
4072 struct pciserial_board tmp;
4075 quirk = find_quirk(dev);
4077 rc = quirk->probe(dev);
4082 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4083 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4088 board = &pci_boards[ent->driver_data];
4090 rc = pci_enable_device(dev);
4091 pci_save_state(dev);
4095 if (ent->driver_data == pbn_default) {
4097 * Use a copy of the pci_board entry for this;
4098 * avoid changing entries in the table.
4100 memcpy(&tmp, board, sizeof(struct pciserial_board));
4104 * We matched one of our class entries. Try to
4105 * determine the parameters of this board.
4107 rc = serial_pci_guess_board(dev, &tmp);
4112 * We matched an explicit entry. If we are able to
4113 * detect this boards settings with our heuristic,
4114 * then we no longer need this entry.
4116 memcpy(&tmp, &pci_boards[pbn_default],
4117 sizeof(struct pciserial_board));
4118 rc = serial_pci_guess_board(dev, &tmp);
4119 if (rc == 0 && serial_pci_matches(board, &tmp))
4120 moan_device("Redundant entry in serial pci_table.",
4124 priv = pciserial_init_ports(dev, board);
4125 if (!IS_ERR(priv)) {
4126 pci_set_drvdata(dev, priv);
4133 pci_disable_device(dev);
4137 static void pciserial_remove_one(struct pci_dev *dev)
4139 struct serial_private *priv = pci_get_drvdata(dev);
4141 pciserial_remove_ports(priv);
4143 pci_disable_device(dev);
4146 #ifdef CONFIG_PM_SLEEP
4147 static int pciserial_suspend_one(struct device *dev)
4149 struct pci_dev *pdev = to_pci_dev(dev);
4150 struct serial_private *priv = pci_get_drvdata(pdev);
4153 pciserial_suspend_ports(priv);
4158 static int pciserial_resume_one(struct device *dev)
4160 struct pci_dev *pdev = to_pci_dev(dev);
4161 struct serial_private *priv = pci_get_drvdata(pdev);
4166 * The device may have been disabled. Re-enable it.
4168 err = pci_enable_device(pdev);
4169 /* FIXME: We cannot simply error out here */
4171 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4172 pciserial_resume_ports(priv);
4178 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4179 pciserial_resume_one);
4181 static struct pci_device_id serial_pci_tbl[] = {
4182 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4183 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4184 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4186 /* Advantech also use 0x3618 and 0xf618 */
4187 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4188 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4190 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4191 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4193 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4194 PCI_SUBVENDOR_ID_CONNECT_TECH,
4195 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4197 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4198 PCI_SUBVENDOR_ID_CONNECT_TECH,
4199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4201 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4202 PCI_SUBVENDOR_ID_CONNECT_TECH,
4203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4205 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4206 PCI_SUBVENDOR_ID_CONNECT_TECH,
4207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4209 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4210 PCI_SUBVENDOR_ID_CONNECT_TECH,
4211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4213 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4214 PCI_SUBVENDOR_ID_CONNECT_TECH,
4215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4217 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4218 PCI_SUBVENDOR_ID_CONNECT_TECH,
4219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4221 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4222 PCI_SUBVENDOR_ID_CONNECT_TECH,
4223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4225 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4226 PCI_SUBVENDOR_ID_CONNECT_TECH,
4227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4229 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4230 PCI_SUBVENDOR_ID_CONNECT_TECH,
4231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4233 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4234 PCI_SUBVENDOR_ID_CONNECT_TECH,
4235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4237 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4238 PCI_SUBVENDOR_ID_CONNECT_TECH,
4239 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4241 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4242 PCI_SUBVENDOR_ID_CONNECT_TECH,
4243 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4245 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246 PCI_SUBVENDOR_ID_CONNECT_TECH,
4247 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4249 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250 PCI_SUBVENDOR_ID_CONNECT_TECH,
4251 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4253 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4254 PCI_SUBVENDOR_ID_CONNECT_TECH,
4255 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4257 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4258 PCI_SUBVENDOR_ID_CONNECT_TECH,
4259 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4261 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4262 PCI_VENDOR_ID_AFAVLAB,
4263 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4265 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4266 PCI_SUBVENDOR_ID_CONNECT_TECH,
4267 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4268 pbn_b0_2_1843200_200 },
4269 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4270 PCI_SUBVENDOR_ID_CONNECT_TECH,
4271 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4272 pbn_b0_4_1843200_200 },
4273 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4274 PCI_SUBVENDOR_ID_CONNECT_TECH,
4275 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4276 pbn_b0_8_1843200_200 },
4277 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4278 PCI_SUBVENDOR_ID_CONNECT_TECH,
4279 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4280 pbn_b0_2_1843200_200 },
4281 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4282 PCI_SUBVENDOR_ID_CONNECT_TECH,
4283 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4284 pbn_b0_4_1843200_200 },
4285 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4286 PCI_SUBVENDOR_ID_CONNECT_TECH,
4287 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4288 pbn_b0_8_1843200_200 },
4289 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4290 PCI_SUBVENDOR_ID_CONNECT_TECH,
4291 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4292 pbn_b0_2_1843200_200 },
4293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4294 PCI_SUBVENDOR_ID_CONNECT_TECH,
4295 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4296 pbn_b0_4_1843200_200 },
4297 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4298 PCI_SUBVENDOR_ID_CONNECT_TECH,
4299 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4300 pbn_b0_8_1843200_200 },
4301 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4302 PCI_SUBVENDOR_ID_CONNECT_TECH,
4303 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4304 pbn_b0_2_1843200_200 },
4305 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4306 PCI_SUBVENDOR_ID_CONNECT_TECH,
4307 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4308 pbn_b0_4_1843200_200 },
4309 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4310 PCI_SUBVENDOR_ID_CONNECT_TECH,
4311 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4312 pbn_b0_8_1843200_200 },
4313 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4314 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4315 0, 0, pbn_exar_ibm_saturn },
4317 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 pbn_b2_bt_1_115200 },
4320 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322 pbn_b2_bt_2_115200 },
4323 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_b2_bt_4_115200 },
4326 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_b2_bt_2_115200 },
4329 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_b2_bt_4_115200 },
4332 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_b2_bt_2_115200 },
4345 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347 pbn_b2_bt_2_921600 },
4349 * VScom SPCOM800, from sl@s.pl
4351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 /* Unknown card - subdevice 0x1584 */
4358 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4360 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4362 /* Unknown card - subdevice 0x1588 */
4363 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4365 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4368 PCI_SUBVENDOR_ID_KEYSPAN,
4369 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4371 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4374 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4378 PCI_VENDOR_ID_ESDGMBH,
4379 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4382 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4383 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4385 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4386 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4387 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4389 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4390 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4391 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4393 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4394 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4395 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4397 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4398 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4399 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4401 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4402 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4403 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4405 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4406 PCI_SUBVENDOR_ID_EXSYS,
4407 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4410 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4413 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4414 0x10b5, 0x106a, 0, 0,
4417 * EndRun Technologies. PCI express device range.
4418 * EndRun PTP/1588 has 2 Native UARTs.
4420 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_endrun_2_4000000 },
4424 * Quatech cards. These actually have configurable clocks but for
4425 * now we just use the default.
4427 * 100 series are RS232, 200 series RS422,
4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4488 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4491 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4492 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4495 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b0_bt_2_921600 },
4500 * The below card is a little controversial since it is the
4501 * subject of a PCI vendor/device ID clash. (See
4502 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4503 * For now just used the hex ID 0x950a.
4505 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4506 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4507 0, 0, pbn_b0_2_115200 },
4508 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4509 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4510 0, 0, pbn_b0_2_115200 },
4511 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4515 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4517 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b0_bt_2_921600 },
4523 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4524 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4528 * Oxford Semiconductor Inc. Tornado PCI express device range.
4530 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_1_4000000 },
4539 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_oxsemi_1_4000000 },
4542 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_oxsemi_1_4000000 },
4551 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_oxsemi_1_4000000 },
4554 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_oxsemi_2_4000000 },
4569 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_oxsemi_2_4000000 },
4572 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_4_4000000 },
4575 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_4_4000000 },
4578 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_oxsemi_8_4000000 },
4581 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_oxsemi_8_4000000 },
4584 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_1_4000000 },
4587 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_oxsemi_1_4000000 },
4590 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_oxsemi_1_4000000 },
4593 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_oxsemi_1_4000000 },
4596 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_oxsemi_1_4000000 },
4599 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_oxsemi_1_4000000 },
4602 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_oxsemi_1_4000000 },
4605 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_oxsemi_1_4000000 },
4608 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_oxsemi_1_4000000 },
4611 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_oxsemi_1_4000000 },
4614 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_oxsemi_1_4000000 },
4617 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_oxsemi_1_4000000 },
4620 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_oxsemi_1_4000000 },
4623 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_oxsemi_1_4000000 },
4626 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_oxsemi_1_4000000 },
4629 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_oxsemi_1_4000000 },
4632 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_oxsemi_1_4000000 },
4635 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_1_4000000 },
4638 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_oxsemi_1_4000000 },
4641 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_oxsemi_1_4000000 },
4644 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_1_4000000 },
4647 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_oxsemi_1_4000000 },
4650 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_oxsemi_1_4000000 },
4653 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_oxsemi_1_4000000 },
4656 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_oxsemi_1_4000000 },
4659 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_oxsemi_1_4000000 },
4663 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4665 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4666 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4667 pbn_oxsemi_1_4000000 },
4668 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4669 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4670 pbn_oxsemi_2_4000000 },
4671 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4672 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4673 pbn_oxsemi_4_4000000 },
4674 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4675 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4676 pbn_oxsemi_8_4000000 },
4679 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4681 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4682 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4683 pbn_oxsemi_2_4000000 },
4686 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4687 * from skokodyn@yahoo.com
4689 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4690 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4692 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4693 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4695 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4696 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4698 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4699 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4703 * Digitan DS560-558, from jimd@esoft.com
4705 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 * Titan Electronic cards
4711 * The 400L and 800L have a custom setup quirk.
4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_b1_bt_2_921600 },
4731 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_b0_bt_4_921600 },
4734 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_b0_bt_8_921600 },
4737 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_b4_bt_2_921600 },
4740 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_b4_bt_4_921600 },
4743 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b4_bt_8_921600 },
4746 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_oxsemi_1_4000000 },
4758 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_oxsemi_2_4000000 },
4761 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_oxsemi_4_4000000 },
4764 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_oxsemi_8_4000000 },
4767 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_oxsemi_2_4000000 },
4770 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_oxsemi_2_4000000 },
4773 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b0_bt_2_921600 },
4776 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b2_bt_2_921600 },
4801 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 pbn_b2_bt_2_921600 },
4804 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 pbn_b2_bt_2_921600 },
4807 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4809 pbn_b2_bt_4_921600 },
4810 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4812 pbn_b2_bt_4_921600 },
4813 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4815 pbn_b2_bt_4_921600 },
4816 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4827 pbn_b0_bt_2_921600 },
4828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 pbn_b0_bt_2_921600 },
4831 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 pbn_b0_bt_2_921600 },
4834 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 pbn_b0_bt_4_921600 },
4837 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 pbn_b0_bt_4_921600 },
4840 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 pbn_b0_bt_4_921600 },
4843 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 pbn_b0_bt_8_921600 },
4846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b0_bt_8_921600 },
4849 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b0_bt_8_921600 },
4854 * Computone devices submitted by Doug McNash dmcnash@computone.com
4856 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4857 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4858 0, 0, pbn_computone_4 },
4859 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4860 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4861 0, 0, pbn_computone_8 },
4862 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4863 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4864 0, 0, pbn_computone_6 },
4866 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4870 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4871 pbn_b0_bt_1_921600 },
4876 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4877 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4878 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4879 pbn_b0_bt_1_921600 },
4881 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4882 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4883 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4884 pbn_b0_bt_1_921600 },
4887 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4889 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b0_bt_8_115200 },
4892 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b0_bt_8_115200 },
4896 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_bt_2_115200 },
4899 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_bt_2_115200 },
4902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b0_bt_2_115200 },
4905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_bt_2_115200 },
4908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b0_bt_2_115200 },
4911 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_b0_bt_4_460800 },
4914 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_b0_bt_4_460800 },
4917 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 pbn_b0_bt_2_460800 },
4920 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 pbn_b0_bt_2_460800 },
4923 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_b0_bt_2_460800 },
4926 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_b0_bt_1_115200 },
4929 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_b0_bt_1_460800 },
4934 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4935 * Cards are identified by their subsystem vendor IDs, which
4936 * (in hex) match the model number.
4938 * Note that JC140x are RS422/485 cards which require ox950
4939 * ACR = 0x10, and as such are not currently fully supported.
4941 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4942 0x1204, 0x0004, 0, 0,
4944 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4945 0x1208, 0x0004, 0, 0,
4947 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4948 0x1402, 0x0002, 0, 0,
4949 pbn_b0_2_921600 }, */
4950 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4951 0x1404, 0x0004, 0, 0,
4952 pbn_b0_4_921600 }, */
4953 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4954 0x1208, 0x0004, 0, 0,
4957 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4958 0x1204, 0x0004, 0, 0,
4960 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4961 0x1208, 0x0004, 0, 0,
4963 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4964 0x1208, 0x0004, 0, 0,
4967 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4969 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4976 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 * RAStel 2 port modem, gerg@moreton.com.au
4983 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b2_bt_2_115200 },
4988 * EKF addition for i960 Boards form EKF with serial port
4990 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4991 0xE4BF, PCI_ANY_ID, 0, 0,
4995 * Xircom Cardbus/Ethernet combos
4997 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5003 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 * Untested PCI modems, sent in from various folks...
5012 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5014 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5015 0x1048, 0x1500, 0, 0,
5018 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5025 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5026 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5028 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5048 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5049 PCI_ANY_ID, PCI_ANY_ID,
5051 0, pbn_exar_XR17C152 },
5052 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5053 PCI_ANY_ID, PCI_ANY_ID,
5055 0, pbn_exar_XR17C154 },
5056 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5057 PCI_ANY_ID, PCI_ANY_ID,
5059 0, pbn_exar_XR17C158 },
5061 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
5063 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5064 PCI_ANY_ID, PCI_ANY_ID,
5066 0, pbn_exar_XR17V352 },
5067 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5068 PCI_ANY_ID, PCI_ANY_ID,
5070 0, pbn_exar_XR17V354 },
5071 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5072 PCI_ANY_ID, PCI_ANY_ID,
5074 0, pbn_exar_XR17V358 },
5075 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5076 PCI_ANY_ID, PCI_ANY_ID,
5078 0, pbn_exar_XR17V4358 },
5079 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5080 PCI_ANY_ID, PCI_ANY_ID,
5082 0, pbn_exar_XR17V8358 },
5084 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5086 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5087 PCI_ANY_ID, PCI_ANY_ID,
5089 0, pbn_pericom_PI7C9X7951 },
5090 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5091 PCI_ANY_ID, PCI_ANY_ID,
5093 0, pbn_pericom_PI7C9X7952 },
5094 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5095 PCI_ANY_ID, PCI_ANY_ID,
5097 0, pbn_pericom_PI7C9X7954 },
5098 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5099 PCI_ANY_ID, PCI_ANY_ID,
5101 0, pbn_pericom_PI7C9X7958 },
5103 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5105 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5111 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5112 PCI_ANY_ID, PCI_ANY_ID,
5114 pbn_b1_bt_1_115200 },
5119 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5125 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5129 * Perle PCI-RAS cards
5131 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5132 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5133 0, 0, pbn_b2_4_921600 },
5134 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5135 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5136 0, 0, pbn_b2_8_921600 },
5139 * Mainpine series cards: Fairly standard layout but fools
5140 * parts of the autodetect in some cases and uses otherwise
5141 * unmatched communications subclasses in the PCI Express case
5144 { /* RockForceDUO */
5145 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5146 PCI_VENDOR_ID_MAINPINE, 0x0200,
5147 0, 0, pbn_b0_2_115200 },
5148 { /* RockForceQUATRO */
5149 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5150 PCI_VENDOR_ID_MAINPINE, 0x0300,
5151 0, 0, pbn_b0_4_115200 },
5152 { /* RockForceDUO+ */
5153 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5154 PCI_VENDOR_ID_MAINPINE, 0x0400,
5155 0, 0, pbn_b0_2_115200 },
5156 { /* RockForceQUATRO+ */
5157 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5158 PCI_VENDOR_ID_MAINPINE, 0x0500,
5159 0, 0, pbn_b0_4_115200 },
5161 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5162 PCI_VENDOR_ID_MAINPINE, 0x0600,
5163 0, 0, pbn_b0_2_115200 },
5165 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5166 PCI_VENDOR_ID_MAINPINE, 0x0700,
5167 0, 0, pbn_b0_4_115200 },
5168 { /* RockForceOCTO+ */
5169 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5170 PCI_VENDOR_ID_MAINPINE, 0x0800,
5171 0, 0, pbn_b0_8_115200 },
5172 { /* RockForceDUO+ */
5173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5174 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5175 0, 0, pbn_b0_2_115200 },
5176 { /* RockForceQUARTRO+ */
5177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5178 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5179 0, 0, pbn_b0_4_115200 },
5180 { /* RockForceOCTO+ */
5181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5182 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5183 0, 0, pbn_b0_8_115200 },
5185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5186 PCI_VENDOR_ID_MAINPINE, 0x2000,
5187 0, 0, pbn_b0_1_115200 },
5189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5190 PCI_VENDOR_ID_MAINPINE, 0x2100,
5191 0, 0, pbn_b0_1_115200 },
5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5194 PCI_VENDOR_ID_MAINPINE, 0x2200,
5195 0, 0, pbn_b0_2_115200 },
5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5198 PCI_VENDOR_ID_MAINPINE, 0x2300,
5199 0, 0, pbn_b0_2_115200 },
5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5202 PCI_VENDOR_ID_MAINPINE, 0x2400,
5203 0, 0, pbn_b0_4_115200 },
5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5206 PCI_VENDOR_ID_MAINPINE, 0x2500,
5207 0, 0, pbn_b0_4_115200 },
5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5210 PCI_VENDOR_ID_MAINPINE, 0x2600,
5211 0, 0, pbn_b0_8_115200 },
5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5214 PCI_VENDOR_ID_MAINPINE, 0x2700,
5215 0, 0, pbn_b0_8_115200 },
5216 { /* IQ Express D1 */
5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5218 PCI_VENDOR_ID_MAINPINE, 0x3000,
5219 0, 0, pbn_b0_1_115200 },
5220 { /* IQ Express F1 */
5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5222 PCI_VENDOR_ID_MAINPINE, 0x3100,
5223 0, 0, pbn_b0_1_115200 },
5224 { /* IQ Express D2 */
5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5226 PCI_VENDOR_ID_MAINPINE, 0x3200,
5227 0, 0, pbn_b0_2_115200 },
5228 { /* IQ Express F2 */
5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5230 PCI_VENDOR_ID_MAINPINE, 0x3300,
5231 0, 0, pbn_b0_2_115200 },
5232 { /* IQ Express D4 */
5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5234 PCI_VENDOR_ID_MAINPINE, 0x3400,
5235 0, 0, pbn_b0_4_115200 },
5236 { /* IQ Express F4 */
5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5238 PCI_VENDOR_ID_MAINPINE, 0x3500,
5239 0, 0, pbn_b0_4_115200 },
5240 { /* IQ Express D8 */
5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5242 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5243 0, 0, pbn_b0_8_115200 },
5244 { /* IQ Express F8 */
5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5246 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5247 0, 0, pbn_b0_8_115200 },
5251 * PA Semi PA6T-1682M on-chip UART
5253 { PCI_VENDOR_ID_PASEMI, 0xa004,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258 * National Instruments
5260 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5263 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5266 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5268 pbn_b1_bt_4_115200 },
5269 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5271 pbn_b1_bt_2_115200 },
5272 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274 pbn_b1_bt_4_115200 },
5275 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5277 pbn_b1_bt_2_115200 },
5278 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5286 pbn_b1_bt_4_115200 },
5287 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289 pbn_b1_bt_2_115200 },
5290 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5292 pbn_b1_bt_4_115200 },
5293 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5295 pbn_b1_bt_2_115200 },
5296 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5334 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5336 { PCI_VENDOR_ID_ADDIDATA,
5337 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5344 { PCI_VENDOR_ID_ADDIDATA,
5345 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5352 { PCI_VENDOR_ID_ADDIDATA,
5353 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5360 { PCI_VENDOR_ID_AMCC,
5361 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5368 { PCI_VENDOR_ID_ADDIDATA,
5369 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5376 { PCI_VENDOR_ID_ADDIDATA,
5377 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5384 { PCI_VENDOR_ID_ADDIDATA,
5385 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5392 { PCI_VENDOR_ID_ADDIDATA,
5393 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5400 { PCI_VENDOR_ID_ADDIDATA,
5401 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5408 { PCI_VENDOR_ID_ADDIDATA,
5409 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5416 { PCI_VENDOR_ID_ADDIDATA,
5417 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5424 { PCI_VENDOR_ID_ADDIDATA,
5425 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5430 pbn_ADDIDATA_PCIe_4_3906250 },
5432 { PCI_VENDOR_ID_ADDIDATA,
5433 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5438 pbn_ADDIDATA_PCIe_2_3906250 },
5440 { PCI_VENDOR_ID_ADDIDATA,
5441 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5446 pbn_ADDIDATA_PCIe_1_3906250 },
5448 { PCI_VENDOR_ID_ADDIDATA,
5449 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5454 pbn_ADDIDATA_PCIe_8_3906250 },
5456 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5457 PCI_VENDOR_ID_IBM, 0x0299,
5458 0, 0, pbn_b0_bt_2_115200 },
5461 * other NetMos 9835 devices are most likely handled by the
5462 * parport_serial driver, check drivers/parport/parport_serial.c
5463 * before adding them here.
5466 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5468 0, 0, pbn_b0_1_115200 },
5470 /* the 9901 is a rebranded 9912 */
5471 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5473 0, 0, pbn_b0_1_115200 },
5475 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5477 0, 0, pbn_b0_1_115200 },
5479 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5481 0, 0, pbn_b0_1_115200 },
5483 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5485 0, 0, pbn_b0_1_115200 },
5487 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5489 0, 0, pbn_NETMOS9900_2s_115200 },
5492 * Best Connectivity and Rosewill PCI Multi I/O cards
5495 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5497 0, 0, pbn_b0_1_115200 },
5499 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5501 0, 0, pbn_b0_bt_2_115200 },
5503 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5505 0, 0, pbn_b0_bt_4_115200 },
5507 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5509 pbn_ce4100_1_115200 },
5510 /* Intel BayTrail */
5511 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5512 PCI_ANY_ID, PCI_ANY_ID,
5513 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5515 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5516 PCI_ANY_ID, PCI_ANY_ID,
5517 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5519 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5520 PCI_ANY_ID, PCI_ANY_ID,
5521 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5523 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5524 PCI_ANY_ID, PCI_ANY_ID,
5525 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5528 /* Intel Broadwell */
5529 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5530 PCI_ANY_ID, PCI_ANY_ID,
5531 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5533 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5534 PCI_ANY_ID, PCI_ANY_ID,
5535 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5541 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5547 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5552 * Broadcom TruManage
5554 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5556 pbn_brcm_trumanage },
5559 * AgeStar as-prs2-009
5561 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5562 PCI_ANY_ID, PCI_ANY_ID,
5563 0, 0, pbn_b0_bt_2_115200 },
5566 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5567 * so not listed here.
5569 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5570 PCI_ANY_ID, PCI_ANY_ID,
5571 0, 0, pbn_b0_bt_4_115200 },
5573 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5574 PCI_ANY_ID, PCI_ANY_ID,
5575 0, 0, pbn_b0_bt_2_115200 },
5577 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5578 PCI_ANY_ID, PCI_ANY_ID,
5579 0, 0, pbn_wch384_4 },
5582 * Commtech, Inc. Fastcom adapters
5584 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5585 PCI_ANY_ID, PCI_ANY_ID,
5587 0, pbn_b0_2_1152000_200 },
5588 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5589 PCI_ANY_ID, PCI_ANY_ID,
5591 0, pbn_b0_4_1152000_200 },
5592 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5593 PCI_ANY_ID, PCI_ANY_ID,
5595 0, pbn_b0_4_1152000_200 },
5596 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5597 PCI_ANY_ID, PCI_ANY_ID,
5599 0, pbn_b0_8_1152000_200 },
5600 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5601 PCI_ANY_ID, PCI_ANY_ID,
5603 0, pbn_exar_XR17V352 },
5604 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5605 PCI_ANY_ID, PCI_ANY_ID,
5607 0, pbn_exar_XR17V354 },
5608 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5609 PCI_ANY_ID, PCI_ANY_ID,
5611 0, pbn_exar_XR17V358 },
5613 /* Fintek PCI serial cards */
5614 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5615 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5616 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5619 * These entries match devices with class COMMUNICATION_SERIAL,
5620 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5622 { PCI_ANY_ID, PCI_ANY_ID,
5623 PCI_ANY_ID, PCI_ANY_ID,
5624 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5625 0xffff00, pbn_default },
5626 { PCI_ANY_ID, PCI_ANY_ID,
5627 PCI_ANY_ID, PCI_ANY_ID,
5628 PCI_CLASS_COMMUNICATION_MODEM << 8,
5629 0xffff00, pbn_default },
5630 { PCI_ANY_ID, PCI_ANY_ID,
5631 PCI_ANY_ID, PCI_ANY_ID,
5632 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5633 0xffff00, pbn_default },
5637 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5638 pci_channel_state_t state)
5640 struct serial_private *priv = pci_get_drvdata(dev);
5642 if (state == pci_channel_io_perm_failure)
5643 return PCI_ERS_RESULT_DISCONNECT;
5646 pciserial_suspend_ports(priv);
5648 pci_disable_device(dev);
5650 return PCI_ERS_RESULT_NEED_RESET;
5653 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5657 rc = pci_enable_device(dev);
5660 return PCI_ERS_RESULT_DISCONNECT;
5662 pci_restore_state(dev);
5663 pci_save_state(dev);
5665 return PCI_ERS_RESULT_RECOVERED;
5668 static void serial8250_io_resume(struct pci_dev *dev)
5670 struct serial_private *priv = pci_get_drvdata(dev);
5673 pciserial_resume_ports(priv);
5676 static const struct pci_error_handlers serial8250_err_handler = {
5677 .error_detected = serial8250_io_error_detected,
5678 .slot_reset = serial8250_io_slot_reset,
5679 .resume = serial8250_io_resume,
5682 static struct pci_driver serial_pci_driver = {
5684 .probe = pciserial_init_one,
5685 .remove = pciserial_remove_one,
5687 .pm = &pciserial_pm_ops,
5689 .id_table = serial_pci_tbl,
5690 .err_handler = &serial8250_err_handler,
5693 module_pci_driver(serial_pci_driver);
5695 MODULE_LICENSE("GPL");
5696 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5697 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);