2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
28 #include <linux/dmaengine.h>
29 #include <linux/platform_data/dma-dw.h>
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*probe)(struct pci_dev *dev);
45 int (*init)(struct pci_dev *dev);
46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
48 struct uart_8250_port *, int);
49 void (*exit)(struct pci_dev *dev);
52 #define PCI_NUM_BAR_RESOURCES 6
54 struct serial_private {
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
62 static int pci_default_setup(struct serial_private*,
63 const struct pciserial_board*, struct uart_8250_port *, int);
65 static void moan_device(const char *str, struct pci_dev *dev)
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to rmk+serial@arm.linux.org.uk.\n",
73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
79 int bar, int offset, int regshift)
81 struct pci_dev *dev = priv->dev;
82 unsigned long base, len;
84 if (bar >= PCI_NUM_BAR_RESOURCES)
87 base = pci_resource_start(dev, bar);
89 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
90 len = pci_resource_len(dev, bar);
92 if (!priv->remapped_bar[bar])
93 priv->remapped_bar[bar] = ioremap_nocache(base, len);
94 if (!priv->remapped_bar[bar])
97 port->port.iotype = UPIO_MEM;
98 port->port.iobase = 0;
99 port->port.mapbase = base + offset;
100 port->port.membase = priv->remapped_bar[bar] + offset;
101 port->port.regshift = regshift;
103 port->port.iotype = UPIO_PORT;
104 port->port.iobase = base + offset;
105 port->port.mapbase = 0;
106 port->port.membase = NULL;
107 port->port.regshift = 0;
113 * ADDI-DATA GmbH communication cards <info@addi-data.com>
115 static int addidata_apci7800_setup(struct serial_private *priv,
116 const struct pciserial_board *board,
117 struct uart_8250_port *port, int idx)
119 unsigned int bar = 0, offset = board->first_offset;
120 bar = FL_GET_BASE(board->flags);
123 offset += idx * board->uart_offset;
124 } else if ((idx >= 2) && (idx < 4)) {
126 offset += ((idx - 2) * board->uart_offset);
127 } else if ((idx >= 4) && (idx < 6)) {
129 offset += ((idx - 4) * board->uart_offset);
130 } else if (idx >= 6) {
132 offset += ((idx - 6) * board->uart_offset);
135 return setup_port(priv, port, bar, offset, board->reg_shift);
139 * AFAVLAB uses a different mixture of BARs and offsets
140 * Not that ugly ;) -- HW
143 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
144 struct uart_8250_port *port, int idx)
146 unsigned int bar, offset = board->first_offset;
148 bar = FL_GET_BASE(board->flags);
153 offset += (idx - 4) * board->uart_offset;
156 return setup_port(priv, port, bar, offset, board->reg_shift);
160 * HP's Remote Management Console. The Diva chip came in several
161 * different versions. N-class, L2000 and A500 have two Diva chips, each
162 * with 3 UARTs (the third UART on the second chip is unused). Superdome
163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
164 * one Diva chip, but it has been expanded to 5 UARTs.
166 static int pci_hp_diva_init(struct pci_dev *dev)
170 switch (dev->subsystem_device) {
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
174 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
184 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
193 * HP's Diva chip puts the 4th/5th serial port further out, and
194 * some serial ports are supposed to be hidden on certain models.
197 pci_hp_diva_setup(struct serial_private *priv,
198 const struct pciserial_board *board,
199 struct uart_8250_port *port, int idx)
201 unsigned int offset = board->first_offset;
202 unsigned int bar = FL_GET_BASE(board->flags);
204 switch (priv->dev->subsystem_device) {
205 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
209 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
219 offset += idx * board->uart_offset;
221 return setup_port(priv, port, bar, offset, board->reg_shift);
225 * Added for EKF Intel i960 serial boards
227 static int pci_inteli960ni_init(struct pci_dev *dev)
229 unsigned long oldval;
231 if (!(dev->subsystem_device & 0x1000))
234 /* is firmware started? */
235 pci_read_config_dword(dev, 0x44, (void *)&oldval);
236 if (oldval == 0x00001000L) { /* RESET value */
237 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
244 * Some PCI serial cards using the PLX 9050 PCI interface chip require
245 * that the card interrupt be explicitly enabled or disabled. This
246 * seems to be mainly needed on card using the PLX which also use I/O
249 static int pci_plx9050_init(struct pci_dev *dev)
254 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
255 moan_device("no memory in bar 0", dev);
260 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
261 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
264 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
265 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
267 * As the megawolf cards have the int pins active
268 * high, and have 2 UART chips, both ints must be
269 * enabled on the 9050. Also, the UARTS are set in
270 * 16450 mode by default, so we have to enable the
271 * 16C950 'enhanced' mode so that we can use the
276 * enable/disable interrupts
278 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
281 writel(irq_config, p + 0x4c);
284 * Read the register back to ensure that it took effect.
292 static void pci_plx9050_exit(struct pci_dev *dev)
296 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
302 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
307 * Read the register back to ensure that it took effect.
314 #define NI8420_INT_ENABLE_REG 0x38
315 #define NI8420_INT_ENABLE_BIT 0x2000
317 static void pci_ni8420_exit(struct pci_dev *dev)
320 unsigned long base, len;
321 unsigned int bar = 0;
323 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
324 moan_device("no memory in bar", dev);
328 base = pci_resource_start(dev, bar);
329 len = pci_resource_len(dev, bar);
330 p = ioremap_nocache(base, len);
334 /* Disable the CPU Interrupt */
335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
336 p + NI8420_INT_ENABLE_REG);
342 #define MITE_IOWBSR1 0xc4
343 #define MITE_IOWCR1 0xf4
344 #define MITE_LCIMR1 0x08
345 #define MITE_LCIMR2 0x10
347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
349 static void pci_ni8430_exit(struct pci_dev *dev)
352 unsigned long base, len;
353 unsigned int bar = 0;
355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
356 moan_device("no memory in bar", dev);
360 base = pci_resource_start(dev, bar);
361 len = pci_resource_len(dev, bar);
362 p = ioremap_nocache(base, len);
366 /* Disable the CPU Interrupt */
367 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
371 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
373 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
374 struct uart_8250_port *port, int idx)
376 unsigned int bar, offset = board->first_offset;
381 /* first four channels map to 0, 0x100, 0x200, 0x300 */
382 offset += idx * board->uart_offset;
383 } else if (idx < 8) {
384 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
385 offset += idx * board->uart_offset + 0xC00;
386 } else /* we have only 8 ports on PMC-OCTALPRO */
389 return setup_port(priv, port, bar, offset, board->reg_shift);
393 * This does initialization for PMC OCTALPRO cards:
394 * maps the device memory, resets the UARTs (needed, bc
395 * if the module is removed and inserted again, the card
396 * is in the sleep mode) and enables global interrupt.
399 /* global control register offset for SBS PMC-OctalPro */
400 #define OCT_REG_CR_OFF 0x500
402 static int sbs_init(struct pci_dev *dev)
406 p = pci_ioremap_bar(dev, 0);
410 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
411 writeb(0x10, p + OCT_REG_CR_OFF);
413 writeb(0x0, p + OCT_REG_CR_OFF);
415 /* Set bit-2 (INTENABLE) of Control Register */
416 writeb(0x4, p + OCT_REG_CR_OFF);
423 * Disables the global interrupt of PMC-OctalPro
426 static void sbs_exit(struct pci_dev *dev)
430 p = pci_ioremap_bar(dev, 0);
431 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
433 writeb(0, p + OCT_REG_CR_OFF);
438 * SIIG serial cards have an PCI interface chip which also controls
439 * the UART clocking frequency. Each UART can be clocked independently
440 * (except cards equipped with 4 UARTs) and initial clocking settings
441 * are stored in the EEPROM chip. It can cause problems because this
442 * version of serial driver doesn't support differently clocked UART's
443 * on single PCI card. To prevent this, initialization functions set
444 * high frequency clocking for all UART's on given card. It is safe (I
445 * hope) because it doesn't touch EEPROM settings to prevent conflicts
446 * with other OSes (like M$ DOS).
448 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
450 * There is two family of SIIG serial cards with different PCI
451 * interface chip and different configuration methods:
452 * - 10x cards have control registers in IO and/or memory space;
453 * - 20x cards have control registers in standard PCI configuration space.
455 * Note: all 10x cards have PCI device ids 0x10..
456 * all 20x cards have PCI device ids 0x20..
458 * There are also Quartet Serial cards which use Oxford Semiconductor
459 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
461 * Note: some SIIG cards are probed by the parport_serial object.
464 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
465 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
467 static int pci_siig10x_init(struct pci_dev *dev)
472 switch (dev->device & 0xfff8) {
473 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
476 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
479 default: /* 1S1P, 4S */
484 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
488 writew(readw(p + 0x28) & data, p + 0x28);
494 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
495 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
497 static int pci_siig20x_init(struct pci_dev *dev)
501 /* Change clock frequency for the first UART. */
502 pci_read_config_byte(dev, 0x6f, &data);
503 pci_write_config_byte(dev, 0x6f, data & 0xef);
505 /* If this card has 2 UART, we have to do the same with second UART. */
506 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
507 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
508 pci_read_config_byte(dev, 0x73, &data);
509 pci_write_config_byte(dev, 0x73, data & 0xef);
514 static int pci_siig_init(struct pci_dev *dev)
516 unsigned int type = dev->device & 0xff00;
519 return pci_siig10x_init(dev);
520 else if (type == 0x2000)
521 return pci_siig20x_init(dev);
523 moan_device("Unknown SIIG card", dev);
527 static int pci_siig_setup(struct serial_private *priv,
528 const struct pciserial_board *board,
529 struct uart_8250_port *port, int idx)
531 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
535 offset = (idx - 4) * 8;
538 return setup_port(priv, port, bar, offset, 0);
542 * Timedia has an explosion of boards, and to avoid the PCI table from
543 * growing *huge*, we use this function to collapse some 70 entries
544 * in the PCI table into one, for sanity's and compactness's sake.
546 static const unsigned short timedia_single_port[] = {
547 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
550 static const unsigned short timedia_dual_port[] = {
551 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
552 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
553 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
554 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
558 static const unsigned short timedia_quad_port[] = {
559 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
560 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
561 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
565 static const unsigned short timedia_eight_port[] = {
566 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
567 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
570 static const struct timedia_struct {
572 const unsigned short *ids;
574 { 1, timedia_single_port },
575 { 2, timedia_dual_port },
576 { 4, timedia_quad_port },
577 { 8, timedia_eight_port }
581 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
582 * listing them individually, this driver merely grabs them all with
583 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
584 * and should be left free to be claimed by parport_serial instead.
586 static int pci_timedia_probe(struct pci_dev *dev)
589 * Check the third digit of the subdevice ID
590 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
592 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
594 "ignoring Timedia subdevice %04x for parport_serial\n",
595 dev->subsystem_device);
602 static int pci_timedia_init(struct pci_dev *dev)
604 const unsigned short *ids;
607 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
608 ids = timedia_data[i].ids;
609 for (j = 0; ids[j]; j++)
610 if (dev->subsystem_device == ids[j])
611 return timedia_data[i].num;
617 * Timedia/SUNIX uses a mixture of BARs and offsets
618 * Ugh, this is ugly as all hell --- TYT
621 pci_timedia_setup(struct serial_private *priv,
622 const struct pciserial_board *board,
623 struct uart_8250_port *port, int idx)
625 unsigned int bar = 0, offset = board->first_offset;
632 offset = board->uart_offset;
639 offset = board->uart_offset;
648 return setup_port(priv, port, bar, offset, board->reg_shift);
652 * Some Titan cards are also a little weird
655 titan_400l_800l_setup(struct serial_private *priv,
656 const struct pciserial_board *board,
657 struct uart_8250_port *port, int idx)
659 unsigned int bar, offset = board->first_offset;
670 offset = (idx - 2) * board->uart_offset;
673 return setup_port(priv, port, bar, offset, board->reg_shift);
676 static int pci_xircom_init(struct pci_dev *dev)
682 static int pci_ni8420_init(struct pci_dev *dev)
685 unsigned long base, len;
686 unsigned int bar = 0;
688 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
689 moan_device("no memory in bar", dev);
693 base = pci_resource_start(dev, bar);
694 len = pci_resource_len(dev, bar);
695 p = ioremap_nocache(base, len);
699 /* Enable CPU Interrupt */
700 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
701 p + NI8420_INT_ENABLE_REG);
707 #define MITE_IOWBSR1_WSIZE 0xa
708 #define MITE_IOWBSR1_WIN_OFFSET 0x800
709 #define MITE_IOWBSR1_WENAB (1 << 7)
710 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
711 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
712 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
714 static int pci_ni8430_init(struct pci_dev *dev)
717 unsigned long base, len;
719 unsigned int bar = 0;
721 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
722 moan_device("no memory in bar", dev);
726 base = pci_resource_start(dev, bar);
727 len = pci_resource_len(dev, bar);
728 p = ioremap_nocache(base, len);
732 /* Set device window address and size in BAR0 */
733 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
734 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
735 writel(device_window, p + MITE_IOWBSR1);
737 /* Set window access to go to RAMSEL IO address space */
738 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
741 /* Enable IO Bus Interrupt 0 */
742 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
744 /* Enable CPU Interrupt */
745 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
751 /* UART Port Control Register */
752 #define NI8430_PORTCON 0x0f
753 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
756 pci_ni8430_setup(struct serial_private *priv,
757 const struct pciserial_board *board,
758 struct uart_8250_port *port, int idx)
761 unsigned long base, len;
762 unsigned int bar, offset = board->first_offset;
764 if (idx >= board->num_ports)
767 bar = FL_GET_BASE(board->flags);
768 offset += idx * board->uart_offset;
770 base = pci_resource_start(priv->dev, bar);
771 len = pci_resource_len(priv->dev, bar);
772 p = ioremap_nocache(base, len);
774 /* enable the transceiver */
775 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
776 p + offset + NI8430_PORTCON);
780 return setup_port(priv, port, bar, offset, board->reg_shift);
783 static int pci_netmos_9900_setup(struct serial_private *priv,
784 const struct pciserial_board *board,
785 struct uart_8250_port *port, int idx)
789 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
790 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
791 /* netmos apparently orders BARs by datasheet layout, so serial
792 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
796 return setup_port(priv, port, bar, 0, board->reg_shift);
798 return pci_default_setup(priv, board, port, idx);
802 /* the 99xx series comes with a range of device IDs and a variety
805 * 9900 has varying capabilities and can cascade to sub-controllers
806 * (cascading should be purely internal)
807 * 9904 is hardwired with 4 serial ports
808 * 9912 and 9922 are hardwired with 2 serial ports
810 static int pci_netmos_9900_numports(struct pci_dev *dev)
812 unsigned int c = dev->class;
814 unsigned short sub_serports;
820 } else if ((pi == 0) &&
821 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
822 /* two possibilities: 0x30ps encodes number of parallel and
823 * serial ports, or 0x1000 indicates *something*. This is not
824 * immediately obvious, since the 2s1p+4s configuration seems
825 * to offer all functionality on functions 0..2, while still
826 * advertising the same function 3 as the 4s+2s1p config.
828 sub_serports = dev->subsystem_device & 0xf;
829 if (sub_serports > 0) {
832 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
837 moan_device("unknown NetMos/Mostech program interface", dev);
841 static int pci_netmos_init(struct pci_dev *dev)
843 /* subdevice 0x00PS means <P> parallel, <S> serial */
844 unsigned int num_serial = dev->subsystem_device & 0xf;
846 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
847 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
850 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
851 dev->subsystem_device == 0x0299)
854 switch (dev->device) { /* FALLTHROUGH on all */
855 case PCI_DEVICE_ID_NETMOS_9904:
856 case PCI_DEVICE_ID_NETMOS_9912:
857 case PCI_DEVICE_ID_NETMOS_9922:
858 case PCI_DEVICE_ID_NETMOS_9900:
859 num_serial = pci_netmos_9900_numports(dev);
863 if (num_serial == 0 ) {
864 moan_device("unknown NetMos/Mostech device", dev);
875 * These chips are available with optionally one parallel port and up to
876 * two serial ports. Unfortunately they all have the same product id.
878 * Basic configuration is done over a region of 32 I/O ports. The base
879 * ioport is called INTA or INTC, depending on docs/other drivers.
881 * The region of the 32 I/O ports is configured in POSIO0R...
885 #define ITE_887x_MISCR 0x9c
886 #define ITE_887x_INTCBAR 0x78
887 #define ITE_887x_UARTBAR 0x7c
888 #define ITE_887x_PS0BAR 0x10
889 #define ITE_887x_POSIO0 0x60
892 #define ITE_887x_IOSIZE 32
893 /* I/O space size (bits 26-24; 8 bytes = 011b) */
894 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
895 /* I/O space size (bits 26-24; 32 bytes = 101b) */
896 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
897 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
898 #define ITE_887x_POSIO_SPEED (3 << 29)
899 /* enable IO_Space bit */
900 #define ITE_887x_POSIO_ENABLE (1 << 31)
902 static int pci_ite887x_init(struct pci_dev *dev)
904 /* inta_addr are the configuration addresses of the ITE */
905 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
908 struct resource *iobase = NULL;
909 u32 miscr, uartbar, ioport;
911 /* search for the base-ioport */
913 while (inta_addr[i] && iobase == NULL) {
914 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
916 if (iobase != NULL) {
917 /* write POSIO0R - speed | size | ioport */
918 pci_write_config_dword(dev, ITE_887x_POSIO0,
919 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
920 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
921 /* write INTCBAR - ioport */
922 pci_write_config_dword(dev, ITE_887x_INTCBAR,
924 ret = inb(inta_addr[i]);
926 /* ioport connected */
929 release_region(iobase->start, ITE_887x_IOSIZE);
936 dev_err(&dev->dev, "ite887x: could not find iobase\n");
940 /* start of undocumented type checking (see parport_pc.c) */
941 type = inb(iobase->start + 0x18) & 0x0f;
944 case 0x2: /* ITE8871 (1P) */
945 case 0xa: /* ITE8875 (1P) */
948 case 0xe: /* ITE8872 (2S1P) */
951 case 0x6: /* ITE8873 (1S) */
954 case 0x8: /* ITE8874 (2S) */
958 moan_device("Unknown ITE887x", dev);
962 /* configure all serial ports */
963 for (i = 0; i < ret; i++) {
964 /* read the I/O port from the device */
965 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
967 ioport &= 0x0000FF00; /* the actual base address */
968 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
969 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
970 ITE_887x_POSIO_IOSIZE_8 | ioport);
972 /* write the ioport to the UARTBAR */
973 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
974 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
975 uartbar |= (ioport << (16 * i)); /* set the ioport */
976 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
978 /* get current config */
979 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
980 /* disable interrupts (UARTx_Routing[3:0]) */
981 miscr &= ~(0xf << (12 - 4 * i));
982 /* activate the UART (UARTx_En) */
983 miscr |= 1 << (23 - i);
984 /* write new config with activated UART */
985 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
989 /* the device has no UARTs if we get here */
990 release_region(iobase->start, ITE_887x_IOSIZE);
996 static void pci_ite887x_exit(struct pci_dev *dev)
999 /* the ioport is bit 0-15 in POSIO0R */
1000 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1002 release_region(ioport, ITE_887x_IOSIZE);
1006 * Oxford Semiconductor Inc.
1007 * Check that device is part of the Tornado range of devices, then determine
1008 * the number of ports available on the device.
1010 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1013 unsigned long deviceID;
1014 unsigned int number_uarts = 0;
1016 /* OxSemi Tornado devices are all 0xCxxx */
1017 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1018 (dev->device & 0xF000) != 0xC000)
1021 p = pci_iomap(dev, 0, 5);
1025 deviceID = ioread32(p);
1026 /* Tornado device */
1027 if (deviceID == 0x07000200) {
1028 number_uarts = ioread8(p + 4);
1030 "%d ports detected on Oxford PCI Express device\n",
1033 pci_iounmap(dev, p);
1034 return number_uarts;
1037 static int pci_asix_setup(struct serial_private *priv,
1038 const struct pciserial_board *board,
1039 struct uart_8250_port *port, int idx)
1041 port->bugs |= UART_BUG_PARITY;
1042 return pci_default_setup(priv, board, port, idx);
1045 /* Quatech devices have their own extra interface features */
1047 struct quatech_feature {
1052 #define QPCR_TEST_FOR1 0x3F
1053 #define QPCR_TEST_GET1 0x00
1054 #define QPCR_TEST_FOR2 0x40
1055 #define QPCR_TEST_GET2 0x40
1056 #define QPCR_TEST_FOR3 0x80
1057 #define QPCR_TEST_GET3 0x40
1058 #define QPCR_TEST_FOR4 0xC0
1059 #define QPCR_TEST_GET4 0x80
1061 #define QOPR_CLOCK_X1 0x0000
1062 #define QOPR_CLOCK_X2 0x0001
1063 #define QOPR_CLOCK_X4 0x0002
1064 #define QOPR_CLOCK_X8 0x0003
1065 #define QOPR_CLOCK_RATE_MASK 0x0003
1068 static struct quatech_feature quatech_cards[] = {
1069 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1073 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1074 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1075 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1078 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1079 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1080 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1084 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1086 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1087 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1091 static int pci_quatech_amcc(u16 devid)
1093 struct quatech_feature *qf = &quatech_cards[0];
1095 if (qf->devid == devid)
1099 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1103 static int pci_quatech_rqopr(struct uart_8250_port *port)
1105 unsigned long base = port->port.iobase;
1108 LCR = inb(base + UART_LCR);
1109 outb(0xBF, base + UART_LCR);
1110 val = inb(base + UART_SCR);
1111 outb(LCR, base + UART_LCR);
1115 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1117 unsigned long base = port->port.iobase;
1120 LCR = inb(base + UART_LCR);
1121 outb(0xBF, base + UART_LCR);
1122 val = inb(base + UART_SCR);
1123 outb(qopr, base + UART_SCR);
1124 outb(LCR, base + UART_LCR);
1127 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1129 unsigned long base = port->port.iobase;
1132 LCR = inb(base + UART_LCR);
1133 outb(0xBF, base + UART_LCR);
1134 val = inb(base + UART_SCR);
1135 outb(val | 0x10, base + UART_SCR);
1136 qmcr = inb(base + UART_MCR);
1137 outb(val, base + UART_SCR);
1138 outb(LCR, base + UART_LCR);
1143 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1145 unsigned long base = port->port.iobase;
1148 LCR = inb(base + UART_LCR);
1149 outb(0xBF, base + UART_LCR);
1150 val = inb(base + UART_SCR);
1151 outb(val | 0x10, base + UART_SCR);
1152 outb(qmcr, base + UART_MCR);
1153 outb(val, base + UART_SCR);
1154 outb(LCR, base + UART_LCR);
1157 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1159 unsigned long base = port->port.iobase;
1162 LCR = inb(base + UART_LCR);
1163 outb(0xBF, base + UART_LCR);
1164 val = inb(base + UART_SCR);
1166 outb(0x80, UART_LCR);
1167 if (!(inb(UART_SCR) & 0x20)) {
1168 outb(LCR, base + UART_LCR);
1175 static int pci_quatech_test(struct uart_8250_port *port)
1178 u8 qopr = pci_quatech_rqopr(port);
1179 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1180 reg = pci_quatech_rqopr(port) & 0xC0;
1181 if (reg != QPCR_TEST_GET1)
1183 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1184 reg = pci_quatech_rqopr(port) & 0xC0;
1185 if (reg != QPCR_TEST_GET2)
1187 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1188 reg = pci_quatech_rqopr(port) & 0xC0;
1189 if (reg != QPCR_TEST_GET3)
1191 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1192 reg = pci_quatech_rqopr(port) & 0xC0;
1193 if (reg != QPCR_TEST_GET4)
1196 pci_quatech_wqopr(port, qopr);
1200 static int pci_quatech_clock(struct uart_8250_port *port)
1203 unsigned long clock;
1205 if (pci_quatech_test(port) < 0)
1208 qopr = pci_quatech_rqopr(port);
1210 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1211 reg = pci_quatech_rqopr(port);
1212 if (reg & QOPR_CLOCK_X8) {
1216 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1217 reg = pci_quatech_rqopr(port);
1218 if (!(reg & QOPR_CLOCK_X8)) {
1222 reg &= QOPR_CLOCK_X8;
1223 if (reg == QOPR_CLOCK_X2) {
1225 set = QOPR_CLOCK_X2;
1226 } else if (reg == QOPR_CLOCK_X4) {
1228 set = QOPR_CLOCK_X4;
1229 } else if (reg == QOPR_CLOCK_X8) {
1231 set = QOPR_CLOCK_X8;
1234 set = QOPR_CLOCK_X1;
1236 qopr &= ~QOPR_CLOCK_RATE_MASK;
1240 pci_quatech_wqopr(port, qopr);
1244 static int pci_quatech_rs422(struct uart_8250_port *port)
1249 if (!pci_quatech_has_qmcr(port))
1251 qmcr = pci_quatech_rqmcr(port);
1252 pci_quatech_wqmcr(port, 0xFF);
1253 if (pci_quatech_rqmcr(port))
1255 pci_quatech_wqmcr(port, qmcr);
1259 static int pci_quatech_init(struct pci_dev *dev)
1261 if (pci_quatech_amcc(dev->device)) {
1262 unsigned long base = pci_resource_start(dev, 0);
1265 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1266 tmp = inl(base + 0x3c);
1267 outl(tmp | 0x01000000, base + 0x3c);
1268 outl(tmp &= ~0x01000000, base + 0x3c);
1274 static int pci_quatech_setup(struct serial_private *priv,
1275 const struct pciserial_board *board,
1276 struct uart_8250_port *port, int idx)
1278 /* Needed by pci_quatech calls below */
1279 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1280 /* Set up the clocking */
1281 port->port.uartclk = pci_quatech_clock(port);
1282 /* For now just warn about RS422 */
1283 if (pci_quatech_rs422(port))
1284 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1285 return pci_default_setup(priv, board, port, idx);
1288 static void pci_quatech_exit(struct pci_dev *dev)
1292 static int pci_default_setup(struct serial_private *priv,
1293 const struct pciserial_board *board,
1294 struct uart_8250_port *port, int idx)
1296 unsigned int bar, offset = board->first_offset, maxnr;
1298 bar = FL_GET_BASE(board->flags);
1299 if (board->flags & FL_BASE_BARS)
1302 offset += idx * board->uart_offset;
1304 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1305 (board->reg_shift + 3);
1307 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1310 return setup_port(priv, port, bar, offset, board->reg_shift);
1313 static int pci_pericom_setup(struct serial_private *priv,
1314 const struct pciserial_board *board,
1315 struct uart_8250_port *port, int idx)
1317 unsigned int bar, offset = board->first_offset, maxnr;
1319 bar = FL_GET_BASE(board->flags);
1320 if (board->flags & FL_BASE_BARS)
1323 offset += idx * board->uart_offset;
1325 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1326 (board->reg_shift + 3);
1328 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331 port->port.uartclk = 14745600;
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1337 ce4100_serial_setup(struct serial_private *priv,
1338 const struct pciserial_board *board,
1339 struct uart_8250_port *port, int idx)
1343 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1344 port->port.iotype = UPIO_MEM32;
1345 port->port.type = PORT_XSCALE;
1346 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1347 port->port.regshift = 2;
1352 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1355 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1358 #define BYT_PRV_CLK 0x800
1359 #define BYT_PRV_CLK_EN (1 << 0)
1360 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1361 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1362 #define BYT_PRV_CLK_UPDATE (1 << 31)
1364 #define BYT_GENERAL_REG 0x808
1365 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1367 #define BYT_TX_OVF_INT 0x820
1368 #define BYT_TX_OVF_INT_MASK (1 << 1)
1371 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1372 struct ktermios *old)
1374 unsigned int baud = tty_termios_baud_rate(termios);
1379 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1380 * dividers must be adjusted.
1382 * uartclk = (m / n) * 100 MHz, where m <= n
1391 p->uartclk = 64000000;
1396 p->uartclk = 56000000;
1402 p->uartclk = 48000000;
1407 p->uartclk = 40000000;
1412 p->uartclk = 73728000;
1415 /* Reset the clock */
1416 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1417 writel(reg, p->membase + BYT_PRV_CLK);
1418 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1419 writel(reg, p->membase + BYT_PRV_CLK);
1422 * If auto-handshake mechanism is not enabled,
1423 * disable rts_n override
1425 reg = readl(p->membase + BYT_GENERAL_REG);
1426 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1427 if (termios->c_cflag & CRTSCTS)
1428 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1429 writel(reg, p->membase + BYT_GENERAL_REG);
1431 serial8250_do_set_termios(p, termios, old);
1434 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1436 struct dw_dma_slave *dws = param;
1438 if (dws->dma_dev != chan->device->dev)
1441 chan->private = dws;
1446 byt_serial_setup(struct serial_private *priv,
1447 const struct pciserial_board *board,
1448 struct uart_8250_port *port, int idx)
1450 struct pci_dev *pdev = priv->dev;
1451 struct device *dev = port->port.dev;
1452 struct uart_8250_dma *dma;
1453 struct dw_dma_slave *tx_param, *rx_param;
1454 struct pci_dev *dma_dev;
1457 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1461 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1465 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1469 switch (pdev->device) {
1470 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1471 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1472 rx_param->src_id = 3;
1473 tx_param->dst_id = 2;
1475 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1476 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1477 rx_param->src_id = 5;
1478 tx_param->dst_id = 4;
1484 rx_param->src_master = 1;
1485 rx_param->dst_master = 0;
1487 dma->rxconf.src_maxburst = 16;
1489 tx_param->src_master = 1;
1490 tx_param->dst_master = 0;
1492 dma->txconf.dst_maxburst = 16;
1494 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1495 rx_param->dma_dev = &dma_dev->dev;
1496 tx_param->dma_dev = &dma_dev->dev;
1498 dma->fn = byt_dma_filter;
1499 dma->rx_param = rx_param;
1500 dma->tx_param = tx_param;
1502 ret = pci_default_setup(priv, board, port, idx);
1503 port->port.iotype = UPIO_MEM;
1504 port->port.type = PORT_16550A;
1505 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1506 port->port.set_termios = byt_set_termios;
1507 port->port.fifosize = 64;
1508 port->tx_loadsz = 64;
1510 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1512 /* Disable Tx counter interrupts */
1513 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1519 pci_omegapci_setup(struct serial_private *priv,
1520 const struct pciserial_board *board,
1521 struct uart_8250_port *port, int idx)
1523 return setup_port(priv, port, 2, idx * 8, 0);
1527 pci_brcm_trumanage_setup(struct serial_private *priv,
1528 const struct pciserial_board *board,
1529 struct uart_8250_port *port, int idx)
1531 int ret = pci_default_setup(priv, board, port, idx);
1533 port->port.type = PORT_BRCM_TRUMANAGE;
1534 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1538 static int pci_fintek_setup(struct serial_private *priv,
1539 const struct pciserial_board *board,
1540 struct uart_8250_port *port, int idx)
1542 struct pci_dev *pdev = priv->dev;
1544 unsigned long iobase;
1545 unsigned long ciobase = 0;
1549 * We are supposed to be able to read these from the PCI config space,
1550 * but the values there don't seem to match what we need to use, so
1551 * just use these hard-coded values for now, as they are correct.
1554 case 0: iobase = 0xe000; config_base = 0x40; break;
1555 case 1: iobase = 0xe008; config_base = 0x48; break;
1556 case 2: iobase = 0xe010; config_base = 0x50; break;
1557 case 3: iobase = 0xe018; config_base = 0x58; break;
1558 case 4: iobase = 0xe020; config_base = 0x60; break;
1559 case 5: iobase = 0xe028; config_base = 0x68; break;
1560 case 6: iobase = 0xe030; config_base = 0x70; break;
1561 case 7: iobase = 0xe038; config_base = 0x78; break;
1562 case 8: iobase = 0xe040; config_base = 0x80; break;
1563 case 9: iobase = 0xe048; config_base = 0x88; break;
1564 case 10: iobase = 0xe050; config_base = 0x90; break;
1565 case 11: iobase = 0xe058; config_base = 0x98; break;
1567 /* Unknown number of ports, get out of here */
1572 base = pci_resource_start(priv->dev, 3);
1573 ciobase = (int)(base + (0x8 * idx));
1576 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1577 __func__, idx, iobase, ciobase, config_base);
1579 /* Enable UART I/O port */
1580 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1582 /* Select 128-byte FIFO and 8x FIFO threshold */
1583 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1586 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1589 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1591 /* irq number, this usually fails, but the spec says to do it anyway. */
1592 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1594 port->port.iotype = UPIO_PORT;
1595 port->port.iobase = iobase;
1596 port->port.mapbase = 0;
1597 port->port.membase = NULL;
1598 port->port.regshift = 0;
1603 static int skip_tx_en_setup(struct serial_private *priv,
1604 const struct pciserial_board *board,
1605 struct uart_8250_port *port, int idx)
1607 port->port.flags |= UPF_NO_TXEN_TEST;
1608 dev_dbg(&priv->dev->dev,
1609 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1610 priv->dev->vendor, priv->dev->device,
1611 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1613 return pci_default_setup(priv, board, port, idx);
1616 static void kt_handle_break(struct uart_port *p)
1618 struct uart_8250_port *up = up_to_u8250p(p);
1620 * On receipt of a BI, serial device in Intel ME (Intel
1621 * management engine) needs to have its fifos cleared for sane
1622 * SOL (Serial Over Lan) output.
1624 serial8250_clear_and_reinit_fifos(up);
1627 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1629 struct uart_8250_port *up = up_to_u8250p(p);
1633 * When the Intel ME (management engine) gets reset its serial
1634 * port registers could return 0 momentarily. Functions like
1635 * serial8250_console_write, read and save the IER, perform
1636 * some operation and then restore it. In order to avoid
1637 * setting IER register inadvertently to 0, if the value read
1638 * is 0, double check with ier value in uart_8250_port and use
1639 * that instead. up->ier should be the same value as what is
1640 * currently configured.
1642 val = inb(p->iobase + offset);
1643 if (offset == UART_IER) {
1650 static int kt_serial_setup(struct serial_private *priv,
1651 const struct pciserial_board *board,
1652 struct uart_8250_port *port, int idx)
1654 port->port.flags |= UPF_BUG_THRE;
1655 port->port.serial_in = kt_serial_in;
1656 port->port.handle_break = kt_handle_break;
1657 return skip_tx_en_setup(priv, board, port, idx);
1660 static int pci_eg20t_init(struct pci_dev *dev)
1662 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1670 pci_xr17c154_setup(struct serial_private *priv,
1671 const struct pciserial_board *board,
1672 struct uart_8250_port *port, int idx)
1674 port->port.flags |= UPF_EXAR_EFR;
1675 return pci_default_setup(priv, board, port, idx);
1679 pci_xr17v35x_setup(struct serial_private *priv,
1680 const struct pciserial_board *board,
1681 struct uart_8250_port *port, int idx)
1685 p = pci_ioremap_bar(priv->dev, 0);
1689 port->port.flags |= UPF_EXAR_EFR;
1692 * Setup Multipurpose Input/Output pins.
1695 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1696 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1697 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1698 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1699 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1700 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1701 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1702 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1703 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1704 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1705 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1706 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1708 writeb(0x00, p + UART_EXAR_8XMODE);
1709 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1710 writeb(128, p + UART_EXAR_TXTRG);
1711 writeb(128, p + UART_EXAR_RXTRG);
1714 return pci_default_setup(priv, board, port, idx);
1717 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1718 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1719 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1720 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1723 pci_fastcom335_setup(struct serial_private *priv,
1724 const struct pciserial_board *board,
1725 struct uart_8250_port *port, int idx)
1729 p = pci_ioremap_bar(priv->dev, 0);
1733 port->port.flags |= UPF_EXAR_EFR;
1736 * Setup Multipurpose Input/Output pins.
1739 switch (priv->dev->device) {
1740 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1741 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1742 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1743 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1744 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1746 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1747 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1748 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1749 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1750 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1753 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1754 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1755 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1757 writeb(0x00, p + UART_EXAR_8XMODE);
1758 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1759 writeb(32, p + UART_EXAR_TXTRG);
1760 writeb(32, p + UART_EXAR_RXTRG);
1763 return pci_default_setup(priv, board, port, idx);
1767 pci_wch_ch353_setup(struct serial_private *priv,
1768 const struct pciserial_board *board,
1769 struct uart_8250_port *port, int idx)
1771 port->port.flags |= UPF_FIXED_TYPE;
1772 port->port.type = PORT_16550A;
1773 return pci_default_setup(priv, board, port, idx);
1776 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1777 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1778 #define PCI_DEVICE_ID_OCTPRO 0x0001
1779 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1780 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1781 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1782 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1783 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1784 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1785 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1786 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1787 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1788 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1789 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1790 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1791 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1792 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1793 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1794 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1795 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1796 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1797 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1798 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1799 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1800 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1801 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1802 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1803 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1804 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1805 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1806 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1807 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1808 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1809 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1810 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1811 #define PCI_VENDOR_ID_WCH 0x4348
1812 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1813 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1814 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1815 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1816 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1817 #define PCI_VENDOR_ID_AGESTAR 0x5372
1818 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1819 #define PCI_VENDOR_ID_ASIX 0x9710
1820 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1821 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1822 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1823 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1824 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1826 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1827 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1830 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1831 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1832 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1835 * Master list of serial port init/setup/exit quirks.
1836 * This does not describe the general nature of the port.
1837 * (ie, baud base, number and location of ports, etc)
1839 * This list is ordered alphabetically by vendor then device.
1840 * Specific entries must come before more generic entries.
1842 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1844 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1847 .vendor = PCI_VENDOR_ID_AMCC,
1848 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1849 .subvendor = PCI_ANY_ID,
1850 .subdevice = PCI_ANY_ID,
1851 .setup = addidata_apci7800_setup,
1854 * AFAVLAB cards - these may be called via parport_serial
1855 * It is not clear whether this applies to all products.
1858 .vendor = PCI_VENDOR_ID_AFAVLAB,
1859 .device = PCI_ANY_ID,
1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .setup = afavlab_setup,
1868 .vendor = PCI_VENDOR_ID_HP,
1869 .device = PCI_DEVICE_ID_HP_DIVA,
1870 .subvendor = PCI_ANY_ID,
1871 .subdevice = PCI_ANY_ID,
1872 .init = pci_hp_diva_init,
1873 .setup = pci_hp_diva_setup,
1879 .vendor = PCI_VENDOR_ID_INTEL,
1880 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1881 .subvendor = 0xe4bf,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_inteli960ni_init,
1884 .setup = pci_default_setup,
1887 .vendor = PCI_VENDOR_ID_INTEL,
1888 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1889 .subvendor = PCI_ANY_ID,
1890 .subdevice = PCI_ANY_ID,
1891 .setup = skip_tx_en_setup,
1894 .vendor = PCI_VENDOR_ID_INTEL,
1895 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1896 .subvendor = PCI_ANY_ID,
1897 .subdevice = PCI_ANY_ID,
1898 .setup = skip_tx_en_setup,
1901 .vendor = PCI_VENDOR_ID_INTEL,
1902 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1903 .subvendor = PCI_ANY_ID,
1904 .subdevice = PCI_ANY_ID,
1905 .setup = skip_tx_en_setup,
1908 .vendor = PCI_VENDOR_ID_INTEL,
1909 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1910 .subvendor = PCI_ANY_ID,
1911 .subdevice = PCI_ANY_ID,
1912 .setup = ce4100_serial_setup,
1915 .vendor = PCI_VENDOR_ID_INTEL,
1916 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .setup = kt_serial_setup,
1922 .vendor = PCI_VENDOR_ID_INTEL,
1923 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1924 .subvendor = PCI_ANY_ID,
1925 .subdevice = PCI_ANY_ID,
1926 .setup = byt_serial_setup,
1929 .vendor = PCI_VENDOR_ID_INTEL,
1930 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1931 .subvendor = PCI_ANY_ID,
1932 .subdevice = PCI_ANY_ID,
1933 .setup = byt_serial_setup,
1936 .vendor = PCI_VENDOR_ID_INTEL,
1937 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .setup = byt_serial_setup,
1943 .vendor = PCI_VENDOR_ID_INTEL,
1944 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
1945 .subvendor = PCI_ANY_ID,
1946 .subdevice = PCI_ANY_ID,
1947 .setup = byt_serial_setup,
1953 .vendor = PCI_VENDOR_ID_ITE,
1954 .device = PCI_DEVICE_ID_ITE_8872,
1955 .subvendor = PCI_ANY_ID,
1956 .subdevice = PCI_ANY_ID,
1957 .init = pci_ite887x_init,
1958 .setup = pci_default_setup,
1959 .exit = pci_ite887x_exit,
1962 * National Instruments
1965 .vendor = PCI_VENDOR_ID_NI,
1966 .device = PCI_DEVICE_ID_NI_PCI23216,
1967 .subvendor = PCI_ANY_ID,
1968 .subdevice = PCI_ANY_ID,
1969 .init = pci_ni8420_init,
1970 .setup = pci_default_setup,
1971 .exit = pci_ni8420_exit,
1974 .vendor = PCI_VENDOR_ID_NI,
1975 .device = PCI_DEVICE_ID_NI_PCI2328,
1976 .subvendor = PCI_ANY_ID,
1977 .subdevice = PCI_ANY_ID,
1978 .init = pci_ni8420_init,
1979 .setup = pci_default_setup,
1980 .exit = pci_ni8420_exit,
1983 .vendor = PCI_VENDOR_ID_NI,
1984 .device = PCI_DEVICE_ID_NI_PCI2324,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .init = pci_ni8420_init,
1988 .setup = pci_default_setup,
1989 .exit = pci_ni8420_exit,
1992 .vendor = PCI_VENDOR_ID_NI,
1993 .device = PCI_DEVICE_ID_NI_PCI2322,
1994 .subvendor = PCI_ANY_ID,
1995 .subdevice = PCI_ANY_ID,
1996 .init = pci_ni8420_init,
1997 .setup = pci_default_setup,
1998 .exit = pci_ni8420_exit,
2001 .vendor = PCI_VENDOR_ID_NI,
2002 .device = PCI_DEVICE_ID_NI_PCI2324I,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .init = pci_ni8420_init,
2006 .setup = pci_default_setup,
2007 .exit = pci_ni8420_exit,
2010 .vendor = PCI_VENDOR_ID_NI,
2011 .device = PCI_DEVICE_ID_NI_PCI2322I,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .init = pci_ni8420_init,
2015 .setup = pci_default_setup,
2016 .exit = pci_ni8420_exit,
2019 .vendor = PCI_VENDOR_ID_NI,
2020 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2021 .subvendor = PCI_ANY_ID,
2022 .subdevice = PCI_ANY_ID,
2023 .init = pci_ni8420_init,
2024 .setup = pci_default_setup,
2025 .exit = pci_ni8420_exit,
2028 .vendor = PCI_VENDOR_ID_NI,
2029 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2030 .subvendor = PCI_ANY_ID,
2031 .subdevice = PCI_ANY_ID,
2032 .init = pci_ni8420_init,
2033 .setup = pci_default_setup,
2034 .exit = pci_ni8420_exit,
2037 .vendor = PCI_VENDOR_ID_NI,
2038 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .init = pci_ni8420_init,
2042 .setup = pci_default_setup,
2043 .exit = pci_ni8420_exit,
2046 .vendor = PCI_VENDOR_ID_NI,
2047 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2048 .subvendor = PCI_ANY_ID,
2049 .subdevice = PCI_ANY_ID,
2050 .init = pci_ni8420_init,
2051 .setup = pci_default_setup,
2052 .exit = pci_ni8420_exit,
2055 .vendor = PCI_VENDOR_ID_NI,
2056 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .init = pci_ni8420_init,
2060 .setup = pci_default_setup,
2061 .exit = pci_ni8420_exit,
2064 .vendor = PCI_VENDOR_ID_NI,
2065 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2066 .subvendor = PCI_ANY_ID,
2067 .subdevice = PCI_ANY_ID,
2068 .init = pci_ni8420_init,
2069 .setup = pci_default_setup,
2070 .exit = pci_ni8420_exit,
2073 .vendor = PCI_VENDOR_ID_NI,
2074 .device = PCI_ANY_ID,
2075 .subvendor = PCI_ANY_ID,
2076 .subdevice = PCI_ANY_ID,
2077 .init = pci_ni8430_init,
2078 .setup = pci_ni8430_setup,
2079 .exit = pci_ni8430_exit,
2083 .vendor = PCI_VENDOR_ID_QUATECH,
2084 .device = PCI_ANY_ID,
2085 .subvendor = PCI_ANY_ID,
2086 .subdevice = PCI_ANY_ID,
2087 .init = pci_quatech_init,
2088 .setup = pci_quatech_setup,
2089 .exit = pci_quatech_exit,
2095 .vendor = PCI_VENDOR_ID_PANACOM,
2096 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2097 .subvendor = PCI_ANY_ID,
2098 .subdevice = PCI_ANY_ID,
2099 .init = pci_plx9050_init,
2100 .setup = pci_default_setup,
2101 .exit = pci_plx9050_exit,
2104 .vendor = PCI_VENDOR_ID_PANACOM,
2105 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2106 .subvendor = PCI_ANY_ID,
2107 .subdevice = PCI_ANY_ID,
2108 .init = pci_plx9050_init,
2109 .setup = pci_default_setup,
2110 .exit = pci_plx9050_exit,
2118 .subvendor = PCI_ANY_ID,
2119 .subdevice = PCI_ANY_ID,
2120 .setup = pci_pericom_setup,
2125 .subvendor = PCI_ANY_ID,
2126 .subdevice = PCI_ANY_ID,
2127 .setup = pci_pericom_setup,
2132 .subvendor = PCI_ANY_ID,
2133 .subdevice = PCI_ANY_ID,
2134 .setup = pci_pericom_setup,
2141 .vendor = PCI_VENDOR_ID_PLX,
2142 .device = PCI_DEVICE_ID_PLX_9030,
2143 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2144 .subdevice = PCI_ANY_ID,
2145 .setup = pci_default_setup,
2148 .vendor = PCI_VENDOR_ID_PLX,
2149 .device = PCI_DEVICE_ID_PLX_9050,
2150 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2151 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2152 .init = pci_plx9050_init,
2153 .setup = pci_default_setup,
2154 .exit = pci_plx9050_exit,
2157 .vendor = PCI_VENDOR_ID_PLX,
2158 .device = PCI_DEVICE_ID_PLX_9050,
2159 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2160 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2161 .init = pci_plx9050_init,
2162 .setup = pci_default_setup,
2163 .exit = pci_plx9050_exit,
2166 .vendor = PCI_VENDOR_ID_PLX,
2167 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2168 .subvendor = PCI_VENDOR_ID_PLX,
2169 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2170 .init = pci_plx9050_init,
2171 .setup = pci_default_setup,
2172 .exit = pci_plx9050_exit,
2175 * SBS Technologies, Inc., PMC-OCTALPRO 232
2178 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2179 .device = PCI_DEVICE_ID_OCTPRO,
2180 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2181 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2187 * SBS Technologies, Inc., PMC-OCTALPRO 422
2190 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2191 .device = PCI_DEVICE_ID_OCTPRO,
2192 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2193 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2199 * SBS Technologies, Inc., P-Octal 232
2202 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2203 .device = PCI_DEVICE_ID_OCTPRO,
2204 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2205 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2211 * SBS Technologies, Inc., P-Octal 422
2214 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2215 .device = PCI_DEVICE_ID_OCTPRO,
2216 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2217 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2223 * SIIG cards - these may be called via parport_serial
2226 .vendor = PCI_VENDOR_ID_SIIG,
2227 .device = PCI_ANY_ID,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .init = pci_siig_init,
2231 .setup = pci_siig_setup,
2237 .vendor = PCI_VENDOR_ID_TITAN,
2238 .device = PCI_DEVICE_ID_TITAN_400L,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .setup = titan_400l_800l_setup,
2244 .vendor = PCI_VENDOR_ID_TITAN,
2245 .device = PCI_DEVICE_ID_TITAN_800L,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = titan_400l_800l_setup,
2254 .vendor = PCI_VENDOR_ID_TIMEDIA,
2255 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2256 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2257 .subdevice = PCI_ANY_ID,
2258 .probe = pci_timedia_probe,
2259 .init = pci_timedia_init,
2260 .setup = pci_timedia_setup,
2263 .vendor = PCI_VENDOR_ID_TIMEDIA,
2264 .device = PCI_ANY_ID,
2265 .subvendor = PCI_ANY_ID,
2266 .subdevice = PCI_ANY_ID,
2267 .setup = pci_timedia_setup,
2270 * SUNIX (Timedia) cards
2271 * Do not "probe" for these cards as there is at least one combination
2272 * card that should be handled by parport_pc that doesn't match the
2273 * rule in pci_timedia_probe.
2274 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2275 * There are some boards with part number SER5037AL that report
2276 * subdevice ID 0x0002.
2279 .vendor = PCI_VENDOR_ID_SUNIX,
2280 .device = PCI_DEVICE_ID_SUNIX_1999,
2281 .subvendor = PCI_VENDOR_ID_SUNIX,
2282 .subdevice = PCI_ANY_ID,
2283 .init = pci_timedia_init,
2284 .setup = pci_timedia_setup,
2290 .vendor = PCI_VENDOR_ID_EXAR,
2291 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2292 .subvendor = PCI_ANY_ID,
2293 .subdevice = PCI_ANY_ID,
2294 .setup = pci_xr17c154_setup,
2297 .vendor = PCI_VENDOR_ID_EXAR,
2298 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2299 .subvendor = PCI_ANY_ID,
2300 .subdevice = PCI_ANY_ID,
2301 .setup = pci_xr17c154_setup,
2304 .vendor = PCI_VENDOR_ID_EXAR,
2305 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2306 .subvendor = PCI_ANY_ID,
2307 .subdevice = PCI_ANY_ID,
2308 .setup = pci_xr17c154_setup,
2311 .vendor = PCI_VENDOR_ID_EXAR,
2312 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .setup = pci_xr17v35x_setup,
2318 .vendor = PCI_VENDOR_ID_EXAR,
2319 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .setup = pci_xr17v35x_setup,
2325 .vendor = PCI_VENDOR_ID_EXAR,
2326 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .setup = pci_xr17v35x_setup,
2335 .vendor = PCI_VENDOR_ID_XIRCOM,
2336 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
2339 .init = pci_xircom_init,
2340 .setup = pci_default_setup,
2343 * Netmos cards - these may be called via parport_serial
2346 .vendor = PCI_VENDOR_ID_NETMOS,
2347 .device = PCI_ANY_ID,
2348 .subvendor = PCI_ANY_ID,
2349 .subdevice = PCI_ANY_ID,
2350 .init = pci_netmos_init,
2351 .setup = pci_netmos_9900_setup,
2354 * For Oxford Semiconductor Tornado based devices
2357 .vendor = PCI_VENDOR_ID_OXSEMI,
2358 .device = PCI_ANY_ID,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .init = pci_oxsemi_tornado_init,
2362 .setup = pci_default_setup,
2365 .vendor = PCI_VENDOR_ID_MAINPINE,
2366 .device = PCI_ANY_ID,
2367 .subvendor = PCI_ANY_ID,
2368 .subdevice = PCI_ANY_ID,
2369 .init = pci_oxsemi_tornado_init,
2370 .setup = pci_default_setup,
2373 .vendor = PCI_VENDOR_ID_DIGI,
2374 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2375 .subvendor = PCI_SUBVENDOR_ID_IBM,
2376 .subdevice = PCI_ANY_ID,
2377 .init = pci_oxsemi_tornado_init,
2378 .setup = pci_default_setup,
2381 .vendor = PCI_VENDOR_ID_INTEL,
2383 .subvendor = PCI_ANY_ID,
2384 .subdevice = PCI_ANY_ID,
2385 .init = pci_eg20t_init,
2386 .setup = pci_default_setup,
2389 .vendor = PCI_VENDOR_ID_INTEL,
2391 .subvendor = PCI_ANY_ID,
2392 .subdevice = PCI_ANY_ID,
2393 .init = pci_eg20t_init,
2394 .setup = pci_default_setup,
2397 .vendor = PCI_VENDOR_ID_INTEL,
2399 .subvendor = PCI_ANY_ID,
2400 .subdevice = PCI_ANY_ID,
2401 .init = pci_eg20t_init,
2402 .setup = pci_default_setup,
2405 .vendor = PCI_VENDOR_ID_INTEL,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .init = pci_eg20t_init,
2410 .setup = pci_default_setup,
2415 .subvendor = PCI_ANY_ID,
2416 .subdevice = PCI_ANY_ID,
2417 .init = pci_eg20t_init,
2418 .setup = pci_default_setup,
2423 .subvendor = PCI_ANY_ID,
2424 .subdevice = PCI_ANY_ID,
2425 .init = pci_eg20t_init,
2426 .setup = pci_default_setup,
2431 .subvendor = PCI_ANY_ID,
2432 .subdevice = PCI_ANY_ID,
2433 .init = pci_eg20t_init,
2434 .setup = pci_default_setup,
2439 .subvendor = PCI_ANY_ID,
2440 .subdevice = PCI_ANY_ID,
2441 .init = pci_eg20t_init,
2442 .setup = pci_default_setup,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .init = pci_eg20t_init,
2450 .setup = pci_default_setup,
2453 * Cronyx Omega PCI (PLX-chip based)
2456 .vendor = PCI_VENDOR_ID_PLX,
2457 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2458 .subvendor = PCI_ANY_ID,
2459 .subdevice = PCI_ANY_ID,
2460 .setup = pci_omegapci_setup,
2462 /* WCH CH353 1S1P card (16550 clone) */
2464 .vendor = PCI_VENDOR_ID_WCH,
2465 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2466 .subvendor = PCI_ANY_ID,
2467 .subdevice = PCI_ANY_ID,
2468 .setup = pci_wch_ch353_setup,
2470 /* WCH CH353 2S1P card (16550 clone) */
2472 .vendor = PCI_VENDOR_ID_WCH,
2473 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .setup = pci_wch_ch353_setup,
2478 /* WCH CH353 4S card (16550 clone) */
2480 .vendor = PCI_VENDOR_ID_WCH,
2481 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2482 .subvendor = PCI_ANY_ID,
2483 .subdevice = PCI_ANY_ID,
2484 .setup = pci_wch_ch353_setup,
2486 /* WCH CH353 2S1PF card (16550 clone) */
2488 .vendor = PCI_VENDOR_ID_WCH,
2489 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = pci_wch_ch353_setup,
2494 /* WCH CH352 2S card (16550 clone) */
2496 .vendor = PCI_VENDOR_ID_WCH,
2497 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2498 .subvendor = PCI_ANY_ID,
2499 .subdevice = PCI_ANY_ID,
2500 .setup = pci_wch_ch353_setup,
2503 * ASIX devices with FIFO bug
2506 .vendor = PCI_VENDOR_ID_ASIX,
2507 .device = PCI_ANY_ID,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .setup = pci_asix_setup,
2513 * Commtech, Inc. Fastcom adapters
2517 .vendor = PCI_VENDOR_ID_COMMTECH,
2518 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2519 .subvendor = PCI_ANY_ID,
2520 .subdevice = PCI_ANY_ID,
2521 .setup = pci_fastcom335_setup,
2524 .vendor = PCI_VENDOR_ID_COMMTECH,
2525 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2526 .subvendor = PCI_ANY_ID,
2527 .subdevice = PCI_ANY_ID,
2528 .setup = pci_fastcom335_setup,
2531 .vendor = PCI_VENDOR_ID_COMMTECH,
2532 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2533 .subvendor = PCI_ANY_ID,
2534 .subdevice = PCI_ANY_ID,
2535 .setup = pci_fastcom335_setup,
2538 .vendor = PCI_VENDOR_ID_COMMTECH,
2539 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2540 .subvendor = PCI_ANY_ID,
2541 .subdevice = PCI_ANY_ID,
2542 .setup = pci_fastcom335_setup,
2545 .vendor = PCI_VENDOR_ID_COMMTECH,
2546 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2547 .subvendor = PCI_ANY_ID,
2548 .subdevice = PCI_ANY_ID,
2549 .setup = pci_xr17v35x_setup,
2552 .vendor = PCI_VENDOR_ID_COMMTECH,
2553 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2554 .subvendor = PCI_ANY_ID,
2555 .subdevice = PCI_ANY_ID,
2556 .setup = pci_xr17v35x_setup,
2559 .vendor = PCI_VENDOR_ID_COMMTECH,
2560 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2561 .subvendor = PCI_ANY_ID,
2562 .subdevice = PCI_ANY_ID,
2563 .setup = pci_xr17v35x_setup,
2566 * Broadcom TruManage (NetXtreme)
2569 .vendor = PCI_VENDOR_ID_BROADCOM,
2570 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2571 .subvendor = PCI_ANY_ID,
2572 .subdevice = PCI_ANY_ID,
2573 .setup = pci_brcm_trumanage_setup,
2578 .subvendor = PCI_ANY_ID,
2579 .subdevice = PCI_ANY_ID,
2580 .setup = pci_fintek_setup,
2585 .subvendor = PCI_ANY_ID,
2586 .subdevice = PCI_ANY_ID,
2587 .setup = pci_fintek_setup,
2592 .subvendor = PCI_ANY_ID,
2593 .subdevice = PCI_ANY_ID,
2594 .setup = pci_fintek_setup,
2598 * Default "match everything" terminator entry
2601 .vendor = PCI_ANY_ID,
2602 .device = PCI_ANY_ID,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .setup = pci_default_setup,
2609 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2611 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2614 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2616 struct pci_serial_quirk *quirk;
2618 for (quirk = pci_serial_quirks; ; quirk++)
2619 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2620 quirk_id_matches(quirk->device, dev->device) &&
2621 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2622 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2627 static inline int get_pci_irq(struct pci_dev *dev,
2628 const struct pciserial_board *board)
2630 if (board->flags & FL_NOIRQ)
2637 * This is the configuration table for all of the PCI serial boards
2638 * which we support. It is directly indexed by the pci_board_num_t enum
2639 * value, which is encoded in the pci_device_id PCI probe table's
2640 * driver_data member.
2642 * The makeup of these names are:
2643 * pbn_bn{_bt}_n_baud{_offsetinhex}
2645 * bn = PCI BAR number
2646 * bt = Index using PCI BARs
2647 * n = number of serial ports
2649 * offsetinhex = offset for each sequential port (in hex)
2651 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2653 * Please note: in theory if n = 1, _bt infix should make no difference.
2654 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2656 enum pci_board_num_t {
2673 pbn_b0_2_1152000_200,
2674 pbn_b0_4_1152000_200,
2675 pbn_b0_8_1152000_200,
2680 pbn_b0_2_1843200_200,
2681 pbn_b0_4_1843200_200,
2682 pbn_b0_8_1843200_200,
2756 * Board-specific versions.
2763 pbn_oxsemi_1_4000000,
2764 pbn_oxsemi_2_4000000,
2765 pbn_oxsemi_4_4000000,
2766 pbn_oxsemi_8_4000000,
2779 pbn_exar_ibm_saturn,
2785 pbn_ADDIDATA_PCIe_1_3906250,
2786 pbn_ADDIDATA_PCIe_2_3906250,
2787 pbn_ADDIDATA_PCIe_4_3906250,
2788 pbn_ADDIDATA_PCIe_8_3906250,
2789 pbn_ce4100_1_115200,
2792 pbn_NETMOS9900_2s_115200,
2800 * uart_offset - the space between channels
2801 * reg_shift - describes how the UART registers are mapped
2802 * to PCI memory by the card.
2803 * For example IER register on SBS, Inc. PMC-OctPro is located at
2804 * offset 0x10 from the UART base, while UART_IER is defined as 1
2805 * in include/linux/serial_reg.h,
2806 * see first lines of serial_in() and serial_out() in 8250.c
2809 static struct pciserial_board pci_boards[] = {
2813 .base_baud = 115200,
2816 [pbn_b0_1_115200] = {
2819 .base_baud = 115200,
2822 [pbn_b0_2_115200] = {
2825 .base_baud = 115200,
2828 [pbn_b0_4_115200] = {
2831 .base_baud = 115200,
2834 [pbn_b0_5_115200] = {
2837 .base_baud = 115200,
2840 [pbn_b0_8_115200] = {
2843 .base_baud = 115200,
2846 [pbn_b0_1_921600] = {
2849 .base_baud = 921600,
2852 [pbn_b0_2_921600] = {
2855 .base_baud = 921600,
2858 [pbn_b0_4_921600] = {
2861 .base_baud = 921600,
2865 [pbn_b0_2_1130000] = {
2868 .base_baud = 1130000,
2872 [pbn_b0_4_1152000] = {
2875 .base_baud = 1152000,
2879 [pbn_b0_2_1152000_200] = {
2882 .base_baud = 1152000,
2883 .uart_offset = 0x200,
2886 [pbn_b0_4_1152000_200] = {
2889 .base_baud = 1152000,
2890 .uart_offset = 0x200,
2893 [pbn_b0_8_1152000_200] = {
2896 .base_baud = 1152000,
2897 .uart_offset = 0x200,
2900 [pbn_b0_2_1843200] = {
2903 .base_baud = 1843200,
2906 [pbn_b0_4_1843200] = {
2909 .base_baud = 1843200,
2913 [pbn_b0_2_1843200_200] = {
2916 .base_baud = 1843200,
2917 .uart_offset = 0x200,
2919 [pbn_b0_4_1843200_200] = {
2922 .base_baud = 1843200,
2923 .uart_offset = 0x200,
2925 [pbn_b0_8_1843200_200] = {
2928 .base_baud = 1843200,
2929 .uart_offset = 0x200,
2931 [pbn_b0_1_4000000] = {
2934 .base_baud = 4000000,
2938 [pbn_b0_bt_1_115200] = {
2939 .flags = FL_BASE0|FL_BASE_BARS,
2941 .base_baud = 115200,
2944 [pbn_b0_bt_2_115200] = {
2945 .flags = FL_BASE0|FL_BASE_BARS,
2947 .base_baud = 115200,
2950 [pbn_b0_bt_4_115200] = {
2951 .flags = FL_BASE0|FL_BASE_BARS,
2953 .base_baud = 115200,
2956 [pbn_b0_bt_8_115200] = {
2957 .flags = FL_BASE0|FL_BASE_BARS,
2959 .base_baud = 115200,
2963 [pbn_b0_bt_1_460800] = {
2964 .flags = FL_BASE0|FL_BASE_BARS,
2966 .base_baud = 460800,
2969 [pbn_b0_bt_2_460800] = {
2970 .flags = FL_BASE0|FL_BASE_BARS,
2972 .base_baud = 460800,
2975 [pbn_b0_bt_4_460800] = {
2976 .flags = FL_BASE0|FL_BASE_BARS,
2978 .base_baud = 460800,
2982 [pbn_b0_bt_1_921600] = {
2983 .flags = FL_BASE0|FL_BASE_BARS,
2985 .base_baud = 921600,
2988 [pbn_b0_bt_2_921600] = {
2989 .flags = FL_BASE0|FL_BASE_BARS,
2991 .base_baud = 921600,
2994 [pbn_b0_bt_4_921600] = {
2995 .flags = FL_BASE0|FL_BASE_BARS,
2997 .base_baud = 921600,
3000 [pbn_b0_bt_8_921600] = {
3001 .flags = FL_BASE0|FL_BASE_BARS,
3003 .base_baud = 921600,
3007 [pbn_b1_1_115200] = {
3010 .base_baud = 115200,
3013 [pbn_b1_2_115200] = {
3016 .base_baud = 115200,
3019 [pbn_b1_4_115200] = {
3022 .base_baud = 115200,
3025 [pbn_b1_8_115200] = {
3028 .base_baud = 115200,
3031 [pbn_b1_16_115200] = {
3034 .base_baud = 115200,
3038 [pbn_b1_1_921600] = {
3041 .base_baud = 921600,
3044 [pbn_b1_2_921600] = {
3047 .base_baud = 921600,
3050 [pbn_b1_4_921600] = {
3053 .base_baud = 921600,
3056 [pbn_b1_8_921600] = {
3059 .base_baud = 921600,
3062 [pbn_b1_2_1250000] = {
3065 .base_baud = 1250000,
3069 [pbn_b1_bt_1_115200] = {
3070 .flags = FL_BASE1|FL_BASE_BARS,
3072 .base_baud = 115200,
3075 [pbn_b1_bt_2_115200] = {
3076 .flags = FL_BASE1|FL_BASE_BARS,
3078 .base_baud = 115200,
3081 [pbn_b1_bt_4_115200] = {
3082 .flags = FL_BASE1|FL_BASE_BARS,
3084 .base_baud = 115200,
3088 [pbn_b1_bt_2_921600] = {
3089 .flags = FL_BASE1|FL_BASE_BARS,
3091 .base_baud = 921600,
3095 [pbn_b1_1_1382400] = {
3098 .base_baud = 1382400,
3101 [pbn_b1_2_1382400] = {
3104 .base_baud = 1382400,
3107 [pbn_b1_4_1382400] = {
3110 .base_baud = 1382400,
3113 [pbn_b1_8_1382400] = {
3116 .base_baud = 1382400,
3120 [pbn_b2_1_115200] = {
3123 .base_baud = 115200,
3126 [pbn_b2_2_115200] = {
3129 .base_baud = 115200,
3132 [pbn_b2_4_115200] = {
3135 .base_baud = 115200,
3138 [pbn_b2_8_115200] = {
3141 .base_baud = 115200,
3145 [pbn_b2_1_460800] = {
3148 .base_baud = 460800,
3151 [pbn_b2_4_460800] = {
3154 .base_baud = 460800,
3157 [pbn_b2_8_460800] = {
3160 .base_baud = 460800,
3163 [pbn_b2_16_460800] = {
3166 .base_baud = 460800,
3170 [pbn_b2_1_921600] = {
3173 .base_baud = 921600,
3176 [pbn_b2_4_921600] = {
3179 .base_baud = 921600,
3182 [pbn_b2_8_921600] = {
3185 .base_baud = 921600,
3189 [pbn_b2_8_1152000] = {
3192 .base_baud = 1152000,
3196 [pbn_b2_bt_1_115200] = {
3197 .flags = FL_BASE2|FL_BASE_BARS,
3199 .base_baud = 115200,
3202 [pbn_b2_bt_2_115200] = {
3203 .flags = FL_BASE2|FL_BASE_BARS,
3205 .base_baud = 115200,
3208 [pbn_b2_bt_4_115200] = {
3209 .flags = FL_BASE2|FL_BASE_BARS,
3211 .base_baud = 115200,
3215 [pbn_b2_bt_2_921600] = {
3216 .flags = FL_BASE2|FL_BASE_BARS,
3218 .base_baud = 921600,
3221 [pbn_b2_bt_4_921600] = {
3222 .flags = FL_BASE2|FL_BASE_BARS,
3224 .base_baud = 921600,
3228 [pbn_b3_2_115200] = {
3231 .base_baud = 115200,
3234 [pbn_b3_4_115200] = {
3237 .base_baud = 115200,
3240 [pbn_b3_8_115200] = {
3243 .base_baud = 115200,
3247 [pbn_b4_bt_2_921600] = {
3250 .base_baud = 921600,
3253 [pbn_b4_bt_4_921600] = {
3256 .base_baud = 921600,
3259 [pbn_b4_bt_8_921600] = {
3262 .base_baud = 921600,
3267 * Entries following this are board-specific.
3276 .base_baud = 921600,
3277 .uart_offset = 0x400,
3281 .flags = FL_BASE2|FL_BASE_BARS,
3283 .base_baud = 921600,
3284 .uart_offset = 0x400,
3288 .flags = FL_BASE2|FL_BASE_BARS,
3290 .base_baud = 921600,
3291 .uart_offset = 0x400,
3295 /* I think this entry is broken - the first_offset looks wrong --rmk */
3296 [pbn_plx_romulus] = {
3299 .base_baud = 921600,
3300 .uart_offset = 8 << 2,
3302 .first_offset = 0x03,
3306 * This board uses the size of PCI Base region 0 to
3307 * signal now many ports are available
3310 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3312 .base_baud = 115200,
3315 [pbn_oxsemi_1_4000000] = {
3318 .base_baud = 4000000,
3319 .uart_offset = 0x200,
3320 .first_offset = 0x1000,
3322 [pbn_oxsemi_2_4000000] = {
3325 .base_baud = 4000000,
3326 .uart_offset = 0x200,
3327 .first_offset = 0x1000,
3329 [pbn_oxsemi_4_4000000] = {
3332 .base_baud = 4000000,
3333 .uart_offset = 0x200,
3334 .first_offset = 0x1000,
3336 [pbn_oxsemi_8_4000000] = {
3339 .base_baud = 4000000,
3340 .uart_offset = 0x200,
3341 .first_offset = 0x1000,
3346 * EKF addition for i960 Boards form EKF with serial port.
3349 [pbn_intel_i960] = {
3352 .base_baud = 921600,
3353 .uart_offset = 8 << 2,
3355 .first_offset = 0x10000,
3358 .flags = FL_BASE0|FL_NOIRQ,
3360 .base_baud = 458333,
3363 .first_offset = 0x20178,
3367 * Computone - uses IOMEM.
3369 [pbn_computone_4] = {
3372 .base_baud = 921600,
3373 .uart_offset = 0x40,
3375 .first_offset = 0x200,
3377 [pbn_computone_6] = {
3380 .base_baud = 921600,
3381 .uart_offset = 0x40,
3383 .first_offset = 0x200,
3385 [pbn_computone_8] = {
3388 .base_baud = 921600,
3389 .uart_offset = 0x40,
3391 .first_offset = 0x200,
3396 .base_baud = 460800,
3401 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3402 * Only basic 16550A support.
3403 * XR17C15[24] are not tested, but they should work.
3405 [pbn_exar_XR17C152] = {
3408 .base_baud = 921600,
3409 .uart_offset = 0x200,
3411 [pbn_exar_XR17C154] = {
3414 .base_baud = 921600,
3415 .uart_offset = 0x200,
3417 [pbn_exar_XR17C158] = {
3420 .base_baud = 921600,
3421 .uart_offset = 0x200,
3423 [pbn_exar_XR17V352] = {
3426 .base_baud = 7812500,
3427 .uart_offset = 0x400,
3431 [pbn_exar_XR17V354] = {
3434 .base_baud = 7812500,
3435 .uart_offset = 0x400,
3439 [pbn_exar_XR17V358] = {
3442 .base_baud = 7812500,
3443 .uart_offset = 0x400,
3447 [pbn_exar_ibm_saturn] = {
3450 .base_baud = 921600,
3451 .uart_offset = 0x200,
3455 * PA Semi PWRficient PA6T-1682M on-chip UART
3457 [pbn_pasemi_1682M] = {
3460 .base_baud = 8333333,
3463 * National Instruments 843x
3468 .base_baud = 3686400,
3469 .uart_offset = 0x10,
3470 .first_offset = 0x800,
3475 .base_baud = 3686400,
3476 .uart_offset = 0x10,
3477 .first_offset = 0x800,
3482 .base_baud = 3686400,
3483 .uart_offset = 0x10,
3484 .first_offset = 0x800,
3489 .base_baud = 3686400,
3490 .uart_offset = 0x10,
3491 .first_offset = 0x800,
3494 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3496 [pbn_ADDIDATA_PCIe_1_3906250] = {
3499 .base_baud = 3906250,
3500 .uart_offset = 0x200,
3501 .first_offset = 0x1000,
3503 [pbn_ADDIDATA_PCIe_2_3906250] = {
3506 .base_baud = 3906250,
3507 .uart_offset = 0x200,
3508 .first_offset = 0x1000,
3510 [pbn_ADDIDATA_PCIe_4_3906250] = {
3513 .base_baud = 3906250,
3514 .uart_offset = 0x200,
3515 .first_offset = 0x1000,
3517 [pbn_ADDIDATA_PCIe_8_3906250] = {
3520 .base_baud = 3906250,
3521 .uart_offset = 0x200,
3522 .first_offset = 0x1000,
3524 [pbn_ce4100_1_115200] = {
3525 .flags = FL_BASE_BARS,
3527 .base_baud = 921600,
3531 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3532 * but is overridden by byt_set_termios.
3537 .base_baud = 2764800,
3538 .uart_offset = 0x80,
3544 .base_baud = 115200,
3545 .uart_offset = 0x200,
3547 [pbn_NETMOS9900_2s_115200] = {
3550 .base_baud = 115200,
3552 [pbn_brcm_trumanage] = {
3556 .base_baud = 115200,
3561 .base_baud = 115200,
3562 .first_offset = 0x40,
3567 .base_baud = 115200,
3568 .first_offset = 0x40,
3573 .base_baud = 115200,
3574 .first_offset = 0x40,
3578 static const struct pci_device_id blacklist[] = {
3580 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3581 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3582 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3584 /* multi-io cards handled by parport_serial */
3585 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3586 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3590 * Given a complete unknown PCI device, try to use some heuristics to
3591 * guess what the configuration might be, based on the pitiful PCI
3592 * serial specs. Returns 0 on success, 1 on failure.
3595 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3597 const struct pci_device_id *bldev;
3598 int num_iomem, num_port, first_port = -1, i;
3601 * If it is not a communications device or the programming
3602 * interface is greater than 6, give up.
3604 * (Should we try to make guesses for multiport serial devices
3607 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3608 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3609 (dev->class & 0xff) > 6)
3613 * Do not access blacklisted devices that are known not to
3614 * feature serial ports or are handled by other modules.
3616 for (bldev = blacklist;
3617 bldev < blacklist + ARRAY_SIZE(blacklist);
3619 if (dev->vendor == bldev->vendor &&
3620 dev->device == bldev->device)
3624 num_iomem = num_port = 0;
3625 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3626 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3628 if (first_port == -1)
3631 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3636 * If there is 1 or 0 iomem regions, and exactly one port,
3637 * use it. We guess the number of ports based on the IO
3640 if (num_iomem <= 1 && num_port == 1) {
3641 board->flags = first_port;
3642 board->num_ports = pci_resource_len(dev, first_port) / 8;
3647 * Now guess if we've got a board which indexes by BARs.
3648 * Each IO BAR should be 8 bytes, and they should follow
3653 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3654 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3655 pci_resource_len(dev, i) == 8 &&
3656 (first_port == -1 || (first_port + num_port) == i)) {
3658 if (first_port == -1)
3664 board->flags = first_port | FL_BASE_BARS;
3665 board->num_ports = num_port;
3673 serial_pci_matches(const struct pciserial_board *board,
3674 const struct pciserial_board *guessed)
3677 board->num_ports == guessed->num_ports &&
3678 board->base_baud == guessed->base_baud &&
3679 board->uart_offset == guessed->uart_offset &&
3680 board->reg_shift == guessed->reg_shift &&
3681 board->first_offset == guessed->first_offset;
3684 struct serial_private *
3685 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3687 struct uart_8250_port uart;
3688 struct serial_private *priv;
3689 struct pci_serial_quirk *quirk;
3690 int rc, nr_ports, i;
3692 nr_ports = board->num_ports;
3695 * Find an init and setup quirks.
3697 quirk = find_quirk(dev);
3700 * Run the new-style initialization function.
3701 * The initialization function returns:
3703 * 0 - use board->num_ports
3704 * >0 - number of ports
3707 rc = quirk->init(dev);
3716 priv = kzalloc(sizeof(struct serial_private) +
3717 sizeof(unsigned int) * nr_ports,
3720 priv = ERR_PTR(-ENOMEM);
3725 priv->quirk = quirk;
3727 memset(&uart, 0, sizeof(uart));
3728 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3729 uart.port.uartclk = board->base_baud * 16;
3730 uart.port.irq = get_pci_irq(dev, board);
3731 uart.port.dev = &dev->dev;
3733 for (i = 0; i < nr_ports; i++) {
3734 if (quirk->setup(priv, board, &uart, i))
3737 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3738 uart.port.iobase, uart.port.irq, uart.port.iotype);
3740 priv->line[i] = serial8250_register_8250_port(&uart);
3741 if (priv->line[i] < 0) {
3743 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3744 uart.port.iobase, uart.port.irq,
3745 uart.port.iotype, priv->line[i]);
3758 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3760 void pciserial_remove_ports(struct serial_private *priv)
3762 struct pci_serial_quirk *quirk;
3765 for (i = 0; i < priv->nr; i++)
3766 serial8250_unregister_port(priv->line[i]);
3768 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3769 if (priv->remapped_bar[i])
3770 iounmap(priv->remapped_bar[i]);
3771 priv->remapped_bar[i] = NULL;
3775 * Find the exit quirks.
3777 quirk = find_quirk(priv->dev);
3779 quirk->exit(priv->dev);
3783 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3785 void pciserial_suspend_ports(struct serial_private *priv)
3789 for (i = 0; i < priv->nr; i++)
3790 if (priv->line[i] >= 0)
3791 serial8250_suspend_port(priv->line[i]);
3794 * Ensure that every init quirk is properly torn down
3796 if (priv->quirk->exit)
3797 priv->quirk->exit(priv->dev);
3799 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3801 void pciserial_resume_ports(struct serial_private *priv)
3806 * Ensure that the board is correctly configured.
3808 if (priv->quirk->init)
3809 priv->quirk->init(priv->dev);
3811 for (i = 0; i < priv->nr; i++)
3812 if (priv->line[i] >= 0)
3813 serial8250_resume_port(priv->line[i]);
3815 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3818 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3819 * to the arrangement of serial ports on a PCI card.
3822 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3824 struct pci_serial_quirk *quirk;
3825 struct serial_private *priv;
3826 const struct pciserial_board *board;
3827 struct pciserial_board tmp;
3830 quirk = find_quirk(dev);
3832 rc = quirk->probe(dev);
3837 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3838 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3843 board = &pci_boards[ent->driver_data];
3845 rc = pci_enable_device(dev);
3846 pci_save_state(dev);
3850 if (ent->driver_data == pbn_default) {
3852 * Use a copy of the pci_board entry for this;
3853 * avoid changing entries in the table.
3855 memcpy(&tmp, board, sizeof(struct pciserial_board));
3859 * We matched one of our class entries. Try to
3860 * determine the parameters of this board.
3862 rc = serial_pci_guess_board(dev, &tmp);
3867 * We matched an explicit entry. If we are able to
3868 * detect this boards settings with our heuristic,
3869 * then we no longer need this entry.
3871 memcpy(&tmp, &pci_boards[pbn_default],
3872 sizeof(struct pciserial_board));
3873 rc = serial_pci_guess_board(dev, &tmp);
3874 if (rc == 0 && serial_pci_matches(board, &tmp))
3875 moan_device("Redundant entry in serial pci_table.",
3879 priv = pciserial_init_ports(dev, board);
3880 if (!IS_ERR(priv)) {
3881 pci_set_drvdata(dev, priv);
3888 pci_disable_device(dev);
3892 static void pciserial_remove_one(struct pci_dev *dev)
3894 struct serial_private *priv = pci_get_drvdata(dev);
3896 pciserial_remove_ports(priv);
3898 pci_disable_device(dev);
3902 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3904 struct serial_private *priv = pci_get_drvdata(dev);
3907 pciserial_suspend_ports(priv);
3909 pci_save_state(dev);
3910 pci_set_power_state(dev, pci_choose_state(dev, state));
3914 static int pciserial_resume_one(struct pci_dev *dev)
3917 struct serial_private *priv = pci_get_drvdata(dev);
3919 pci_set_power_state(dev, PCI_D0);
3920 pci_restore_state(dev);
3924 * The device may have been disabled. Re-enable it.
3926 err = pci_enable_device(dev);
3927 /* FIXME: We cannot simply error out here */
3929 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3930 pciserial_resume_ports(priv);
3936 static struct pci_device_id serial_pci_tbl[] = {
3937 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3938 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3939 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3941 /* Advantech also use 0x3618 and 0xf618 */
3942 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3943 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3945 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3946 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3948 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3949 PCI_SUBVENDOR_ID_CONNECT_TECH,
3950 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3952 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3953 PCI_SUBVENDOR_ID_CONNECT_TECH,
3954 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3956 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3957 PCI_SUBVENDOR_ID_CONNECT_TECH,
3958 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3960 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3961 PCI_SUBVENDOR_ID_CONNECT_TECH,
3962 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3964 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3965 PCI_SUBVENDOR_ID_CONNECT_TECH,
3966 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3968 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3969 PCI_SUBVENDOR_ID_CONNECT_TECH,
3970 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3972 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3973 PCI_SUBVENDOR_ID_CONNECT_TECH,
3974 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3976 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3977 PCI_SUBVENDOR_ID_CONNECT_TECH,
3978 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3980 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3981 PCI_SUBVENDOR_ID_CONNECT_TECH,
3982 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3984 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3985 PCI_SUBVENDOR_ID_CONNECT_TECH,
3986 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3988 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3989 PCI_SUBVENDOR_ID_CONNECT_TECH,
3990 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3992 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3993 PCI_SUBVENDOR_ID_CONNECT_TECH,
3994 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3996 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3997 PCI_SUBVENDOR_ID_CONNECT_TECH,
3998 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4000 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4001 PCI_SUBVENDOR_ID_CONNECT_TECH,
4002 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4004 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4005 PCI_SUBVENDOR_ID_CONNECT_TECH,
4006 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4008 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4009 PCI_SUBVENDOR_ID_CONNECT_TECH,
4010 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4012 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4013 PCI_SUBVENDOR_ID_CONNECT_TECH,
4014 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4016 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4017 PCI_VENDOR_ID_AFAVLAB,
4018 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4020 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4021 PCI_SUBVENDOR_ID_CONNECT_TECH,
4022 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4023 pbn_b0_2_1843200_200 },
4024 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4025 PCI_SUBVENDOR_ID_CONNECT_TECH,
4026 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4027 pbn_b0_4_1843200_200 },
4028 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4029 PCI_SUBVENDOR_ID_CONNECT_TECH,
4030 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4031 pbn_b0_8_1843200_200 },
4032 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4033 PCI_SUBVENDOR_ID_CONNECT_TECH,
4034 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4035 pbn_b0_2_1843200_200 },
4036 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4037 PCI_SUBVENDOR_ID_CONNECT_TECH,
4038 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4039 pbn_b0_4_1843200_200 },
4040 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4041 PCI_SUBVENDOR_ID_CONNECT_TECH,
4042 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4043 pbn_b0_8_1843200_200 },
4044 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4045 PCI_SUBVENDOR_ID_CONNECT_TECH,
4046 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4047 pbn_b0_2_1843200_200 },
4048 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4049 PCI_SUBVENDOR_ID_CONNECT_TECH,
4050 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4051 pbn_b0_4_1843200_200 },
4052 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4053 PCI_SUBVENDOR_ID_CONNECT_TECH,
4054 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4055 pbn_b0_8_1843200_200 },
4056 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4057 PCI_SUBVENDOR_ID_CONNECT_TECH,
4058 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4059 pbn_b0_2_1843200_200 },
4060 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4061 PCI_SUBVENDOR_ID_CONNECT_TECH,
4062 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4063 pbn_b0_4_1843200_200 },
4064 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4065 PCI_SUBVENDOR_ID_CONNECT_TECH,
4066 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4067 pbn_b0_8_1843200_200 },
4068 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4069 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4070 0, 0, pbn_exar_ibm_saturn },
4072 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074 pbn_b2_bt_1_115200 },
4075 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 pbn_b2_bt_2_115200 },
4078 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 pbn_b2_bt_4_115200 },
4081 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 pbn_b2_bt_2_115200 },
4084 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 pbn_b2_bt_4_115200 },
4087 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4090 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099 pbn_b2_bt_2_115200 },
4100 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102 pbn_b2_bt_2_921600 },
4104 * VScom SPCOM800, from sl@s.pl
4106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 /* Unknown card - subdevice 0x1584 */
4113 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4115 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4117 /* Unknown card - subdevice 0x1588 */
4118 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4120 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4122 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4123 PCI_SUBVENDOR_ID_KEYSPAN,
4124 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4126 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4133 PCI_VENDOR_ID_ESDGMBH,
4134 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4136 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4137 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4138 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4140 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4141 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4142 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4144 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4145 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4146 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4148 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4149 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4150 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4152 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4153 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4154 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4156 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4157 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4158 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4160 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4161 PCI_SUBVENDOR_ID_EXSYS,
4162 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4165 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4168 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4169 0x10b5, 0x106a, 0, 0,
4172 * Quatech cards. These actually have configurable clocks but for
4173 * now we just use the default.
4175 * 100 series are RS232, 200 series RS422,
4177 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4236 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4239 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4240 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4243 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_b0_bt_2_921600 },
4248 * The below card is a little controversial since it is the
4249 * subject of a PCI vendor/device ID clash. (See
4250 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4251 * For now just used the hex ID 0x950a.
4253 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4254 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4255 0, 0, pbn_b0_2_115200 },
4256 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4257 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4258 0, 0, pbn_b0_2_115200 },
4259 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4263 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4265 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_b0_bt_2_921600 },
4271 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4272 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4276 * Oxford Semiconductor Inc. Tornado PCI express device range.
4278 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_oxsemi_1_4000000 },
4287 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_oxsemi_1_4000000 },
4290 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_oxsemi_1_4000000 },
4299 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_oxsemi_1_4000000 },
4302 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 pbn_oxsemi_2_4000000 },
4317 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 pbn_oxsemi_2_4000000 },
4320 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322 pbn_oxsemi_4_4000000 },
4323 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_oxsemi_4_4000000 },
4326 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_oxsemi_8_4000000 },
4329 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_oxsemi_8_4000000 },
4332 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 pbn_oxsemi_1_4000000 },
4335 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337 pbn_oxsemi_1_4000000 },
4338 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 pbn_oxsemi_1_4000000 },
4341 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343 pbn_oxsemi_1_4000000 },
4344 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346 pbn_oxsemi_1_4000000 },
4347 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 pbn_oxsemi_1_4000000 },
4350 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4352 pbn_oxsemi_1_4000000 },
4353 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 pbn_oxsemi_1_4000000 },
4356 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 pbn_oxsemi_1_4000000 },
4359 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361 pbn_oxsemi_1_4000000 },
4362 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364 pbn_oxsemi_1_4000000 },
4365 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 pbn_oxsemi_1_4000000 },
4368 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 pbn_oxsemi_1_4000000 },
4371 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373 pbn_oxsemi_1_4000000 },
4374 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_oxsemi_1_4000000 },
4377 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 pbn_oxsemi_1_4000000 },
4380 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 pbn_oxsemi_1_4000000 },
4383 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 pbn_oxsemi_1_4000000 },
4386 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 pbn_oxsemi_1_4000000 },
4389 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 pbn_oxsemi_1_4000000 },
4392 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 pbn_oxsemi_1_4000000 },
4395 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_oxsemi_1_4000000 },
4398 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_oxsemi_1_4000000 },
4401 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_oxsemi_1_4000000 },
4404 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_oxsemi_1_4000000 },
4407 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_oxsemi_1_4000000 },
4411 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4413 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4414 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4415 pbn_oxsemi_1_4000000 },
4416 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4417 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4418 pbn_oxsemi_2_4000000 },
4419 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4420 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4421 pbn_oxsemi_4_4000000 },
4422 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4423 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4424 pbn_oxsemi_8_4000000 },
4427 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4429 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4430 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4431 pbn_oxsemi_2_4000000 },
4434 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4435 * from skokodyn@yahoo.com
4437 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4438 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4440 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4441 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4443 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4444 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4446 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4447 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4451 * Digitan DS560-558, from jimd@esoft.com
4453 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 * Titan Electronic cards
4459 * The 400L and 800L have a custom setup quirk.
4461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b1_bt_2_921600 },
4479 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_b0_bt_4_921600 },
4482 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_b0_bt_8_921600 },
4485 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b4_bt_2_921600 },
4488 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_b4_bt_4_921600 },
4491 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_b4_bt_8_921600 },
4494 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_oxsemi_1_4000000 },
4506 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_oxsemi_2_4000000 },
4509 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_oxsemi_4_4000000 },
4512 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_oxsemi_8_4000000 },
4515 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_oxsemi_2_4000000 },
4518 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_oxsemi_2_4000000 },
4521 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_b0_bt_2_921600 },
4524 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b2_bt_2_921600 },
4549 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b2_bt_2_921600 },
4552 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b2_bt_2_921600 },
4555 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b2_bt_4_921600 },
4558 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b2_bt_4_921600 },
4561 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_b2_bt_4_921600 },
4564 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_b0_bt_2_921600 },
4576 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b0_bt_2_921600 },
4579 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b0_bt_2_921600 },
4582 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b0_bt_4_921600 },
4585 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b0_bt_4_921600 },
4588 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b0_bt_4_921600 },
4591 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_bt_8_921600 },
4594 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_bt_8_921600 },
4597 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b0_bt_8_921600 },
4602 * Computone devices submitted by Doug McNash dmcnash@computone.com
4604 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4605 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4606 0, 0, pbn_computone_4 },
4607 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4608 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4609 0, 0, pbn_computone_8 },
4610 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4611 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4612 0, 0, pbn_computone_6 },
4614 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4618 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4619 pbn_b0_bt_1_921600 },
4624 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4625 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4626 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4627 pbn_b0_bt_1_921600 },
4629 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4630 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4631 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4632 pbn_b0_bt_1_921600 },
4635 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4637 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b0_bt_8_115200 },
4640 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b0_bt_8_115200 },
4644 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_b0_bt_2_115200 },
4647 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_b0_bt_2_115200 },
4650 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_b0_bt_2_115200 },
4653 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_b0_bt_2_115200 },
4656 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_b0_bt_2_115200 },
4659 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_b0_bt_4_460800 },
4662 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_b0_bt_4_460800 },
4665 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_b0_bt_2_460800 },
4668 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_b0_bt_2_460800 },
4671 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_b0_bt_2_460800 },
4674 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 pbn_b0_bt_1_115200 },
4677 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679 pbn_b0_bt_1_460800 },
4682 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4683 * Cards are identified by their subsystem vendor IDs, which
4684 * (in hex) match the model number.
4686 * Note that JC140x are RS422/485 cards which require ox950
4687 * ACR = 0x10, and as such are not currently fully supported.
4689 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4690 0x1204, 0x0004, 0, 0,
4692 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4693 0x1208, 0x0004, 0, 0,
4695 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4696 0x1402, 0x0002, 0, 0,
4697 pbn_b0_2_921600 }, */
4698 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4699 0x1404, 0x0004, 0, 0,
4700 pbn_b0_4_921600 }, */
4701 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4702 0x1208, 0x0004, 0, 0,
4705 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4706 0x1204, 0x0004, 0, 0,
4708 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4709 0x1208, 0x0004, 0, 0,
4711 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4712 0x1208, 0x0004, 0, 0,
4715 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4717 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4724 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 * RAStel 2 port modem, gerg@moreton.com.au
4731 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_b2_bt_2_115200 },
4736 * EKF addition for i960 Boards form EKF with serial port
4738 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4739 0xE4BF, PCI_ANY_ID, 0, 0,
4743 * Xircom Cardbus/Ethernet combos
4745 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4751 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 * Untested PCI modems, sent in from various folks...
4760 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4762 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4763 0x1048, 0x1500, 0, 0,
4766 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4773 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4774 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4776 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4796 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4797 PCI_ANY_ID, PCI_ANY_ID,
4799 0, pbn_exar_XR17C152 },
4800 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4801 PCI_ANY_ID, PCI_ANY_ID,
4803 0, pbn_exar_XR17C154 },
4804 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4805 PCI_ANY_ID, PCI_ANY_ID,
4807 0, pbn_exar_XR17C158 },
4809 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4811 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4812 PCI_ANY_ID, PCI_ANY_ID,
4814 0, pbn_exar_XR17V352 },
4815 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4816 PCI_ANY_ID, PCI_ANY_ID,
4818 0, pbn_exar_XR17V354 },
4819 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4820 PCI_ANY_ID, PCI_ANY_ID,
4822 0, pbn_exar_XR17V358 },
4825 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4827 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4833 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4834 PCI_ANY_ID, PCI_ANY_ID,
4836 pbn_b1_bt_1_115200 },
4841 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4847 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4851 * Perle PCI-RAS cards
4853 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4854 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4855 0, 0, pbn_b2_4_921600 },
4856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4857 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4858 0, 0, pbn_b2_8_921600 },
4861 * Mainpine series cards: Fairly standard layout but fools
4862 * parts of the autodetect in some cases and uses otherwise
4863 * unmatched communications subclasses in the PCI Express case
4866 { /* RockForceDUO */
4867 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4868 PCI_VENDOR_ID_MAINPINE, 0x0200,
4869 0, 0, pbn_b0_2_115200 },
4870 { /* RockForceQUATRO */
4871 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4872 PCI_VENDOR_ID_MAINPINE, 0x0300,
4873 0, 0, pbn_b0_4_115200 },
4874 { /* RockForceDUO+ */
4875 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4876 PCI_VENDOR_ID_MAINPINE, 0x0400,
4877 0, 0, pbn_b0_2_115200 },
4878 { /* RockForceQUATRO+ */
4879 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4880 PCI_VENDOR_ID_MAINPINE, 0x0500,
4881 0, 0, pbn_b0_4_115200 },
4883 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4884 PCI_VENDOR_ID_MAINPINE, 0x0600,
4885 0, 0, pbn_b0_2_115200 },
4887 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4888 PCI_VENDOR_ID_MAINPINE, 0x0700,
4889 0, 0, pbn_b0_4_115200 },
4890 { /* RockForceOCTO+ */
4891 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4892 PCI_VENDOR_ID_MAINPINE, 0x0800,
4893 0, 0, pbn_b0_8_115200 },
4894 { /* RockForceDUO+ */
4895 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4896 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4897 0, 0, pbn_b0_2_115200 },
4898 { /* RockForceQUARTRO+ */
4899 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4900 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4901 0, 0, pbn_b0_4_115200 },
4902 { /* RockForceOCTO+ */
4903 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4904 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4905 0, 0, pbn_b0_8_115200 },
4907 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4908 PCI_VENDOR_ID_MAINPINE, 0x2000,
4909 0, 0, pbn_b0_1_115200 },
4911 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4912 PCI_VENDOR_ID_MAINPINE, 0x2100,
4913 0, 0, pbn_b0_1_115200 },
4915 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4916 PCI_VENDOR_ID_MAINPINE, 0x2200,
4917 0, 0, pbn_b0_2_115200 },
4919 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4920 PCI_VENDOR_ID_MAINPINE, 0x2300,
4921 0, 0, pbn_b0_2_115200 },
4923 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4924 PCI_VENDOR_ID_MAINPINE, 0x2400,
4925 0, 0, pbn_b0_4_115200 },
4927 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4928 PCI_VENDOR_ID_MAINPINE, 0x2500,
4929 0, 0, pbn_b0_4_115200 },
4931 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4932 PCI_VENDOR_ID_MAINPINE, 0x2600,
4933 0, 0, pbn_b0_8_115200 },
4935 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4936 PCI_VENDOR_ID_MAINPINE, 0x2700,
4937 0, 0, pbn_b0_8_115200 },
4938 { /* IQ Express D1 */
4939 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4940 PCI_VENDOR_ID_MAINPINE, 0x3000,
4941 0, 0, pbn_b0_1_115200 },
4942 { /* IQ Express F1 */
4943 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4944 PCI_VENDOR_ID_MAINPINE, 0x3100,
4945 0, 0, pbn_b0_1_115200 },
4946 { /* IQ Express D2 */
4947 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4948 PCI_VENDOR_ID_MAINPINE, 0x3200,
4949 0, 0, pbn_b0_2_115200 },
4950 { /* IQ Express F2 */
4951 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4952 PCI_VENDOR_ID_MAINPINE, 0x3300,
4953 0, 0, pbn_b0_2_115200 },
4954 { /* IQ Express D4 */
4955 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4956 PCI_VENDOR_ID_MAINPINE, 0x3400,
4957 0, 0, pbn_b0_4_115200 },
4958 { /* IQ Express F4 */
4959 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4960 PCI_VENDOR_ID_MAINPINE, 0x3500,
4961 0, 0, pbn_b0_4_115200 },
4962 { /* IQ Express D8 */
4963 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4964 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4965 0, 0, pbn_b0_8_115200 },
4966 { /* IQ Express F8 */
4967 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4968 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4969 0, 0, pbn_b0_8_115200 },
4973 * PA Semi PA6T-1682M on-chip UART
4975 { PCI_VENDOR_ID_PASEMI, 0xa004,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 * National Instruments
4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_b1_bt_4_115200 },
4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_b1_bt_2_115200 },
4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_b1_bt_4_115200 },
4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_b1_bt_2_115200 },
5000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5006 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_b1_bt_4_115200 },
5009 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_b1_bt_2_115200 },
5012 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_b1_bt_4_115200 },
5015 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017 pbn_b1_bt_2_115200 },
5018 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5021 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5024 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5030 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5033 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5036 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5039 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5048 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5058 { PCI_VENDOR_ID_ADDIDATA,
5059 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5066 { PCI_VENDOR_ID_ADDIDATA,
5067 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5074 { PCI_VENDOR_ID_ADDIDATA,
5075 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5082 { PCI_VENDOR_ID_AMCC,
5083 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5090 { PCI_VENDOR_ID_ADDIDATA,
5091 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5098 { PCI_VENDOR_ID_ADDIDATA,
5099 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5106 { PCI_VENDOR_ID_ADDIDATA,
5107 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5114 { PCI_VENDOR_ID_ADDIDATA,
5115 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5122 { PCI_VENDOR_ID_ADDIDATA,
5123 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5130 { PCI_VENDOR_ID_ADDIDATA,
5131 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5138 { PCI_VENDOR_ID_ADDIDATA,
5139 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5146 { PCI_VENDOR_ID_ADDIDATA,
5147 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5152 pbn_ADDIDATA_PCIe_4_3906250 },
5154 { PCI_VENDOR_ID_ADDIDATA,
5155 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5160 pbn_ADDIDATA_PCIe_2_3906250 },
5162 { PCI_VENDOR_ID_ADDIDATA,
5163 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5168 pbn_ADDIDATA_PCIe_1_3906250 },
5170 { PCI_VENDOR_ID_ADDIDATA,
5171 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5176 pbn_ADDIDATA_PCIe_8_3906250 },
5178 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5179 PCI_VENDOR_ID_IBM, 0x0299,
5180 0, 0, pbn_b0_bt_2_115200 },
5183 * other NetMos 9835 devices are most likely handled by the
5184 * parport_serial driver, check drivers/parport/parport_serial.c
5185 * before adding them here.
5188 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5190 0, 0, pbn_b0_1_115200 },
5192 /* the 9901 is a rebranded 9912 */
5193 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5195 0, 0, pbn_b0_1_115200 },
5197 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5199 0, 0, pbn_b0_1_115200 },
5201 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5203 0, 0, pbn_b0_1_115200 },
5205 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5207 0, 0, pbn_b0_1_115200 },
5209 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5211 0, 0, pbn_NETMOS9900_2s_115200 },
5214 * Best Connectivity and Rosewill PCI Multi I/O cards
5217 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5219 0, 0, pbn_b0_1_115200 },
5221 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5223 0, 0, pbn_b0_bt_2_115200 },
5225 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5227 0, 0, pbn_b0_bt_4_115200 },
5229 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5231 pbn_ce4100_1_115200 },
5232 /* Intel BayTrail */
5233 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5234 PCI_ANY_ID, PCI_ANY_ID,
5235 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5237 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5238 PCI_ANY_ID, PCI_ANY_ID,
5239 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5241 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5242 PCI_ANY_ID, PCI_ANY_ID,
5243 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5245 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5246 PCI_ANY_ID, PCI_ANY_ID,
5247 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5253 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258 * Broadcom TruManage
5260 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262 pbn_brcm_trumanage },
5265 * AgeStar as-prs2-009
5267 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5268 PCI_ANY_ID, PCI_ANY_ID,
5269 0, 0, pbn_b0_bt_2_115200 },
5272 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5273 * so not listed here.
5275 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5276 PCI_ANY_ID, PCI_ANY_ID,
5277 0, 0, pbn_b0_bt_4_115200 },
5279 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5280 PCI_ANY_ID, PCI_ANY_ID,
5281 0, 0, pbn_b0_bt_2_115200 },
5283 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 0, 0, pbn_b0_bt_2_115200 },
5288 * Commtech, Inc. Fastcom adapters
5290 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5291 PCI_ANY_ID, PCI_ANY_ID,
5293 0, pbn_b0_2_1152000_200 },
5294 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5295 PCI_ANY_ID, PCI_ANY_ID,
5297 0, pbn_b0_4_1152000_200 },
5298 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5299 PCI_ANY_ID, PCI_ANY_ID,
5301 0, pbn_b0_4_1152000_200 },
5302 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5303 PCI_ANY_ID, PCI_ANY_ID,
5305 0, pbn_b0_8_1152000_200 },
5306 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5307 PCI_ANY_ID, PCI_ANY_ID,
5309 0, pbn_exar_XR17V352 },
5310 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5311 PCI_ANY_ID, PCI_ANY_ID,
5313 0, pbn_exar_XR17V354 },
5314 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5315 PCI_ANY_ID, PCI_ANY_ID,
5317 0, pbn_exar_XR17V358 },
5319 /* Fintek PCI serial cards */
5320 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5321 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5322 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5325 * These entries match devices with class COMMUNICATION_SERIAL,
5326 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5328 { PCI_ANY_ID, PCI_ANY_ID,
5329 PCI_ANY_ID, PCI_ANY_ID,
5330 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5331 0xffff00, pbn_default },
5332 { PCI_ANY_ID, PCI_ANY_ID,
5333 PCI_ANY_ID, PCI_ANY_ID,
5334 PCI_CLASS_COMMUNICATION_MODEM << 8,
5335 0xffff00, pbn_default },
5336 { PCI_ANY_ID, PCI_ANY_ID,
5337 PCI_ANY_ID, PCI_ANY_ID,
5338 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5339 0xffff00, pbn_default },
5343 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5344 pci_channel_state_t state)
5346 struct serial_private *priv = pci_get_drvdata(dev);
5348 if (state == pci_channel_io_perm_failure)
5349 return PCI_ERS_RESULT_DISCONNECT;
5352 pciserial_suspend_ports(priv);
5354 pci_disable_device(dev);
5356 return PCI_ERS_RESULT_NEED_RESET;
5359 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5363 rc = pci_enable_device(dev);
5366 return PCI_ERS_RESULT_DISCONNECT;
5368 pci_restore_state(dev);
5369 pci_save_state(dev);
5371 return PCI_ERS_RESULT_RECOVERED;
5374 static void serial8250_io_resume(struct pci_dev *dev)
5376 struct serial_private *priv = pci_get_drvdata(dev);
5379 pciserial_resume_ports(priv);
5382 static const struct pci_error_handlers serial8250_err_handler = {
5383 .error_detected = serial8250_io_error_detected,
5384 .slot_reset = serial8250_io_slot_reset,
5385 .resume = serial8250_io_resume,
5388 static struct pci_driver serial_pci_driver = {
5390 .probe = pciserial_init_one,
5391 .remove = pciserial_remove_one,
5393 .suspend = pciserial_suspend_one,
5394 .resume = pciserial_resume_one,
5396 .id_table = serial_pci_tbl,
5397 .err_handler = &serial8250_err_handler,
5400 module_pci_driver(serial_pci_driver);
5402 MODULE_LICENSE("GPL");
5403 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5404 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);