2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
31 #define DEFAULT_CLK_SPEED 48000000
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
94 struct omap8250_priv {
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
118 #ifdef CONFIG_SERIAL_8250_DMA
119 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
121 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
124 static u32 uart_read(struct uart_8250_port *up, u32 reg)
126 return readl(up->port.membase + (reg << up->port.regshift));
129 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
131 struct uart_8250_port *up = up_to_u8250p(port);
132 struct omap8250_priv *priv = up->port.private_data;
135 serial8250_do_set_mctrl(port, mctrl);
138 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
141 lcr = serial_in(up, UART_LCR);
142 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
143 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
144 priv->efr |= UART_EFR_RTS;
146 priv->efr &= ~UART_EFR_RTS;
147 serial_out(up, UART_EFR, priv->efr);
148 serial_out(up, UART_LCR, lcr);
152 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
153 * The access to uart register after MDR1 Access
154 * causes UART to corrupt data.
157 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
158 * give 10 times as much
160 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
161 struct omap8250_priv *priv)
166 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
167 if (old_mdr1 == priv->mdr1)
170 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
172 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
173 UART_FCR_CLEAR_RCVR);
175 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
176 * TX_FIFO_E bit is 1.
178 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
179 (UART_LSR_THRE | UART_LSR_DR))) {
182 /* Should *never* happen. we warn and carry on */
183 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
184 serial_in(up, UART_LSR));
191 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
192 struct omap8250_priv *priv)
194 unsigned int uartclk = port->uartclk;
195 unsigned int div_13, div_16;
196 unsigned int abs_d13, abs_d16;
199 * Old custom speed handling.
201 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
202 priv->quot = port->custom_divisor & 0xffff;
204 * I assume that nobody is using this. But hey, if somebody
205 * would like to specify the divisor _and_ the mode then the
206 * driver is ready and waiting for it.
208 if (port->custom_divisor & (1 << 16))
209 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
211 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
214 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
215 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
222 abs_d13 = abs(baud - uartclk / 13 / div_13);
223 abs_d16 = abs(baud - uartclk / 16 / div_16);
225 if (abs_d13 >= abs_d16) {
226 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
229 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
234 static void omap8250_update_scr(struct uart_8250_port *up,
235 struct omap8250_priv *priv)
239 old_scr = serial_in(up, UART_OMAP_SCR);
240 if (old_scr == priv->scr)
244 * The manual recommends not to enable the DMA mode selector in the SCR
245 * (instead of the FCR) register _and_ selecting the DMA mode as one
246 * register write because this may lead to malfunction.
248 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
249 serial_out(up, UART_OMAP_SCR,
250 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
251 serial_out(up, UART_OMAP_SCR, priv->scr);
254 static void omap8250_update_mdr1(struct uart_8250_port *up,
255 struct omap8250_priv *priv)
257 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
258 omap_8250_mdr1_errataset(up, priv);
260 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
263 static void omap8250_restore_regs(struct uart_8250_port *up)
265 struct omap8250_priv *priv = up->port.private_data;
266 struct uart_8250_dma *dma = up->dma;
268 if (dma && dma->tx_running) {
270 * TCSANOW requests the change to occur immediately however if
271 * we have a TX-DMA operation in progress then it has been
272 * observed that it might stall and never complete. Therefore we
273 * delay DMA completes to prevent this hang from happen.
275 priv->delayed_restore = 1;
279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
280 serial_out(up, UART_EFR, UART_EFR_ECB);
282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
283 serial8250_out_MCR(up, UART_MCR_TCRTLR);
284 serial_out(up, UART_FCR, up->fcr);
286 omap8250_update_scr(up, priv);
288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
290 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
291 OMAP_UART_TCR_HALT(52));
292 serial_out(up, UART_TI752_TLR,
293 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
294 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
296 serial_out(up, UART_LCR, 0);
298 /* drop TCR + TLR access, we setup XON/XOFF later */
299 serial8250_out_MCR(up, up->mcr);
300 serial_out(up, UART_IER, up->ier);
302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
303 serial_dl_write(up, priv->quot);
305 serial_out(up, UART_EFR, priv->efr);
307 /* Configure flow control */
308 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
309 serial_out(up, UART_XON1, priv->xon);
310 serial_out(up, UART_XOFF1, priv->xoff);
312 serial_out(up, UART_LCR, up->lcr);
314 omap8250_update_mdr1(up, priv);
316 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
320 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
321 * some differences in how we want to handle flow control.
323 static void omap_8250_set_termios(struct uart_port *port,
324 struct ktermios *termios,
325 struct ktermios *old)
327 struct uart_8250_port *up = up_to_u8250p(port);
328 struct omap8250_priv *priv = up->port.private_data;
329 unsigned char cval = 0;
332 switch (termios->c_cflag & CSIZE) {
334 cval = UART_LCR_WLEN5;
337 cval = UART_LCR_WLEN6;
340 cval = UART_LCR_WLEN7;
344 cval = UART_LCR_WLEN8;
348 if (termios->c_cflag & CSTOPB)
349 cval |= UART_LCR_STOP;
350 if (termios->c_cflag & PARENB)
351 cval |= UART_LCR_PARITY;
352 if (!(termios->c_cflag & PARODD))
353 cval |= UART_LCR_EPAR;
354 if (termios->c_cflag & CMSPAR)
355 cval |= UART_LCR_SPAR;
358 * Ask the core to calculate the divisor for us.
360 baud = uart_get_baud_rate(port, termios, old,
361 port->uartclk / 16 / 0xffff,
363 omap_8250_get_divisor(port, baud, priv);
366 * Ok, we're now changing the port state. Do it with
367 * interrupts disabled.
369 pm_runtime_get_sync(port->dev);
370 spin_lock_irq(&port->lock);
373 * Update the per-port timeout.
375 uart_update_timeout(port, termios->c_cflag, baud);
377 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
378 if (termios->c_iflag & INPCK)
379 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
380 if (termios->c_iflag & (IGNBRK | PARMRK))
381 up->port.read_status_mask |= UART_LSR_BI;
384 * Characters to ignore
386 up->port.ignore_status_mask = 0;
387 if (termios->c_iflag & IGNPAR)
388 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
389 if (termios->c_iflag & IGNBRK) {
390 up->port.ignore_status_mask |= UART_LSR_BI;
392 * If we're ignoring parity and break indicators,
393 * ignore overruns too (for real raw support).
395 if (termios->c_iflag & IGNPAR)
396 up->port.ignore_status_mask |= UART_LSR_OE;
400 * ignore all characters if CREAD is not set
402 if ((termios->c_cflag & CREAD) == 0)
403 up->port.ignore_status_mask |= UART_LSR_DR;
406 * Modem status interrupts
408 up->ier &= ~UART_IER_MSI;
409 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
410 up->ier |= UART_IER_MSI;
413 /* Up to here it was mostly serial8250_do_set_termios() */
416 * We enable TRIG_GRANU for RX and TX and additionaly we set
417 * SCR_TX_EMPTY bit. The result is the following:
418 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
419 * - less than RX_TRIGGER number of bytes will also cause an interrupt
420 * once the UART decides that there no new bytes arriving.
421 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
422 * empty - the trigger level is ignored here.
424 * Once DMA is enabled:
425 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
426 * bytes in the TX FIFO. On each assert the DMA engine will move
427 * TX_TRIGGER bytes into the FIFO.
428 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
429 * the FIFO and move RX_TRIGGER bytes.
430 * This is because threshold and trigger values are the same.
432 up->fcr = UART_FCR_ENABLE_FIFO;
433 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
434 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
436 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
437 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
440 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
441 OMAP_UART_SCR_DMAMODE_CTL;
443 priv->xon = termios->c_cc[VSTART];
444 priv->xoff = termios->c_cc[VSTOP];
447 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
449 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
450 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
451 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
452 priv->efr |= UART_EFR_CTS;
453 } else if (up->port.flags & UPF_SOFT_FLOW) {
455 * OMAP rx s/w flow control is borked; the transmitter remains
456 * stuck off even if rx flow control is subsequently disabled
461 * Enable XON/XOFF flow control on output.
462 * Transmit XON1, XOFF1
464 if (termios->c_iflag & IXOFF) {
465 up->port.status |= UPSTAT_AUTOXOFF;
466 priv->efr |= OMAP_UART_SW_TX;
469 omap8250_restore_regs(up);
471 spin_unlock_irq(&up->port.lock);
472 pm_runtime_mark_last_busy(port->dev);
473 pm_runtime_put_autosuspend(port->dev);
475 /* calculate wakeup latency constraint */
476 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
477 priv->latency = priv->calc_latency;
479 schedule_work(&priv->qos_work);
481 /* Don't rewrite B0 */
482 if (tty_termios_baud_rate(termios))
483 tty_termios_encode_baud_rate(termios, baud, baud);
486 /* same as 8250 except that we may have extra flow bits set in EFR */
487 static void omap_8250_pm(struct uart_port *port, unsigned int state,
488 unsigned int oldstate)
490 struct uart_8250_port *up = up_to_u8250p(port);
493 pm_runtime_get_sync(port->dev);
494 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
495 efr = serial_in(up, UART_EFR);
496 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
497 serial_out(up, UART_LCR, 0);
499 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
500 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
501 serial_out(up, UART_EFR, efr);
502 serial_out(up, UART_LCR, 0);
504 pm_runtime_mark_last_busy(port->dev);
505 pm_runtime_put_autosuspend(port->dev);
508 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
509 struct omap8250_priv *priv)
512 u16 revision, major, minor;
514 mvr = uart_read(up, UART_OMAP_MVER);
516 /* Check revision register scheme */
517 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
520 case 0: /* Legacy Scheme: OMAP2/3 */
521 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
522 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
523 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
524 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
527 /* New Scheme: OMAP4+ */
528 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
529 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
530 OMAP_UART_MVR_MAJ_SHIFT;
531 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
534 dev_warn(up->port.dev,
535 "Unknown revision, defaulting to highest\n");
536 /* highest possible revision */
540 /* normalize revision for the driver */
541 revision = UART_BUILD_REVISION(major, minor);
544 case OMAP_UART_REV_46:
545 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
547 case OMAP_UART_REV_52:
548 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
549 OMAP_UART_WER_HAS_TX_WAKEUP;
551 case OMAP_UART_REV_63:
552 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
553 OMAP_UART_WER_HAS_TX_WAKEUP;
560 static void omap8250_uart_qos_work(struct work_struct *work)
562 struct omap8250_priv *priv;
564 priv = container_of(work, struct omap8250_priv, qos_work);
565 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
568 #ifdef CONFIG_SERIAL_8250_DMA
569 static int omap_8250_dma_handle_irq(struct uart_port *port);
572 static irqreturn_t omap8250_irq(int irq, void *dev_id)
574 struct uart_port *port = dev_id;
575 struct uart_8250_port *up = up_to_u8250p(port);
579 #ifdef CONFIG_SERIAL_8250_DMA
581 ret = omap_8250_dma_handle_irq(port);
582 return IRQ_RETVAL(ret);
586 serial8250_rpm_get(up);
587 iir = serial_port_in(port, UART_IIR);
588 ret = serial8250_handle_irq(port, iir);
589 serial8250_rpm_put(up);
591 return IRQ_RETVAL(ret);
594 static int omap_8250_startup(struct uart_port *port)
596 struct uart_8250_port *up = up_to_u8250p(port);
597 struct omap8250_priv *priv = port->private_data;
601 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
606 pm_runtime_get_sync(port->dev);
609 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
611 serial_out(up, UART_LCR, UART_LCR_WLEN8);
613 up->lsr_saved_flags = 0;
614 up->msr_saved_flags = 0;
616 /* Disable DMA for console UART */
617 if (uart_console(port))
621 ret = serial8250_request_dma(up);
623 dev_warn_ratelimited(port->dev,
624 "failed to request DMA\n");
629 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
630 dev_name(port->dev), port);
634 up->ier = UART_IER_RLSI | UART_IER_RDI;
635 serial_out(up, UART_IER, up->ier);
638 up->capabilities |= UART_CAP_RPM;
641 /* Enable module level wake up */
642 priv->wer = OMAP_UART_WER_MOD_WKUP;
643 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
644 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
645 serial_out(up, UART_OMAP_WER, priv->wer);
650 pm_runtime_mark_last_busy(port->dev);
651 pm_runtime_put_autosuspend(port->dev);
654 pm_runtime_mark_last_busy(port->dev);
655 pm_runtime_put_autosuspend(port->dev);
656 dev_pm_clear_wake_irq(port->dev);
660 static void omap_8250_shutdown(struct uart_port *port)
662 struct uart_8250_port *up = up_to_u8250p(port);
663 struct omap8250_priv *priv = port->private_data;
665 flush_work(&priv->qos_work);
667 omap_8250_rx_dma_flush(up);
669 pm_runtime_get_sync(port->dev);
671 serial_out(up, UART_OMAP_WER, 0);
674 serial_out(up, UART_IER, 0);
677 serial8250_release_dma(up);
680 * Disable break condition and FIFOs
682 if (up->lcr & UART_LCR_SBC)
683 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
684 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
686 pm_runtime_mark_last_busy(port->dev);
687 pm_runtime_put_autosuspend(port->dev);
688 free_irq(port->irq, port);
689 dev_pm_clear_wake_irq(port->dev);
692 static void omap_8250_throttle(struct uart_port *port)
694 struct uart_8250_port *up = up_to_u8250p(port);
697 pm_runtime_get_sync(port->dev);
699 spin_lock_irqsave(&port->lock, flags);
700 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
701 serial_out(up, UART_IER, up->ier);
702 spin_unlock_irqrestore(&port->lock, flags);
704 pm_runtime_mark_last_busy(port->dev);
705 pm_runtime_put_autosuspend(port->dev);
708 static int omap_8250_rs485_config(struct uart_port *port,
709 struct serial_rs485 *rs485)
711 struct uart_8250_port *up = up_to_u8250p(port);
713 /* Clamp the delays to [0, 100ms] */
714 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
715 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
717 port->rs485 = *rs485;
720 * Both serial8250_em485_init and serial8250_em485_destroy
723 if (rs485->flags & SER_RS485_ENABLED) {
724 int ret = serial8250_em485_init(up);
727 rs485->flags &= ~SER_RS485_ENABLED;
728 port->rs485.flags &= ~SER_RS485_ENABLED;
733 serial8250_em485_destroy(up);
738 static void omap_8250_unthrottle(struct uart_port *port)
740 struct uart_8250_port *up = up_to_u8250p(port);
743 pm_runtime_get_sync(port->dev);
745 spin_lock_irqsave(&port->lock, flags);
746 up->ier |= UART_IER_RLSI | UART_IER_RDI;
747 serial_out(up, UART_IER, up->ier);
748 spin_unlock_irqrestore(&port->lock, flags);
750 pm_runtime_mark_last_busy(port->dev);
751 pm_runtime_put_autosuspend(port->dev);
754 #ifdef CONFIG_SERIAL_8250_DMA
755 static int omap_8250_rx_dma(struct uart_8250_port *p);
757 static void __dma_rx_do_complete(struct uart_8250_port *p)
759 struct omap8250_priv *priv = p->port.private_data;
760 struct uart_8250_dma *dma = p->dma;
761 struct tty_port *tty_port = &p->port.state->port;
762 struct dma_tx_state state;
767 spin_lock_irqsave(&priv->rx_dma_lock, flags);
769 if (!dma->rx_running)
773 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
775 count = dma->rx_size - state.residue;
777 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
779 p->port.icount.rx += ret;
780 p->port.icount.buf_overrun += count - ret;
782 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
784 tty_flip_buffer_push(tty_port);
787 static void __dma_rx_complete(void *param)
789 struct uart_8250_port *p = param;
790 struct uart_8250_dma *dma = p->dma;
791 struct dma_tx_state state;
794 spin_lock_irqsave(&p->port.lock, flags);
797 * If the tx status is not DMA_COMPLETE, then this is a delayed
798 * completion callback. A previous RX timeout flush would have
799 * already pushed the data, so exit.
801 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
803 spin_unlock_irqrestore(&p->port.lock, flags);
806 __dma_rx_do_complete(p);
809 spin_unlock_irqrestore(&p->port.lock, flags);
812 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
814 struct omap8250_priv *priv = p->port.private_data;
815 struct uart_8250_dma *dma = p->dma;
816 struct dma_tx_state state;
820 spin_lock_irqsave(&priv->rx_dma_lock, flags);
822 if (!dma->rx_running) {
823 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
827 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
828 if (ret == DMA_IN_PROGRESS) {
829 ret = dmaengine_pause(dma->rxchan);
830 if (WARN_ON_ONCE(ret))
831 priv->rx_dma_broken = true;
833 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
835 __dma_rx_do_complete(p);
836 dmaengine_terminate_all(dma->rxchan);
839 static int omap_8250_rx_dma(struct uart_8250_port *p)
841 struct omap8250_priv *priv = p->port.private_data;
842 struct uart_8250_dma *dma = p->dma;
844 struct dma_async_tx_descriptor *desc;
847 if (priv->rx_dma_broken)
850 spin_lock_irqsave(&priv->rx_dma_lock, flags);
855 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
856 dma->rx_size, DMA_DEV_TO_MEM,
857 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
864 desc->callback = __dma_rx_complete;
865 desc->callback_param = p;
867 dma->rx_cookie = dmaengine_submit(desc);
869 dma_async_issue_pending(dma->rxchan);
871 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
875 static int omap_8250_tx_dma(struct uart_8250_port *p);
877 static void omap_8250_dma_tx_complete(void *param)
879 struct uart_8250_port *p = param;
880 struct uart_8250_dma *dma = p->dma;
881 struct circ_buf *xmit = &p->port.state->xmit;
883 bool en_thri = false;
884 struct omap8250_priv *priv = p->port.private_data;
886 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
887 UART_XMIT_SIZE, DMA_TO_DEVICE);
889 spin_lock_irqsave(&p->port.lock, flags);
893 xmit->tail += dma->tx_size;
894 xmit->tail &= UART_XMIT_SIZE - 1;
895 p->port.icount.tx += dma->tx_size;
897 if (priv->delayed_restore) {
898 priv->delayed_restore = 0;
899 omap8250_restore_regs(p);
902 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
903 uart_write_wakeup(&p->port);
905 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
908 ret = omap_8250_tx_dma(p);
912 } else if (p->capabilities & UART_CAP_RPM) {
918 p->ier |= UART_IER_THRI;
919 serial_port_out(&p->port, UART_IER, p->ier);
922 spin_unlock_irqrestore(&p->port.lock, flags);
925 static int omap_8250_tx_dma(struct uart_8250_port *p)
927 struct uart_8250_dma *dma = p->dma;
928 struct omap8250_priv *priv = p->port.private_data;
929 struct circ_buf *xmit = &p->port.state->xmit;
930 struct dma_async_tx_descriptor *desc;
931 unsigned int skip_byte = 0;
936 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
939 * Even if no data, we need to return an error for the two cases
940 * below so serial8250_tx_chars() is invoked and properly clears
941 * THRI and/or runtime suspend.
943 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
947 if (p->ier & UART_IER_THRI) {
948 p->ier &= ~UART_IER_THRI;
949 serial_out(p, UART_IER, p->ier);
954 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
955 if (priv->habit & OMAP_DMA_TX_KICK) {
959 * We need to put the first byte into the FIFO in order to start
960 * the DMA transfer. For transfers smaller than four bytes we
961 * don't bother doing DMA at all. It seem not matter if there
962 * are still bytes in the FIFO from the last transfer (in case
963 * we got here directly from omap_8250_dma_tx_complete()). Bytes
964 * leaving the FIFO seem not to trigger the DMA transfer. It is
965 * really the byte that we put into the FIFO.
966 * If the FIFO is already full then we most likely got here from
967 * omap_8250_dma_tx_complete(). And this means the DMA engine
968 * just completed its work. We don't have to wait the complete
969 * 86us at 115200,8n1 but around 60us (not to mention lower
970 * baudrates). So in that case we take the interrupt and try
971 * again with an empty FIFO.
973 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
974 if (tx_lvl == p->tx_loadsz) {
978 if (dma->tx_size < 4) {
985 desc = dmaengine_prep_slave_single(dma->txchan,
986 dma->tx_addr + xmit->tail + skip_byte,
987 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
988 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
996 desc->callback = omap_8250_dma_tx_complete;
997 desc->callback_param = p;
999 dma->tx_cookie = dmaengine_submit(desc);
1001 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1002 UART_XMIT_SIZE, DMA_TO_DEVICE);
1004 dma_async_issue_pending(dma->txchan);
1008 if (p->ier & UART_IER_THRI) {
1009 p->ier &= ~UART_IER_THRI;
1010 serial_out(p, UART_IER, p->ier);
1013 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1020 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1022 switch (iir & 0x3f) {
1024 case UART_IIR_RX_TIMEOUT:
1026 omap_8250_rx_dma_flush(up);
1029 return omap_8250_rx_dma(up);
1033 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1034 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1035 * use the default routine in the non-DMA case and this one for with DMA.
1037 static int omap_8250_dma_handle_irq(struct uart_port *port)
1039 struct uart_8250_port *up = up_to_u8250p(port);
1040 unsigned char status;
1041 unsigned long flags;
1044 serial8250_rpm_get(up);
1046 iir = serial_port_in(port, UART_IIR);
1047 if (iir & UART_IIR_NO_INT) {
1048 serial8250_rpm_put(up);
1052 spin_lock_irqsave(&port->lock, flags);
1054 status = serial_port_in(port, UART_LSR);
1056 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1057 if (handle_rx_dma(up, iir)) {
1058 status = serial8250_rx_chars(up, status);
1059 omap_8250_rx_dma(up);
1062 serial8250_modem_status(up);
1063 if (status & UART_LSR_THRE && up->dma->tx_err) {
1064 if (uart_tx_stopped(&up->port) ||
1065 uart_circ_empty(&up->port.state->xmit)) {
1066 up->dma->tx_err = 0;
1067 serial8250_tx_chars(up);
1070 * try again due to an earlier failer which
1071 * might have been resolved by now.
1073 if (omap_8250_tx_dma(up))
1074 serial8250_tx_chars(up);
1078 spin_unlock_irqrestore(&port->lock, flags);
1079 serial8250_rpm_put(up);
1083 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1090 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1096 static int omap8250_no_handle_irq(struct uart_port *port)
1098 /* IRQ has not been requested but handling irq? */
1099 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1103 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1104 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1106 static const struct of_device_id omap8250_dt_ids[] = {
1107 { .compatible = "ti,omap2-uart" },
1108 { .compatible = "ti,omap3-uart" },
1109 { .compatible = "ti,omap4-uart" },
1110 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1111 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1112 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1115 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1117 static int omap8250_probe(struct platform_device *pdev)
1119 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1121 struct omap8250_priv *priv;
1122 struct uart_8250_port up;
1124 void __iomem *membase;
1126 if (!regs || !irq) {
1127 dev_err(&pdev->dev, "missing registers or irq\n");
1131 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1135 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1136 resource_size(regs));
1140 memset(&up, 0, sizeof(up));
1141 up.port.dev = &pdev->dev;
1142 up.port.mapbase = regs->start;
1143 up.port.membase = membase;
1144 up.port.irq = irq->start;
1146 * It claims to be 16C750 compatible however it is a little different.
1147 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1148 * have) is enabled via EFR instead of MCR. The type is set here 8250
1149 * just to get things going. UNKNOWN does not work for a few reasons and
1150 * we don't need our own type since we don't use 8250's set_termios()
1153 up.port.type = PORT_8250;
1154 up.port.iotype = UPIO_MEM;
1155 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1157 up.port.private_data = priv;
1159 up.port.regshift = 2;
1160 up.port.fifosize = 64;
1162 up.capabilities = UART_CAP_FIFO;
1165 * Runtime PM is mostly transparent. However to do it right we need to a
1166 * TX empty interrupt before we can put the device to auto idle. So if
1167 * PM is not enabled we don't add that flag and can spare that one extra
1168 * interrupt in the TX path.
1170 up.capabilities |= UART_CAP_RPM;
1172 up.port.set_termios = omap_8250_set_termios;
1173 up.port.set_mctrl = omap8250_set_mctrl;
1174 up.port.pm = omap_8250_pm;
1175 up.port.startup = omap_8250_startup;
1176 up.port.shutdown = omap_8250_shutdown;
1177 up.port.throttle = omap_8250_throttle;
1178 up.port.unthrottle = omap_8250_unthrottle;
1179 up.port.rs485_config = omap_8250_rs485_config;
1181 if (pdev->dev.of_node) {
1182 const struct of_device_id *id;
1184 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1186 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1188 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1190 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1192 priv->habit |= *(u8 *)id->data;
1197 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1202 if (!up.port.uartclk) {
1203 up.port.uartclk = DEFAULT_CLK_SPEED;
1204 dev_warn(&pdev->dev,
1205 "No clock speed specified: using default: %d\n",
1209 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1210 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1211 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1213 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1215 spin_lock_init(&priv->rx_dma_lock);
1217 device_init_wakeup(&pdev->dev, true);
1218 pm_runtime_use_autosuspend(&pdev->dev);
1219 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1221 pm_runtime_irq_safe(&pdev->dev);
1222 pm_runtime_enable(&pdev->dev);
1224 pm_runtime_get_sync(&pdev->dev);
1226 omap_serial_fill_features_erratas(&up, priv);
1227 up.port.handle_irq = omap8250_no_handle_irq;
1228 #ifdef CONFIG_SERIAL_8250_DMA
1229 if (pdev->dev.of_node) {
1231 * Oh DMA support. If there are no DMA properties in the DT then
1232 * we will fall back to a generic DMA channel which does not
1233 * really work here. To ensure that we do not get a generic DMA
1234 * channel assigned, we have the the_no_dma_filter_fn() here.
1235 * To avoid "failed to request DMA" messages we check for DMA
1238 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1240 up.dma = &priv->omap8250_dma;
1241 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1242 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1243 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1244 priv->omap8250_dma.rx_size = RX_TRIGGER;
1245 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1246 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1250 ret = serial8250_register_8250_port(&up);
1252 dev_err(&pdev->dev, "unable to register 8250 port\n");
1256 platform_set_drvdata(pdev, priv);
1257 pm_runtime_mark_last_busy(&pdev->dev);
1258 pm_runtime_put_autosuspend(&pdev->dev);
1261 pm_runtime_dont_use_autosuspend(&pdev->dev);
1262 pm_runtime_put_sync(&pdev->dev);
1263 pm_runtime_disable(&pdev->dev);
1267 static int omap8250_remove(struct platform_device *pdev)
1269 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1271 pm_runtime_dont_use_autosuspend(&pdev->dev);
1272 pm_runtime_put_sync(&pdev->dev);
1273 pm_runtime_disable(&pdev->dev);
1274 serial8250_unregister_port(priv->line);
1275 pm_qos_remove_request(&priv->pm_qos_request);
1276 device_init_wakeup(&pdev->dev, false);
1280 #ifdef CONFIG_PM_SLEEP
1281 static int omap8250_prepare(struct device *dev)
1283 struct omap8250_priv *priv = dev_get_drvdata(dev);
1287 priv->is_suspending = true;
1291 static void omap8250_complete(struct device *dev)
1293 struct omap8250_priv *priv = dev_get_drvdata(dev);
1297 priv->is_suspending = false;
1300 static int omap8250_suspend(struct device *dev)
1302 struct omap8250_priv *priv = dev_get_drvdata(dev);
1304 serial8250_suspend_port(priv->line);
1305 flush_work(&priv->qos_work);
1309 static int omap8250_resume(struct device *dev)
1311 struct omap8250_priv *priv = dev_get_drvdata(dev);
1313 serial8250_resume_port(priv->line);
1317 #define omap8250_prepare NULL
1318 #define omap8250_complete NULL
1322 static int omap8250_lost_context(struct uart_8250_port *up)
1326 val = serial_in(up, UART_OMAP_SCR);
1328 * If we lose context, then SCR is set to its reset value of zero.
1329 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1330 * among other bits, to never set the register back to zero again.
1337 /* TODO: in future, this should happen via API in drivers/reset/ */
1338 static int omap8250_soft_reset(struct device *dev)
1340 struct omap8250_priv *priv = dev_get_drvdata(dev);
1341 struct uart_8250_port *up = serial8250_get_port(priv->line);
1346 sysc = serial_in(up, UART_OMAP_SYSC);
1348 /* softreset the UART */
1349 sysc |= OMAP_UART_SYSC_SOFTRESET;
1350 serial_out(up, UART_OMAP_SYSC, sysc);
1352 /* By experiments, 1us enough for reset complete on AM335x */
1355 syss = serial_in(up, UART_OMAP_SYSS);
1356 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1359 dev_err(dev, "timed out waiting for reset done\n");
1366 static int omap8250_runtime_suspend(struct device *dev)
1368 struct omap8250_priv *priv = dev_get_drvdata(dev);
1369 struct uart_8250_port *up;
1371 /* In case runtime-pm tries this before we are setup */
1375 up = serial8250_get_port(priv->line);
1377 * When using 'no_console_suspend', the console UART must not be
1378 * suspended. Since driver suspend is managed by runtime suspend,
1379 * preventing runtime suspend (by returning error) will keep device
1380 * active during suspend.
1382 if (priv->is_suspending && !console_suspend_enabled) {
1383 if (uart_console(&up->port))
1387 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1390 ret = omap8250_soft_reset(dev);
1394 /* Restore to UART mode after reset (for wakeup) */
1395 omap8250_update_mdr1(up, priv);
1398 if (up->dma && up->dma->rxchan)
1399 omap_8250_rx_dma_flush(up);
1401 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1402 schedule_work(&priv->qos_work);
1407 static int omap8250_runtime_resume(struct device *dev)
1409 struct omap8250_priv *priv = dev_get_drvdata(dev);
1410 struct uart_8250_port *up;
1412 /* In case runtime-pm tries this before we are setup */
1416 up = serial8250_get_port(priv->line);
1418 if (omap8250_lost_context(up))
1419 omap8250_restore_regs(up);
1421 if (up->dma && up->dma->rxchan)
1422 omap_8250_rx_dma(up);
1424 priv->latency = priv->calc_latency;
1425 schedule_work(&priv->qos_work);
1430 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1431 static int __init omap8250_console_fixup(void)
1437 if (strstr(boot_command_line, "console=ttyS"))
1438 /* user set a ttyS based name for the console */
1441 omap_str = strstr(boot_command_line, "console=ttyO");
1443 /* user did not set ttyO based console, so we don't care */
1447 if ('0' <= *omap_str && *omap_str <= '9')
1448 idx = *omap_str - '0';
1453 if (omap_str[0] == ',') {
1460 add_preferred_console("ttyS", idx, options);
1461 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1463 pr_err("This ensures that you still see kernel messages. Please\n");
1464 pr_err("update your kernel commandline.\n");
1467 console_initcall(omap8250_console_fixup);
1470 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1471 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1472 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1473 omap8250_runtime_resume, NULL)
1474 .prepare = omap8250_prepare,
1475 .complete = omap8250_complete,
1478 static struct platform_driver omap8250_platform_driver = {
1481 .pm = &omap8250_dev_pm_ops,
1482 .of_match_table = omap8250_dt_ids,
1484 .probe = omap8250_probe,
1485 .remove = omap8250_remove,
1487 module_platform_driver(omap8250_platform_driver);
1489 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1490 MODULE_DESCRIPTION("OMAP 8250 Driver");
1491 MODULE_LICENSE("GPL v2");