2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_reg.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30 #include <linux/pm_runtime.h>
32 #include <asm/byteorder.h>
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
68 #define BYT_PRV_CLK 0x800
69 #define BYT_PRV_CLK_EN (1 << 0)
70 #define BYT_PRV_CLK_M_VAL_SHIFT 1
71 #define BYT_PRV_CLK_N_VAL_SHIFT 16
72 #define BYT_PRV_CLK_UPDATE (1 << 31)
74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
76 struct dw8250_data *d = p->private_data;
78 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
79 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
80 value |= UART_MSR_CTS;
81 value &= ~UART_MSR_DCTS;
87 static void dw8250_force_idle(struct uart_port *p)
89 struct uart_8250_port *up = up_to_u8250p(p);
91 serial8250_clear_and_reinit_fifos(up);
92 (void)p->serial_in(p, UART_RX);
95 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
97 struct dw8250_data *d = p->private_data;
99 if (offset == UART_MCR)
102 writeb(value, p->membase + (offset << p->regshift));
104 /* Make sure LCR write wasn't ignored */
105 if (offset == UART_LCR) {
108 unsigned int lcr = p->serial_in(p, UART_LCR);
109 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
111 dw8250_force_idle(p);
112 writeb(value, p->membase + (UART_LCR << p->regshift));
114 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
118 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
120 unsigned int value = readb(p->membase + (offset << p->regshift));
122 return dw8250_modify_msr(p, offset, value);
125 /* Read Back (rb) version to ensure register access ording. */
126 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
128 dw8250_serial_out(p, offset, value);
129 dw8250_serial_in(p, UART_LCR);
132 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
134 struct dw8250_data *d = p->private_data;
136 if (offset == UART_MCR)
139 writel(value, p->membase + (offset << p->regshift));
141 /* Make sure LCR write wasn't ignored */
142 if (offset == UART_LCR) {
145 unsigned int lcr = p->serial_in(p, UART_LCR);
146 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
148 dw8250_force_idle(p);
149 writel(value, p->membase + (UART_LCR << p->regshift));
151 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
155 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
157 unsigned int value = readl(p->membase + (offset << p->regshift));
159 return dw8250_modify_msr(p, offset, value);
162 static int dw8250_handle_irq(struct uart_port *p)
164 struct dw8250_data *d = p->private_data;
165 unsigned int iir = p->serial_in(p, UART_IIR);
167 if (serial8250_handle_irq(p, iir)) {
169 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
171 (void)p->serial_in(p, d->usr_reg);
180 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
183 pm_runtime_get_sync(port->dev);
185 serial8250_do_pm(port, state, old);
188 pm_runtime_put_sync_suspend(port->dev);
191 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
192 struct ktermios *old)
194 unsigned int baud = tty_termios_baud_rate(termios);
195 struct dw8250_data *d = p->private_data;
199 if (IS_ERR(d->clk) || !old)
202 /* Not requesting clock rates below 1.8432Mhz */
206 clk_disable_unprepare(d->clk);
207 rate = clk_round_rate(d->clk, baud * 16);
208 ret = clk_set_rate(d->clk, rate);
209 clk_prepare_enable(d->clk);
214 serial8250_do_set_termios(p, termios, old);
217 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
222 static void dw8250_setup_port(struct uart_8250_port *up)
224 struct uart_port *p = &up->port;
225 u32 reg = readl(p->membase + DW_UART_UCV);
228 * If the Component Version Register returns zero, we know that
229 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
234 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
235 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
237 reg = readl(p->membase + DW_UART_CPR);
241 /* Select the type based on fifo */
242 if (reg & DW_UART_CPR_FIFO_MODE) {
243 p->type = PORT_16550A;
244 p->flags |= UPF_FIXED_TYPE;
245 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
246 up->tx_loadsz = p->fifosize;
247 up->capabilities = UART_CAP_FIFO;
250 if (reg & DW_UART_CPR_AFCE_MODE)
251 up->capabilities |= UART_CAP_AFE;
254 static int dw8250_probe_of(struct uart_port *p,
255 struct dw8250_data *data)
257 struct device_node *np = p->dev->of_node;
258 struct uart_8250_port *up = up_to_u8250p(p);
262 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
265 * Low order bits of these 64-bit registers, when
266 * accessed as a byte, are 7 bytes further down in the
267 * address space in big endian mode.
271 p->serial_out = dw8250_serial_out_rb;
272 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
273 p->type = PORT_OCTEON;
274 data->usr_reg = 0x27;
276 } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
281 p->iotype = UPIO_MEM32;
282 p->serial_in = dw8250_serial_in32;
283 p->serial_out = dw8250_serial_out32;
286 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
291 dw8250_setup_port(up);
293 if (!of_property_read_u32(np, "reg-shift", &val))
296 /* clock got configured through clk api, all done */
300 /* try to find out clock frequency from DT as fallback */
301 if (of_property_read_u32(np, "clock-frequency", &val)) {
302 dev_err(p->dev, "clk or clock-frequency not defined\n");
310 static int dw8250_probe_acpi(struct uart_8250_port *up,
311 struct dw8250_data *data)
313 struct uart_port *p = &up->port;
315 dw8250_setup_port(up);
317 p->iotype = UPIO_MEM32;
318 p->serial_in = dw8250_serial_in32;
319 p->serial_out = dw8250_serial_out32;
322 up->dma = &data->dma;
324 up->dma->rxconf.src_maxburst = p->fifosize / 4;
325 up->dma->txconf.dst_maxburst = p->fifosize / 4;
327 up->port.set_termios = dw8250_set_termios;
332 static int dw8250_probe(struct platform_device *pdev)
334 struct uart_8250_port uart = {};
335 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
337 struct dw8250_data *data;
341 dev_err(&pdev->dev, "no registers/irq defined\n");
345 spin_lock_init(&uart.port.lock);
346 uart.port.mapbase = regs->start;
347 uart.port.irq = irq->start;
348 uart.port.handle_irq = dw8250_handle_irq;
349 uart.port.pm = dw8250_do_pm;
350 uart.port.type = PORT_8250;
351 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
352 uart.port.dev = &pdev->dev;
354 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
355 resource_size(regs));
356 if (!uart.port.membase)
359 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
363 data->usr_reg = DW_UART_USR;
364 data->clk = devm_clk_get(&pdev->dev, "baudclk");
365 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
366 data->clk = devm_clk_get(&pdev->dev, NULL);
367 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
368 return -EPROBE_DEFER;
369 if (!IS_ERR(data->clk)) {
370 err = clk_prepare_enable(data->clk);
372 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
375 uart.port.uartclk = clk_get_rate(data->clk);
378 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
379 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
383 if (!IS_ERR(data->pclk)) {
384 err = clk_prepare_enable(data->pclk);
386 dev_err(&pdev->dev, "could not enable apb_pclk\n");
391 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
392 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
396 if (!IS_ERR(data->rst))
397 reset_control_deassert(data->rst);
399 data->dma.rx_param = data;
400 data->dma.tx_param = data;
401 data->dma.fn = dw8250_dma_filter;
403 uart.port.iotype = UPIO_MEM;
404 uart.port.serial_in = dw8250_serial_in;
405 uart.port.serial_out = dw8250_serial_out;
406 uart.port.private_data = data;
408 if (pdev->dev.of_node) {
409 err = dw8250_probe_of(&uart.port, data);
412 } else if (ACPI_HANDLE(&pdev->dev)) {
413 err = dw8250_probe_acpi(&uart, data);
421 data->line = serial8250_register_8250_port(&uart);
422 if (data->line < 0) {
427 platform_set_drvdata(pdev, data);
429 pm_runtime_set_active(&pdev->dev);
430 pm_runtime_enable(&pdev->dev);
435 if (!IS_ERR(data->rst))
436 reset_control_assert(data->rst);
439 if (!IS_ERR(data->pclk))
440 clk_disable_unprepare(data->pclk);
443 if (!IS_ERR(data->clk))
444 clk_disable_unprepare(data->clk);
449 static int dw8250_remove(struct platform_device *pdev)
451 struct dw8250_data *data = platform_get_drvdata(pdev);
453 pm_runtime_get_sync(&pdev->dev);
455 serial8250_unregister_port(data->line);
457 if (!IS_ERR(data->rst))
458 reset_control_assert(data->rst);
460 if (!IS_ERR(data->pclk))
461 clk_disable_unprepare(data->pclk);
463 if (!IS_ERR(data->clk))
464 clk_disable_unprepare(data->clk);
466 pm_runtime_disable(&pdev->dev);
467 pm_runtime_put_noidle(&pdev->dev);
472 #ifdef CONFIG_PM_SLEEP
473 static int dw8250_suspend(struct device *dev)
475 struct dw8250_data *data = dev_get_drvdata(dev);
477 serial8250_suspend_port(data->line);
482 static int dw8250_resume(struct device *dev)
484 struct dw8250_data *data = dev_get_drvdata(dev);
486 serial8250_resume_port(data->line);
490 #endif /* CONFIG_PM_SLEEP */
492 #ifdef CONFIG_PM_RUNTIME
493 static int dw8250_runtime_suspend(struct device *dev)
495 struct dw8250_data *data = dev_get_drvdata(dev);
497 if (!IS_ERR(data->clk))
498 clk_disable_unprepare(data->clk);
500 if (!IS_ERR(data->pclk))
501 clk_disable_unprepare(data->pclk);
506 static int dw8250_runtime_resume(struct device *dev)
508 struct dw8250_data *data = dev_get_drvdata(dev);
510 if (!IS_ERR(data->pclk))
511 clk_prepare_enable(data->pclk);
513 if (!IS_ERR(data->clk))
514 clk_prepare_enable(data->clk);
520 static const struct dev_pm_ops dw8250_pm_ops = {
521 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
522 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
525 static const struct of_device_id dw8250_of_match[] = {
526 { .compatible = "snps,dw-apb-uart" },
527 { .compatible = "cavium,octeon-3860-uart" },
530 MODULE_DEVICE_TABLE(of, dw8250_of_match);
532 static const struct acpi_device_id dw8250_acpi_match[] = {
541 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
543 static struct platform_driver dw8250_platform_driver = {
545 .name = "dw-apb-uart",
546 .owner = THIS_MODULE,
547 .pm = &dw8250_pm_ops,
548 .of_match_table = dw8250_of_match,
549 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
551 .probe = dw8250_probe,
552 .remove = dw8250_remove,
555 module_platform_driver(dw8250_platform_driver);
557 MODULE_AUTHOR("Jamie Iles");
558 MODULE_LICENSE("GPL");
559 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");