2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_reg.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30 #include <linux/pm_runtime.h>
32 #include <asm/byteorder.h>
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
68 #define BYT_PRV_CLK 0x800
69 #define BYT_PRV_CLK_EN (1 << 0)
70 #define BYT_PRV_CLK_M_VAL_SHIFT 1
71 #define BYT_PRV_CLK_N_VAL_SHIFT 16
72 #define BYT_PRV_CLK_UPDATE (1 << 31)
74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
76 struct dw8250_data *d = p->private_data;
78 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
79 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
80 value |= UART_MSR_CTS;
81 value &= ~UART_MSR_DCTS;
87 static void dw8250_force_idle(struct uart_port *p)
89 struct uart_8250_port *up = up_to_u8250p(p);
91 serial8250_clear_and_reinit_fifos(up);
92 (void)p->serial_in(p, UART_RX);
95 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
97 struct dw8250_data *d = p->private_data;
99 if (offset == UART_MCR)
102 writeb(value, p->membase + (offset << p->regshift));
104 /* Make sure LCR write wasn't ignored */
105 if (offset == UART_LCR) {
108 unsigned int lcr = p->serial_in(p, UART_LCR);
109 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
111 dw8250_force_idle(p);
112 writeb(value, p->membase + (UART_LCR << p->regshift));
114 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
118 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
120 unsigned int value = readb(p->membase + (offset << p->regshift));
122 return dw8250_modify_msr(p, offset, value);
126 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
130 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
132 return dw8250_modify_msr(p, offset, value);
135 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
137 struct dw8250_data *d = p->private_data;
139 if (offset == UART_MCR)
143 __raw_writeq(value, p->membase + (offset << p->regshift));
144 /* Read back to ensure register write ordering. */
145 __raw_readq(p->membase + (UART_LCR << p->regshift));
147 /* Make sure LCR write wasn't ignored */
148 if (offset == UART_LCR) {
151 unsigned int lcr = p->serial_in(p, UART_LCR);
152 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
154 dw8250_force_idle(p);
155 __raw_writeq(value & 0xff,
156 p->membase + (UART_LCR << p->regshift));
158 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
161 #endif /* CONFIG_64BIT */
163 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
165 struct dw8250_data *d = p->private_data;
167 if (offset == UART_MCR)
170 writel(value, p->membase + (offset << p->regshift));
172 /* Make sure LCR write wasn't ignored */
173 if (offset == UART_LCR) {
176 unsigned int lcr = p->serial_in(p, UART_LCR);
177 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
179 dw8250_force_idle(p);
180 writel(value, p->membase + (UART_LCR << p->regshift));
182 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
186 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
188 unsigned int value = readl(p->membase + (offset << p->regshift));
190 return dw8250_modify_msr(p, offset, value);
193 static int dw8250_handle_irq(struct uart_port *p)
195 struct dw8250_data *d = p->private_data;
196 unsigned int iir = p->serial_in(p, UART_IIR);
198 if (serial8250_handle_irq(p, iir)) {
200 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
202 (void)p->serial_in(p, d->usr_reg);
211 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
214 pm_runtime_get_sync(port->dev);
216 serial8250_do_pm(port, state, old);
219 pm_runtime_put_sync_suspend(port->dev);
222 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
223 struct ktermios *old)
225 unsigned int baud = tty_termios_baud_rate(termios);
226 struct dw8250_data *d = p->private_data;
230 if (IS_ERR(d->clk) || !old)
233 /* Not requesting clock rates below 1.8432Mhz */
237 clk_disable_unprepare(d->clk);
238 rate = clk_round_rate(d->clk, baud * 16);
239 ret = clk_set_rate(d->clk, rate);
240 clk_prepare_enable(d->clk);
245 serial8250_do_set_termios(p, termios, old);
248 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
253 static void dw8250_setup_port(struct uart_8250_port *up)
255 struct uart_port *p = &up->port;
256 u32 reg = readl(p->membase + DW_UART_UCV);
259 * If the Component Version Register returns zero, we know that
260 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
265 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
266 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
268 reg = readl(p->membase + DW_UART_CPR);
272 /* Select the type based on fifo */
273 if (reg & DW_UART_CPR_FIFO_MODE) {
274 p->type = PORT_16550A;
275 p->flags |= UPF_FIXED_TYPE;
276 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
277 up->tx_loadsz = p->fifosize;
278 up->capabilities = UART_CAP_FIFO;
281 if (reg & DW_UART_CPR_AFCE_MODE)
282 up->capabilities |= UART_CAP_AFE;
285 static int dw8250_probe_of(struct uart_port *p,
286 struct dw8250_data *data)
288 struct device_node *np = p->dev->of_node;
289 struct uart_8250_port *up = up_to_u8250p(p);
295 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
296 p->serial_in = dw8250_serial_inq;
297 p->serial_out = dw8250_serial_outq;
298 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
299 p->type = PORT_OCTEON;
300 data->usr_reg = 0x27;
304 if (!of_property_read_u32(np, "reg-io-width", &val)) {
309 p->iotype = UPIO_MEM32;
310 p->serial_in = dw8250_serial_in32;
311 p->serial_out = dw8250_serial_out32;
314 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
319 dw8250_setup_port(up);
321 /* if we have a valid fifosize, try hooking up DMA here */
323 up->dma = &data->dma;
325 up->dma->rxconf.src_maxburst = p->fifosize / 4;
326 up->dma->txconf.dst_maxburst = p->fifosize / 4;
329 if (!of_property_read_u32(np, "reg-shift", &val))
332 /* get index of serial line, if found in DT aliases */
333 id = of_alias_get_id(np, "serial");
337 /* clock got configured through clk api, all done */
341 /* try to find out clock frequency from DT as fallback */
342 if (of_property_read_u32(np, "clock-frequency", &val)) {
343 dev_err(p->dev, "clk or clock-frequency not defined\n");
351 static int dw8250_probe_acpi(struct uart_8250_port *up,
352 struct dw8250_data *data)
354 struct uart_port *p = &up->port;
356 dw8250_setup_port(up);
358 p->iotype = UPIO_MEM32;
359 p->serial_in = dw8250_serial_in32;
360 p->serial_out = dw8250_serial_out32;
363 up->dma = &data->dma;
365 up->dma->rxconf.src_maxburst = p->fifosize / 4;
366 up->dma->txconf.dst_maxburst = p->fifosize / 4;
368 up->port.set_termios = dw8250_set_termios;
373 static int dw8250_probe(struct platform_device *pdev)
375 struct uart_8250_port uart = {};
376 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
378 struct dw8250_data *data;
382 dev_err(&pdev->dev, "no registers/irq defined\n");
386 spin_lock_init(&uart.port.lock);
387 uart.port.mapbase = regs->start;
388 uart.port.irq = irq->start;
389 uart.port.handle_irq = dw8250_handle_irq;
390 uart.port.pm = dw8250_do_pm;
391 uart.port.type = PORT_8250;
392 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
393 uart.port.dev = &pdev->dev;
395 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
396 resource_size(regs));
397 if (!uart.port.membase)
400 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
404 data->usr_reg = DW_UART_USR;
405 data->clk = devm_clk_get(&pdev->dev, "baudclk");
406 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
407 data->clk = devm_clk_get(&pdev->dev, NULL);
408 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
409 return -EPROBE_DEFER;
410 if (!IS_ERR(data->clk)) {
411 err = clk_prepare_enable(data->clk);
413 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
416 uart.port.uartclk = clk_get_rate(data->clk);
419 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
420 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
424 if (!IS_ERR(data->pclk)) {
425 err = clk_prepare_enable(data->pclk);
427 dev_err(&pdev->dev, "could not enable apb_pclk\n");
432 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
433 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
437 if (!IS_ERR(data->rst))
438 reset_control_deassert(data->rst);
440 data->dma.rx_param = data;
441 data->dma.tx_param = data;
442 data->dma.fn = dw8250_dma_filter;
444 uart.port.iotype = UPIO_MEM;
445 uart.port.serial_in = dw8250_serial_in;
446 uart.port.serial_out = dw8250_serial_out;
447 uart.port.private_data = data;
449 if (pdev->dev.of_node) {
450 err = dw8250_probe_of(&uart.port, data);
453 } else if (ACPI_HANDLE(&pdev->dev)) {
454 err = dw8250_probe_acpi(&uart, data);
462 data->line = serial8250_register_8250_port(&uart);
463 if (data->line < 0) {
468 platform_set_drvdata(pdev, data);
470 pm_runtime_set_active(&pdev->dev);
471 pm_runtime_enable(&pdev->dev);
476 if (!IS_ERR(data->rst))
477 reset_control_assert(data->rst);
480 if (!IS_ERR(data->pclk))
481 clk_disable_unprepare(data->pclk);
484 if (!IS_ERR(data->clk))
485 clk_disable_unprepare(data->clk);
490 static int dw8250_remove(struct platform_device *pdev)
492 struct dw8250_data *data = platform_get_drvdata(pdev);
494 pm_runtime_get_sync(&pdev->dev);
496 serial8250_unregister_port(data->line);
498 if (!IS_ERR(data->rst))
499 reset_control_assert(data->rst);
501 if (!IS_ERR(data->pclk))
502 clk_disable_unprepare(data->pclk);
504 if (!IS_ERR(data->clk))
505 clk_disable_unprepare(data->clk);
507 pm_runtime_disable(&pdev->dev);
508 pm_runtime_put_noidle(&pdev->dev);
513 #ifdef CONFIG_PM_SLEEP
514 static int dw8250_suspend(struct device *dev)
516 struct dw8250_data *data = dev_get_drvdata(dev);
518 serial8250_suspend_port(data->line);
523 static int dw8250_resume(struct device *dev)
525 struct dw8250_data *data = dev_get_drvdata(dev);
527 serial8250_resume_port(data->line);
531 #endif /* CONFIG_PM_SLEEP */
533 #ifdef CONFIG_PM_RUNTIME
534 static int dw8250_runtime_suspend(struct device *dev)
536 struct dw8250_data *data = dev_get_drvdata(dev);
538 if (!IS_ERR(data->clk))
539 clk_disable_unprepare(data->clk);
541 if (!IS_ERR(data->pclk))
542 clk_disable_unprepare(data->pclk);
547 static int dw8250_runtime_resume(struct device *dev)
549 struct dw8250_data *data = dev_get_drvdata(dev);
551 if (!IS_ERR(data->pclk))
552 clk_prepare_enable(data->pclk);
554 if (!IS_ERR(data->clk))
555 clk_prepare_enable(data->clk);
561 static const struct dev_pm_ops dw8250_pm_ops = {
562 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
563 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
566 static const struct of_device_id dw8250_of_match[] = {
567 { .compatible = "snps,dw-apb-uart" },
568 { .compatible = "cavium,octeon-3860-uart" },
571 MODULE_DEVICE_TABLE(of, dw8250_of_match);
573 static const struct acpi_device_id dw8250_acpi_match[] = {
582 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
584 static struct platform_driver dw8250_platform_driver = {
586 .name = "dw-apb-uart",
587 .pm = &dw8250_pm_ops,
588 .of_match_table = dw8250_of_match,
589 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
591 .probe = dw8250_probe,
592 .remove = dw8250_remove,
595 module_platform_driver(dw8250_platform_driver);
597 MODULE_AUTHOR("Jamie Iles");
598 MODULE_LICENSE("GPL");
599 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");