2 * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.daniel@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/cpu_cooling.h>
27 #include "exynos_thermal_common.h"
29 enum calibration_type {
30 TYPE_ONE_POINT_TRIMMING,
31 TYPE_ONE_POINT_TRIMMING_25,
32 TYPE_ONE_POINT_TRIMMING_85,
33 TYPE_TWO_POINT_TRIMMING,
38 SOC_ARCH_EXYNOS3250 = 1,
43 SOC_ARCH_EXYNOS5420_TRIMINFO,
48 * EXYNOS TMU supported features.
49 * TMU_SUPPORT_EMULATION - This features is used to set user defined
50 * temperature to the TMU controller.
51 * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
52 * has many instances of TMU.
53 * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
55 * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
56 * be registered for falling trips also.
57 * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
58 * state(active/idle) can be checked.
59 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
61 * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
62 * sensors shares some common registers.
63 * TMU_SUPPORT - macro to compare the above features with the supplied.
65 #define TMU_SUPPORT_EMULATION BIT(0)
66 #define TMU_SUPPORT_MULTI_INST BIT(1)
67 #define TMU_SUPPORT_TRIM_RELOAD BIT(2)
68 #define TMU_SUPPORT_FALLING_TRIP BIT(3)
69 #define TMU_SUPPORT_READY_STATUS BIT(4)
70 #define TMU_SUPPORT_EMUL_TIME BIT(5)
71 #define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
73 #define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
76 * struct exynos_tmu_register - register descriptors to access registers and
77 * bitfields. The register validity, offsets and bitfield values may vary
78 * slightly across different exynos SOC's.
79 * @triminfo_data: register containing 2 pont trimming data
80 * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
81 * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
82 * @triminfo_ctrl: trim info controller register.
83 * @tmu_ctrl: TMU main controller register.
84 * @test_mux_addr_shift: shift bits of test mux address.
85 * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
86 * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
87 * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
88 * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
89 * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
90 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
92 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
93 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
94 * @tmu_status: register drescribing the TMU status.
95 * @tmu_cur_temp: register containing the current temperature of the TMU.
96 * @threshold_temp: register containing the base threshold level.
97 * @threshold_th0: Register containing first set of rising levels.
98 * @threshold_th1: Register containing second set of rising levels.
99 * @threshold_th2: Register containing third set of rising levels.
100 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
101 * @tmu_inten: register containing the different threshold interrupt
103 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
104 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
105 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
106 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
107 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
108 * @tmu_intstat: Register containing the interrupt status values.
109 * @tmu_intclear: Register for clearing the raised interrupt status.
110 * @intclr_fall_shift: shift bits for interrupt clear fall 0
111 * @intclr_rise_shift: shift bits of all rising interrupt bits.
112 * @intclr_rise_mask: mask bits of all rising interrupt bits.
113 * @intclr_fall_mask: mask bits of all rising interrupt bits.
114 * @emul_con: TMU emulation controller register.
115 * @emul_temp_shift: shift bits of emulation temperature.
116 * @emul_time_shift: shift bits of emulation time.
117 * @tmu_irqstatus: register to find which TMU generated interrupts.
118 * @tmu_pmin: register to get/set the Pmin value.
120 struct exynos_tmu_registers {
122 u32 triminfo_25_shift;
123 u32 triminfo_85_shift;
129 u32 test_mux_addr_shift;
130 u32 buf_vref_sel_shift;
131 u32 buf_vref_sel_mask;
132 u32 therm_trip_mode_shift;
133 u32 therm_trip_mode_mask;
134 u32 therm_trip_en_shift;
135 u32 buf_slope_sel_shift;
136 u32 buf_slope_sel_mask;
148 u32 threshold_th3_l0_shift;
151 u32 inten_rise0_shift;
152 u32 inten_rise1_shift;
153 u32 inten_rise2_shift;
154 u32 inten_rise3_shift;
155 u32 inten_fall0_shift;
160 u32 intclr_fall_shift;
161 u32 intclr_rise_shift;
162 u32 intclr_fall_mask;
163 u32 intclr_rise_mask;
174 * struct exynos_tmu_platform_data
175 * @threshold: basic temperature for generating interrupt
176 * 25 <= threshold <= 125 [unit: degree Celsius]
177 * @threshold_falling: differntial value for setting threshold
178 * of temperature falling interrupt.
179 * @trigger_levels: array for each interrupt levels
180 * [unit: degree Celsius]
181 * 0: temperature for trigger_level0 interrupt
182 * condition for trigger_level0 interrupt:
183 * current temperature > threshold + trigger_levels[0]
184 * 1: temperature for trigger_level1 interrupt
185 * condition for trigger_level1 interrupt:
186 * current temperature > threshold + trigger_levels[1]
187 * 2: temperature for trigger_level2 interrupt
188 * condition for trigger_level2 interrupt:
189 * current temperature > threshold + trigger_levels[2]
190 * 3: temperature for trigger_level3 interrupt
191 * condition for trigger_level3 interrupt:
192 * current temperature > threshold + trigger_levels[3]
193 * @trigger_type: defines the type of trigger. Possible values are,
194 * THROTTLE_ACTIVE trigger type
195 * THROTTLE_PASSIVE trigger type
196 * SW_TRIP trigger type
198 * @trigger_enable[]: array to denote which trigger levels are enabled.
199 * 1 = enable trigger_level[] interrupt,
200 * 0 = disable trigger_level[] interrupt
201 * @max_trigger_level: max trigger level supported by the TMU
202 * @non_hw_trigger_levels: number of defined non-hardware trigger levels
203 * @gain: gain of amplifier in the positive-TC generator block
205 * @reference_voltage: reference voltage of amplifier
206 * in the positive-TC generator block
207 * 0 < reference_voltage <= 31
208 * @noise_cancel_mode: noise cancellation mode
209 * 000, 100, 101, 110 and 111 can be different modes
210 * @type: determines the type of SOC
211 * @efuse_value: platform defined fuse value
212 * @min_efuse_value: minimum valid trimming data
213 * @max_efuse_value: maximum valid trimming data
214 * @first_point_trim: temp value of the first point trimming
215 * @second_point_trim: temp value of the second point trimming
216 * @default_temp_offset: default temperature offset in case of no trimming
217 * @test_mux; information if SoC supports test MUX
218 * @cal_type: calibration type for temperature
219 * @freq_clip_table: Table representing frequency reduction percentage.
220 * @freq_tab_count: Count of the above table as frequency reduction may
221 * applicable to only some of the trigger levels.
222 * @registers: Pointer to structure containing all the TMU controller registers
223 * and bitfields shifts and masks.
224 * @features: a bitfield value indicating the features supported in SOC like
225 * emulation, multi instance etc
227 * This structure is required for configuration of exynos_tmu driver.
229 struct exynos_tmu_platform_data {
231 u8 threshold_falling;
232 u8 trigger_levels[MAX_TRIP_COUNT];
233 enum trigger_type trigger_type[MAX_TRIP_COUNT];
234 bool trigger_enable[MAX_TRIP_COUNT];
235 u8 max_trigger_level;
236 u8 non_hw_trigger_levels;
238 u8 reference_voltage;
239 u8 noise_cancel_mode;
245 u8 second_point_trim;
246 u8 default_temp_offset;
249 enum calibration_type cal_type;
251 struct freq_clip_table freq_tab[4];
252 unsigned int freq_tab_count;
253 const struct exynos_tmu_registers *registers;
254 unsigned int features;
258 * struct exynos_tmu_init_data
259 * @tmu_count: number of TMU instances.
260 * @tmu_data: platform data of all TMU instances.
261 * This structure is required to store data for multi-instance exynos tmu
264 struct exynos_tmu_init_data {
266 struct exynos_tmu_platform_data tmu_data[];
269 #endif /* _EXYNOS_TMU_H */