1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/errno.h>
4 #include <linux/string.h>
6 #include <linux/slab.h>
7 #include <linux/delay.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/pci.h>
12 #include <linux/vmalloc.h>
13 #include <linux/pagemap.h>
14 #include <linux/console.h>
18 #include <linux/platform_device.h>
19 #include <linux/screen_info.h>
20 #include <linux/sizes.h>
24 #include "sm750_accel.h"
26 void __iomem *mmio750;
28 int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
34 sm750_dev->vidreg_start = pci_resource_start(pdev, 1);
35 sm750_dev->vidreg_size = SZ_2M;
37 pr_info("mmio phyAddr = %lx\n", sm750_dev->vidreg_start);
40 * reserve the vidreg space of smi adaptor
41 * if you do this, you need to add release region code
42 * in lynxfb_remove, or memory will not be mapped again
45 ret = pci_request_region(pdev, 1, "sm750fb");
47 pr_err("Can not request PCI regions.\n");
51 /* now map mmio and vidmem */
52 sm750_dev->pvReg = ioremap_nocache(sm750_dev->vidreg_start,
53 sm750_dev->vidreg_size);
54 if (!sm750_dev->pvReg) {
55 pr_err("mmio failed\n");
59 pr_info("mmio virtual addr = %p\n", sm750_dev->pvReg);
62 sm750_dev->accel.dprBase = sm750_dev->pvReg + DE_BASE_ADDR_TYPE1;
63 sm750_dev->accel.dpPortBase = sm750_dev->pvReg + DE_PORT_ADDR_TYPE1;
65 mmio750 = sm750_dev->pvReg;
66 sm750_set_chip_type(sm750_dev->devid, sm750_dev->revid);
68 sm750_dev->vidmem_start = pci_resource_start(pdev, 0);
70 * don't use pdev_resource[x].end - resource[x].start to
71 * calculate the resource size, it's only the maximum available
72 * size but not the actual size, using
73 * @ddk750_get_vm_size function can be safe.
75 sm750_dev->vidmem_size = ddk750_get_vm_size();
76 pr_info("video memory phyAddr = %lx, size = %u bytes\n",
77 sm750_dev->vidmem_start, sm750_dev->vidmem_size);
79 /* reserve the vidmem space of smi adaptor */
80 sm750_dev->pvMem = ioremap_wc(sm750_dev->vidmem_start,
81 sm750_dev->vidmem_size);
82 if (!sm750_dev->pvMem) {
83 pr_err("Map video memory failed\n");
87 pr_info("video memory vaddr = %p\n", sm750_dev->pvMem);
93 int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
95 struct init_status *parm;
97 parm = &sm750_dev->initParm;
98 if (parm->chip_clk == 0)
99 parm->chip_clk = (sm750_get_chip_type() == SM750LE) ?
100 DEFAULT_SM750LE_CHIP_CLOCK :
101 DEFAULT_SM750_CHIP_CLOCK;
103 if (parm->mem_clk == 0)
104 parm->mem_clk = parm->chip_clk;
105 if (parm->master_clk == 0)
106 parm->master_clk = parm->chip_clk / 3;
108 ddk750_init_hw((struct initchip_param *)&sm750_dev->initParm);
109 /* for sm718, open pci burst */
110 if (sm750_dev->devid == 0x718) {
112 peek32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST);
115 if (sm750_get_chip_type() != SM750LE) {
117 /* does user need CRT? */
118 if (sm750_dev->nocrt) {
120 peek32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF);
122 val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
123 val |= SYSTEM_CTRL_DPMS_VPHN;
124 poke32(SYSTEM_CTRL, val);
127 peek32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF);
129 val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
130 val |= SYSTEM_CTRL_DPMS_VPHP;
131 poke32(SYSTEM_CTRL, val);
134 val = peek32(PANEL_DISPLAY_CTRL) &
135 ~(PANEL_DISPLAY_CTRL_DUAL_DISPLAY |
136 PANEL_DISPLAY_CTRL_DOUBLE_PIXEL);
137 switch (sm750_dev->pnltype) {
140 case sm750_doubleTFT:
141 val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL;
144 val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY;
147 poke32(PANEL_DISPLAY_CTRL, val);
150 * for 750LE, no DVI chip initialization
151 * makes Monitor no signal
153 * Set up GPIO for software I2C to program DVI chip in the
154 * Xilinx SP605 board, in order to have video signal.
156 sm750_sw_i2c_init(0, 1);
159 * Customer may NOT use CH7301 DVI chip, which has to be
160 * initialized differently.
162 if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) {
164 * The following register values for CH7301 are from
165 * Chrontel app note and our experiment.
167 pr_info("yes,CH7301 DVI chip found\n");
168 sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16);
169 sm750_sw_i2c_write_reg(0xec, 0x21, 0x9);
170 sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0);
171 pr_info("okay,CH7301 DVI chip setup done\n");
176 if (!sm750_dev->accel_off)
177 hw_sm750_initAccel(sm750_dev);
182 int hw_sm750_output_setMode(struct lynxfb_output *output,
183 struct fb_var_screeninfo *var,
184 struct fb_fix_screeninfo *fix)
187 disp_output_t dispSet;
192 channel = *output->channel;
194 if (sm750_get_chip_type() != SM750LE) {
195 if (channel == sm750_primary) {
196 pr_info("primary channel\n");
197 if (output->paths & sm750_panel)
198 dispSet |= do_LCD1_PRI;
199 if (output->paths & sm750_crt)
200 dispSet |= do_CRT_PRI;
203 pr_info("secondary channel\n");
204 if (output->paths & sm750_panel)
205 dispSet |= do_LCD1_SEC;
206 if (output->paths & sm750_crt)
207 dispSet |= do_CRT_SEC;
209 ddk750_setLogicalDispOut(dispSet);
211 /* just open DISPLAY_CONTROL_750LE register bit 3:0 */
214 reg = peek32(DISPLAY_CONTROL_750LE);
216 poke32(DISPLAY_CONTROL_750LE, reg);
219 pr_info("ddk setlogicdispout done\n");
223 int hw_sm750_crtc_checkMode(struct lynxfb_crtc *crtc,
224 struct fb_var_screeninfo *var)
226 struct sm750_dev *sm750_dev;
227 struct lynxfb_par *par = container_of(crtc, struct lynxfb_par, crtc);
229 sm750_dev = par->dev;
231 switch (var->bits_per_pixel) {
236 if (sm750_dev->revid == SM750LE_REVISION_ID) {
237 pr_debug("750le do not support 32bpp\n");
248 /* set the controller's mode for @crtc charged with @var and @fix parameters */
249 int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
250 struct fb_var_screeninfo *var,
251 struct fb_fix_screeninfo *fix)
255 struct mode_parameter modparm;
257 struct sm750_dev *sm750_dev;
258 struct lynxfb_par *par;
261 par = container_of(crtc, struct lynxfb_par, crtc);
262 sm750_dev = par->dev;
264 if (!sm750_dev->accel_off) {
265 /* set 2d engine pixel format according to mode bpp */
266 switch (var->bits_per_pixel) {
278 sm750_hw_set2dformat(&sm750_dev->accel, fmt);
282 modparm.pixel_clock = ps_to_hz(var->pixclock);
283 modparm.vertical_sync_polarity = (var->sync & FB_SYNC_HOR_HIGH_ACT)
285 modparm.horizontal_sync_polarity = (var->sync & FB_SYNC_VERT_HIGH_ACT)
287 modparm.clock_phase_polarity = (var->sync & FB_SYNC_COMP_HIGH_ACT)
289 modparm.horizontal_display_end = var->xres;
290 modparm.horizontal_sync_width = var->hsync_len;
291 modparm.horizontal_sync_start = var->xres + var->right_margin;
292 modparm.horizontal_total = var->xres + var->left_margin +
293 var->right_margin + var->hsync_len;
294 modparm.vertical_display_end = var->yres;
295 modparm.vertical_sync_height = var->vsync_len;
296 modparm.vertical_sync_start = var->yres + var->lower_margin;
297 modparm.vertical_total = var->yres + var->upper_margin +
298 var->lower_margin + var->vsync_len;
301 if (crtc->channel != sm750_secondary)
304 clock = SECONDARY_PLL;
306 pr_debug("Request pixel clock = %lu\n", modparm.pixel_clock);
307 ret = ddk750_setModeTiming(&modparm, clock);
309 pr_err("Set mode timing failed\n");
313 if (crtc->channel != sm750_secondary) {
314 /* set pitch, offset, width, start address, etc... */
315 poke32(PANEL_FB_ADDRESS,
316 crtc->oScreen & PANEL_FB_ADDRESS_ADDRESS_MASK);
318 reg = var->xres * (var->bits_per_pixel >> 3);
320 * crtc->channel is not equal to par->index on numeric,
323 reg = ALIGN(reg, crtc->line_pad);
324 reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) &
325 PANEL_FB_WIDTH_WIDTH_MASK;
326 reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK);
327 poke32(PANEL_FB_WIDTH, reg);
329 reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) &
330 PANEL_WINDOW_WIDTH_WIDTH_MASK;
331 reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK);
332 poke32(PANEL_WINDOW_WIDTH, reg);
334 reg = (var->yres_virtual - 1) <<
335 PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT;
336 reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK;
337 reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK);
338 poke32(PANEL_WINDOW_HEIGHT, reg);
340 poke32(PANEL_PLANE_TL, 0);
342 reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) &
343 PANEL_PLANE_BR_BOTTOM_MASK;
344 reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK);
345 poke32(PANEL_PLANE_BR, reg);
347 /* set pixel format */
348 reg = peek32(PANEL_DISPLAY_CTRL);
349 poke32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4));
351 /* not implemented now */
352 poke32(CRT_FB_ADDRESS, crtc->oScreen);
353 reg = var->xres * (var->bits_per_pixel >> 3);
355 * crtc->channel is not equal to par->index on numeric,
358 reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT;
359 reg &= CRT_FB_WIDTH_WIDTH_MASK;
360 reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK);
361 poke32(CRT_FB_WIDTH, reg);
363 /* SET PIXEL FORMAT */
364 reg = peek32(CRT_DISPLAY_CTRL);
365 reg |= ((var->bits_per_pixel >> 4) &
366 CRT_DISPLAY_CTRL_FORMAT_MASK);
367 poke32(CRT_DISPLAY_CTRL, reg);
374 int hw_sm750_setColReg(struct lynxfb_crtc *crtc, ushort index,
375 ushort red, ushort green, ushort blue)
377 static unsigned int add[] = {PANEL_PALETTE_RAM, CRT_PALETTE_RAM};
379 poke32(add[crtc->channel] + index * 4,
380 (red << 16) | (green << 8) | blue);
384 int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank)
389 case FB_BLANK_UNBLANK:
390 dpms = CRT_DISPLAY_CTRL_DPMS_0;
393 case FB_BLANK_NORMAL:
394 dpms = CRT_DISPLAY_CTRL_DPMS_0;
395 crtdb = CRT_DISPLAY_CTRL_BLANK;
397 case FB_BLANK_VSYNC_SUSPEND:
398 dpms = CRT_DISPLAY_CTRL_DPMS_2;
399 crtdb = CRT_DISPLAY_CTRL_BLANK;
401 case FB_BLANK_HSYNC_SUSPEND:
402 dpms = CRT_DISPLAY_CTRL_DPMS_1;
403 crtdb = CRT_DISPLAY_CTRL_BLANK;
405 case FB_BLANK_POWERDOWN:
406 dpms = CRT_DISPLAY_CTRL_DPMS_3;
407 crtdb = CRT_DISPLAY_CTRL_BLANK;
413 if (output->paths & sm750_crt) {
416 val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
417 poke32(CRT_DISPLAY_CTRL, val | dpms);
419 val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
420 poke32(CRT_DISPLAY_CTRL, val | crtdb);
425 int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
427 unsigned int dpms, pps, crtdb;
434 case FB_BLANK_UNBLANK:
435 pr_debug("flag = FB_BLANK_UNBLANK\n");
436 dpms = SYSTEM_CTRL_DPMS_VPHP;
437 pps = PANEL_DISPLAY_CTRL_DATA;
439 case FB_BLANK_NORMAL:
440 pr_debug("flag = FB_BLANK_NORMAL\n");
441 dpms = SYSTEM_CTRL_DPMS_VPHP;
442 crtdb = CRT_DISPLAY_CTRL_BLANK;
444 case FB_BLANK_VSYNC_SUSPEND:
445 dpms = SYSTEM_CTRL_DPMS_VNHP;
446 crtdb = CRT_DISPLAY_CTRL_BLANK;
448 case FB_BLANK_HSYNC_SUSPEND:
449 dpms = SYSTEM_CTRL_DPMS_VPHN;
450 crtdb = CRT_DISPLAY_CTRL_BLANK;
452 case FB_BLANK_POWERDOWN:
453 dpms = SYSTEM_CTRL_DPMS_VNHN;
454 crtdb = CRT_DISPLAY_CTRL_BLANK;
458 if (output->paths & sm750_crt) {
459 unsigned int val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
461 poke32(SYSTEM_CTRL, val | dpms);
463 val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
464 poke32(CRT_DISPLAY_CTRL, val | crtdb);
467 if (output->paths & sm750_panel) {
468 unsigned int val = peek32(PANEL_DISPLAY_CTRL);
470 val &= ~PANEL_DISPLAY_CTRL_DATA;
472 poke32(PANEL_DISPLAY_CTRL, val);
478 void hw_sm750_initAccel(struct sm750_dev *sm750_dev)
482 sm750_enable_2d_engine(1);
484 if (sm750_get_chip_type() == SM750LE) {
485 reg = peek32(DE_STATE1);
486 reg |= DE_STATE1_DE_ABORT;
487 poke32(DE_STATE1, reg);
489 reg = peek32(DE_STATE1);
490 reg &= ~DE_STATE1_DE_ABORT;
491 poke32(DE_STATE1, reg);
495 reg = peek32(SYSTEM_CTRL);
496 reg |= SYSTEM_CTRL_DE_ABORT;
497 poke32(SYSTEM_CTRL, reg);
499 reg = peek32(SYSTEM_CTRL);
500 reg &= ~SYSTEM_CTRL_DE_ABORT;
501 poke32(SYSTEM_CTRL, reg);
505 sm750_dev->accel.de_init(&sm750_dev->accel);
508 int hw_sm750le_deWait(void)
511 unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY |
512 DE_STATE2_DE_MEM_FIFO_EMPTY;
515 unsigned int val = peek32(DE_STATE2);
518 (DE_STATE2_DE_FIFO_EMPTY | DE_STATE2_DE_MEM_FIFO_EMPTY))
525 int hw_sm750_deWait(void)
528 unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY |
529 SYSTEM_CTRL_DE_FIFO_EMPTY |
530 SYSTEM_CTRL_DE_MEM_FIFO_EMPTY;
533 unsigned int val = peek32(SYSTEM_CTRL);
536 (SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY))
543 int hw_sm750_pan_display(struct lynxfb_crtc *crtc,
544 const struct fb_var_screeninfo *var,
545 const struct fb_info *info)
549 if ((var->xoffset + var->xres > var->xres_virtual) ||
550 (var->yoffset + var->yres > var->yres_virtual)) {
554 total = var->yoffset * info->fix.line_length +
555 ((var->xoffset * var->bits_per_pixel) >> 3);
556 total += crtc->oScreen;
557 if (crtc->channel == sm750_primary) {
558 poke32(PANEL_FB_ADDRESS,
559 peek32(PANEL_FB_ADDRESS) |
560 (total & PANEL_FB_ADDRESS_ADDRESS_MASK));
562 poke32(CRT_FB_ADDRESS,
563 peek32(CRT_FB_ADDRESS) |
564 (total & CRT_FB_ADDRESS_ADDRESS_MASK));