1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
8 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
14 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
18 ---------- --------------- -------------------------------
19 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
20 2011-07-07 Roger Create.
23 #include <drv_types.h>
24 #include <rtw_debug.h>
25 #include <HalPwrSeqCmd.h>
30 /* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
33 /* We should follow specific format which was released from HW SD. */
35 /* 2011.07.07, added by Roger. */
37 u8 HalPwrSeqCmdParsing(
38 struct adapter *padapter,
42 WLAN_PWR_CFG PwrSeqCmd[]
45 WLAN_PWR_CFG PwrCfgCmd;
46 u8 bPollingBit = false;
50 u32 pollingCount = 0; /* polling autoload done. */
51 u32 maxPollingCnt = 5000;
54 PwrCfgCmd = PwrSeqCmd[AryIdx];
60 "HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
61 GET_PWR_CFG_OFFSET(PwrCfgCmd),
62 GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
63 GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
64 GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
65 GET_PWR_CFG_BASE(PwrCfgCmd),
66 GET_PWR_CFG_CMD(PwrCfgCmd),
67 GET_PWR_CFG_MASK(PwrCfgCmd),
68 GET_PWR_CFG_VALUE(PwrCfgCmd)
72 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
74 (GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
75 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
76 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
78 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
83 ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")
91 ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")
93 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
96 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
99 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
100 /* Read Back SDIO Local value */
101 value = SdioLocalCmd52Read1Byte(padapter, offset);
103 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
105 GET_PWR_CFG_VALUE(PwrCfgCmd) &
106 GET_PWR_CFG_MASK(PwrCfgCmd)
109 /* Write Back SDIO Local value */
110 SdioLocalCmd52Write1Byte(padapter, offset, value);
112 /* Read the value from system register */
113 value = rtw_read8(padapter, offset);
115 value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
117 GET_PWR_CFG_VALUE(PwrCfgCmd)
118 &GET_PWR_CFG_MASK(PwrCfgCmd)
121 /* Write the value back to sytem register */
122 rtw_write8(padapter, offset, value);
126 case PWR_CMD_POLLING:
130 ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")
134 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
136 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
137 value = SdioLocalCmd52Read1Byte(padapter, offset);
139 value = rtw_read8(padapter, offset);
141 value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
143 value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
144 GET_PWR_CFG_MASK(PwrCfgCmd))
150 if (pollingCount++ > maxPollingCnt) {
152 "Fail to polling Offset[%#x]=%02x\n",
158 } while (!bPollingBit);
166 ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")
168 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
169 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
171 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
175 /* When this command is parsed, end the process */
179 ("HalPwrSeqCmdParsing: PWR_CMD_END\n")
187 ("HalPwrSeqCmdParsing: Unknown CMD!!\n")
193 AryIdx++;/* Add Array Index */