1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
5 * Contact Information: wlanfae <wlanfae@realtek.com>
7 #include <linux/bitops.h>
10 #include "r8192E_phyreg.h"
11 #include "r8190P_rtl8256.h"
12 #include "r8192E_phy.h"
15 #include "r8192E_hwimg.h"
17 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
35 /*************************Define local function prototype**********************/
37 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
38 enum rf90_radio_path eRFPath, u32 Offset);
39 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
40 enum rf90_radio_path eRFPath, u32 Offset,
43 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask)
47 return ffs(dwBitMask) - 1;
50 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
53 struct r8192_priv *priv = rtllib_priv(dev);
55 if (priv->rf_type == RF_2T4R)
57 else if (priv->rf_type == RF_1T2R) {
58 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
60 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
66 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
70 u32 OriginalValue, BitShift, NewValue;
72 if (dwBitMask != bMaskDWord) {
73 OriginalValue = rtl92e_readl(dev, dwRegAddr);
74 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
75 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift);
76 rtl92e_writel(dev, dwRegAddr, NewValue);
78 rtl92e_writel(dev, dwRegAddr, dwData);
81 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
83 u32 OriginalValue, BitShift;
85 OriginalValue = rtl92e_readl(dev, dwRegAddr);
86 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
88 return (OriginalValue & dwBitMask) >> BitShift;
91 static u32 _rtl92e_phy_rf_read(struct net_device *dev,
92 enum rf90_radio_path eRFPath, u32 Offset)
94 struct r8192_priv *priv = rtllib_priv(dev);
97 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
101 if (priv->rf_chip == RF_8256) {
102 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
104 priv->RfReg0Value[eRFPath] |= 0x140;
105 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
107 (priv->RfReg0Value[eRFPath]<<16));
108 NewOffset = Offset - 30;
109 } else if (Offset >= 16) {
110 priv->RfReg0Value[eRFPath] |= 0x100;
111 priv->RfReg0Value[eRFPath] &= (~0x40);
112 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
114 (priv->RfReg0Value[eRFPath]<<16));
116 NewOffset = Offset - 15;
120 RT_TRACE((COMP_PHY|COMP_ERR),
121 "check RF type here, need to be 8256\n");
124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
126 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
127 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
131 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
134 if (priv->rf_chip == RF_8256) {
135 priv->RfReg0Value[eRFPath] &= 0xebf;
137 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
138 (priv->RfReg0Value[eRFPath] << 16));
140 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
148 static void _rtl92e_phy_rf_write(struct net_device *dev,
149 enum rf90_radio_path eRFPath, u32 Offset,
152 struct r8192_priv *priv = rtllib_priv(dev);
153 u32 DataAndAddr = 0, NewOffset = 0;
154 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
157 if (priv->rf_chip == RF_8256) {
158 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
161 priv->RfReg0Value[eRFPath] |= 0x140;
162 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
164 (priv->RfReg0Value[eRFPath] << 16));
165 NewOffset = Offset - 30;
166 } else if (Offset >= 16) {
167 priv->RfReg0Value[eRFPath] |= 0x100;
168 priv->RfReg0Value[eRFPath] &= (~0x40);
169 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
171 (priv->RfReg0Value[eRFPath] << 16));
172 NewOffset = Offset - 15;
176 RT_TRACE((COMP_PHY|COMP_ERR),
177 "check RF type here, need to be 8256\n");
181 DataAndAddr = (NewOffset & 0x3f) | (Data << 16);
183 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
186 priv->RfReg0Value[eRFPath] = Data;
188 if (priv->rf_chip == RF_8256) {
190 priv->RfReg0Value[eRFPath] &= 0xebf;
191 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
193 (priv->RfReg0Value[eRFPath] << 16));
195 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
199 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
200 u32 RegAddr, u32 BitMask, u32 Data)
202 struct r8192_priv *priv = rtllib_priv(dev);
203 u32 Original_Value, BitShift, New_Value;
205 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
207 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
210 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
211 if (priv->Rf_Mode == RF_OP_By_FW) {
212 if (BitMask != bMask12Bits) {
213 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath,
215 BitShift = _rtl92e_calculate_bit_shift(BitMask);
216 New_Value = (Original_Value & ~BitMask) | (Data << BitShift);
218 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr,
221 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data);
225 if (BitMask != bMask12Bits) {
226 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath,
228 BitShift = _rtl92e_calculate_bit_shift(BitMask);
229 New_Value = (Original_Value & ~BitMask) | (Data << BitShift);
231 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value);
233 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data);
237 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
238 u32 RegAddr, u32 BitMask)
240 u32 Original_Value, Readback_Value, BitShift;
241 struct r8192_priv *priv = rtllib_priv(dev);
243 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
245 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
247 mutex_lock(&priv->rf_mutex);
248 if (priv->Rf_Mode == RF_OP_By_FW) {
249 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr);
252 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr);
254 BitShift = _rtl92e_calculate_bit_shift(BitMask);
255 Readback_Value = (Original_Value & BitMask) >> BitShift;
256 mutex_unlock(&priv->rf_mutex);
257 return Readback_Value;
260 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
261 enum rf90_radio_path eRFPath, u32 Offset)
266 Data |= ((Offset & 0xFF) << 12);
267 Data |= ((eRFPath & 0x3) << 20);
269 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
275 rtl92e_writel(dev, QPNR, Data);
276 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
282 return rtl92e_readl(dev, RF_DATA);
286 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
287 enum rf90_radio_path eRFPath, u32 Offset,
292 Data |= ((Offset & 0xFF) << 12);
293 Data |= ((eRFPath & 0x3) << 20);
297 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
303 rtl92e_writel(dev, QPNR, Data);
308 void rtl92e_config_mac(struct net_device *dev)
310 u32 dwArrayLen = 0, i = 0;
311 u32 *pdwArray = NULL;
312 struct r8192_priv *priv = rtllib_priv(dev);
314 if (priv->bTXPowerDataReadFromEEPORM) {
315 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
316 dwArrayLen = MACPHY_Array_PGLength;
317 pdwArray = Rtl819XMACPHY_Array_PG;
320 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
321 dwArrayLen = MACPHY_ArrayLength;
322 pdwArray = Rtl819XMACPHY_Array;
324 for (i = 0; i < dwArrayLen; i += 3) {
326 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
327 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
328 if (pdwArray[i] == 0x318)
329 pdwArray[i+2] = 0x00000800;
330 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1],
337 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
340 u32 *Rtl819XPHY_REGArray_Table = NULL;
341 u32 *Rtl819XAGCTAB_Array_Table = NULL;
342 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
343 struct r8192_priv *priv = rtllib_priv(dev);
345 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
346 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
347 if (priv->rf_type == RF_2T4R) {
348 PHY_REGArrayLen = PHY_REGArrayLength;
349 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
350 } else if (priv->rf_type == RF_1T2R) {
351 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
352 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
355 if (ConfigType == BaseBand_Config_PHY_REG) {
356 for (i = 0; i < PHY_REGArrayLen; i += 2) {
357 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
359 Rtl819XPHY_REGArray_Table[i+1]);
361 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
362 i, Rtl819XPHY_REGArray_Table[i],
363 Rtl819XPHY_REGArray_Table[i+1]);
365 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
366 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
367 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
369 Rtl819XAGCTAB_Array_Table[i+1]);
371 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
372 i, Rtl819XAGCTAB_Array_Table[i],
373 Rtl819XAGCTAB_Array_Table[i+1]);
378 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
380 struct r8192_priv *priv = rtllib_priv(dev);
382 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
383 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
384 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
385 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
387 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
388 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
389 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
390 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
392 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
393 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
394 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
395 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
397 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
398 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
399 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
400 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
402 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
403 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
404 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
405 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
407 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
408 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
409 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
410 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
412 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
413 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
414 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
415 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
417 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
418 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
419 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
420 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
422 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
423 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
424 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
425 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
427 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
428 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
429 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
430 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
432 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
433 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
434 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
435 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
437 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
438 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
439 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
440 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
442 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
443 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
444 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
445 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
447 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
448 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
449 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
450 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
452 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
453 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
454 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
455 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
457 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
458 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
459 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
460 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
462 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
463 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
464 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
465 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
469 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
470 enum rf90_radio_path eRFPath)
473 u32 i, CheckTimes = 4, dwRegRead = 0;
475 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
477 WriteAddr[HW90_BLOCK_MAC] = 0x100;
478 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
479 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
480 WriteAddr[HW90_BLOCK_RF] = 0x3;
481 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
484 if (CheckBlock == HW90_BLOCK_MAC) {
485 netdev_warn(dev, "%s(): No checks available for MAC block.\n",
490 for (i = 0; i < CheckTimes; i++) {
491 switch (CheckBlock) {
492 case HW90_BLOCK_PHY0:
493 case HW90_BLOCK_PHY1:
494 rtl92e_writel(dev, WriteAddr[CheckBlock],
496 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
500 WriteData[i] &= 0xfff;
501 rtl92e_set_rf_reg(dev, eRFPath,
502 WriteAddr[HW90_BLOCK_RF],
503 bMask12Bits, WriteData[i]);
505 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
506 WriteAddr[HW90_BLOCK_RF],
517 if (dwRegRead != WriteData[i]) {
518 netdev_warn(dev, "%s(): Check failed.\n", __func__);
527 static bool _rtl92e_bb_config_para_file(struct net_device *dev)
529 struct r8192_priv *priv = rtllib_priv(dev);
530 bool rtStatus = true;
531 u8 bRegValue = 0, eCheckItem = 0;
534 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
535 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
537 dwRegValue = rtl92e_readl(dev, CPU_GEN);
538 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
540 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
541 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
542 rtStatus = rtl92e_check_bb_and_rf(dev,
543 (enum hw90_block)eCheckItem,
544 (enum rf90_radio_path)0);
546 RT_TRACE((COMP_ERR | COMP_PHY),
547 "rtl92e_config_rf():Check PHY%d Fail!!\n",
552 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
553 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG);
555 dwRegValue = rtl92e_readl(dev, CPU_GEN);
556 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
558 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB);
560 if (priv->IC_Cut > VERSION_8190_BD) {
561 if (priv->rf_type == RF_2T4R)
562 dwRegValue = priv->AntennaTxPwDiff[2]<<8 |
563 priv->AntennaTxPwDiff[1]<<4 |
564 priv->AntennaTxPwDiff[0];
567 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
568 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
571 dwRegValue = priv->CrystalCap;
572 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
578 bool rtl92e_config_bb(struct net_device *dev)
580 _rtl92e_init_bb_rf_reg_def(dev);
581 return _rtl92e_bb_config_para_file(dev);
584 void rtl92e_get_tx_power(struct net_device *dev)
586 struct r8192_priv *priv = rtllib_priv(dev);
588 priv->MCSTxPowerLevelOriginalOffset[0] =
589 rtl92e_readl(dev, rTxAGC_Rate18_06);
590 priv->MCSTxPowerLevelOriginalOffset[1] =
591 rtl92e_readl(dev, rTxAGC_Rate54_24);
592 priv->MCSTxPowerLevelOriginalOffset[2] =
593 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
594 priv->MCSTxPowerLevelOriginalOffset[3] =
595 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
596 priv->MCSTxPowerLevelOriginalOffset[4] =
597 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
598 priv->MCSTxPowerLevelOriginalOffset[5] =
599 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
601 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
602 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
603 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
604 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
606 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
607 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
608 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
610 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
611 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2);
612 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
613 rOFDM0_RxDetector3, priv->framesync);
614 priv->SifsTime = rtl92e_readw(dev, SIFS);
617 void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
619 struct r8192_priv *priv = rtllib_priv(dev);
620 u8 powerlevel = 0, powerlevelOFDM24G = 0;
624 if (priv->epromtype == EEPROM_93C46) {
625 powerlevel = priv->TxPowerLevelCCK[channel-1];
626 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
627 } else if (priv->epromtype == EEPROM_93C56) {
628 if (priv->rf_type == RF_1T2R) {
629 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
630 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
631 } else if (priv->rf_type == RF_2T4R) {
632 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
633 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
635 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
636 - priv->TxPowerLevelOFDM24G_A[channel-1];
638 priv->RF_C_TxPwDiff = ant_pwr_diff;
642 priv->AntennaTxPwDiff[2] = 0;
643 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
644 priv->AntennaTxPwDiff[0] = 0;
646 u4RegValue = priv->AntennaTxPwDiff[2]<<8 |
647 priv->AntennaTxPwDiff[1]<<4 |
648 priv->AntennaTxPwDiff[0];
650 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
651 (bXBTxAGC|bXCTxAGC|bXDTxAGC),
655 switch (priv->rf_chip) {
659 rtl92e_set_cck_tx_power(dev, powerlevel);
660 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
665 netdev_err(dev, "Invalid RF Chip ID.\n");
670 bool rtl92e_config_phy(struct net_device *dev)
672 struct r8192_priv *priv = rtllib_priv(dev);
673 bool rtStatus = true;
675 switch (priv->rf_chip) {
679 rtStatus = rtl92e_config_rf(dev);
688 netdev_err(dev, "Invalid RF Chip ID.\n");
694 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
701 for (i = 0; i < RadioA_ArrayLength; i += 2) {
702 if (Rtl819XRadioA_Array[i] == 0xfe) {
706 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i],
708 Rtl819XRadioA_Array[i+1]);
713 for (i = 0; i < RadioB_ArrayLength; i += 2) {
714 if (Rtl819XRadioB_Array[i] == 0xfe) {
718 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
720 Rtl819XRadioB_Array[i+1]);
725 for (i = 0; i < RadioC_ArrayLength; i += 2) {
726 if (Rtl819XRadioC_Array[i] == 0xfe) {
730 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i],
732 Rtl819XRadioC_Array[i+1]);
737 for (i = 0; i < RadioD_ArrayLength; i += 2) {
738 if (Rtl819XRadioD_Array[i] == 0xfe) {
742 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i],
744 Rtl819XRadioD_Array[i+1]);
756 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel)
758 struct r8192_priv *priv = rtllib_priv(dev);
759 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
760 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
762 switch (priv->rf_chip) {
767 rtl92e_set_cck_tx_power(dev, powerlevel);
768 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
774 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__);
779 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev,
780 struct sw_chnl_cmd *CmdTable,
781 u32 CmdTableIdx, u32 CmdTableSz,
782 enum sw_chnl_cmd_id CmdID,
783 u32 Para1, u32 Para2, u32 msDelay)
785 struct sw_chnl_cmd *pCmd;
787 if (CmdTable == NULL) {
788 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__);
791 if (CmdTableIdx >= CmdTableSz) {
792 netdev_err(dev, "%s(): Invalid index requested.\n", __func__);
796 pCmd = CmdTable + CmdTableIdx;
800 pCmd->msDelay = msDelay;
805 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel,
806 u8 *stage, u8 *step, u32 *delay)
808 struct r8192_priv *priv = rtllib_priv(dev);
809 struct rtllib_device *ieee = priv->rtllib;
811 u32 PostCommonCmdCnt;
813 struct sw_chnl_cmd *CurrentCmd = NULL;
816 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
817 __func__, *stage, *step, channel);
819 if (!rtllib_legal_channel(priv->rtllib, channel)) {
820 netdev_err(dev, "Invalid channel requested: %d\n", channel);
826 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
829 CmdID_SetTxPowerLevel,
831 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
833 MAX_PRECMD_CNT, CmdID_End,
836 PostCommonCmdCnt = 0;
838 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd,
840 MAX_POSTCMD_CNT, CmdID_End,
844 switch (priv->rf_chip) {
846 if (!(channel >= 1 && channel <= 14)) {
848 "Invalid channel requested for 8225: %d\n",
852 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
858 RF_CHANNEL_TABLE_ZEBRA[channel],
860 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
868 if (!(channel >= 1 && channel <= 14)) {
870 "Invalid channel requested for 8256: %d\n",
874 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
881 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
892 netdev_warn(dev, "Unknown RF Chip ID\n");
900 CurrentCmd = &ieee->PreCommonCmd[*step];
903 CurrentCmd = &ieee->RfDependCmd[*step];
906 CurrentCmd = &ieee->PostCommonCmd[*step];
910 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
920 switch (CurrentCmd->CmdID) {
921 case CmdID_SetTxPowerLevel:
922 if (priv->IC_Cut > (u8)VERSION_8190_BD)
923 _rtl92e_set_tx_power_level(dev,
926 case CmdID_WritePortUlong:
927 rtl92e_writel(dev, CurrentCmd->Para1,
930 case CmdID_WritePortUshort:
931 rtl92e_writew(dev, CurrentCmd->Para1,
932 (u16)CurrentCmd->Para2);
934 case CmdID_WritePortUchar:
935 rtl92e_writeb(dev, CurrentCmd->Para1,
936 (u8)CurrentCmd->Para2);
938 case CmdID_RF_WriteReg:
939 for (eRFPath = 0; eRFPath <
940 priv->NumTotalRFPath; eRFPath++)
941 rtl92e_set_rf_reg(dev,
942 (enum rf90_radio_path)eRFPath,
943 CurrentCmd->Para1, bMask12Bits,
944 CurrentCmd->Para2<<7);
952 } /*for (Number of RF paths)*/
954 (*delay) = CurrentCmd->msDelay;
959 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel)
961 struct r8192_priv *priv = rtllib_priv(dev);
964 while (!_rtl92e_phy_switch_channel_step(dev, channel,
966 &priv->SwChnlStep, &delay)) {
974 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev)
977 struct r8192_priv *priv = rtllib_priv(dev);
979 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
981 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
984 _rtl92e_phy_switch_channel(dev, priv->chan);
986 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
989 u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
991 struct r8192_priv *priv = rtllib_priv(dev);
993 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
995 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
998 if (priv->SwChnlInProgress)
1002 switch (priv->rtllib->mode) {
1003 case WIRELESS_MODE_A:
1004 case WIRELESS_MODE_N_5G:
1005 if (channel <= 14) {
1007 "Channel %d not available in 802.11a.\n",
1012 case WIRELESS_MODE_B:
1015 "Channel %d not available in 802.11b.\n",
1020 case WIRELESS_MODE_G:
1021 case WIRELESS_MODE_N_24G:
1024 "Channel %d not available in 802.11g.\n",
1031 priv->SwChnlInProgress = true;
1035 priv->chan = channel;
1037 priv->SwChnlStage = 0;
1038 priv->SwChnlStep = 0;
1041 _rtl92e_phy_switch_channel_work_item(dev);
1042 priv->SwChnlInProgress = false;
1046 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev)
1048 struct r8192_priv *priv = rtllib_priv(dev);
1050 switch (priv->CurrentChannelBW) {
1051 case HT_CHANNEL_WIDTH_20:
1052 priv->CCKPresentAttentuation =
1053 priv->CCKPresentAttentuation_20Mdefault +
1054 priv->CCKPresentAttentuation_difference;
1056 if (priv->CCKPresentAttentuation >
1057 (CCKTxBBGainTableLength-1))
1058 priv->CCKPresentAttentuation =
1059 CCKTxBBGainTableLength-1;
1060 if (priv->CCKPresentAttentuation < 0)
1061 priv->CCKPresentAttentuation = 0;
1063 RT_TRACE(COMP_POWER_TRACKING,
1064 "20M, priv->CCKPresentAttentuation = %d\n",
1065 priv->CCKPresentAttentuation);
1067 if (priv->rtllib->current_network.channel == 14 &&
1068 !priv->bcck_in_ch14) {
1069 priv->bcck_in_ch14 = true;
1070 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1071 } else if (priv->rtllib->current_network.channel !=
1072 14 && priv->bcck_in_ch14) {
1073 priv->bcck_in_ch14 = false;
1074 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1076 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1080 case HT_CHANNEL_WIDTH_20_40:
1081 priv->CCKPresentAttentuation =
1082 priv->CCKPresentAttentuation_40Mdefault +
1083 priv->CCKPresentAttentuation_difference;
1085 RT_TRACE(COMP_POWER_TRACKING,
1086 "40M, priv->CCKPresentAttentuation = %d\n",
1087 priv->CCKPresentAttentuation);
1088 if (priv->CCKPresentAttentuation >
1089 (CCKTxBBGainTableLength - 1))
1090 priv->CCKPresentAttentuation =
1091 CCKTxBBGainTableLength-1;
1092 if (priv->CCKPresentAttentuation < 0)
1093 priv->CCKPresentAttentuation = 0;
1095 if (priv->rtllib->current_network.channel == 14 &&
1096 !priv->bcck_in_ch14) {
1097 priv->bcck_in_ch14 = true;
1098 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1099 } else if (priv->rtllib->current_network.channel != 14
1100 && priv->bcck_in_ch14) {
1101 priv->bcck_in_ch14 = false;
1102 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1104 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1110 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev)
1112 struct r8192_priv *priv = rtllib_priv(dev);
1114 if (priv->rtllib->current_network.channel == 14 &&
1115 !priv->bcck_in_ch14)
1116 priv->bcck_in_ch14 = true;
1117 else if (priv->rtllib->current_network.channel != 14 &&
1119 priv->bcck_in_ch14 = false;
1121 switch (priv->CurrentChannelBW) {
1122 case HT_CHANNEL_WIDTH_20:
1123 if (priv->Record_CCK_20Mindex == 0)
1124 priv->Record_CCK_20Mindex = 6;
1125 priv->CCK_index = priv->Record_CCK_20Mindex;
1126 RT_TRACE(COMP_POWER_TRACKING,
1127 "20MHz, %s,CCK_index = %d\n", __func__,
1131 case HT_CHANNEL_WIDTH_20_40:
1132 priv->CCK_index = priv->Record_CCK_40Mindex;
1133 RT_TRACE(COMP_POWER_TRACKING,
1134 "40MHz, %s, CCK_index = %d\n", __func__,
1138 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1141 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev)
1143 struct r8192_priv *priv = rtllib_priv(dev);
1145 if (priv->IC_Cut >= IC_VersionCut_D)
1146 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev);
1148 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev);
1151 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
1154 struct r8192_priv *priv = rtllib_priv(dev);
1158 "==>%s Switch to %s bandwidth\n", __func__,
1159 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1163 if (priv->rf_chip == RF_PSEUDO_11N) {
1164 priv->SetBWModeInProgress = false;
1168 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1171 regBwOpMode = rtl92e_readb(dev, BW_OPMODE);
1173 switch (priv->CurrentChannelBW) {
1174 case HT_CHANNEL_WIDTH_20:
1175 regBwOpMode |= BW_OPMODE_20MHZ;
1176 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1179 case HT_CHANNEL_WIDTH_20_40:
1180 regBwOpMode &= ~BW_OPMODE_20MHZ;
1181 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1185 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1186 priv->CurrentChannelBW);
1190 switch (priv->CurrentChannelBW) {
1191 case HT_CHANNEL_WIDTH_20:
1192 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1193 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1195 if (!priv->btxpower_tracking) {
1196 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000);
1197 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317);
1198 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204);
1200 _rtl92e_cck_tx_power_track_bw_switch(dev);
1203 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1206 case HT_CHANNEL_WIDTH_20_40:
1207 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1208 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1210 if (!priv->btxpower_tracking) {
1211 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000);
1212 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e);
1213 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409);
1215 _rtl92e_cck_tx_power_track_bw_switch(dev);
1218 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
1219 (priv->nCur40MhzPrimeSC>>1));
1220 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
1221 priv->nCur40MhzPrimeSC);
1223 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1226 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1227 priv->CurrentChannelBW);
1232 switch (priv->rf_chip) {
1237 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW);
1247 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__,
1252 atomic_dec(&(priv->rtllib->atm_swbw));
1253 priv->SetBWModeInProgress = false;
1255 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1258 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth,
1259 enum ht_extchnl_offset Offset)
1261 struct r8192_priv *priv = rtllib_priv(dev);
1264 if (priv->SetBWModeInProgress)
1267 atomic_inc(&(priv->rtllib->atm_swbw));
1268 priv->SetBWModeInProgress = true;
1270 priv->CurrentChannelBW = Bandwidth;
1272 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1273 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1274 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1275 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1277 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1279 _rtl92e_set_bw_mode_work_item(dev);
1283 void rtl92e_init_gain(struct net_device *dev, u8 Operation)
1285 #define SCAN_RX_INITIAL_GAIN 0x17
1286 #define POWER_DETECTION_TH 0x08
1287 struct r8192_priv *priv = rtllib_priv(dev);
1292 switch (Operation) {
1295 "IG_Backup, backup the initial gain.\n");
1296 initial_gain = SCAN_RX_INITIAL_GAIN;
1297 BitMask = bMaskByte0;
1298 if (dm_digtable.dig_algorithm ==
1299 DIG_ALGO_BY_FALSE_ALARM)
1300 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1301 priv->initgain_backup.xaagccore1 =
1302 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
1304 priv->initgain_backup.xbagccore1 =
1305 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1,
1307 priv->initgain_backup.xcagccore1 =
1308 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1,
1310 priv->initgain_backup.xdagccore1 =
1311 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1,
1313 BitMask = bMaskByte2;
1314 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev,
1315 rCCK0_CCA, BitMask);
1318 "Scan InitialGainBackup 0xc50 is %x\n",
1319 priv->initgain_backup.xaagccore1);
1321 "Scan InitialGainBackup 0xc58 is %x\n",
1322 priv->initgain_backup.xbagccore1);
1324 "Scan InitialGainBackup 0xc60 is %x\n",
1325 priv->initgain_backup.xcagccore1);
1327 "Scan InitialGainBackup 0xc68 is %x\n",
1328 priv->initgain_backup.xdagccore1);
1330 "Scan InitialGainBackup 0xa0a is %x\n",
1331 priv->initgain_backup.cca);
1333 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1335 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
1336 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
1337 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
1338 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
1339 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1340 POWER_DETECTION_TH);
1341 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH);
1345 "IG_Restore, restore the initial gain.\n");
1347 if (dm_digtable.dig_algorithm ==
1348 DIG_ALGO_BY_FALSE_ALARM)
1349 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1351 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
1352 (u32)priv->initgain_backup.xaagccore1);
1353 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
1354 (u32)priv->initgain_backup.xbagccore1);
1355 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
1356 (u32)priv->initgain_backup.xcagccore1);
1357 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
1358 (u32)priv->initgain_backup.xdagccore1);
1359 BitMask = bMaskByte2;
1360 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
1361 (u32)priv->initgain_backup.cca);
1364 "Scan BBInitialGainRestore 0xc50 is %x\n",
1365 priv->initgain_backup.xaagccore1);
1367 "Scan BBInitialGainRestore 0xc58 is %x\n",
1368 priv->initgain_backup.xbagccore1);
1370 "Scan BBInitialGainRestore 0xc60 is %x\n",
1371 priv->initgain_backup.xcagccore1);
1373 "Scan BBInitialGainRestore 0xc68 is %x\n",
1374 priv->initgain_backup.xdagccore1);
1376 "Scan BBInitialGainRestore 0xa0a is %x\n",
1377 priv->initgain_backup.cca);
1379 rtl92e_set_tx_power(dev,
1380 priv->rtllib->current_network.channel);
1382 if (dm_digtable.dig_algorithm ==
1383 DIG_ALGO_BY_FALSE_ALARM)
1384 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1387 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1393 void rtl92e_set_rf_off(struct net_device *dev)
1396 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1397 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1398 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1399 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1400 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1401 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1402 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1403 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);
1407 static bool _rtl92e_set_rf_power_state(struct net_device *dev,
1408 enum rt_rf_power_state eRFPowerState)
1410 struct r8192_priv *priv = rtllib_priv(dev);
1411 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1412 (&(priv->rtllib->PowerSaveControl));
1413 bool bResult = true;
1414 u8 i = 0, QueueID = 0;
1415 struct rtl8192_tx_ring *ring = NULL;
1417 if (priv->SetRFPowerStateInProgress)
1419 RT_TRACE(COMP_PS, "===========> %s!\n", __func__);
1420 priv->SetRFPowerStateInProgress = true;
1422 switch (priv->rf_chip) {
1424 switch (eRFPowerState) {
1426 RT_TRACE(COMP_PS, "%s eRfOn!\n", __func__);
1427 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1428 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1430 u32 InitilizeCount = 3;
1434 priv->RegRfOff = false;
1435 rtstatus = rtl92e_enable_nic(dev);
1436 } while (!rtstatus && (InitilizeCount > 0));
1440 "%s(): Failed to initialize Adapter.\n",
1442 priv->SetRFPowerStateInProgress = false;
1446 RT_CLEAR_PS_LEVEL(pPSC,
1447 RT_RF_OFF_LEVL_HALT_NIC);
1449 rtl92e_writeb(dev, ANAPAR, 0x37);
1451 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1453 priv->bHwRfOffAction = 0;
1455 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
1457 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
1459 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1461 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
1463 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
1465 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1473 if (priv->rtllib->eRFPowerState == eRfOff)
1477 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1478 ring = &priv->tx_ring[QueueID];
1480 if (skb_queue_len(&ring->queue) == 0) {
1484 RT_TRACE((COMP_POWER|COMP_RF),
1485 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1491 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1492 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! %s: eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1493 __func__, MAX_DOZE_WAITING_TIMES_9x, QueueID);
1497 rtl92e_set_rf_off(dev);
1501 RT_TRACE(COMP_PS, "%s eRfOff/Sleep !\n", __func__);
1503 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1504 ring = &priv->tx_ring[QueueID];
1506 if (skb_queue_len(&ring->queue) == 0) {
1510 RT_TRACE(COMP_POWER,
1511 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1517 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1518 RT_TRACE(COMP_POWER,
1519 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1520 MAX_DOZE_WAITING_TIMES_9x,
1526 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1527 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1528 rtl92e_disable_nic(dev);
1529 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1530 } else if (!(pPSC->RegRfPsLevel &
1531 RT_RF_OFF_LEVL_HALT_NIC)) {
1532 rtl92e_set_rf_off(dev);
1540 "%s(): Unknown state requested: 0x%X.\n",
1541 __func__, eRFPowerState);
1548 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1553 priv->rtllib->eRFPowerState = eRFPowerState;
1555 switch (priv->rf_chip) {
1560 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1565 priv->SetRFPowerStateInProgress = false;
1566 RT_TRACE(COMP_PS, "<=========== %s bResult = %d!\n", __func__, bResult);
1570 bool rtl92e_set_rf_power_state(struct net_device *dev,
1571 enum rt_rf_power_state eRFPowerState)
1573 struct r8192_priv *priv = rtllib_priv(dev);
1575 bool bResult = false;
1578 "---------> %s: eRFPowerState(%d)\n", __func__, eRFPowerState);
1579 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1580 priv->bHwRfOffAction == 0) {
1581 RT_TRACE(COMP_PS, "<--------- %s: discard the request for eRFPowerState(%d) is the same.\n",
1582 __func__, eRFPowerState);
1586 bResult = _rtl92e_set_rf_power_state(dev, eRFPowerState);
1588 RT_TRACE(COMP_PS, "<--------- %s: bResult(%d)\n", __func__, bResult);
1593 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation)
1595 struct r8192_priv *priv = rtllib_priv(dev);
1598 switch (Operation) {
1599 case SCAN_OPT_BACKUP:
1600 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1603 case SCAN_OPT_RESTORE:
1604 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1608 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");