drivers/staging/rtl8188eu/hal/rtl8188e_mp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _RTL8188E_MP_C_
  21
  22 #include <drv_types.h>
  23 #include <rtw_mp.h>
  24 #include <rtl8188e_hal.h>
  25 #include <rtl8188e_dm.h>
  26
  27 s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
  28 {
  29         struct hal_data_8188e   *pHalData = GET_HAL_DATA(padapter);
  30         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
  31
  32         if (!netif_running(padapter->pnetdev)) {
  33                 RT_TRACE(_module_mp_, _drv_warning_,
  34                          ("SetPowerTracking! Fail: interface not opened!\n"));
  35                 return _FAIL;
  36         }
  37
  38         if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE)) {
  39                 RT_TRACE(_module_mp_, _drv_warning_,
  40                          ("SetPowerTracking! Fail: not in MP mode!\n"));
  41                 return _FAIL;
  42         }
  43
  44         if (enable)
  45                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
  46         else
  47                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
  48
  49         return _SUCCESS;
  50 }
  51
  52 void Hal_GetPowerTracking(struct adapter *padapter, u8 *enable)
  53 {
  54         struct hal_data_8188e   *pHalData = GET_HAL_DATA(padapter);
  55         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
  56
  57         *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
  58 }
  59
  60 /*-----------------------------------------------------------------------------
  61  * Function:    mpt_SwitchRfSetting
  62  *
  63  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.
  64  *
  65  * Input:       struct adapter *                                pAdapter
  66  *
  67  * Output:      NONE
  68  *
  69  * Return:      NONE
  70  *
  71  * Revised History:
  72  * When                 Who             Remark
  73  * 01/08/2009   MHC             Suggestion from SD3 Willis for 92S series.
  74  * 01/09/2009   MHC             Add CCK modification for 40MHZ. Suggestion from SD3.
  75  *
  76  *---------------------------------------------------------------------------*/
  77 void Hal_mpt_SwitchRfSetting(struct adapter *pAdapter)
  78 {
  79         struct mp_priv  *pmp = &pAdapter->mppriv;
  80
  81         /*  <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
  82                 pmp->MptCtx.backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
  83                 pmp->MptCtx.backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
  84                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
  85                 PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
  86
  87         return;
  88 }
  89 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
  90
  91 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
  92 void Hal_MPT_CCKTxPowerAdjust(struct adapter *Adapter, bool bInCH14)
  93 {
  94         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;
  95         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;
  96         u8              i;
  97
  98         /*  get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
  99         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
 100
 101         if (!bInCH14) {
 102                 /*  Readback the current bb cck swing value and compare with the table to */
 103                 /*  get the current swing index */
 104                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 105                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
 106                             (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
 107                                 CCKSwingIndex = i;
 108                                 break;
 109                         }
 110                 }
 111
 112                 /* Write 0xa22 0xa23 */
 113                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
 114                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
 115
 116
 117                 /* Write 0xa24 ~ 0xa27 */
 118                 TempVal2 = 0;
 119                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
 120                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
 121                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16)+
 122                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
 123
 124                 /* Write 0xa28  0xa29 */
 125                 TempVal3 = 0;
 126                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
 127                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
 128         } else {
 129                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 130                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
 131                             (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
 132                                 CCKSwingIndex = i;
 133                                 break;
 134                         }
 135                 }
 136
 137                 /* Write 0xa22 0xa23 */
 138                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
 139                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
 140
 141                 /* Write 0xa24 ~ 0xa27 */
 142                 TempVal2 = 0;
 143                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
 144                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
 145                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16)+
 146                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
 147
 148                 /* Write 0xa28  0xa29 */
 149                 TempVal3 = 0;
 150                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
 151                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
 152         }
 153
 154         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
 155         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
 156         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
 157 }
 158
 159 void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter *pAdapter, bool beven)
 160 {
 161         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 162         struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
 163         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
 164         s32             TempCCk;
 165         u8              CCK_index, CCK_index_old = 0;
 166         u8              Action = 0;     /* 0: no action, 1: even->odd, 2:odd->even */
 167         s32             i = 0;
 168
 169
 170         if (!IS_92C_SERIAL(pHalData->VersionID))
 171                 return;
 172         if (beven && !pMptCtx->bMptIndexEven) {
 173                 /* odd->even */
 174                 Action = 2;
 175                 pMptCtx->bMptIndexEven = true;
 176         } else if (!beven && pMptCtx->bMptIndexEven) {
 177                 /* even->odd */
 178                 Action = 1;
 179                 pMptCtx->bMptIndexEven = false;
 180         }
 181
 182         if (Action != 0) {
 183                 /* Query CCK default setting From 0xa24 */
 184                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
 185                 for (i = 0; i < CCK_TABLE_SIZE; i++) {
 186                         if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 187                                 if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
 188                                         CCK_index_old = (u8)i;
 189                                         break;
 190                                 }
 191                         } else {
 192                                 if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
 193                                         CCK_index_old = (u8)i;
 194                                         break;
 195                                 }
 196                         }
 197                 }
 198
 199                 if (Action == 1)
 200                         CCK_index = CCK_index_old - 1;
 201                 else
 202                         CCK_index = CCK_index_old + 1;
 203
 204                 /* Adjust CCK according to gain index */
 205                 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 206                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
 207                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
 208                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
 209                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
 210                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
 211                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
 212                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
 213                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
 214                 } else {
 215                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
 216                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
 217                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
 218                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
 219                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
 220                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
 221                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
 222                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
 223                 }
 224         }
 225 }
 226 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
 227
 228 /*
 229  * SetChannel
 230  * Description
 231  *      Use H2C command to change channel,
 232  *      not only modify rf register, but also other setting need to be done.
 233  */
 234 void Hal_SetChannel(struct adapter *pAdapter)
 235 {
 236         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 237         struct mp_priv  *pmp = &pAdapter->mppriv;
 238         struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
 239         u8              eRFPath;
 240         u8              channel = pmp->channel;
 241
 242         /*  set RF channel register */
 243         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
 244                 _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
 245         Hal_mpt_SwitchRfSetting(pAdapter);
 246
 247         SelectChannel(pAdapter, channel);
 248
 249         if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 250                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
 251                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
 252         } else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
 253                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
 254                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
 255         }
 256 }
 257
 258 /*
 259  * Notice
 260  *      Switch bandwitdth may change center frequency(channel)
 261  */
 262 void Hal_SetBandwidth(struct adapter *pAdapter)
 263 {
 264         struct mp_priv *pmp = &pAdapter->mppriv;
 265
 266
 267         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
 268         Hal_mpt_SwitchRfSetting(pAdapter);
 269 }
 270
 271 void Hal_SetCCKTxPower(struct adapter *pAdapter, u8 *TxPower)
 272 {
 273         u32 tmpval = 0;
 274
 275
 276         /*  rf-A cck tx power */
 277         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
 278         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
 279         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 280
 281         /*  rf-B cck tx power */
 282         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
 283         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
 284         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
 285
 286         RT_TRACE(_module_mp_, _drv_notice_,
 287                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
 288                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
 289 }
 290
 291 void Hal_SetOFDMTxPower(struct adapter *pAdapter, u8 *TxPower)
 292 {
 293         u32 TxAGC = 0;
 294         u8 tmpval = 0;
 295
 296         /*  HT Tx-rf(A) */
 297         tmpval = TxPower[RF_PATH_A];
 298         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
 299
 300         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
 301         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
 302         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
 303         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
 304         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
 305         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
 306
 307         /*  HT Tx-rf(B) */
 308         tmpval = TxPower[RF_PATH_B];
 309         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
 310
 311         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
 312         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
 313         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
 314         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
 315         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
 316         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
 317 }
 318
 319 void Hal_SetAntennaPathPower(struct adapter *pAdapter)
 320 {
 321         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 322         u8 TxPowerLevel[MAX_RF_PATH_NUMS];
 323         u8 rfPath;
 324
 325         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
 326         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
 327
 328         switch (pAdapter->mppriv.antenna_tx) {
 329         case ANTENNA_A:
 330         default:
 331                 rfPath = RF_PATH_A;
 332                 break;
 333         case ANTENNA_B:
 334                 rfPath = RF_PATH_B;
 335                 break;
 336         case ANTENNA_C:
 337                 rfPath = RF_PATH_C;
 338                 break;
 339         }
 340
 341         switch (pHalData->rf_chip) {
 342         case RF_8225:
 343         case RF_8256:
 344         case RF_6052:
 345                 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
 346                 if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     /*  CCK rate */
 347                         Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
 348                 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
 349                 break;
 350         default:
 351                 break;
 352         }
 353 }
 354
 355 void Hal_SetTxPower(struct adapter *pAdapter)
 356 {
 357         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 358         u8 TxPower = pAdapter->mppriv.txpoweridx;
 359         u8 TxPowerLevel[MAX_RF_PATH_NUMS];
 360         u8 rf, rfPath;
 361
 362         for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++)
 363                 TxPowerLevel[rf] = TxPower;
 364
 365         switch (pAdapter->mppriv.antenna_tx) {
 366         case ANTENNA_A:
 367         default:
 368                 rfPath = RF_PATH_A;
 369                 break;
 370         case ANTENNA_B:
 371                 rfPath = RF_PATH_B;
 372                 break;
 373         case ANTENNA_C:
 374                 rfPath = RF_PATH_C;
 375                 break;
 376         }
 377
 378         switch (pHalData->rf_chip) {
 379         /*  2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
 380         /*  We should call normal driver API later!! */
 381         case RF_8225:
 382         case RF_8256:
 383         case RF_6052:
 384                 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
 385                 if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     /*  CCK rate */
 386                         Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
 387                 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
 388                 break;
 389         default:
 390                 break;
 391         }
 392 }
 393
 394 void Hal_SetDataRate(struct adapter *pAdapter)
 395 {
 396         Hal_mpt_SwitchRfSetting(pAdapter);
 397 }
 398
 399 void Hal_SetAntenna(struct adapter *pAdapter)
 400 {
 401         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 402
 403         struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
 404         struct ant_sel_cck *p_cck_txrx;
 405         u8      r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
 406         u8      chgTx = 0, chgRx = 0;
 407         u32     r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
 408
 409
 410         p_ofdm_tx = (struct ant_sel_ofdm *)&r_ant_select_ofdm_val;
 411         p_cck_txrx = (struct ant_sel_cck *)&r_ant_select_cck_val;
 412
 413         p_ofdm_tx->r_ant_ht1    = 0x1;
 414         p_ofdm_tx->r_ant_ht2    = 0x2;  /*  Second TX RF path is A */
 415         p_ofdm_tx->r_ant_non_ht = 0x3;  /*  0x1+0x2=0x3 */
 416
 417         switch (pAdapter->mppriv.antenna_tx) {
 418         case ANTENNA_A:
 419                 p_ofdm_tx->r_tx_antenna         = 0x1;
 420                 r_ofdm_tx_en_val                = 0x1;
 421                 p_ofdm_tx->r_ant_l              = 0x1;
 422                 p_ofdm_tx->r_ant_ht_s1          = 0x1;
 423                 p_ofdm_tx->r_ant_non_ht_s1      = 0x1;
 424                 p_cck_txrx->r_ccktx_enable      = 0x8;
 425                 chgTx = 1;
 426
 427                 /*  From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
 428                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 429                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
 430                 r_ofdm_tx_en_val                = 0x3;
 431
 432                 /*  Power save */
 433
 434                 /*  We need to close RFB by SW control */
 435                 if (pHalData->rf_type == RF_2T2R) {
 436                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
 437                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
 438                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
 439                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
 440                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
 441                 }
 442                 break;
 443         case ANTENNA_B:
 444                 p_ofdm_tx->r_tx_antenna         = 0x2;
 445                 r_ofdm_tx_en_val                = 0x2;
 446                 p_ofdm_tx->r_ant_l              = 0x2;
 447                 p_ofdm_tx->r_ant_ht_s1          = 0x2;
 448                 p_ofdm_tx->r_ant_non_ht_s1      = 0x2;
 449                 p_cck_txrx->r_ccktx_enable      = 0x4;
 450                 chgTx = 1;
 451                 /*  From SD3 Willis suggestion !!! Set RF A as standby */
 452                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
 453                 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 454
 455                 /*  Power save */
 456                 /* cosa r_ant_select_ofdm_val = 0x22222222; */
 457
 458                 /*  2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
 459                 /*  2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
 460                 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
 461                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
 462                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
 463                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
 464                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
 465                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
 466                 }
 467                 break;
 468         case ANTENNA_AB:        /*  For 8192S */
 469                 p_ofdm_tx->r_tx_antenna         = 0x3;
 470                 r_ofdm_tx_en_val                = 0x3;
 471                 p_ofdm_tx->r_ant_l              = 0x3;
 472                 p_ofdm_tx->r_ant_ht_s1          = 0x3;
 473                 p_ofdm_tx->r_ant_non_ht_s1      = 0x3;
 474                 p_cck_txrx->r_ccktx_enable      = 0xC;
 475                 chgTx = 1;
 476
 477                 /*  From SD3 Willis suggestion !!! Set RF B as standby */
 478                 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
 479                 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
 480
 481                 /*  Disable Power save */
 482                 /* cosa r_ant_select_ofdm_val = 0x3321333; */
 483                 /*  2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
 484                 if (pHalData->rf_type == RF_2T2R) {
 485                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
 486                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
 487                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
 488                         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
 489                 }
 490                 break;
 491         default:
 492                 break;
 493         }
 494
 495         /*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
 496         /*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
 497         /*  r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
 498         switch (pAdapter->mppriv.antenna_rx) {
 499         case ANTENNA_A:
 500                 r_rx_antenna_ofdm               = 0x1;  /*  A */
 501                 p_cck_txrx->r_cckrx_enable      = 0x0;  /*  default: A */
 502                 p_cck_txrx->r_cckrx_enable_2    = 0x0;  /*  option: A */
 503                 chgRx = 1;
 504                 break;
 505         case ANTENNA_B:
 506                 r_rx_antenna_ofdm               = 0x2;  /*  B */
 507                 p_cck_txrx->r_cckrx_enable      = 0x1;  /*  default: B */
 508                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*  option: B */
 509                 chgRx = 1;
 510                 break;
 511         case ANTENNA_AB:
 512                 r_rx_antenna_ofdm               = 0x3;  /*  AB */
 513                 p_cck_txrx->r_cckrx_enable      = 0x0;  /*  default:A */
 514                 p_cck_txrx->r_cckrx_enable_2    = 0x1;  /*  option:B */
 515                 chgRx = 1;
 516                 break;
 517         default:
 518                 break;
 519         }
 520
 521         if (chgTx && chgRx) {
 522                 switch (pHalData->rf_chip) {
 523                 case RF_8225:
 524                 case RF_8256:
 525                 case RF_6052:
 526                         /* r_ant_sel_cck_val = r_ant_select_cck_val; */
 527                         PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);       /* OFDM Tx */
 528                         PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);            /* OFDM Tx */
 529                         PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /* OFDM Rx */
 530                         PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    /* OFDM Rx */
 531                         PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);     /* CCK TxRx */
 532
 533                         break;
 534                 default:
 535                         break;
 536                 }
 537         }
 538
 539         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
 540 }
 541
 542 s32 Hal_SetThermalMeter(struct adapter *pAdapter, u8 target_ther)
 543 {
 544         struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
 545
 546
 547         if (!netif_running(pAdapter->pnetdev)) {
 548                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
 549                 return _FAIL;
 550         }
 551
 552         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == false) {
 553                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
 554                 return _FAIL;
 555         }
 556
 557         target_ther &= 0xff;
 558         if (target_ther < 0x07)
 559                 target_ther = 0x07;
 560         else if (target_ther > 0x1d)
 561                 target_ther = 0x1d;
 562
 563         pHalData->EEPROMThermalMeter = target_ther;
 564
 565         return _SUCCESS;
 566 }
 567
 568 void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
 569 {
 570         _write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03);
 571 }
 572
 573 u8 Hal_ReadRFThermalMeter(struct adapter *pAdapter)
 574 {
 575         u32 ThermalValue = 0;
 576
 577         ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
 578         return (u8)ThermalValue;
 579 }
 580
 581 void Hal_GetThermalMeter(struct adapter *pAdapter, u8 *value)
 582 {
 583         Hal_TriggerRFThermalMeter(pAdapter);
 584         rtw_msleep_os(1000);
 585         *value = Hal_ReadRFThermalMeter(pAdapter);
 586 }
 587
 588 void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
 589 {
 590         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
 591         if (bStart) {
 592                 /*  Start Single Carrier. */
 593                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
 594                 /*  1. if OFDM block on? */
 595                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 596                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
 597
 598                 /*  2. set CCK test mode off, set to CCK normal mode */
 599                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 600                 /*  3. turn on scramble setting */
 601                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 602                 /*  4. Turn On Single Carrier Tx and turn off the other test modes. */
 603                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 604                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
 605                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 606                 /* for dynamic set Power index. */
 607                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 608                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 609         } else {
 610                 /*  Stop Single Carrier. */
 611                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n"));
 612
 613                 /*  Turn off all test modes. */
 614                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 615                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 616                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 617                 rtw_msleep_os(10);
 618
 619                 /* BB Reset */
 620                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 621                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 622
 623                 /* Stop for dynamic set Power index. */
 624                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 625                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 626         }
 627 }
 628
 629
 630 void Hal_SetSingleToneTx(struct adapter *pAdapter, u8 bStart)
 631 {
 632         struct hal_data_8188e   *pHalData = GET_HAL_DATA(pAdapter);
 633         bool            is92C = IS_92C_SERIAL(pHalData->VersionID);
 634
 635         u8 rfPath;
 636         u32              reg58 = 0x0;
 637         switch (pAdapter->mppriv.antenna_tx) {
 638         case ANTENNA_A:
 639         default:
 640                 rfPath = RF_PATH_A;
 641                 break;
 642         case ANTENNA_B:
 643                 rfPath = RF_PATH_B;
 644                 break;
 645         case ANTENNA_C:
 646                 rfPath = RF_PATH_C;
 647                 break;
 648         }
 649
 650         pAdapter->mppriv.MptCtx.bSingleTone = bStart;
 651         if (bStart) {
 652                 /*  Start Single Tone. */
 653                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n"));
 654                 /*  <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
 655                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 656                         reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
 657                         reg58 &= 0xFFFFFFF0;
 658                         reg58 += 2;
 659                         PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
 660                 }
 661                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
 662                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
 663
 664                 if (is92C) {
 665                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
 666                         rtw_usleep_os(100);
 667                         if (rfPath == RF_PATH_A)
 668                                 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /*  PAD all on. */
 669                         else if (rfPath == RF_PATH_B)
 670                                 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /*  PAD all on. */
 671                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /*  PAD all on. */
 672                         rtw_usleep_os(100);
 673                 } else {
 674                         write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
 675                         rtw_usleep_os(100);
 676                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /*  PAD all on. */
 677                         rtw_usleep_os(100);
 678                 }
 679
 680                 /* for dynamic set Power index. */
 681                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 682                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 683
 684         } else {
 685                 /*  Stop Single Tone. */
 686                 RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n"));
 687
 688                 /*  <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
 689                 /*  <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
 690                 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
 691                         reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
 692                         reg58 &= 0xFFFFFFF0;
 693                         PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
 694                 }
 695                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 696                 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 697                 if (is92C) {
 698                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
 699                         rtw_usleep_os(100);
 700                         write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /*  PAD all on. */
 701                         write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /*  PAD all on. */
 702                         rtw_usleep_os(100);
 703                 } else {
 704                         write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
 705                         rtw_usleep_os(100);
 706                         write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /*  PAD all on. */
 707                         rtw_usleep_os(100);
 708                 }
 709
 710                 /* Stop for dynamic set Power index. */
 711                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 712                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 713         }
 714 }
 715
 716
 717
 718 void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
 719 {
 720         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
 721         if (bStart) {
 722                 /*  Start Carrier Suppression. */
 723                 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
 724                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
 725                         /*  1. if CCK block on? */
 726                         if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
 727                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
 728
 729                         /* Turn Off All Test Mode */
 730                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 731                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 732                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 733
 734                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /* transmit mode */
 735                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /* turn off scramble setting */
 736
 737                         /* Set CCK Tx Test Rate */
 738                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /* Set FTxRate to 1Mbps */
 739                 }
 740
 741                 /* for dynamic set Power index. */
 742                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 743                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 744         } else {
 745                 /*  Stop Carrier Suppression. */
 746                 RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
 747                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
 748                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /* normal mode */
 749                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /* turn on scramble setting */
 750
 751                         /* BB Reset */
 752                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 753                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 754                 }
 755
 756                 /* Stop for dynamic set Power index. */
 757                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 758                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 759         }
 760 }
 761
 762 void Hal_SetCCKContinuousTx(struct adapter *pAdapter, u8 bStart)
 763 {
 764         u32 cckrate;
 765
 766         if (bStart) {
 767                 RT_TRACE(_module_mp_, _drv_alert_,
 768                          ("SetCCKContinuousTx: test start\n"));
 769
 770                 /*  1. if CCK block on? */
 771                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
 772                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
 773
 774                 /* Turn Off All Test Mode */
 775                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 776                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 777                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 778                 /* Set CCK Tx Test Rate */
 779                 cckrate  = pAdapter->mppriv.rateidx;
 780                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
 781                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   /* transmit mode */
 782                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /* turn on scramble setting */
 783
 784                 /* for dynamic set Power index. */
 785                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 786                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 787         } else {
 788                 RT_TRACE(_module_mp_, _drv_info_,
 789                          ("SetCCKContinuousTx: test stop\n"));
 790
 791                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   /* normal mode */
 792                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     /* turn on scramble setting */
 793
 794                 /* BB Reset */
 795                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 796                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 797
 798                 /* Stop for dynamic set Power index. */
 799                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 800                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 801         }
 802
 803         pAdapter->mppriv.MptCtx.bCckContTx = bStart;
 804         pAdapter->mppriv.MptCtx.bOfdmContTx = false;
 805 } /* mpt_StartCckContTx */
 806
 807 void Hal_SetOFDMContinuousTx(struct adapter *pAdapter, u8 bStart)
 808 {
 809         if (bStart) {
 810                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
 811                 /*  1. if OFDM block on? */
 812                 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
 813                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
 814
 815                 /*  2. set CCK test mode off, set to CCK normal mode */
 816                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
 817
 818                 /*  3. turn on scramble setting */
 819                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
 820                 /*  4. Turn On Continue Tx and turn off the other test modes. */
 821                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
 822                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 823                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 824
 825                 /* for dynamic set Power index. */
 826                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
 827                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
 828
 829         } else {
 830                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
 831                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
 832                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
 833                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
 834                 /* Delay 10 ms */
 835                 rtw_msleep_os(10);
 836                 /* BB Reset */
 837                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
 838                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
 839
 840                 /* Stop for dynamic set Power index. */
 841                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
 842                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
 843         }
 844
 845         pAdapter->mppriv.MptCtx.bCckContTx = false;
 846         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
 847 } /* mpt_StartOfdmContTx */
 848
 849 void Hal_SetContinuousTx(struct adapter *pAdapter, u8 bStart)
 850 {
 851         RT_TRACE(_module_mp_, _drv_info_,
 852                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
 853
 854         pAdapter->mppriv.MptCtx.bStartContTx = bStart;
 855         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
 856                 Hal_SetCCKContinuousTx(pAdapter, bStart);
 857         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
 858                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
 859                 Hal_SetOFDMContinuousTx(pAdapter, bStart);
 860 }