1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
27 static u32 array_agc_tab_1t_8188e[] = {
158 static bool set_baseband_agc_config(struct adapter *adapt)
161 const u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e);
162 u32 *array = array_agc_tab_1t_8188e;
164 for (i = 0; i < arraylen; i += 2) {
166 u32 v2 = array[i + 1];
168 if (v1 < 0xCDCDCDCD) {
169 phy_set_bb_reg(adapt, v1, bMaskDWord, v2);
178 static u32 array_phy_reg_1t_8188e[] = {
372 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
376 } else if (addr == 0xfd) {
378 } else if (addr == 0xfc) {
380 } else if (addr == 0xfb) {
382 } else if (addr == 0xfa) {
384 } else if (addr == 0xf9) {
387 phy_set_bb_reg(adapt, addr, bMaskDWord, data);
388 /* Add 1us delay between BB/RF register setting. */
393 static bool set_baseband_phy_config(struct adapter *adapt)
396 const u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e);
397 u32 *array = array_phy_reg_1t_8188e;
399 for (i = 0; i < arraylen; i += 2) {
401 u32 v2 = array[i + 1];
404 rtl_bb_delay(adapt, v1, v2);
411 static u32 array_phy_reg_pg_8188e[] = {
412 0xE00, 0xFFFFFFFF, 0x06070809,
413 0xE04, 0xFFFFFFFF, 0x02020405,
414 0xE08, 0x0000FF00, 0x00000006,
415 0x86C, 0xFFFFFF00, 0x00020400,
416 0xE10, 0xFFFFFFFF, 0x08090A0B,
417 0xE14, 0xFFFFFFFF, 0x01030607,
418 0xE18, 0xFFFFFFFF, 0x08090A0B,
419 0xE1C, 0xFFFFFFFF, 0x01030607,
420 0xE00, 0xFFFFFFFF, 0x00000000,
421 0xE04, 0xFFFFFFFF, 0x00000000,
422 0xE08, 0x0000FF00, 0x00000000,
423 0x86C, 0xFFFFFF00, 0x00000000,
424 0xE10, 0xFFFFFFFF, 0x00000000,
425 0xE14, 0xFFFFFFFF, 0x00000000,
426 0xE18, 0xFFFFFFFF, 0x00000000,
427 0xE1C, 0xFFFFFFFF, 0x00000000,
428 0xE00, 0xFFFFFFFF, 0x02020202,
429 0xE04, 0xFFFFFFFF, 0x00020202,
430 0xE08, 0x0000FF00, 0x00000000,
431 0x86C, 0xFFFFFF00, 0x00000000,
432 0xE10, 0xFFFFFFFF, 0x04040404,
433 0xE14, 0xFFFFFFFF, 0x00020404,
434 0xE18, 0xFFFFFFFF, 0x00000000,
435 0xE1C, 0xFFFFFFFF, 0x00000000,
436 0xE00, 0xFFFFFFFF, 0x02020202,
437 0xE04, 0xFFFFFFFF, 0x00020202,
438 0xE08, 0x0000FF00, 0x00000000,
439 0x86C, 0xFFFFFF00, 0x00000000,
440 0xE10, 0xFFFFFFFF, 0x04040404,
441 0xE14, 0xFFFFFFFF, 0x00020404,
442 0xE18, 0xFFFFFFFF, 0x00000000,
443 0xE1C, 0xFFFFFFFF, 0x00000000,
444 0xE00, 0xFFFFFFFF, 0x00000000,
445 0xE04, 0xFFFFFFFF, 0x00000000,
446 0xE08, 0x0000FF00, 0x00000000,
447 0x86C, 0xFFFFFF00, 0x00000000,
448 0xE10, 0xFFFFFFFF, 0x00000000,
449 0xE14, 0xFFFFFFFF, 0x00000000,
450 0xE18, 0xFFFFFFFF, 0x00000000,
451 0xE1C, 0xFFFFFFFF, 0x00000000,
452 0xE00, 0xFFFFFFFF, 0x02020202,
453 0xE04, 0xFFFFFFFF, 0x00020202,
454 0xE08, 0x0000FF00, 0x00000000,
455 0x86C, 0xFFFFFF00, 0x00000000,
456 0xE10, 0xFFFFFFFF, 0x04040404,
457 0xE14, 0xFFFFFFFF, 0x00020404,
458 0xE18, 0xFFFFFFFF, 0x00000000,
459 0xE1C, 0xFFFFFFFF, 0x00000000,
460 0xE00, 0xFFFFFFFF, 0x00000000,
461 0xE04, 0xFFFFFFFF, 0x00000000,
462 0xE08, 0x0000FF00, 0x00000000,
463 0x86C, 0xFFFFFF00, 0x00000000,
464 0xE10, 0xFFFFFFFF, 0x00000000,
465 0xE14, 0xFFFFFFFF, 0x00000000,
466 0xE18, 0xFFFFFFFF, 0x00000000,
467 0xE1C, 0xFFFFFFFF, 0x00000000,
468 0xE00, 0xFFFFFFFF, 0x00000000,
469 0xE04, 0xFFFFFFFF, 0x00000000,
470 0xE08, 0x0000FF00, 0x00000000,
471 0x86C, 0xFFFFFF00, 0x00000000,
472 0xE10, 0xFFFFFFFF, 0x00000000,
473 0xE14, 0xFFFFFFFF, 0x00000000,
474 0xE18, 0xFFFFFFFF, 0x00000000,
475 0xE1C, 0xFFFFFFFF, 0x00000000,
476 0xE00, 0xFFFFFFFF, 0x00000000,
477 0xE04, 0xFFFFFFFF, 0x00000000,
478 0xE08, 0x0000FF00, 0x00000000,
479 0x86C, 0xFFFFFF00, 0x00000000,
480 0xE10, 0xFFFFFFFF, 0x00000000,
481 0xE14, 0xFFFFFFFF, 0x00000000,
482 0xE18, 0xFFFFFFFF, 0x00000000,
483 0xE1C, 0xFFFFFFFF, 0x00000000,
484 0xE00, 0xFFFFFFFF, 0x00000000,
485 0xE04, 0xFFFFFFFF, 0x00000000,
486 0xE08, 0x0000FF00, 0x00000000,
487 0x86C, 0xFFFFFF00, 0x00000000,
488 0xE10, 0xFFFFFFFF, 0x00000000,
489 0xE14, 0xFFFFFFFF, 0x00000000,
490 0xE18, 0xFFFFFFFF, 0x00000000,
491 0xE1C, 0xFFFFFFFF, 0x00000000,
492 0xE00, 0xFFFFFFFF, 0x00000000,
493 0xE04, 0xFFFFFFFF, 0x00000000,
494 0xE08, 0x0000FF00, 0x00000000,
495 0x86C, 0xFFFFFF00, 0x00000000,
496 0xE10, 0xFFFFFFFF, 0x00000000,
497 0xE14, 0xFFFFFFFF, 0x00000000,
498 0xE18, 0xFFFFFFFF, 0x00000000,
499 0xE1C, 0xFFFFFFFF, 0x00000000,
503 static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data)
505 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
506 u8 pwrGrpCnt = hal_data->pwrGroupCnt;
508 if (regaddr == rTxAGC_A_Rate18_06)
509 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][0] = data;
510 if (regaddr == rTxAGC_A_Rate54_24)
511 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][1] = data;
512 if (regaddr == rTxAGC_A_CCK1_Mcs32)
513 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][6] = data;
514 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
515 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][7] = data;
516 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
517 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][2] = data;
518 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
519 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][3] = data;
520 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
521 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][4] = data;
522 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
523 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][5] = data;
524 if (hal_data->rf_type == RF_1T1R)
525 hal_data->pwrGroupCnt++;
527 if (regaddr == rTxAGC_B_Rate18_06)
528 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][8] = data;
529 if (regaddr == rTxAGC_B_Rate54_24)
530 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][9] = data;
531 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
532 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][14] = data;
533 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
534 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][15] = data;
535 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
536 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][10] = data;
537 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
538 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][11] = data;
539 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
540 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][12] = data;
541 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
542 hal_data->MCSTxPowerLevelOriginalOffset[pwrGrpCnt][13] = data;
543 if (hal_data->rf_type != RF_1T1R)
544 hal_data->pwrGroupCnt++;
548 static void rtl_addr_delay(struct adapter *adapt,
549 u32 addr, u32 bit_mask, u32 data)
571 store_pwrindex_offset(adapt, addr, bit_mask, data);
575 static bool config_bb_with_pgheader(struct adapter *adapt)
578 const u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e);
579 u32 *array = array_phy_reg_pg_8188e;
581 for (i = 0; i < arraylen; i += 3) {
583 u32 v2 = array[i + 1];
584 u32 v3 = array[i + 2];
587 rtl_addr_delay(adapt, v1, v2, v3);
592 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter)
594 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
595 struct bb_reg_def *reg[4];
597 reg[RF_PATH_A] = &hal_data->PHYRegDef[RF_PATH_A];
598 reg[RF_PATH_B] = &hal_data->PHYRegDef[RF_PATH_B];
599 reg[RF_PATH_C] = &hal_data->PHYRegDef[RF_PATH_C];
600 reg[RF_PATH_D] = &hal_data->PHYRegDef[RF_PATH_D];
602 reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
603 reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
604 reg[RF_PATH_C]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
605 reg[RF_PATH_D]->rfintfs = rFPGA0_XCD_RFInterfaceSW;
607 reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
608 reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB;
609 reg[RF_PATH_C]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
610 reg[RF_PATH_D]->rfintfi = rFPGA0_XCD_RFInterfaceRB;
612 reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE;
613 reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE;
615 reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE;
616 reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE;
618 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter;
619 reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter;
621 reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
622 reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter;
623 reg[RF_PATH_C]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
624 reg[RF_PATH_D]->rfLSSI_Select = rFPGA0_XCD_RFParameter;
626 reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage;
627 reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage;
628 reg[RF_PATH_C]->rfTxGainStage = rFPGA0_TxGainStage;
629 reg[RF_PATH_D]->rfTxGainStage = rFPGA0_TxGainStage;
631 reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
632 reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
634 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
635 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
637 reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
638 reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl;
639 reg[RF_PATH_C]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
640 reg[RF_PATH_D]->rfSwitchControl = rFPGA0_XCD_SwitchControl;
642 reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1;
643 reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1;
644 reg[RF_PATH_C]->rfAGCControl1 = rOFDM0_XCAGCCore1;
645 reg[RF_PATH_D]->rfAGCControl1 = rOFDM0_XDAGCCore1;
647 reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2;
648 reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2;
649 reg[RF_PATH_C]->rfAGCControl2 = rOFDM0_XCAGCCore2;
650 reg[RF_PATH_D]->rfAGCControl2 = rOFDM0_XDAGCCore2;
652 reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance;
653 reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
654 reg[RF_PATH_C]->rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
655 reg[RF_PATH_D]->rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
657 reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE;
658 reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE;
659 reg[RF_PATH_C]->rfRxAFE = rOFDM0_XCRxAFE;
660 reg[RF_PATH_D]->rfRxAFE = rOFDM0_XDRxAFE;
662 reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance;
663 reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
664 reg[RF_PATH_C]->rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
665 reg[RF_PATH_D]->rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
667 reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE;
668 reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE;
669 reg[RF_PATH_C]->rfTxAFE = rOFDM0_XCTxAFE;
670 reg[RF_PATH_D]->rfTxAFE = rOFDM0_XDTxAFE;
672 reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
673 reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
674 reg[RF_PATH_C]->rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
675 reg[RF_PATH_D]->rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
677 reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
678 reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
681 static bool config_parafile(struct adapter *adapt)
683 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt);
684 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
686 set_baseband_phy_config(adapt);
688 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
689 if (!pEEPROM->bautoload_fail_flag) {
690 hal_data->pwrGroupCnt = 0;
691 config_bb_with_pgheader(adapt);
693 set_baseband_agc_config(adapt);
697 bool rtl88eu_phy_bb_config(struct adapter *adapt)
700 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
704 rtl88e_phy_init_bb_rf_register_definition(adapt);
706 /* Enable BB and RF */
707 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
708 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
710 usb_write8(adapt, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
712 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
714 /* Config BB and AGC */
715 rtstatus = config_parafile(adapt);
717 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
718 crystal_cap = hal_data->CrystalCap & 0x3F;
719 phy_set_bb_reg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6)));