drivers/staging/octeon/octeon-stubs.h

   1 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE        512
   2
   3 #ifndef XKPHYS_TO_PHYS
   4 # define XKPHYS_TO_PHYS(p)                      (p)
   5 #endif
   6
   7 #define OCTEON_IRQ_WORKQ0 0
   8 #define OCTEON_IRQ_RML 0
   9 #define OCTEON_IRQ_TIMER1 0
  10 #define OCTEON_IS_MODEL(x) 0
  11 #define octeon_has_feature(x)   0
  12 #define octeon_get_clock_rate() 0
  13
  14 #define CVMX_SYNCIOBDMA         do { } while (0)
  15
  16 #define CVMX_HELPER_INPUT_TAG_TYPE      0
  17 #define CVMX_HELPER_FIRST_MBUFF_SKIP    7
  18 #define CVMX_FAU_REG_END                (2048)
  19 #define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
  20 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    16
  21 #define CVMX_FPA_PACKET_POOL                (0)
  22 #define CVMX_FPA_PACKET_POOL_SIZE           16
  23 #define CVMX_FPA_WQE_POOL                   (1)
  24 #define CVMX_FPA_WQE_POOL_SIZE              16
  25 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b)  ((a) + (b))
  26 #define CVMX_GMXX_RXX_ADR_CTL(a, b)     ((a) + (b))
  27 #define CVMX_GMXX_PRTX_CFG(a, b)        ((a) + (b))
  28 #define CVMX_GMXX_RXX_FRM_MAX(a, b)     ((a) + (b))
  29 #define CVMX_GMXX_RXX_JABBER(a, b)      ((a) + (b))
  30 #define CVMX_IPD_CTL_STATUS             0
  31 #define CVMX_PIP_FRM_LEN_CHKX(a)        (a)
  32 #define CVMX_PIP_NUM_INPUT_PORTS        1
  33 #define CVMX_SCR_SCRATCH                0
  34 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0     2
  35 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1     2
  36 #define CVMX_IPD_SUB_PORT_FCS           0
  37 #define CVMX_SSO_WQ_IQ_DIS              0
  38 #define CVMX_SSO_WQ_INT                 0
  39 #define CVMX_POW_WQ_INT                 0
  40 #define CVMX_SSO_WQ_INT_PC              0
  41 #define CVMX_NPI_RSL_INT_BLOCKS         0
  42 #define CVMX_POW_WQ_INT_PC              0
  43
  44 union cvmx_pip_wqe_word2 {
  45         uint64_t u64;
  46         struct {
  47                 uint64_t bufs:8;
  48                 uint64_t ip_offset:8;
  49                 uint64_t vlan_valid:1;
  50                 uint64_t vlan_stacked:1;
  51                 uint64_t unassigned:1;
  52                 uint64_t vlan_cfi:1;
  53                 uint64_t vlan_id:12;
  54                 uint64_t pr:4;
  55                 uint64_t unassigned2:8;
  56                 uint64_t dec_ipcomp:1;
  57                 uint64_t tcp_or_udp:1;
  58                 uint64_t dec_ipsec:1;
  59                 uint64_t is_v6:1;
  60                 uint64_t software:1;
  61                 uint64_t L4_error:1;
  62                 uint64_t is_frag:1;
  63                 uint64_t IP_exc:1;
  64                 uint64_t is_bcast:1;
  65                 uint64_t is_mcast:1;
  66                 uint64_t not_IP:1;
  67                 uint64_t rcv_error:1;
  68                 uint64_t err_code:8;
  69         } s;
  70         struct {
  71                 uint64_t bufs:8;
  72                 uint64_t ip_offset:8;
  73                 uint64_t vlan_valid:1;
  74                 uint64_t vlan_stacked:1;
  75                 uint64_t unassigned:1;
  76                 uint64_t vlan_cfi:1;
  77                 uint64_t vlan_id:12;
  78                 uint64_t port:12;
  79                 uint64_t dec_ipcomp:1;
  80                 uint64_t tcp_or_udp:1;
  81                 uint64_t dec_ipsec:1;
  82                 uint64_t is_v6:1;
  83                 uint64_t software:1;
  84                 uint64_t L4_error:1;
  85                 uint64_t is_frag:1;
  86                 uint64_t IP_exc:1;
  87                 uint64_t is_bcast:1;
  88                 uint64_t is_mcast:1;
  89                 uint64_t not_IP:1;
  90                 uint64_t rcv_error:1;
  91                 uint64_t err_code:8;
  92         } s_cn68xx;
  93
  94         struct {
  95                 uint64_t unused1:16;
  96                 uint64_t vlan:16;
  97                 uint64_t unused2:32;
  98         } svlan;
  99         struct {
 100                 uint64_t bufs:8;
 101                 uint64_t unused:8;
 102                 uint64_t vlan_valid:1;
 103                 uint64_t vlan_stacked:1;
 104                 uint64_t unassigned:1;
 105                 uint64_t vlan_cfi:1;
 106                 uint64_t vlan_id:12;
 107                 uint64_t pr:4;
 108                 uint64_t unassigned2:12;
 109                 uint64_t software:1;
 110                 uint64_t unassigned3:1;
 111                 uint64_t is_rarp:1;
 112                 uint64_t is_arp:1;
 113                 uint64_t is_bcast:1;
 114                 uint64_t is_mcast:1;
 115                 uint64_t not_IP:1;
 116                 uint64_t rcv_error:1;
 117                 uint64_t err_code:8;
 118         } snoip;
 119
 120 };
 121
 122 union cvmx_pip_wqe_word0 {
 123         struct {
 124                 uint64_t next_ptr:40;
 125                 uint8_t unused;
 126                 __wsum hw_chksum;
 127         } cn38xx;
 128         struct {
 129                 uint64_t pknd:6;        /* 0..5 */
 130                 uint64_t unused2:2;     /* 6..7 */
 131                 uint64_t bpid:6;        /* 8..13 */
 132                 uint64_t unused1:18;    /* 14..31 */
 133                 uint64_t l2ptr:8;       /* 32..39 */
 134                 uint64_t l3ptr:8;       /* 40..47 */
 135                 uint64_t unused0:8;     /* 48..55 */
 136                 uint64_t l4ptr:8;       /* 56..63 */
 137         } cn68xx;
 138 };
 139
 140 union cvmx_wqe_word0 {
 141         uint64_t u64;
 142         union cvmx_pip_wqe_word0 pip;
 143 };
 144
 145 union cvmx_wqe_word1 {
 146         uint64_t u64;
 147         struct {
 148                 uint64_t tag:32;
 149                 uint64_t tag_type:2;
 150                 uint64_t varies:14;
 151                 uint64_t len:16;
 152         };
 153         struct {
 154                 uint64_t tag:32;
 155                 uint64_t tag_type:2;
 156                 uint64_t zero_2:3;
 157                 uint64_t grp:6;
 158                 uint64_t zero_1:1;
 159                 uint64_t qos:3;
 160                 uint64_t zero_0:1;
 161                 uint64_t len:16;
 162         } cn68xx;
 163         struct {
 164                 uint64_t tag:32;
 165                 uint64_t tag_type:2;
 166                 uint64_t zero_2:1;
 167                 uint64_t grp:4;
 168                 uint64_t qos:3;
 169                 uint64_t ipprt:6;
 170                 uint64_t len:16;
 171         } cn38xx;
 172 };
 173
 174 union cvmx_buf_ptr {
 175         void *ptr;
 176         uint64_t u64;
 177         struct {
 178                 uint64_t i:1;
 179                 uint64_t back:4;
 180                 uint64_t pool:3;
 181                 uint64_t size:16;
 182                 uint64_t addr:40;
 183         } s;
 184 };
 185
 186 struct cvmx_wqe {
 187         union cvmx_wqe_word0 word0;
 188         union cvmx_wqe_word1 word1;
 189         union cvmx_pip_wqe_word2 word2;
 190         union cvmx_buf_ptr packet_ptr;
 191         uint8_t packet_data[96];
 192 };
 193
 194 union cvmx_helper_link_info {
 195         uint64_t u64;
 196         struct {
 197                 uint64_t reserved_20_63:44;
 198                 uint64_t link_up:1;         /**< Is the physical link up? */
 199                 uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
 200                 uint64_t speed:18;          /**< Speed of the link in Mbps */
 201         } s;
 202 };
 203
 204 enum cvmx_fau_reg_32 {
 205         CVMX_FAU_REG_32_START   = 0,
 206 };
 207
 208 enum cvmx_fau_op_size {
 209         CVMX_FAU_OP_SIZE_8 = 0,
 210         CVMX_FAU_OP_SIZE_16 = 1,
 211         CVMX_FAU_OP_SIZE_32 = 2,
 212         CVMX_FAU_OP_SIZE_64 = 3
 213 };
 214
 215 typedef enum {
 216         CVMX_SPI_MODE_UNKNOWN = 0,
 217         CVMX_SPI_MODE_TX_HALFPLEX = 1,
 218         CVMX_SPI_MODE_RX_HALFPLEX = 2,
 219         CVMX_SPI_MODE_DUPLEX = 3
 220 } cvmx_spi_mode_t;
 221
 222 typedef enum {
 223         CVMX_HELPER_INTERFACE_MODE_DISABLED,
 224         CVMX_HELPER_INTERFACE_MODE_RGMII,
 225         CVMX_HELPER_INTERFACE_MODE_GMII,
 226         CVMX_HELPER_INTERFACE_MODE_SPI,
 227         CVMX_HELPER_INTERFACE_MODE_PCIE,
 228         CVMX_HELPER_INTERFACE_MODE_XAUI,
 229         CVMX_HELPER_INTERFACE_MODE_SGMII,
 230         CVMX_HELPER_INTERFACE_MODE_PICMG,
 231         CVMX_HELPER_INTERFACE_MODE_NPI,
 232         CVMX_HELPER_INTERFACE_MODE_LOOP,
 233 } cvmx_helper_interface_mode_t;
 234
 235 typedef enum {
 236         CVMX_POW_WAIT = 1,
 237         CVMX_POW_NO_WAIT = 0,
 238 } cvmx_pow_wait_t;
 239
 240 typedef enum {
 241         CVMX_PKO_LOCK_NONE = 0,
 242         CVMX_PKO_LOCK_ATOMIC_TAG = 1,
 243         CVMX_PKO_LOCK_CMD_QUEUE = 2,
 244 } cvmx_pko_lock_t;
 245
 246 typedef enum {
 247         CVMX_PKO_SUCCESS,
 248         CVMX_PKO_INVALID_PORT,
 249         CVMX_PKO_INVALID_QUEUE,
 250         CVMX_PKO_INVALID_PRIORITY,
 251         CVMX_PKO_NO_MEMORY,
 252         CVMX_PKO_PORT_ALREADY_SETUP,
 253         CVMX_PKO_CMD_QUEUE_INIT_ERROR
 254 } cvmx_pko_status_t;
 255
 256 enum cvmx_pow_tag_type {
 257         CVMX_POW_TAG_TYPE_ORDERED   = 0L,
 258         CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
 259         CVMX_POW_TAG_TYPE_NULL      = 2L,
 260         CVMX_POW_TAG_TYPE_NULL_NULL = 3L
 261 };
 262
 263 union cvmx_ipd_ctl_status {
 264         uint64_t u64;
 265         struct cvmx_ipd_ctl_status_s {
 266                 uint64_t reserved_18_63:46;
 267                 uint64_t use_sop:1;
 268                 uint64_t rst_done:1;
 269                 uint64_t clken:1;
 270                 uint64_t no_wptr:1;
 271                 uint64_t pq_apkt:1;
 272                 uint64_t pq_nabuf:1;
 273                 uint64_t ipd_full:1;
 274                 uint64_t pkt_off:1;
 275                 uint64_t len_m8:1;
 276                 uint64_t reset:1;
 277                 uint64_t addpkt:1;
 278                 uint64_t naddbuf:1;
 279                 uint64_t pkt_lend:1;
 280                 uint64_t wqe_lend:1;
 281                 uint64_t pbp_en:1;
 282                 uint64_t opc_mode:2;
 283                 uint64_t ipd_en:1;
 284         } s;
 285         struct cvmx_ipd_ctl_status_cn30xx {
 286                 uint64_t reserved_10_63:54;
 287                 uint64_t len_m8:1;
 288                 uint64_t reset:1;
 289                 uint64_t addpkt:1;
 290                 uint64_t naddbuf:1;
 291                 uint64_t pkt_lend:1;
 292                 uint64_t wqe_lend:1;
 293                 uint64_t pbp_en:1;
 294                 uint64_t opc_mode:2;
 295                 uint64_t ipd_en:1;
 296         } cn30xx;
 297         struct cvmx_ipd_ctl_status_cn38xxp2 {
 298                 uint64_t reserved_9_63:55;
 299                 uint64_t reset:1;
 300                 uint64_t addpkt:1;
 301                 uint64_t naddbuf:1;
 302                 uint64_t pkt_lend:1;
 303                 uint64_t wqe_lend:1;
 304                 uint64_t pbp_en:1;
 305                 uint64_t opc_mode:2;
 306                 uint64_t ipd_en:1;
 307         } cn38xxp2;
 308         struct cvmx_ipd_ctl_status_cn50xx {
 309                 uint64_t reserved_15_63:49;
 310                 uint64_t no_wptr:1;
 311                 uint64_t pq_apkt:1;
 312                 uint64_t pq_nabuf:1;
 313                 uint64_t ipd_full:1;
 314                 uint64_t pkt_off:1;
 315                 uint64_t len_m8:1;
 316                 uint64_t reset:1;
 317                 uint64_t addpkt:1;
 318                 uint64_t naddbuf:1;
 319                 uint64_t pkt_lend:1;
 320                 uint64_t wqe_lend:1;
 321                 uint64_t pbp_en:1;
 322                 uint64_t opc_mode:2;
 323                 uint64_t ipd_en:1;
 324         } cn50xx;
 325         struct cvmx_ipd_ctl_status_cn58xx {
 326                 uint64_t reserved_12_63:52;
 327                 uint64_t ipd_full:1;
 328                 uint64_t pkt_off:1;
 329                 uint64_t len_m8:1;
 330                 uint64_t reset:1;
 331                 uint64_t addpkt:1;
 332                 uint64_t naddbuf:1;
 333                 uint64_t pkt_lend:1;
 334                 uint64_t wqe_lend:1;
 335                 uint64_t pbp_en:1;
 336                 uint64_t opc_mode:2;
 337                 uint64_t ipd_en:1;
 338         } cn58xx;
 339         struct cvmx_ipd_ctl_status_cn63xxp1 {
 340                 uint64_t reserved_16_63:48;
 341                 uint64_t clken:1;
 342                 uint64_t no_wptr:1;
 343                 uint64_t pq_apkt:1;
 344                 uint64_t pq_nabuf:1;
 345                 uint64_t ipd_full:1;
 346                 uint64_t pkt_off:1;
 347                 uint64_t len_m8:1;
 348                 uint64_t reset:1;
 349                 uint64_t addpkt:1;
 350                 uint64_t naddbuf:1;
 351                 uint64_t pkt_lend:1;
 352                 uint64_t wqe_lend:1;
 353                 uint64_t pbp_en:1;
 354                 uint64_t opc_mode:2;
 355                 uint64_t ipd_en:1;
 356         } cn63xxp1;
 357 };
 358
 359 union cvmx_ipd_sub_port_fcs {
 360         uint64_t u64;
 361         struct cvmx_ipd_sub_port_fcs_s {
 362                 uint64_t port_bit:32;
 363                 uint64_t reserved_32_35:4;
 364                 uint64_t port_bit2:4;
 365                 uint64_t reserved_40_63:24;
 366         } s;
 367         struct cvmx_ipd_sub_port_fcs_cn30xx {
 368                 uint64_t port_bit:3;
 369                 uint64_t reserved_3_63:61;
 370         } cn30xx;
 371         struct cvmx_ipd_sub_port_fcs_cn38xx {
 372                 uint64_t port_bit:32;
 373                 uint64_t reserved_32_63:32;
 374         } cn38xx;
 375 };
 376
 377 union cvmx_ipd_sub_port_qos_cnt {
 378         uint64_t u64;
 379         struct cvmx_ipd_sub_port_qos_cnt_s {
 380                 uint64_t cnt:32;
 381                 uint64_t port_qos:9;
 382                 uint64_t reserved_41_63:23;
 383         } s;
 384 };
 385
 386 typedef struct {
 387         uint32_t dropped_octets;
 388         uint32_t dropped_packets;
 389         uint32_t pci_raw_packets;
 390         uint32_t octets;
 391         uint32_t packets;
 392         uint32_t multicast_packets;
 393         uint32_t broadcast_packets;
 394         uint32_t len_64_packets;
 395         uint32_t len_65_127_packets;
 396         uint32_t len_128_255_packets;
 397         uint32_t len_256_511_packets;
 398         uint32_t len_512_1023_packets;
 399         uint32_t len_1024_1518_packets;
 400         uint32_t len_1519_max_packets;
 401         uint32_t fcs_align_err_packets;
 402         uint32_t runt_packets;
 403         uint32_t runt_crc_packets;
 404         uint32_t oversize_packets;
 405         uint32_t oversize_crc_packets;
 406         uint32_t inb_packets;
 407         uint64_t inb_octets;
 408         uint16_t inb_errors;
 409 } cvmx_pip_port_status_t;
 410
 411 typedef struct {
 412         uint32_t packets;
 413         uint64_t octets;
 414         uint64_t doorbell;
 415 } cvmx_pko_port_status_t;
 416
 417 union cvmx_pip_frm_len_chkx {
 418         uint64_t u64;
 419         struct cvmx_pip_frm_len_chkx_s {
 420                 uint64_t reserved_32_63:32;
 421                 uint64_t maxlen:16;
 422                 uint64_t minlen:16;
 423         } s;
 424 };
 425
 426 union cvmx_gmxx_rxx_frm_ctl {
 427         uint64_t u64;
 428         struct cvmx_gmxx_rxx_frm_ctl_s {
 429                 uint64_t pre_chk:1;
 430                 uint64_t pre_strp:1;
 431                 uint64_t ctl_drp:1;
 432                 uint64_t ctl_bck:1;
 433                 uint64_t ctl_mcst:1;
 434                 uint64_t ctl_smac:1;
 435                 uint64_t pre_free:1;
 436                 uint64_t vlan_len:1;
 437                 uint64_t pad_len:1;
 438                 uint64_t pre_align:1;
 439                 uint64_t null_dis:1;
 440                 uint64_t reserved_11_11:1;
 441                 uint64_t ptp_mode:1;
 442                 uint64_t reserved_13_63:51;
 443         } s;
 444         struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
 445                 uint64_t pre_chk:1;
 446                 uint64_t pre_strp:1;
 447                 uint64_t ctl_drp:1;
 448                 uint64_t ctl_bck:1;
 449                 uint64_t ctl_mcst:1;
 450                 uint64_t ctl_smac:1;
 451                 uint64_t pre_free:1;
 452                 uint64_t vlan_len:1;
 453                 uint64_t pad_len:1;
 454                 uint64_t reserved_9_63:55;
 455         } cn30xx;
 456         struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
 457                 uint64_t pre_chk:1;
 458                 uint64_t pre_strp:1;
 459                 uint64_t ctl_drp:1;
 460                 uint64_t ctl_bck:1;
 461                 uint64_t ctl_mcst:1;
 462                 uint64_t ctl_smac:1;
 463                 uint64_t pre_free:1;
 464                 uint64_t vlan_len:1;
 465                 uint64_t reserved_8_63:56;
 466         } cn31xx;
 467         struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
 468                 uint64_t pre_chk:1;
 469                 uint64_t pre_strp:1;
 470                 uint64_t ctl_drp:1;
 471                 uint64_t ctl_bck:1;
 472                 uint64_t ctl_mcst:1;
 473                 uint64_t ctl_smac:1;
 474                 uint64_t pre_free:1;
 475                 uint64_t reserved_7_8:2;
 476                 uint64_t pre_align:1;
 477                 uint64_t null_dis:1;
 478                 uint64_t reserved_11_63:53;
 479         } cn50xx;
 480         struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
 481                 uint64_t pre_chk:1;
 482                 uint64_t pre_strp:1;
 483                 uint64_t ctl_drp:1;
 484                 uint64_t ctl_bck:1;
 485                 uint64_t ctl_mcst:1;
 486                 uint64_t ctl_smac:1;
 487                 uint64_t pre_free:1;
 488                 uint64_t reserved_7_8:2;
 489                 uint64_t pre_align:1;
 490                 uint64_t reserved_10_63:54;
 491         } cn56xxp1;
 492         struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
 493                 uint64_t pre_chk:1;
 494                 uint64_t pre_strp:1;
 495                 uint64_t ctl_drp:1;
 496                 uint64_t ctl_bck:1;
 497                 uint64_t ctl_mcst:1;
 498                 uint64_t ctl_smac:1;
 499                 uint64_t pre_free:1;
 500                 uint64_t vlan_len:1;
 501                 uint64_t pad_len:1;
 502                 uint64_t pre_align:1;
 503                 uint64_t null_dis:1;
 504                 uint64_t reserved_11_63:53;
 505         } cn58xx;
 506         struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
 507                 uint64_t pre_chk:1;
 508                 uint64_t pre_strp:1;
 509                 uint64_t ctl_drp:1;
 510                 uint64_t ctl_bck:1;
 511                 uint64_t ctl_mcst:1;
 512                 uint64_t ctl_smac:1;
 513                 uint64_t pre_free:1;
 514                 uint64_t reserved_7_8:2;
 515                 uint64_t pre_align:1;
 516                 uint64_t null_dis:1;
 517                 uint64_t reserved_11_11:1;
 518                 uint64_t ptp_mode:1;
 519                 uint64_t reserved_13_63:51;
 520         } cn61xx;
 521 };
 522
 523 union cvmx_gmxx_rxx_int_reg {
 524         uint64_t u64;
 525         struct cvmx_gmxx_rxx_int_reg_s {
 526                 uint64_t minerr:1;
 527                 uint64_t carext:1;
 528                 uint64_t maxerr:1;
 529                 uint64_t jabber:1;
 530                 uint64_t fcserr:1;
 531                 uint64_t alnerr:1;
 532                 uint64_t lenerr:1;
 533                 uint64_t rcverr:1;
 534                 uint64_t skperr:1;
 535                 uint64_t niberr:1;
 536                 uint64_t ovrerr:1;
 537                 uint64_t pcterr:1;
 538                 uint64_t rsverr:1;
 539                 uint64_t falerr:1;
 540                 uint64_t coldet:1;
 541                 uint64_t ifgerr:1;
 542                 uint64_t phy_link:1;
 543                 uint64_t phy_spd:1;
 544                 uint64_t phy_dupx:1;
 545                 uint64_t pause_drp:1;
 546                 uint64_t loc_fault:1;
 547                 uint64_t rem_fault:1;
 548                 uint64_t bad_seq:1;
 549                 uint64_t bad_term:1;
 550                 uint64_t unsop:1;
 551                 uint64_t uneop:1;
 552                 uint64_t undat:1;
 553                 uint64_t hg2fld:1;
 554                 uint64_t hg2cc:1;
 555                 uint64_t reserved_29_63:35;
 556         } s;
 557         struct cvmx_gmxx_rxx_int_reg_cn30xx {
 558                 uint64_t minerr:1;
 559                 uint64_t carext:1;
 560                 uint64_t maxerr:1;
 561                 uint64_t jabber:1;
 562                 uint64_t fcserr:1;
 563                 uint64_t alnerr:1;
 564                 uint64_t lenerr:1;
 565                 uint64_t rcverr:1;
 566                 uint64_t skperr:1;
 567                 uint64_t niberr:1;
 568                 uint64_t ovrerr:1;
 569                 uint64_t pcterr:1;
 570                 uint64_t rsverr:1;
 571                 uint64_t falerr:1;
 572                 uint64_t coldet:1;
 573                 uint64_t ifgerr:1;
 574                 uint64_t phy_link:1;
 575                 uint64_t phy_spd:1;
 576                 uint64_t phy_dupx:1;
 577                 uint64_t reserved_19_63:45;
 578         } cn30xx;
 579         struct cvmx_gmxx_rxx_int_reg_cn50xx {
 580                 uint64_t reserved_0_0:1;
 581                 uint64_t carext:1;
 582                 uint64_t reserved_2_2:1;
 583                 uint64_t jabber:1;
 584                 uint64_t fcserr:1;
 585                 uint64_t alnerr:1;
 586                 uint64_t reserved_6_6:1;
 587                 uint64_t rcverr:1;
 588                 uint64_t skperr:1;
 589                 uint64_t niberr:1;
 590                 uint64_t ovrerr:1;
 591                 uint64_t pcterr:1;
 592                 uint64_t rsverr:1;
 593                 uint64_t falerr:1;
 594                 uint64_t coldet:1;
 595                 uint64_t ifgerr:1;
 596                 uint64_t phy_link:1;
 597                 uint64_t phy_spd:1;
 598                 uint64_t phy_dupx:1;
 599                 uint64_t pause_drp:1;
 600                 uint64_t reserved_20_63:44;
 601         } cn50xx;
 602         struct cvmx_gmxx_rxx_int_reg_cn52xx {
 603                 uint64_t reserved_0_0:1;
 604                 uint64_t carext:1;
 605                 uint64_t reserved_2_2:1;
 606                 uint64_t jabber:1;
 607                 uint64_t fcserr:1;
 608                 uint64_t reserved_5_6:2;
 609                 uint64_t rcverr:1;
 610                 uint64_t skperr:1;
 611                 uint64_t reserved_9_9:1;
 612                 uint64_t ovrerr:1;
 613                 uint64_t pcterr:1;
 614                 uint64_t rsverr:1;
 615                 uint64_t falerr:1;
 616                 uint64_t coldet:1;
 617                 uint64_t ifgerr:1;
 618                 uint64_t reserved_16_18:3;
 619                 uint64_t pause_drp:1;
 620                 uint64_t loc_fault:1;
 621                 uint64_t rem_fault:1;
 622                 uint64_t bad_seq:1;
 623                 uint64_t bad_term:1;
 624                 uint64_t unsop:1;
 625                 uint64_t uneop:1;
 626                 uint64_t undat:1;
 627                 uint64_t hg2fld:1;
 628                 uint64_t hg2cc:1;
 629                 uint64_t reserved_29_63:35;
 630         } cn52xx;
 631         struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
 632                 uint64_t reserved_0_0:1;
 633                 uint64_t carext:1;
 634                 uint64_t reserved_2_2:1;
 635                 uint64_t jabber:1;
 636                 uint64_t fcserr:1;
 637                 uint64_t reserved_5_6:2;
 638                 uint64_t rcverr:1;
 639                 uint64_t skperr:1;
 640                 uint64_t reserved_9_9:1;
 641                 uint64_t ovrerr:1;
 642                 uint64_t pcterr:1;
 643                 uint64_t rsverr:1;
 644                 uint64_t falerr:1;
 645                 uint64_t coldet:1;
 646                 uint64_t ifgerr:1;
 647                 uint64_t reserved_16_18:3;
 648                 uint64_t pause_drp:1;
 649                 uint64_t loc_fault:1;
 650                 uint64_t rem_fault:1;
 651                 uint64_t bad_seq:1;
 652                 uint64_t bad_term:1;
 653                 uint64_t unsop:1;
 654                 uint64_t uneop:1;
 655                 uint64_t undat:1;
 656                 uint64_t reserved_27_63:37;
 657         } cn56xxp1;
 658         struct cvmx_gmxx_rxx_int_reg_cn58xx {
 659                 uint64_t minerr:1;
 660                 uint64_t carext:1;
 661                 uint64_t maxerr:1;
 662                 uint64_t jabber:1;
 663                 uint64_t fcserr:1;
 664                 uint64_t alnerr:1;
 665                 uint64_t lenerr:1;
 666                 uint64_t rcverr:1;
 667                 uint64_t skperr:1;
 668                 uint64_t niberr:1;
 669                 uint64_t ovrerr:1;
 670                 uint64_t pcterr:1;
 671                 uint64_t rsverr:1;
 672                 uint64_t falerr:1;
 673                 uint64_t coldet:1;
 674                 uint64_t ifgerr:1;
 675                 uint64_t phy_link:1;
 676                 uint64_t phy_spd:1;
 677                 uint64_t phy_dupx:1;
 678                 uint64_t pause_drp:1;
 679                 uint64_t reserved_20_63:44;
 680         } cn58xx;
 681         struct cvmx_gmxx_rxx_int_reg_cn61xx {
 682                 uint64_t minerr:1;
 683                 uint64_t carext:1;
 684                 uint64_t reserved_2_2:1;
 685                 uint64_t jabber:1;
 686                 uint64_t fcserr:1;
 687                 uint64_t reserved_5_6:2;
 688                 uint64_t rcverr:1;
 689                 uint64_t skperr:1;
 690                 uint64_t reserved_9_9:1;
 691                 uint64_t ovrerr:1;
 692                 uint64_t pcterr:1;
 693                 uint64_t rsverr:1;
 694                 uint64_t falerr:1;
 695                 uint64_t coldet:1;
 696                 uint64_t ifgerr:1;
 697                 uint64_t reserved_16_18:3;
 698                 uint64_t pause_drp:1;
 699                 uint64_t loc_fault:1;
 700                 uint64_t rem_fault:1;
 701                 uint64_t bad_seq:1;
 702                 uint64_t bad_term:1;
 703                 uint64_t unsop:1;
 704                 uint64_t uneop:1;
 705                 uint64_t undat:1;
 706                 uint64_t hg2fld:1;
 707                 uint64_t hg2cc:1;
 708                 uint64_t reserved_29_63:35;
 709         } cn61xx;
 710 };
 711
 712 union cvmx_gmxx_prtx_cfg {
 713         uint64_t u64;
 714         struct cvmx_gmxx_prtx_cfg_s {
 715                 uint64_t reserved_22_63:42;
 716                 uint64_t pknd:6;
 717                 uint64_t reserved_14_15:2;
 718                 uint64_t tx_idle:1;
 719                 uint64_t rx_idle:1;
 720                 uint64_t reserved_9_11:3;
 721                 uint64_t speed_msb:1;
 722                 uint64_t reserved_4_7:4;
 723                 uint64_t slottime:1;
 724                 uint64_t duplex:1;
 725                 uint64_t speed:1;
 726                 uint64_t en:1;
 727         } s;
 728         struct cvmx_gmxx_prtx_cfg_cn30xx {
 729                 uint64_t reserved_4_63:60;
 730                 uint64_t slottime:1;
 731                 uint64_t duplex:1;
 732                 uint64_t speed:1;
 733                 uint64_t en:1;
 734         } cn30xx;
 735         struct cvmx_gmxx_prtx_cfg_cn52xx {
 736                 uint64_t reserved_14_63:50;
 737                 uint64_t tx_idle:1;
 738                 uint64_t rx_idle:1;
 739                 uint64_t reserved_9_11:3;
 740                 uint64_t speed_msb:1;
 741                 uint64_t reserved_4_7:4;
 742                 uint64_t slottime:1;
 743                 uint64_t duplex:1;
 744                 uint64_t speed:1;
 745                 uint64_t en:1;
 746         } cn52xx;
 747 };
 748
 749 union cvmx_gmxx_rxx_adr_ctl {
 750         uint64_t u64;
 751         struct cvmx_gmxx_rxx_adr_ctl_s {
 752                 uint64_t reserved_4_63:60;
 753                 uint64_t cam_mode:1;
 754                 uint64_t mcst:2;
 755                 uint64_t bcst:1;
 756         } s;
 757 };
 758
 759 union cvmx_pip_prt_tagx {
 760         uint64_t u64;
 761         struct cvmx_pip_prt_tagx_s {
 762                 uint64_t reserved_54_63:10;
 763                 uint64_t portadd_en:1;
 764                 uint64_t inc_hwchk:1;
 765                 uint64_t reserved_50_51:2;
 766                 uint64_t grptagbase_msb:2;
 767                 uint64_t reserved_46_47:2;
 768                 uint64_t grptagmask_msb:2;
 769                 uint64_t reserved_42_43:2;
 770                 uint64_t grp_msb:2;
 771                 uint64_t grptagbase:4;
 772                 uint64_t grptagmask:4;
 773                 uint64_t grptag:1;
 774                 uint64_t grptag_mskip:1;
 775                 uint64_t tag_mode:2;
 776                 uint64_t inc_vs:2;
 777                 uint64_t inc_vlan:1;
 778                 uint64_t inc_prt_flag:1;
 779                 uint64_t ip6_dprt_flag:1;
 780                 uint64_t ip4_dprt_flag:1;
 781                 uint64_t ip6_sprt_flag:1;
 782                 uint64_t ip4_sprt_flag:1;
 783                 uint64_t ip6_nxth_flag:1;
 784                 uint64_t ip4_pctl_flag:1;
 785                 uint64_t ip6_dst_flag:1;
 786                 uint64_t ip4_dst_flag:1;
 787                 uint64_t ip6_src_flag:1;
 788                 uint64_t ip4_src_flag:1;
 789                 uint64_t tcp6_tag_type:2;
 790                 uint64_t tcp4_tag_type:2;
 791                 uint64_t ip6_tag_type:2;
 792                 uint64_t ip4_tag_type:2;
 793                 uint64_t non_tag_type:2;
 794                 uint64_t grp:4;
 795         } s;
 796         struct cvmx_pip_prt_tagx_cn30xx {
 797                 uint64_t reserved_40_63:24;
 798                 uint64_t grptagbase:4;
 799                 uint64_t grptagmask:4;
 800                 uint64_t grptag:1;
 801                 uint64_t reserved_30_30:1;
 802                 uint64_t tag_mode:2;
 803                 uint64_t inc_vs:2;
 804                 uint64_t inc_vlan:1;
 805                 uint64_t inc_prt_flag:1;
 806                 uint64_t ip6_dprt_flag:1;
 807                 uint64_t ip4_dprt_flag:1;
 808                 uint64_t ip6_sprt_flag:1;
 809                 uint64_t ip4_sprt_flag:1;
 810                 uint64_t ip6_nxth_flag:1;
 811                 uint64_t ip4_pctl_flag:1;
 812                 uint64_t ip6_dst_flag:1;
 813                 uint64_t ip4_dst_flag:1;
 814                 uint64_t ip6_src_flag:1;
 815                 uint64_t ip4_src_flag:1;
 816                 uint64_t tcp6_tag_type:2;
 817                 uint64_t tcp4_tag_type:2;
 818                 uint64_t ip6_tag_type:2;
 819                 uint64_t ip4_tag_type:2;
 820                 uint64_t non_tag_type:2;
 821                 uint64_t grp:4;
 822         } cn30xx;
 823         struct cvmx_pip_prt_tagx_cn50xx {
 824                 uint64_t reserved_40_63:24;
 825                 uint64_t grptagbase:4;
 826                 uint64_t grptagmask:4;
 827                 uint64_t grptag:1;
 828                 uint64_t grptag_mskip:1;
 829                 uint64_t tag_mode:2;
 830                 uint64_t inc_vs:2;
 831                 uint64_t inc_vlan:1;
 832                 uint64_t inc_prt_flag:1;
 833                 uint64_t ip6_dprt_flag:1;
 834                 uint64_t ip4_dprt_flag:1;
 835                 uint64_t ip6_sprt_flag:1;
 836                 uint64_t ip4_sprt_flag:1;
 837                 uint64_t ip6_nxth_flag:1;
 838                 uint64_t ip4_pctl_flag:1;
 839                 uint64_t ip6_dst_flag:1;
 840                 uint64_t ip4_dst_flag:1;
 841                 uint64_t ip6_src_flag:1;
 842                 uint64_t ip4_src_flag:1;
 843                 uint64_t tcp6_tag_type:2;
 844                 uint64_t tcp4_tag_type:2;
 845                 uint64_t ip6_tag_type:2;
 846                 uint64_t ip4_tag_type:2;
 847                 uint64_t non_tag_type:2;
 848                 uint64_t grp:4;
 849         } cn50xx;
 850 };
 851
 852 union cvmx_spxx_int_reg {
 853         uint64_t u64;
 854         struct cvmx_spxx_int_reg_s {
 855                 uint64_t reserved_32_63:32;
 856                 uint64_t spf:1;
 857                 uint64_t reserved_12_30:19;
 858                 uint64_t calerr:1;
 859                 uint64_t syncerr:1;
 860                 uint64_t diperr:1;
 861                 uint64_t tpaovr:1;
 862                 uint64_t rsverr:1;
 863                 uint64_t drwnng:1;
 864                 uint64_t clserr:1;
 865                 uint64_t spiovr:1;
 866                 uint64_t reserved_2_3:2;
 867                 uint64_t abnorm:1;
 868                 uint64_t prtnxa:1;
 869         } s;
 870 };
 871
 872 union cvmx_spxx_int_msk {
 873         uint64_t u64;
 874         struct cvmx_spxx_int_msk_s {
 875                 uint64_t reserved_12_63:52;
 876                 uint64_t calerr:1;
 877                 uint64_t syncerr:1;
 878                 uint64_t diperr:1;
 879                 uint64_t tpaovr:1;
 880                 uint64_t rsverr:1;
 881                 uint64_t drwnng:1;
 882                 uint64_t clserr:1;
 883                 uint64_t spiovr:1;
 884                 uint64_t reserved_2_3:2;
 885                 uint64_t abnorm:1;
 886                 uint64_t prtnxa:1;
 887         } s;
 888 };
 889
 890 union cvmx_pow_wq_int {
 891         uint64_t u64;
 892         struct cvmx_pow_wq_int_s {
 893                 uint64_t wq_int:16;
 894                 uint64_t iq_dis:16;
 895                 uint64_t reserved_32_63:32;
 896         } s;
 897 };
 898
 899 union cvmx_sso_wq_int_thrx {
 900         uint64_t u64;
 901         struct {
 902                 uint64_t iq_thr:12;
 903                 uint64_t reserved_12_13:2;
 904                 uint64_t ds_thr:12;
 905                 uint64_t reserved_26_27:2;
 906                 uint64_t tc_thr:4;
 907                 uint64_t tc_en:1;
 908                 uint64_t reserved_33_63:31;
 909         } s;
 910 };
 911
 912 union cvmx_stxx_int_reg {
 913         uint64_t u64;
 914         struct cvmx_stxx_int_reg_s {
 915                 uint64_t reserved_9_63:55;
 916                 uint64_t syncerr:1;
 917                 uint64_t frmerr:1;
 918                 uint64_t unxfrm:1;
 919                 uint64_t nosync:1;
 920                 uint64_t diperr:1;
 921                 uint64_t datovr:1;
 922                 uint64_t ovrbst:1;
 923                 uint64_t calpar1:1;
 924                 uint64_t calpar0:1;
 925         } s;
 926 };
 927
 928 union cvmx_stxx_int_msk {
 929         uint64_t u64;
 930         struct cvmx_stxx_int_msk_s {
 931                 uint64_t reserved_8_63:56;
 932                 uint64_t frmerr:1;
 933                 uint64_t unxfrm:1;
 934                 uint64_t nosync:1;
 935                 uint64_t diperr:1;
 936                 uint64_t datovr:1;
 937                 uint64_t ovrbst:1;
 938                 uint64_t calpar1:1;
 939                 uint64_t calpar0:1;
 940         } s;
 941 };
 942
 943 union cvmx_pow_wq_int_pc {
 944         uint64_t u64;
 945         struct cvmx_pow_wq_int_pc_s {
 946                 uint64_t reserved_0_7:8;
 947                 uint64_t pc_thr:20;
 948                 uint64_t reserved_28_31:4;
 949                 uint64_t pc:28;
 950                 uint64_t reserved_60_63:4;
 951         } s;
 952 };
 953
 954 union cvmx_pow_wq_int_thrx {
 955         uint64_t u64;
 956         struct cvmx_pow_wq_int_thrx_s {
 957                 uint64_t reserved_29_63:35;
 958                 uint64_t tc_en:1;
 959                 uint64_t tc_thr:4;
 960                 uint64_t reserved_23_23:1;
 961                 uint64_t ds_thr:11;
 962                 uint64_t reserved_11_11:1;
 963                 uint64_t iq_thr:11;
 964         } s;
 965         struct cvmx_pow_wq_int_thrx_cn30xx {
 966                 uint64_t reserved_29_63:35;
 967                 uint64_t tc_en:1;
 968                 uint64_t tc_thr:4;
 969                 uint64_t reserved_18_23:6;
 970                 uint64_t ds_thr:6;
 971                 uint64_t reserved_6_11:6;
 972                 uint64_t iq_thr:6;
 973         } cn30xx;
 974         struct cvmx_pow_wq_int_thrx_cn31xx {
 975                 uint64_t reserved_29_63:35;
 976                 uint64_t tc_en:1;
 977                 uint64_t tc_thr:4;
 978                 uint64_t reserved_20_23:4;
 979                 uint64_t ds_thr:8;
 980                 uint64_t reserved_8_11:4;
 981                 uint64_t iq_thr:8;
 982         } cn31xx;
 983         struct cvmx_pow_wq_int_thrx_cn52xx {
 984                 uint64_t reserved_29_63:35;
 985                 uint64_t tc_en:1;
 986                 uint64_t tc_thr:4;
 987                 uint64_t reserved_21_23:3;
 988                 uint64_t ds_thr:9;
 989                 uint64_t reserved_9_11:3;
 990                 uint64_t iq_thr:9;
 991         } cn52xx;
 992         struct cvmx_pow_wq_int_thrx_cn63xx {
 993                 uint64_t reserved_29_63:35;
 994                 uint64_t tc_en:1;
 995                 uint64_t tc_thr:4;
 996                 uint64_t reserved_22_23:2;
 997                 uint64_t ds_thr:10;
 998                 uint64_t reserved_10_11:2;
 999                 uint64_t iq_thr:10;
1000         } cn63xx;
1001 };
1002
1003 union cvmx_npi_rsl_int_blocks {
1004         uint64_t u64;
1005         struct cvmx_npi_rsl_int_blocks_s {
1006                 uint64_t reserved_32_63:32;
1007                 uint64_t rint_31:1;
1008                 uint64_t iob:1;
1009                 uint64_t reserved_28_29:2;
1010                 uint64_t rint_27:1;
1011                 uint64_t rint_26:1;
1012                 uint64_t rint_25:1;
1013                 uint64_t rint_24:1;
1014                 uint64_t asx1:1;
1015                 uint64_t asx0:1;
1016                 uint64_t rint_21:1;
1017                 uint64_t pip:1;
1018                 uint64_t spx1:1;
1019                 uint64_t spx0:1;
1020                 uint64_t lmc:1;
1021                 uint64_t l2c:1;
1022                 uint64_t rint_15:1;
1023                 uint64_t reserved_13_14:2;
1024                 uint64_t pow:1;
1025                 uint64_t tim:1;
1026                 uint64_t pko:1;
1027                 uint64_t ipd:1;
1028                 uint64_t rint_8:1;
1029                 uint64_t zip:1;
1030                 uint64_t dfa:1;
1031                 uint64_t fpa:1;
1032                 uint64_t key:1;
1033                 uint64_t npi:1;
1034                 uint64_t gmx1:1;
1035                 uint64_t gmx0:1;
1036                 uint64_t mio:1;
1037         } s;
1038         struct cvmx_npi_rsl_int_blocks_cn30xx {
1039                 uint64_t reserved_32_63:32;
1040                 uint64_t rint_31:1;
1041                 uint64_t iob:1;
1042                 uint64_t rint_29:1;
1043                 uint64_t rint_28:1;
1044                 uint64_t rint_27:1;
1045                 uint64_t rint_26:1;
1046                 uint64_t rint_25:1;
1047                 uint64_t rint_24:1;
1048                 uint64_t asx1:1;
1049                 uint64_t asx0:1;
1050                 uint64_t rint_21:1;
1051                 uint64_t pip:1;
1052                 uint64_t spx1:1;
1053                 uint64_t spx0:1;
1054                 uint64_t lmc:1;
1055                 uint64_t l2c:1;
1056                 uint64_t rint_15:1;
1057                 uint64_t rint_14:1;
1058                 uint64_t usb:1;
1059                 uint64_t pow:1;
1060                 uint64_t tim:1;
1061                 uint64_t pko:1;
1062                 uint64_t ipd:1;
1063                 uint64_t rint_8:1;
1064                 uint64_t zip:1;
1065                 uint64_t dfa:1;
1066                 uint64_t fpa:1;
1067                 uint64_t key:1;
1068                 uint64_t npi:1;
1069                 uint64_t gmx1:1;
1070                 uint64_t gmx0:1;
1071                 uint64_t mio:1;
1072         } cn30xx;
1073         struct cvmx_npi_rsl_int_blocks_cn38xx {
1074                 uint64_t reserved_32_63:32;
1075                 uint64_t rint_31:1;
1076                 uint64_t iob:1;
1077                 uint64_t rint_29:1;
1078                 uint64_t rint_28:1;
1079                 uint64_t rint_27:1;
1080                 uint64_t rint_26:1;
1081                 uint64_t rint_25:1;
1082                 uint64_t rint_24:1;
1083                 uint64_t asx1:1;
1084                 uint64_t asx0:1;
1085                 uint64_t rint_21:1;
1086                 uint64_t pip:1;
1087                 uint64_t spx1:1;
1088                 uint64_t spx0:1;
1089                 uint64_t lmc:1;
1090                 uint64_t l2c:1;
1091                 uint64_t rint_15:1;
1092                 uint64_t rint_14:1;
1093                 uint64_t rint_13:1;
1094                 uint64_t pow:1;
1095                 uint64_t tim:1;
1096                 uint64_t pko:1;
1097                 uint64_t ipd:1;
1098                 uint64_t rint_8:1;
1099                 uint64_t zip:1;
1100                 uint64_t dfa:1;
1101                 uint64_t fpa:1;
1102                 uint64_t key:1;
1103                 uint64_t npi:1;
1104                 uint64_t gmx1:1;
1105                 uint64_t gmx0:1;
1106                 uint64_t mio:1;
1107         } cn38xx;
1108         struct cvmx_npi_rsl_int_blocks_cn50xx {
1109                 uint64_t reserved_31_63:33;
1110                 uint64_t iob:1;
1111                 uint64_t lmc1:1;
1112                 uint64_t agl:1;
1113                 uint64_t reserved_24_27:4;
1114                 uint64_t asx1:1;
1115                 uint64_t asx0:1;
1116                 uint64_t reserved_21_21:1;
1117                 uint64_t pip:1;
1118                 uint64_t spx1:1;
1119                 uint64_t spx0:1;
1120                 uint64_t lmc:1;
1121                 uint64_t l2c:1;
1122                 uint64_t reserved_15_15:1;
1123                 uint64_t rad:1;
1124                 uint64_t usb:1;
1125                 uint64_t pow:1;
1126                 uint64_t tim:1;
1127                 uint64_t pko:1;
1128                 uint64_t ipd:1;
1129                 uint64_t reserved_8_8:1;
1130                 uint64_t zip:1;
1131                 uint64_t dfa:1;
1132                 uint64_t fpa:1;
1133                 uint64_t key:1;
1134                 uint64_t npi:1;
1135                 uint64_t gmx1:1;
1136                 uint64_t gmx0:1;
1137                 uint64_t mio:1;
1138         } cn50xx;
1139 };
1140
1141 union cvmx_pko_command_word0 {
1142         uint64_t u64;
1143         struct {
1144                 uint64_t total_bytes:16;
1145                 uint64_t segs:6;
1146                 uint64_t dontfree:1;
1147                 uint64_t ignore_i:1;
1148                 uint64_t ipoffp1:7;
1149                 uint64_t gather:1;
1150                 uint64_t rsp:1;
1151                 uint64_t wqp:1;
1152                 uint64_t n2:1;
1153                 uint64_t le:1;
1154                 uint64_t reg0:11;
1155                 uint64_t subone0:1;
1156                 uint64_t reg1:11;
1157                 uint64_t subone1:1;
1158                 uint64_t size0:2;
1159                 uint64_t size1:2;
1160         } s;
1161 };
1162
1163 union cvmx_ciu_timx {
1164         uint64_t u64;
1165         struct cvmx_ciu_timx_s {
1166                 uint64_t reserved_37_63:27;
1167                 uint64_t one_shot:1;
1168                 uint64_t len:36;
1169         } s;
1170 };
1171
1172 union cvmx_gmxx_rxx_rx_inbnd {
1173         uint64_t u64;
1174         struct cvmx_gmxx_rxx_rx_inbnd_s {
1175                 uint64_t status:1;
1176                 uint64_t speed:2;
1177                 uint64_t duplex:1;
1178                 uint64_t reserved_4_63:60;
1179         } s;
1180 };
1181
1182 static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,
1183                                                int32_t value)
1184 {
1185         return value;
1186 }
1187
1188 static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,
1189                                          int32_t value)
1190 { }
1191
1192 static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,
1193                                            int32_t value)
1194 { }
1195
1196 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1197 {
1198         return 0;
1199 }
1200
1201 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1202 { }
1203
1204 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
1205 {
1206         return 0;
1207 }
1208
1209 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1210 {
1211         return (void *)(uintptr_t)(physical_address);
1212 }
1213
1214 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
1215 {
1216         return (unsigned long)ptr;
1217 }
1218
1219 static inline int cvmx_helper_get_interface_num(int ipd_port)
1220 {
1221         return ipd_port;
1222 }
1223
1224 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1225 {
1226         return ipd_port;
1227 }
1228
1229 static inline void cvmx_fpa_enable(void)
1230 { }
1231
1232 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1233 {
1234         return 0;
1235 }
1236
1237 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1238 { }
1239
1240 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1241 {
1242         return 0;
1243 }
1244
1245 static inline void *cvmx_fpa_alloc(uint64_t pool)
1246 {
1247         return NULL;
1248 }
1249
1250 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1251                                  uint64_t num_cache_lines)
1252 { }
1253
1254 static inline int octeon_is_simulation(void)
1255 {
1256         return 1;
1257 }
1258
1259 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1260                                             cvmx_pip_port_status_t *status)
1261 { }
1262
1263 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1264                                             cvmx_pko_port_status_t *status)
1265 { }
1266
1267 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1268                                                                    interface)
1269 {
1270         return 0;
1271 }
1272
1273 static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
1274 {
1275         union cvmx_helper_link_info ret = { .u64 = 0 };
1276
1277         return ret;
1278 }
1279
1280 static inline int cvmx_helper_link_set(int ipd_port,
1281                                        union cvmx_helper_link_info link_info)
1282 {
1283         return 0;
1284 }
1285
1286 static inline int cvmx_helper_initialize_packet_io_global(void)
1287 {
1288         return 0;
1289 }
1290
1291 static inline int cvmx_helper_get_number_of_interfaces(void)
1292 {
1293         return 2;
1294 }
1295
1296 static inline int cvmx_helper_ports_on_interface(int interface)
1297 {
1298         return 1;
1299 }
1300
1301 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1302 {
1303         return 0;
1304 }
1305
1306 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1307 {
1308         return 0;
1309 }
1310
1311 static inline void cvmx_ipd_disable(void)
1312 { }
1313
1314 static inline void cvmx_ipd_free_ptr(void)
1315 { }
1316
1317 static inline void cvmx_pko_disable(void)
1318 { }
1319
1320 static inline void cvmx_pko_shutdown(void)
1321 { }
1322
1323 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1324 {
1325         return port;
1326 }
1327
1328 static inline int cvmx_pko_get_base_queue(int port)
1329 {
1330         return port;
1331 }
1332
1333 static inline int cvmx_pko_get_num_queues(int port)
1334 {
1335         return port;
1336 }
1337
1338 static inline unsigned int cvmx_get_core_num(void)
1339 {
1340         return 0;
1341 }
1342
1343 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1344                                                        cvmx_pow_wait_t wait)
1345 { }
1346
1347 static inline void cvmx_pow_work_request_async(int scr_addr,
1348                                                cvmx_pow_wait_t wait)
1349 { }
1350
1351 static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
1352 {
1353         struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr;
1354
1355         return wqe;
1356 }
1357
1358 static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1359 {
1360         return (void *)(unsigned long)wait;
1361 }
1362
1363 static inline int cvmx_spi_restart_interface(int interface,
1364                                         cvmx_spi_mode_t mode, int timeout)
1365 {
1366         return 0;
1367 }
1368
1369 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1370                                                   enum cvmx_fau_reg_32 reg,
1371                                                   int32_t value)
1372 { }
1373
1374 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
1375         int interface,
1376         int port)
1377 {
1378         union cvmx_gmxx_rxx_rx_inbnd r;
1379
1380         r.u64 = 0;
1381         return r;
1382 }
1383
1384 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1385                                                 cvmx_pko_lock_t use_locking)
1386 { }
1387
1388 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1389                 uint64_t queue, union cvmx_pko_command_word0 pko_command,
1390                 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1391 {
1392         return 0;
1393 }
1394
1395 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
1396 { }
1397
1398 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
1399 { }
1400
1401 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
1402 {
1403         return 0;
1404 }
1405
1406 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
1407 { }
1408
1409 static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
1410                                         enum cvmx_pow_tag_type tag_type,
1411                                         uint64_t qos, uint64_t grp)
1412 { }
1413
1414 #define CVMX_ASXX_RX_CLK_SETX(a, b)     ((a) + (b))
1415 #define CVMX_ASXX_TX_CLK_SETX(a, b)     ((a) + (b))
1416 #define CVMX_CIU_TIMX(a)                (a)
1417 #define CVMX_GMXX_RXX_ADR_CAM0(a, b)    ((a) + (b))
1418 #define CVMX_GMXX_RXX_ADR_CAM1(a, b)    ((a) + (b))
1419 #define CVMX_GMXX_RXX_ADR_CAM2(a, b)    ((a) + (b))
1420 #define CVMX_GMXX_RXX_ADR_CAM3(a, b)    ((a) + (b))
1421 #define CVMX_GMXX_RXX_ADR_CAM4(a, b)    ((a) + (b))
1422 #define CVMX_GMXX_RXX_ADR_CAM5(a, b)    ((a) + (b))
1423 #define CVMX_GMXX_RXX_FRM_CTL(a, b)     ((a) + (b))
1424 #define CVMX_GMXX_RXX_INT_REG(a, b)     ((a) + (b))
1425 #define CVMX_GMXX_SMACX(a, b)           ((a) + (b))
1426 #define CVMX_PIP_PRT_TAGX(a)            (a)
1427 #define CVMX_POW_PP_GRP_MSKX(a)         (a)
1428 #define CVMX_POW_WQ_INT_THRX(a)         (a)
1429 #define CVMX_SPXX_INT_MSK(a)            (a)
1430 #define CVMX_SPXX_INT_REG(a)            (a)
1431 #define CVMX_SSO_PPX_GRP_MSK(a)         (a)
1432 #define CVMX_SSO_WQ_INT_THRX(a)         (a)
1433 #define CVMX_STXX_INT_MSK(a)            (a)
1434 #define CVMX_STXX_INT_REG(a)            (a)