drivers/staging/mt7621-dma/mtk-hsdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
   4  *  MTK HSDMA support
   5  */
   6
   7 #include <linux/dmaengine.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/err.h>
  10 #include <linux/init.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/irq.h>
  17 #include <linux/of_dma.h>
  18 #include <linux/reset.h>
  19 #include <linux/of_device.h>
  20
  21 #include "virt-dma.h"
  22
  23 #define HSDMA_BASE_OFFSET               0x800
  24
  25 #define HSDMA_REG_TX_BASE               0x00
  26 #define HSDMA_REG_TX_CNT                0x04
  27 #define HSDMA_REG_TX_CTX                0x08
  28 #define HSDMA_REG_TX_DTX                0x0c
  29 #define HSDMA_REG_RX_BASE               0x100
  30 #define HSDMA_REG_RX_CNT                0x104
  31 #define HSDMA_REG_RX_CRX                0x108
  32 #define HSDMA_REG_RX_DRX                0x10c
  33 #define HSDMA_REG_INFO                  0x200
  34 #define HSDMA_REG_GLO_CFG               0x204
  35 #define HSDMA_REG_RST_CFG               0x208
  36 #define HSDMA_REG_DELAY_INT             0x20c
  37 #define HSDMA_REG_FREEQ_THRES           0x210
  38 #define HSDMA_REG_INT_STATUS            0x220
  39 #define HSDMA_REG_INT_MASK              0x228
  40 #define HSDMA_REG_SCH_Q01               0x280
  41 #define HSDMA_REG_SCH_Q23               0x284
  42
  43 #define HSDMA_DESCS_MAX                 0xfff
  44 #define HSDMA_DESCS_NUM                 8
  45 #define HSDMA_DESCS_MASK                (HSDMA_DESCS_NUM - 1)
  46 #define HSDMA_NEXT_DESC(x)              (((x) + 1) & HSDMA_DESCS_MASK)
  47
  48 /* HSDMA_REG_INFO */
  49 #define HSDMA_INFO_INDEX_MASK           0xf
  50 #define HSDMA_INFO_INDEX_SHIFT          24
  51 #define HSDMA_INFO_BASE_MASK            0xff
  52 #define HSDMA_INFO_BASE_SHIFT           16
  53 #define HSDMA_INFO_RX_MASK              0xff
  54 #define HSDMA_INFO_RX_SHIFT             8
  55 #define HSDMA_INFO_TX_MASK              0xff
  56 #define HSDMA_INFO_TX_SHIFT             0
  57
  58 /* HSDMA_REG_GLO_CFG */
  59 #define HSDMA_GLO_TX_2B_OFFSET          BIT(31)
  60 #define HSDMA_GLO_CLK_GATE              BIT(30)
  61 #define HSDMA_GLO_BYTE_SWAP             BIT(29)
  62 #define HSDMA_GLO_MULTI_DMA             BIT(10)
  63 #define HSDMA_GLO_TWO_BUF               BIT(9)
  64 #define HSDMA_GLO_32B_DESC              BIT(8)
  65 #define HSDMA_GLO_BIG_ENDIAN            BIT(7)
  66 #define HSDMA_GLO_TX_DONE               BIT(6)
  67 #define HSDMA_GLO_BT_MASK               0x3
  68 #define HSDMA_GLO_BT_SHIFT              4
  69 #define HSDMA_GLO_RX_BUSY               BIT(3)
  70 #define HSDMA_GLO_RX_DMA                BIT(2)
  71 #define HSDMA_GLO_TX_BUSY               BIT(1)
  72 #define HSDMA_GLO_TX_DMA                BIT(0)
  73
  74 #define HSDMA_BT_SIZE_16BYTES           (0 << HSDMA_GLO_BT_SHIFT)
  75 #define HSDMA_BT_SIZE_32BYTES           (1 << HSDMA_GLO_BT_SHIFT)
  76 #define HSDMA_BT_SIZE_64BYTES           (2 << HSDMA_GLO_BT_SHIFT)
  77 #define HSDMA_BT_SIZE_128BYTES          (3 << HSDMA_GLO_BT_SHIFT)
  78
  79 #define HSDMA_GLO_DEFAULT               (HSDMA_GLO_MULTI_DMA | \
  80                 HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
  81
  82 /* HSDMA_REG_RST_CFG */
  83 #define HSDMA_RST_RX_SHIFT              16
  84 #define HSDMA_RST_TX_SHIFT              0
  85
  86 /* HSDMA_REG_DELAY_INT */
  87 #define HSDMA_DELAY_INT_EN              BIT(15)
  88 #define HSDMA_DELAY_PEND_OFFSET         8
  89 #define HSDMA_DELAY_TIME_OFFSET         0
  90 #define HSDMA_DELAY_TX_OFFSET           16
  91 #define HSDMA_DELAY_RX_OFFSET           0
  92
  93 #define HSDMA_DELAY_INIT(x)             (HSDMA_DELAY_INT_EN | \
  94                 ((x) << HSDMA_DELAY_PEND_OFFSET))
  95 #define HSDMA_DELAY(x)                  ((HSDMA_DELAY_INIT(x) << \
  96                 HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
  97
  98 /* HSDMA_REG_INT_STATUS */
  99 #define HSDMA_INT_DELAY_RX_COH          BIT(31)
 100 #define HSDMA_INT_DELAY_RX_INT          BIT(30)
 101 #define HSDMA_INT_DELAY_TX_COH          BIT(29)
 102 #define HSDMA_INT_DELAY_TX_INT          BIT(28)
 103 #define HSDMA_INT_RX_MASK               0x3
 104 #define HSDMA_INT_RX_SHIFT              16
 105 #define HSDMA_INT_RX_Q0                 BIT(16)
 106 #define HSDMA_INT_TX_MASK               0xf
 107 #define HSDMA_INT_TX_SHIFT              0
 108 #define HSDMA_INT_TX_Q0                 BIT(0)
 109
 110 /* tx/rx dma desc flags */
 111 #define HSDMA_PLEN_MASK                 0x3fff
 112 #define HSDMA_DESC_DONE                 BIT(31)
 113 #define HSDMA_DESC_LS0                  BIT(30)
 114 #define HSDMA_DESC_PLEN0(_x)            (((_x) & HSDMA_PLEN_MASK) << 16)
 115 #define HSDMA_DESC_TAG                  BIT(15)
 116 #define HSDMA_DESC_LS1                  BIT(14)
 117 #define HSDMA_DESC_PLEN1(_x)            ((_x) & HSDMA_PLEN_MASK)
 118
 119 /* align 4 bytes */
 120 #define HSDMA_ALIGN_SIZE                3
 121 /* align size 128bytes */
 122 #define HSDMA_MAX_PLEN                  0x3f80
 123
 124 struct hsdma_desc {
 125         u32 addr0;
 126         u32 flags;
 127         u32 addr1;
 128         u32 unused;
 129 };
 130
 131 struct mtk_hsdma_sg {
 132         dma_addr_t src_addr;
 133         dma_addr_t dst_addr;
 134         u32 len;
 135 };
 136
 137 struct mtk_hsdma_desc {
 138         struct virt_dma_desc vdesc;
 139         unsigned int num_sgs;
 140         struct mtk_hsdma_sg sg[1];
 141 };
 142
 143 struct mtk_hsdma_chan {
 144         struct virt_dma_chan vchan;
 145         unsigned int id;
 146         dma_addr_t desc_addr;
 147         int tx_idx;
 148         int rx_idx;
 149         struct hsdma_desc *tx_ring;
 150         struct hsdma_desc *rx_ring;
 151         struct mtk_hsdma_desc *desc;
 152         unsigned int next_sg;
 153 };
 154
 155 struct mtk_hsdam_engine {
 156         struct dma_device ddev;
 157         struct device_dma_parameters dma_parms;
 158         void __iomem *base;
 159         struct tasklet_struct task;
 160         volatile unsigned long chan_issued;
 161
 162         struct mtk_hsdma_chan chan[1];
 163 };
 164
 165 static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(
 166                 struct mtk_hsdma_chan *chan)
 167 {
 168         return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
 169                         ddev);
 170 }
 171
 172 static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
 173 {
 174         return container_of(c, struct mtk_hsdma_chan, vchan.chan);
 175 }
 176
 177 static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(
 178                 struct virt_dma_desc *vdesc)
 179 {
 180         return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
 181 }
 182
 183 static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
 184 {
 185         return readl(hsdma->base + reg);
 186 }
 187
 188 static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
 189                                    unsigned int reg, u32 val)
 190 {
 191         writel(val, hsdma->base + reg);
 192 }
 193
 194 static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
 195                                  struct mtk_hsdma_chan *chan)
 196 {
 197         chan->tx_idx = 0;
 198         chan->rx_idx = HSDMA_DESCS_NUM - 1;
 199
 200         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 201         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 202
 203         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 204                         0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
 205         mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
 206                         0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
 207 }
 208
 209 static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
 210 {
 211         dev_dbg(hsdma->ddev.dev, "tbase %08x, tcnt %08x, "
 212                         "tctx %08x, tdtx: %08x, rbase %08x, "
 213                         "rcnt %08x, rctx %08x, rdtx %08x\n",
 214                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
 215                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
 216                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
 217                         mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
 218                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
 219                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
 220                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
 221                         mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
 222
 223         dev_dbg(hsdma->ddev.dev, "info %08x, glo %08x, delay %08x, "
 224                         "intr_stat %08x, intr_mask %08x\n",
 225                         mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
 226                         mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
 227                         mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
 228                         mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
 229                         mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
 230 }
 231
 232 static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
 233                             struct mtk_hsdma_chan *chan)
 234 {
 235         struct hsdma_desc *tx_desc;
 236         struct hsdma_desc *rx_desc;
 237         int i;
 238
 239         dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
 240                 chan->tx_idx, chan->rx_idx);
 241
 242         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 243                 tx_desc = &chan->tx_ring[i];
 244                 rx_desc = &chan->rx_ring[i];
 245
 246                 dev_dbg(hsdma->ddev.dev, "%d tx addr0: %08x, flags %08x, "
 247                                 "tx addr1: %08x, rx addr0 %08x, flags %08x\n",
 248                                 i, tx_desc->addr0, tx_desc->flags,
 249                                 tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
 250         }
 251 }
 252
 253 static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
 254                             struct mtk_hsdma_chan *chan)
 255 {
 256         int i;
 257
 258         /* disable dma */
 259         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 260
 261         /* disable intr */
 262         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 263
 264         /* init desc value */
 265         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 266                 chan->tx_ring[i].addr0 = 0;
 267                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 268         }
 269         for (i = 0; i < HSDMA_DESCS_NUM; i++) {
 270                 chan->rx_ring[i].addr0 = 0;
 271                 chan->rx_ring[i].flags = 0;
 272         }
 273
 274         /* reset */
 275         mtk_hsdma_reset_chan(hsdma, chan);
 276
 277         /* enable intr */
 278         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 279
 280         /* enable dma */
 281         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 282 }
 283
 284 static int mtk_hsdma_terminate_all(struct dma_chan *c)
 285 {
 286         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 287         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 288         unsigned long timeout;
 289         LIST_HEAD(head);
 290
 291         spin_lock_bh(&chan->vchan.lock);
 292         chan->desc = NULL;
 293         clear_bit(chan->id, &hsdma->chan_issued);
 294         vchan_get_all_descriptors(&chan->vchan, &head);
 295         spin_unlock_bh(&chan->vchan.lock);
 296
 297         vchan_dma_desc_free_list(&chan->vchan, &head);
 298
 299         /* wait dma transfer complete */
 300         timeout = jiffies + msecs_to_jiffies(2000);
 301         while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
 302                         (HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
 303                 if (time_after_eq(jiffies, timeout)) {
 304                         hsdma_dump_desc(hsdma, chan);
 305                         mtk_hsdma_reset(hsdma, chan);
 306                         dev_err(hsdma->ddev.dev, "timeout, reset it\n");
 307                         break;
 308                 }
 309                 cpu_relax();
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
 316                                     struct mtk_hsdma_chan *chan)
 317 {
 318         dma_addr_t src, dst;
 319         size_t len, tlen;
 320         struct hsdma_desc *tx_desc, *rx_desc;
 321         struct mtk_hsdma_sg *sg;
 322         unsigned int i;
 323         int rx_idx;
 324
 325         sg = &chan->desc->sg[0];
 326         len = sg->len;
 327         chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
 328
 329         /* tx desc */
 330         src = sg->src_addr;
 331         for (i = 0; i < chan->desc->num_sgs; i++) {
 332                 tx_desc = &chan->tx_ring[chan->tx_idx];
 333
 334                 if (len > HSDMA_MAX_PLEN)
 335                         tlen = HSDMA_MAX_PLEN;
 336                 else
 337                         tlen = len;
 338
 339                 if (i & 0x1) {
 340                         tx_desc->addr1 = src;
 341                         tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
 342                 } else {
 343                         tx_desc->addr0 = src;
 344                         tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 345
 346                         /* update index */
 347                         chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
 348                 }
 349
 350                 src += tlen;
 351                 len -= tlen;
 352         }
 353         if (i & 0x1)
 354                 tx_desc->flags |= HSDMA_DESC_LS0;
 355         else
 356                 tx_desc->flags |= HSDMA_DESC_LS1;
 357
 358         /* rx desc */
 359         rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 360         len = sg->len;
 361         dst = sg->dst_addr;
 362         for (i = 0; i < chan->desc->num_sgs; i++) {
 363                 rx_desc = &chan->rx_ring[rx_idx];
 364                 if (len > HSDMA_MAX_PLEN)
 365                         tlen = HSDMA_MAX_PLEN;
 366                 else
 367                         tlen = len;
 368
 369                 rx_desc->addr0 = dst;
 370                 rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
 371
 372                 dst += tlen;
 373                 len -= tlen;
 374
 375                 /* update index */
 376                 rx_idx = HSDMA_NEXT_DESC(rx_idx);
 377         }
 378
 379         /* make sure desc and index all up to date */
 380         wmb();
 381         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
 382
 383         return 0;
 384 }
 385
 386 static int gdma_next_desc(struct mtk_hsdma_chan *chan)
 387 {
 388         struct virt_dma_desc *vdesc;
 389
 390         vdesc = vchan_next_desc(&chan->vchan);
 391         if (!vdesc) {
 392                 chan->desc = NULL;
 393                 return 0;
 394         }
 395         chan->desc = to_mtk_hsdma_desc(vdesc);
 396         chan->next_sg = 0;
 397
 398         return 1;
 399 }
 400
 401 static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
 402                                 struct mtk_hsdma_chan *chan)
 403 {
 404         struct mtk_hsdma_desc *desc;
 405         int chan_issued;
 406
 407         chan_issued = 0;
 408         spin_lock_bh(&chan->vchan.lock);
 409         desc = chan->desc;
 410         if (likely(desc)) {
 411                 if (chan->next_sg == desc->num_sgs) {
 412                         list_del(&desc->vdesc.node);
 413                         vchan_cookie_complete(&desc->vdesc);
 414                         chan_issued = gdma_next_desc(chan);
 415                 }
 416         } else {
 417                 dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
 418         }
 419
 420         if (chan_issued)
 421                 set_bit(chan->id, &hsdma->chan_issued);
 422         spin_unlock_bh(&chan->vchan.lock);
 423 }
 424
 425 static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
 426 {
 427         struct mtk_hsdam_engine *hsdma = devid;
 428         u32 status;
 429
 430         status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
 431         if (unlikely(!status))
 432                 return IRQ_NONE;
 433
 434         if (likely(status & HSDMA_INT_RX_Q0))
 435                 tasklet_schedule(&hsdma->task);
 436         else
 437                 dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
 438         /* clean intr bits */
 439         mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
 440
 441         return IRQ_HANDLED;
 442 }
 443
 444 static void mtk_hsdma_issue_pending(struct dma_chan *c)
 445 {
 446         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 447         struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
 448
 449         spin_lock_bh(&chan->vchan.lock);
 450         if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
 451                 if (gdma_next_desc(chan)) {
 452                         set_bit(chan->id, &hsdma->chan_issued);
 453                         tasklet_schedule(&hsdma->task);
 454                 } else {
 455                         dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
 456                 }
 457         }
 458         spin_unlock_bh(&chan->vchan.lock);
 459 }
 460
 461 static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
 462                 struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
 463                 size_t len, unsigned long flags)
 464 {
 465         struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
 466         struct mtk_hsdma_desc *desc;
 467
 468         if (len <= 0)
 469                 return NULL;
 470
 471         desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
 472         if (!desc) {
 473                 dev_err(c->device->dev, "alloc memcpy decs error\n");
 474                 return NULL;
 475         }
 476
 477         desc->sg[0].src_addr = src;
 478         desc->sg[0].dst_addr = dest;
 479         desc->sg[0].len = len;
 480
 481         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 482 }
 483
 484 static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
 485                                            dma_cookie_t cookie,
 486                                            struct dma_tx_state *state)
 487 {
 488         return dma_cookie_status(c, cookie, state);
 489 }
 490
 491 static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
 492 {
 493         vchan_free_chan_resources(to_virt_chan(c));
 494 }
 495
 496 static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
 497 {
 498         kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
 499 }
 500
 501 static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
 502 {
 503         struct mtk_hsdma_chan *chan;
 504
 505         if (test_and_clear_bit(0, &hsdma->chan_issued)) {
 506                 chan = &hsdma->chan[0];
 507                 if (chan->desc)
 508                         mtk_hsdma_start_transfer(hsdma, chan);
 509                 else
 510                         dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
 511         }
 512 }
 513
 514 static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
 515 {
 516         struct mtk_hsdma_chan *chan;
 517         int next_idx, drx_idx, cnt;
 518
 519         chan = &hsdma->chan[0];
 520         next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
 521         drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
 522
 523         cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
 524         if (!cnt)
 525                 return;
 526
 527         chan->next_sg += cnt;
 528         chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
 529
 530         /* update rx crx */
 531         wmb();
 532         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
 533
 534         mtk_hsdma_chan_done(hsdma, chan);
 535 }
 536
 537 static void mtk_hsdma_tasklet(unsigned long arg)
 538 {
 539         struct mtk_hsdam_engine *hsdma = (struct mtk_hsdam_engine *)arg;
 540
 541         mtk_hsdma_rx(hsdma);
 542         mtk_hsdma_tx(hsdma);
 543 }
 544
 545 static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
 546                                 struct mtk_hsdma_chan *chan)
 547 {
 548         int i;
 549
 550         chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
 551                                            2 * HSDMA_DESCS_NUM *
 552                                            sizeof(*chan->tx_ring),
 553                         &chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
 554         if (!chan->tx_ring)
 555                 goto no_mem;
 556
 557         chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
 558
 559         /* init tx ring value */
 560         for (i = 0; i < HSDMA_DESCS_NUM; i++)
 561                 chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
 562
 563         return 0;
 564 no_mem:
 565         return -ENOMEM;
 566 }
 567
 568 static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
 569                                 struct mtk_hsdma_chan *chan)
 570 {
 571         if (chan->tx_ring) {
 572                 dma_free_coherent(hsdma->ddev.dev,
 573                                   2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
 574                                   chan->tx_ring, chan->desc_addr);
 575                 chan->tx_ring = NULL;
 576                 chan->rx_ring = NULL;
 577         }
 578 }
 579
 580 static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
 581 {
 582         struct mtk_hsdma_chan *chan;
 583         int ret;
 584         u32 reg;
 585
 586         /* init desc */
 587         chan = &hsdma->chan[0];
 588         ret = mtk_hsdam_alloc_desc(hsdma, chan);
 589         if (ret)
 590                 return ret;
 591
 592         /* tx */
 593         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
 594         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
 595         /* rx */
 596         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
 597                         (sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
 598         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
 599         /* reset */
 600         mtk_hsdma_reset_chan(hsdma, chan);
 601
 602         /* enable rx intr */
 603         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
 604
 605         /* enable dma */
 606         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
 607
 608         /* hardware info */
 609         reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
 610         dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
 611                  (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
 612                  (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
 613
 614         hsdma_dump_reg(hsdma);
 615
 616         return ret;
 617 }
 618
 619 static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
 620 {
 621         struct mtk_hsdma_chan *chan;
 622
 623         /* disable dma */
 624         mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
 625
 626         /* disable intr */
 627         mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
 628
 629         /* free desc */
 630         chan = &hsdma->chan[0];
 631         mtk_hsdam_free_desc(hsdma, chan);
 632
 633         /* tx */
 634         mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
 635         mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
 636         /* rx */
 637         mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
 638         mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
 639         /* reset */
 640         mtk_hsdma_reset_chan(hsdma, chan);
 641 }
 642
 643 static const struct of_device_id mtk_hsdma_of_match[] = {
 644         { .compatible = "mediatek,mt7621-hsdma" },
 645         { },
 646 };
 647
 648 static int mtk_hsdma_probe(struct platform_device *pdev)
 649 {
 650         const struct of_device_id *match;
 651         struct mtk_hsdma_chan *chan;
 652         struct mtk_hsdam_engine *hsdma;
 653         struct dma_device *dd;
 654         int ret;
 655         int irq;
 656         void __iomem *base;
 657
 658         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 659         if (ret)
 660                 return ret;
 661
 662         match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
 663         if (!match)
 664                 return -EINVAL;
 665
 666         hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
 667         if (!hsdma)
 668                 return -EINVAL;
 669
 670         base = devm_platform_ioremap_resource(pdev, 0);
 671         if (IS_ERR(base))
 672                 return PTR_ERR(base);
 673         hsdma->base = base + HSDMA_BASE_OFFSET;
 674         tasklet_init(&hsdma->task, mtk_hsdma_tasklet, (unsigned long)hsdma);
 675
 676         irq = platform_get_irq(pdev, 0);
 677         if (irq < 0)
 678                 return -EINVAL;
 679         ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
 680                                0, dev_name(&pdev->dev), hsdma);
 681         if (ret) {
 682                 dev_err(&pdev->dev, "failed to request irq\n");
 683                 return ret;
 684         }
 685
 686         device_reset(&pdev->dev);
 687
 688         dd = &hsdma->ddev;
 689         dma_cap_set(DMA_MEMCPY, dd->cap_mask);
 690         dd->copy_align = HSDMA_ALIGN_SIZE;
 691         dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
 692         dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
 693         dd->device_terminate_all = mtk_hsdma_terminate_all;
 694         dd->device_tx_status = mtk_hsdma_tx_status;
 695         dd->device_issue_pending = mtk_hsdma_issue_pending;
 696         dd->dev = &pdev->dev;
 697         dd->dev->dma_parms = &hsdma->dma_parms;
 698         dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
 699         INIT_LIST_HEAD(&dd->channels);
 700
 701         chan = &hsdma->chan[0];
 702         chan->id = 0;
 703         chan->vchan.desc_free = mtk_hsdma_desc_free;
 704         vchan_init(&chan->vchan, dd);
 705
 706         /* init hardware */
 707         ret = mtk_hsdma_init(hsdma);
 708         if (ret) {
 709                 dev_err(&pdev->dev, "failed to alloc ring descs\n");
 710                 return ret;
 711         }
 712
 713         ret = dma_async_device_register(dd);
 714         if (ret) {
 715                 dev_err(&pdev->dev, "failed to register dma device\n");
 716                 return ret;
 717         }
 718
 719         ret = of_dma_controller_register(pdev->dev.of_node,
 720                                          of_dma_xlate_by_chan_id, hsdma);
 721         if (ret) {
 722                 dev_err(&pdev->dev, "failed to register of dma controller\n");
 723                 goto err_unregister;
 724         }
 725
 726         platform_set_drvdata(pdev, hsdma);
 727
 728         return 0;
 729
 730 err_unregister:
 731         dma_async_device_unregister(dd);
 732         return ret;
 733 }
 734
 735 static int mtk_hsdma_remove(struct platform_device *pdev)
 736 {
 737         struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
 738
 739         mtk_hsdma_uninit(hsdma);
 740
 741         of_dma_controller_free(pdev->dev.of_node);
 742         dma_async_device_unregister(&hsdma->ddev);
 743
 744         return 0;
 745 }
 746
 747 static struct platform_driver mtk_hsdma_driver = {
 748         .probe = mtk_hsdma_probe,
 749         .remove = mtk_hsdma_remove,
 750         .driver = {
 751                 .name = "hsdma-mt7621",
 752                 .of_match_table = mtk_hsdma_of_match,
 753         },
 754 };
 755 module_platform_driver(mtk_hsdma_driver);
 756
 757 MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
 758 MODULE_DESCRIPTION("MTK HSDMA driver");
 759 MODULE_LICENSE("GPL v2");