2 * Copyright (c) 2003-2013 Broadcom Corporation
4 * Copyright (c) 2009-2010 Micron Technology, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/spi/spi.h>
24 #include "mt29f_spinand.h"
26 #define BUFSIZE (10 * 64 * 2048)
27 #define CACHE_BUF 2112
29 * OOB area specification layout: Total 32 available free bytes.
32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
34 struct nand_chip *chip = mtd_to_nand(mtd);
35 struct spinand_info *info = nand_get_controller_data(chip);
36 struct spinand_state *state = info->priv;
41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
42 static int enable_hw_ecc;
43 static int enable_read_hw_ecc;
45 static int spinand_ooblayout_64_ecc(struct mtd_info *mtd, int section,
46 struct mtd_oob_region *oobregion)
51 oobregion->offset = (section * 16) + 1;
52 oobregion->length = 6;
57 static int spinand_ooblayout_64_free(struct mtd_info *mtd, int section,
58 struct mtd_oob_region *oobregion)
63 oobregion->offset = (section * 16) + 8;
64 oobregion->length = 8;
69 static const struct mtd_ooblayout_ops spinand_oob_64_ops = {
70 .ecc = spinand_ooblayout_64_ecc,
71 .free = spinand_ooblayout_64_free,
76 * spinand_cmd - process a command to send to the SPI Nand
78 * Set up the command buffer to send to the SPI controller.
79 * The command buffer has to initialized to 0.
82 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
84 struct spi_message message;
85 struct spi_transfer x[4];
88 spi_message_init(&message);
89 memset(x, 0, sizeof(x));
92 x[0].tx_buf = &cmd->cmd;
93 spi_message_add_tail(&x[0], &message);
96 x[1].len = cmd->n_addr;
97 x[1].tx_buf = cmd->addr;
98 spi_message_add_tail(&x[1], &message);
102 x[2].len = cmd->n_dummy;
103 x[2].tx_buf = &dummy;
104 spi_message_add_tail(&x[2], &message);
108 x[3].len = cmd->n_tx;
109 x[3].tx_buf = cmd->tx_buf;
110 spi_message_add_tail(&x[3], &message);
114 x[3].len = cmd->n_rx;
115 x[3].rx_buf = cmd->rx_buf;
116 spi_message_add_tail(&x[3], &message);
119 return spi_sync(spi, &message);
123 * spinand_read_id - Read SPI Nand ID
125 * read two ID bytes from the SPI Nand device
127 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
131 struct spinand_cmd cmd = {0};
133 cmd.cmd = CMD_READ_ID;
135 cmd.rx_buf = &nand_id[0];
137 retval = spinand_cmd(spi_nand, &cmd);
139 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
148 * spinand_read_status - send command 0xf to the SPI Nand status register
150 * After read, write, or erase, the Nand device is expected to set the
152 * This function is to allow reading the status of the command: read,
154 * Once the status turns to be ready, the other status bits also are
157 static int spinand_read_status(struct spi_device *spi_nand, u8 *status)
159 struct spinand_cmd cmd = {0};
162 cmd.cmd = CMD_READ_REG;
164 cmd.addr[0] = REG_STATUS;
168 ret = spinand_cmd(spi_nand, &cmd);
170 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
175 #define MAX_WAIT_JIFFIES (40 * HZ)
176 static int wait_till_ready(struct spi_device *spi_nand)
178 unsigned long deadline;
182 deadline = jiffies + MAX_WAIT_JIFFIES;
184 retval = spinand_read_status(spi_nand, &stat);
191 } while (!time_after_eq(jiffies, deadline));
193 if ((stat & 0x1) == 0)
200 * spinand_get_otp - send command 0xf to read the SPI Nand OTP register
202 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
203 * Enable chip internal ECC, set the bit to 1
204 * Disable chip internal ECC, clear the bit to 0
206 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
208 struct spinand_cmd cmd = {0};
211 cmd.cmd = CMD_READ_REG;
213 cmd.addr[0] = REG_OTP;
217 retval = spinand_cmd(spi_nand, &cmd);
219 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
224 * spinand_set_otp - send command 0x1f to write the SPI Nand OTP register
226 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
227 * Enable chip internal ECC, set the bit to 1
228 * Disable chip internal ECC, clear the bit to 0
230 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
233 struct spinand_cmd cmd = {0};
235 cmd.cmd = CMD_WRITE_REG;
237 cmd.addr[0] = REG_OTP;
241 retval = spinand_cmd(spi_nand, &cmd);
243 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
248 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
250 * spinand_enable_ecc - send command 0x1f to write the SPI Nand OTP register
252 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
253 * Enable chip internal ECC, set the bit to 1
254 * Disable chip internal ECC, clear the bit to 0
256 static int spinand_enable_ecc(struct spi_device *spi_nand)
261 retval = spinand_get_otp(spi_nand, &otp);
265 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
268 retval = spinand_set_otp(spi_nand, &otp);
271 return spinand_get_otp(spi_nand, &otp);
275 static int spinand_disable_ecc(struct spi_device *spi_nand)
280 retval = spinand_get_otp(spi_nand, &otp);
284 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
285 otp &= ~OTP_ECC_MASK;
286 retval = spinand_set_otp(spi_nand, &otp);
289 return spinand_get_otp(spi_nand, &otp);
295 * spinand_write_enable - send command 0x06 to enable write or erase the
298 * Before write and erase the Nand cells, the write enable has to be set.
299 * After the write or erase, the write enable bit is automatically
300 * cleared (status register bit 2)
301 * Set the bit 2 of the status register has the same effect
303 static int spinand_write_enable(struct spi_device *spi_nand)
305 struct spinand_cmd cmd = {0};
307 cmd.cmd = CMD_WR_ENABLE;
308 return spinand_cmd(spi_nand, &cmd);
311 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
313 struct spinand_cmd cmd = {0};
319 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
320 cmd.addr[2] = (u8)(row & 0x00ff);
322 return spinand_cmd(spi_nand, &cmd);
326 * spinand_read_from_cache - send command 0x03 to read out the data from the
327 * cache register (2112 bytes max)
329 * The read can specify 1 to 2112 bytes of data read at the corresponding
333 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
334 u16 byte_id, u16 len, u8 *rbuf)
336 struct spinand_cmd cmd = {0};
340 cmd.cmd = CMD_READ_RDM;
342 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
343 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
344 cmd.addr[1] = (u8)(column & 0x00ff);
345 cmd.addr[2] = (u8)(0xff);
350 return spinand_cmd(spi_nand, &cmd);
354 * spinand_read_page - read a page
355 * @page_id: the physical page number
356 * @offset: the location from 0 to 2111
357 * @len: number of bytes to read
358 * @rbuf: read buffer to hold @len bytes
361 * The read includes two commands to the Nand - 0x13 and 0x03 commands
362 * Poll to read status to wait for tRD time.
364 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
365 u16 offset, u16 len, u8 *rbuf)
370 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
371 if (enable_read_hw_ecc) {
372 if (spinand_enable_ecc(spi_nand) < 0)
373 dev_err(&spi_nand->dev, "enable HW ECC failed!");
376 ret = spinand_read_page_to_cache(spi_nand, page_id);
380 if (wait_till_ready(spi_nand))
381 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
384 ret = spinand_read_status(spi_nand, &status);
386 dev_err(&spi_nand->dev,
387 "err %d read status register\n", ret);
391 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
392 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
393 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
401 ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
403 dev_err(&spi_nand->dev, "read from cache failed!!\n");
407 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
408 if (enable_read_hw_ecc) {
409 ret = spinand_disable_ecc(spi_nand);
411 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
414 enable_read_hw_ecc = 0;
421 * spinand_program_data_to_cache - write a page to cache
422 * @byte_id: the location to write to the cache
423 * @len: number of bytes to write
424 * @wbuf: write buffer holding @len bytes
427 * The write command used here is 0x84--indicating that the cache is
429 * Since it is writing the data to cache, there is no tPROG time.
431 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
432 u16 page_id, u16 byte_id,
435 struct spinand_cmd cmd = {0};
439 cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
441 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
442 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
443 cmd.addr[1] = (u8)(column & 0x00ff);
447 return spinand_cmd(spi_nand, &cmd);
451 * spinand_program_execute - write a page from cache to the Nand array
452 * @page_id: the physical page location to write the page.
455 * The write command used here is 0x10--indicating the cache is writing to
457 * Need to wait for tPROG time to finish the transaction.
459 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
461 struct spinand_cmd cmd = {0};
465 cmd.cmd = CMD_PROG_PAGE_EXC;
467 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
468 cmd.addr[2] = (u8)(row & 0x00ff);
470 return spinand_cmd(spi_nand, &cmd);
474 * spinand_program_page - write a page
475 * @page_id: the physical page location to write the page.
476 * @offset: the location from the cache starting from 0 to 2111
477 * @len: the number of bytes to write
478 * @buf: the buffer holding @len bytes
481 * The commands used here are 0x06, 0x84, and 0x10--indicating that
482 * the write enable is first sent, the write cache command, and the
483 * write execute command.
484 * Poll to wait for the tPROG time to finish the transaction.
486 static int spinand_program_page(struct spi_device *spi_nand,
487 u16 page_id, u16 offset, u16 len, u8 *buf)
492 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
495 wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
499 enable_read_hw_ecc = 0;
500 spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
502 for (i = offset, j = 0; i < len; i++, j++)
506 retval = spinand_enable_ecc(spi_nand);
508 dev_err(&spi_nand->dev, "enable ecc failed!!\n");
515 retval = spinand_write_enable(spi_nand);
517 dev_err(&spi_nand->dev, "write enable failed!!\n");
520 if (wait_till_ready(spi_nand))
521 dev_err(&spi_nand->dev, "wait timedout!!!\n");
523 retval = spinand_program_data_to_cache(spi_nand, page_id,
527 retval = spinand_program_execute(spi_nand, page_id);
531 retval = spinand_read_status(spi_nand, &status);
533 dev_err(&spi_nand->dev,
534 "error %d reading status register\n", retval);
538 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
539 if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
540 dev_err(&spi_nand->dev,
541 "program error, page %d\n", page_id);
547 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
549 retval = spinand_disable_ecc(spi_nand);
551 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
562 * spinand_erase_block_erase - erase a page
563 * @block_id: the physical block location to erase.
566 * The command used here is 0xd8--indicating an erase command to erase
567 * one block--64 pages
568 * Need to wait for tERS.
570 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
572 struct spinand_cmd cmd = {0};
576 cmd.cmd = CMD_ERASE_BLK;
578 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
579 cmd.addr[2] = (u8)(row & 0x00ff);
581 return spinand_cmd(spi_nand, &cmd);
585 * spinand_erase_block - erase a page
586 * @block_id: the physical block location to erase.
589 * The commands used here are 0x06 and 0xd8--indicating an erase
590 * command to erase one block--64 pages
591 * It will first to enable the write enable bit (0x06 command),
592 * and then send the 0xd8 erase command
593 * Poll to wait for the tERS time to complete the tranaction.
595 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
600 retval = spinand_write_enable(spi_nand);
601 if (wait_till_ready(spi_nand))
602 dev_err(&spi_nand->dev, "wait timedout!!!\n");
604 retval = spinand_erase_block_erase(spi_nand, block_id);
606 retval = spinand_read_status(spi_nand, &status);
608 dev_err(&spi_nand->dev,
609 "error %d reading status register\n", retval);
613 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
614 if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
615 dev_err(&spi_nand->dev,
616 "erase error, block %d\n", block_id);
625 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
626 static int spinand_write_page_hwecc(struct mtd_info *mtd,
627 struct nand_chip *chip,
628 const u8 *buf, int oob_required,
632 int eccsize = chip->ecc.size;
633 int eccsteps = chip->ecc.steps;
636 chip->write_buf(mtd, p, eccsize * eccsteps);
640 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
641 u8 *buf, int oob_required, int page)
646 int eccsize = chip->ecc.size;
647 int eccsteps = chip->ecc.steps;
648 struct spinand_info *info = nand_get_controller_data(chip);
650 enable_read_hw_ecc = 1;
652 chip->read_buf(mtd, p, eccsize * eccsteps);
654 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
657 retval = spinand_read_status(info->spi, &status);
660 "error %d reading status register\n", retval);
664 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
665 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
666 pr_info("spinand: ECC error\n");
667 mtd->ecc_stats.failed++;
668 } else if ((status & STATUS_ECC_MASK) ==
669 STATUS_ECC_1BIT_CORRECTED)
670 mtd->ecc_stats.corrected++;
678 static void spinand_select_chip(struct mtd_info *mtd, int dev)
682 static u8 spinand_read_byte(struct mtd_info *mtd)
684 struct spinand_state *state = mtd_to_state(mtd);
687 data = state->buf[state->buf_ptr];
692 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
694 struct spinand_info *info = nand_get_controller_data(chip);
696 unsigned long timeo = jiffies;
697 int retval, state = chip->state;
700 if (state == FL_ERASING)
701 timeo += (HZ * 400) / 1000;
703 timeo += (HZ * 20) / 1000;
705 while (time_before(jiffies, timeo)) {
706 retval = spinand_read_status(info->spi, &status);
709 "error %d reading status register\n", retval);
713 if ((status & STATUS_OIP_MASK) == STATUS_READY)
721 static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
723 struct spinand_state *state = mtd_to_state(mtd);
725 memcpy(state->buf + state->buf_ptr, buf, len);
726 state->buf_ptr += len;
729 static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
731 struct spinand_state *state = mtd_to_state(mtd);
733 memcpy(buf, state->buf + state->buf_ptr, len);
734 state->buf_ptr += len;
738 * spinand_reset- send RESET command "0xff" to the Nand device.
740 static void spinand_reset(struct spi_device *spi_nand)
742 struct spinand_cmd cmd = {0};
746 if (spinand_cmd(spi_nand, &cmd) < 0)
747 pr_info("spinand reset failed!\n");
749 /* elapse 1ms before issuing any other command */
750 usleep_range(1000, 2000);
752 if (wait_till_ready(spi_nand))
753 dev_err(&spi_nand->dev, "wait timedout!\n");
756 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
757 int column, int page)
759 struct nand_chip *chip = mtd_to_nand(mtd);
760 struct spinand_info *info = nand_get_controller_data(chip);
761 struct spinand_state *state = info->priv;
765 * READ0 - read in first 0x800 bytes
770 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
772 /* READOOB reads only the OOB because no ECC is performed. */
773 case NAND_CMD_READOOB:
775 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
777 case NAND_CMD_RNDOUT:
778 state->buf_ptr = column;
780 case NAND_CMD_READID:
782 spinand_read_id(info->spi, state->buf);
787 /* ERASE1 stores the block and page address */
788 case NAND_CMD_ERASE1:
789 spinand_erase_block(info->spi, page);
791 /* ERASE2 uses the block and page address from ERASE1 */
792 case NAND_CMD_ERASE2:
794 /* SEQIN sets up the addr buffer and all registers except the length */
800 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
801 case NAND_CMD_PAGEPROG:
802 spinand_program_page(info->spi, state->row, state->col,
803 state->buf_ptr, state->buf);
805 case NAND_CMD_STATUS:
806 spinand_get_otp(info->spi, state->buf);
807 if (!(state->buf[0] & 0x80))
808 state->buf[0] = 0x80;
813 if (wait_till_ready(info->spi))
814 dev_err(&info->spi->dev, "WAIT timedout!!!\n");
815 /* a minimum of 250us must elapse before issuing RESET cmd*/
816 usleep_range(250, 1000);
817 spinand_reset(info->spi);
820 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
825 * spinand_lock_block - send write register 0x1f command to the Nand device
828 * After power up, all the Nand blocks are locked. This function allows
829 * one to unlock the blocks, and so it can be written or erased.
831 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
833 struct spinand_cmd cmd = {0};
837 ret = spinand_get_otp(spi_nand, &otp);
839 cmd.cmd = CMD_WRITE_REG;
841 cmd.addr[0] = REG_BLOCK_LOCK;
845 ret = spinand_cmd(spi_nand, &cmd);
847 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
853 * spinand_probe - [spinand Interface]
854 * @spi_nand: registered device driver.
857 * Set up the device driver parameters to make the device available.
859 static int spinand_probe(struct spi_device *spi_nand)
861 struct mtd_info *mtd;
862 struct nand_chip *chip;
863 struct spinand_info *info;
864 struct spinand_state *state;
866 info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
871 info->spi = spi_nand;
873 spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
875 state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
882 state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
886 chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
891 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
892 chip->ecc.mode = NAND_ECC_HW;
893 chip->ecc.size = 0x200;
894 chip->ecc.bytes = 0x6;
895 chip->ecc.steps = 0x4;
897 chip->ecc.strength = 1;
898 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
899 chip->ecc.read_page = spinand_read_page_hwecc;
900 chip->ecc.write_page = spinand_write_page_hwecc;
902 chip->ecc.mode = NAND_ECC_SOFT;
903 chip->ecc.algo = NAND_ECC_HAMMING;
904 if (spinand_disable_ecc(spi_nand) < 0)
905 dev_info(&spi_nand->dev, "%s: disable ecc failed!\n",
909 nand_set_flash_node(chip, spi_nand->dev.of_node);
910 nand_set_controller_data(chip, info);
911 chip->read_buf = spinand_read_buf;
912 chip->write_buf = spinand_write_buf;
913 chip->read_byte = spinand_read_byte;
914 chip->cmdfunc = spinand_cmdfunc;
915 chip->waitfunc = spinand_wait;
916 chip->options |= NAND_CACHEPRG;
917 chip->select_chip = spinand_select_chip;
919 mtd = nand_to_mtd(chip);
921 dev_set_drvdata(&spi_nand->dev, mtd);
923 mtd->dev.parent = &spi_nand->dev;
925 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
926 mtd_set_ooblayout(mtd, &spinand_oob_64_ops);
929 if (nand_scan(mtd, 1))
932 return mtd_device_register(mtd, NULL, 0);
936 * spinand_remove - remove the device driver
937 * @spi: the spi device.
940 * Remove the device driver parameters and free up allocated memories.
942 static int spinand_remove(struct spi_device *spi)
944 mtd_device_unregister(dev_get_drvdata(&spi->dev));
949 static const struct of_device_id spinand_dt[] = {
950 { .compatible = "spinand,mt29f", },
953 MODULE_DEVICE_TABLE(of, spinand_dt);
956 * Device name structure description
958 static struct spi_driver spinand_driver = {
961 .of_match_table = spinand_dt,
963 .probe = spinand_probe,
964 .remove = spinand_remove,
967 module_spi_driver(spinand_driver);
969 MODULE_DESCRIPTION("SPI NAND driver for Micron");
970 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
971 MODULE_LICENSE("GPL v2");