1 // SPDX-License-Identifier: GPL-2.0
3 * V4L2 Capture CSI Subdev for Freescale i.MX6UL/L / i.MX7 SOC
5 * Copyright (c) 2019 Linaro Ltd
10 #include <linux/delay.h>
11 #include <linux/gcd.h>
12 #include <linux/interrupt.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_graph.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/types.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-event.h>
24 #include <media/v4l2-fwnode.h>
25 #include <media/v4l2-mc.h>
26 #include <media/v4l2-subdev.h>
27 #include <media/videobuf2-dma-contig.h>
29 #include <media/imx.h>
30 #include "imx-media.h"
32 #define IMX7_CSI_PAD_SINK 0
33 #define IMX7_CSI_PAD_SRC 1
34 #define IMX7_CSI_PADS_NUM 2
37 #define CSICR1_RESET_VAL 0x40000800
38 #define CSICR2_RESET_VAL 0x0
39 #define CSICR3_RESET_VAL 0x0
41 /* csi control reg 1 */
42 #define BIT_SWAP16_EN BIT(31)
43 #define BIT_EXT_VSYNC BIT(30)
44 #define BIT_EOF_INT_EN BIT(29)
45 #define BIT_PRP_IF_EN BIT(28)
46 #define BIT_CCIR_MODE BIT(27)
47 #define BIT_COF_INT_EN BIT(26)
48 #define BIT_SF_OR_INTEN BIT(25)
49 #define BIT_RF_OR_INTEN BIT(24)
50 #define BIT_SFF_DMA_DONE_INTEN BIT(22)
51 #define BIT_STATFF_INTEN BIT(21)
52 #define BIT_FB2_DMA_DONE_INTEN BIT(20)
53 #define BIT_FB1_DMA_DONE_INTEN BIT(19)
54 #define BIT_RXFF_INTEN BIT(18)
55 #define BIT_SOF_POL BIT(17)
56 #define BIT_SOF_INTEN BIT(16)
57 #define BIT_MCLKDIV (0xF << 12)
58 #define BIT_HSYNC_POL BIT(11)
59 #define BIT_CCIR_EN BIT(10)
60 #define BIT_MCLKEN BIT(9)
61 #define BIT_FCC BIT(8)
62 #define BIT_PACK_DIR BIT(7)
63 #define BIT_CLR_STATFIFO BIT(6)
64 #define BIT_CLR_RXFIFO BIT(5)
65 #define BIT_GCLK_MODE BIT(4)
66 #define BIT_INV_DATA BIT(3)
67 #define BIT_INV_PCLK BIT(2)
68 #define BIT_REDGE BIT(1)
69 #define BIT_PIXEL_BIT BIT(0)
71 #define SHIFT_MCLKDIV 12
74 #define BIT_FRMCNT (0xFFFF << 16)
75 #define BIT_FRMCNT_RST BIT(15)
76 #define BIT_DMA_REFLASH_RFF BIT(14)
77 #define BIT_DMA_REFLASH_SFF BIT(13)
78 #define BIT_DMA_REQ_EN_RFF BIT(12)
79 #define BIT_DMA_REQ_EN_SFF BIT(11)
80 #define BIT_STATFF_LEVEL (0x7 << 8)
81 #define BIT_HRESP_ERR_EN BIT(7)
82 #define BIT_RXFF_LEVEL (0x7 << 4)
83 #define BIT_TWO_8BIT_SENSOR BIT(3)
84 #define BIT_ZERO_PACK_EN BIT(2)
85 #define BIT_ECC_INT_EN BIT(1)
86 #define BIT_ECC_AUTO_EN BIT(0)
88 #define SHIFT_FRMCNT 16
89 #define SHIFT_RXFIFO_LEVEL 4
92 #define BIT_ADDR_CH_ERR_INT BIT(28)
93 #define BIT_FIELD0_INT BIT(27)
94 #define BIT_FIELD1_INT BIT(26)
95 #define BIT_SFF_OR_INT BIT(25)
96 #define BIT_RFF_OR_INT BIT(24)
97 #define BIT_DMA_TSF_DONE_SFF BIT(22)
98 #define BIT_STATFF_INT BIT(21)
99 #define BIT_DMA_TSF_DONE_FB2 BIT(20)
100 #define BIT_DMA_TSF_DONE_FB1 BIT(19)
101 #define BIT_RXFF_INT BIT(18)
102 #define BIT_EOF_INT BIT(17)
103 #define BIT_SOF_INT BIT(16)
104 #define BIT_F2_INT BIT(15)
105 #define BIT_F1_INT BIT(14)
106 #define BIT_COF_INT BIT(13)
107 #define BIT_HRESP_ERR_INT BIT(7)
108 #define BIT_ECC_INT BIT(1)
109 #define BIT_DRDY BIT(0)
111 /* csi control reg 18 */
112 #define BIT_CSI_HW_ENABLE BIT(31)
113 #define BIT_MIPI_DATA_FORMAT_RAW8 (0x2a << 25)
114 #define BIT_MIPI_DATA_FORMAT_RAW10 (0x2b << 25)
115 #define BIT_MIPI_DATA_FORMAT_RAW12 (0x2c << 25)
116 #define BIT_MIPI_DATA_FORMAT_RAW14 (0x2d << 25)
117 #define BIT_MIPI_DATA_FORMAT_YUV422_8B (0x1e << 25)
118 #define BIT_MIPI_DATA_FORMAT_MASK (0x3F << 25)
119 #define BIT_MIPI_DATA_FORMAT_OFFSET 25
120 #define BIT_DATA_FROM_MIPI BIT(22)
121 #define BIT_MIPI_YU_SWAP BIT(21)
122 #define BIT_MIPI_DOUBLE_CMPNT BIT(20)
123 #define BIT_BASEADDR_CHG_ERR_EN BIT(9)
124 #define BIT_BASEADDR_SWITCH_SEL BIT(5)
125 #define BIT_BASEADDR_SWITCH_EN BIT(4)
126 #define BIT_PARALLEL24_EN BIT(3)
127 #define BIT_DEINTERLACE_EN BIT(2)
128 #define BIT_TVDECODER_IN_EN BIT(1)
129 #define BIT_NTSC_EN BIT(0)
131 #define CSI_MCLK_VF 1
132 #define CSI_MCLK_ENC 2
133 #define CSI_MCLK_RAW 4
134 #define CSI_MCLK_I2C 8
136 #define CSI_CSICR1 0x0
137 #define CSI_CSICR2 0x4
138 #define CSI_CSICR3 0x8
139 #define CSI_STATFIFO 0xC
140 #define CSI_CSIRXFIFO 0x10
141 #define CSI_CSIRXCNT 0x14
142 #define CSI_CSISR 0x18
144 #define CSI_CSIDBG 0x1C
145 #define CSI_CSIDMASA_STATFIFO 0x20
146 #define CSI_CSIDMATS_STATFIFO 0x24
147 #define CSI_CSIDMASA_FB1 0x28
148 #define CSI_CSIDMASA_FB2 0x2C
149 #define CSI_CSIFBUF_PARA 0x30
150 #define CSI_CSIIMAG_PARA 0x34
152 #define CSI_CSICR18 0x48
153 #define CSI_CSICR19 0x4c
157 struct v4l2_subdev sd;
158 struct imx_media_video_dev *vdev;
159 struct imx_media_dev *imxmd;
160 struct media_pad pad[IMX7_CSI_PADS_NUM];
162 /* lock to protect members below */
164 /* lock to protect irq handler when stop streaming */
167 struct v4l2_subdev *src_sd;
169 struct media_entity *sink;
171 struct v4l2_fwnode_endpoint upstream_ep;
173 struct v4l2_mbus_framefmt format_mbus[IMX7_CSI_PADS_NUM];
174 const struct imx_media_pixfmt *cc[IMX7_CSI_PADS_NUM];
175 struct v4l2_fract frame_interval[IMX7_CSI_PADS_NUM];
177 struct v4l2_ctrl_handler ctrl_hdlr;
179 void __iomem *regbase;
183 /* active vb2 buffers to send to video dev sink */
184 struct imx_media_buffer *active_vb2_buf[2];
185 struct imx_media_dma_buf underrun_buf;
195 struct completion last_eof_completion;
198 static u32 imx7_csi_reg_read(struct imx7_csi *csi, unsigned int offset)
200 return readl(csi->regbase + offset);
203 static void imx7_csi_reg_write(struct imx7_csi *csi, unsigned int value,
206 writel(value, csi->regbase + offset);
209 static void imx7_csi_hw_reset(struct imx7_csi *csi)
211 imx7_csi_reg_write(csi,
212 imx7_csi_reg_read(csi, CSI_CSICR3) | BIT_FRMCNT_RST,
215 imx7_csi_reg_write(csi, CSICR1_RESET_VAL, CSI_CSICR1);
216 imx7_csi_reg_write(csi, CSICR2_RESET_VAL, CSI_CSICR2);
217 imx7_csi_reg_write(csi, CSICR3_RESET_VAL, CSI_CSICR3);
220 static u32 imx7_csi_irq_clear(struct imx7_csi *csi)
224 isr = imx7_csi_reg_read(csi, CSI_CSISR);
225 imx7_csi_reg_write(csi, isr, CSI_CSISR);
230 static void imx7_csi_init_interface(struct imx7_csi *csi)
232 unsigned int val = 0;
233 unsigned int imag_para;
235 val = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL |
236 BIT_FCC | 1 << SHIFT_MCLKDIV | BIT_MCLKEN;
237 imx7_csi_reg_write(csi, val, CSI_CSICR1);
239 imag_para = (800 << 16) | 600;
240 imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA);
242 val = BIT_DMA_REFLASH_RFF;
243 imx7_csi_reg_write(csi, val, CSI_CSICR3);
246 static void imx7_csi_hw_enable_irq(struct imx7_csi *csi)
248 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
250 cr1 |= BIT_SOF_INTEN;
251 cr1 |= BIT_RFF_OR_INT;
253 /* still capture needs DMA interrupt */
254 cr1 |= BIT_FB1_DMA_DONE_INTEN;
255 cr1 |= BIT_FB2_DMA_DONE_INTEN;
257 cr1 |= BIT_EOF_INT_EN;
259 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
262 static void imx7_csi_hw_disable_irq(struct imx7_csi *csi)
264 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
266 cr1 &= ~BIT_SOF_INTEN;
267 cr1 &= ~BIT_RFF_OR_INT;
268 cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
269 cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
270 cr1 &= ~BIT_EOF_INT_EN;
272 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
275 static void imx7_csi_hw_enable(struct imx7_csi *csi)
277 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
279 cr |= BIT_CSI_HW_ENABLE;
281 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
284 static void imx7_csi_hw_disable(struct imx7_csi *csi)
286 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
288 cr &= ~BIT_CSI_HW_ENABLE;
290 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
293 static void imx7_csi_dma_reflash(struct imx7_csi *csi)
295 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR18);
297 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
298 cr3 |= BIT_DMA_REFLASH_RFF;
299 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
302 static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi)
306 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
307 imx7_csi_reg_write(csi, cr1 & ~BIT_FCC, CSI_CSICR1);
308 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
309 imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
311 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
312 imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);
315 static void imx7_csi_buf_stride_set(struct imx7_csi *csi, u32 stride)
317 imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);
320 static void imx7_csi_deinterlace_enable(struct imx7_csi *csi, bool enable)
322 u32 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
325 cr18 |= BIT_DEINTERLACE_EN;
327 cr18 &= ~BIT_DEINTERLACE_EN;
329 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
332 static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi)
334 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
335 u32 cr2 = imx7_csi_reg_read(csi, CSI_CSICR2);
337 /* Burst Type of DMA Transfer from RxFIFO. INCR16 */
340 cr3 |= BIT_DMA_REQ_EN_RFF;
341 cr3 |= BIT_HRESP_ERR_EN;
342 cr3 &= ~BIT_RXFF_LEVEL;
345 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
346 imx7_csi_reg_write(csi, cr2, CSI_CSICR2);
349 static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi)
351 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
353 cr3 &= ~BIT_DMA_REQ_EN_RFF;
354 cr3 &= ~BIT_HRESP_ERR_EN;
355 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
358 static void imx7_csi_set_imagpara(struct imx7_csi *csi, int width, int height)
363 rx_count = (width * height) >> 2;
364 imx7_csi_reg_write(csi, rx_count, CSI_CSIRXCNT);
366 imag_para = (width << 16) | height;
367 imx7_csi_reg_write(csi, imag_para, CSI_CSIIMAG_PARA);
369 /* reflash the embedded DMA controller */
370 imx7_csi_dma_reflash(csi);
373 static void imx7_csi_sw_reset(struct imx7_csi *csi)
375 imx7_csi_hw_disable(csi);
377 imx7_csi_rx_fifo_clear(csi);
379 imx7_csi_dma_reflash(csi);
381 usleep_range(2000, 3000);
383 imx7_csi_irq_clear(csi);
385 imx7_csi_hw_enable(csi);
388 static void imx7_csi_error_recovery(struct imx7_csi *csi)
390 imx7_csi_hw_disable(csi);
392 imx7_csi_rx_fifo_clear(csi);
394 imx7_csi_dma_reflash(csi);
396 imx7_csi_hw_enable(csi);
399 static int imx7_csi_init(struct imx7_csi *csi)
406 ret = clk_prepare_enable(csi->mclk);
409 imx7_csi_hw_reset(csi);
410 imx7_csi_init_interface(csi);
411 imx7_csi_dmareq_rff_enable(csi);
418 static void imx7_csi_deinit(struct imx7_csi *csi)
423 imx7_csi_hw_reset(csi);
424 imx7_csi_init_interface(csi);
425 imx7_csi_dmareq_rff_disable(csi);
426 clk_disable_unprepare(csi->mclk);
428 csi->is_init = false;
431 static int imx7_csi_get_upstream_endpoint(struct imx7_csi *csi,
432 struct v4l2_fwnode_endpoint *ep,
435 struct device_node *endpoint, *port;
436 struct media_entity *src;
437 struct v4l2_subdev *sd;
438 struct media_pad *pad;
443 src = &csi->src_sd->entity;
446 * if the source is neither a mux or csi2 get the one directly upstream
449 if (src->function != MEDIA_ENT_F_VID_IF_BRIDGE &&
450 src->function != MEDIA_ENT_F_VID_MUX)
451 src = &csi->sd.entity;
454 /* get source pad of entity directly upstream from src */
455 pad = imx_media_pipeline_pad(src, 0, 0, true);
459 sd = media_entity_to_v4l2_subdev(pad->entity);
461 /* To get bus type we may need to skip video mux */
462 if (skip_mux && src->function == MEDIA_ENT_F_VID_MUX) {
468 * NOTE: this assumes an OF-graph port id is the same as a
471 port = of_graph_get_port_by_id(sd->dev->of_node, pad->index);
475 endpoint = of_get_next_child(port, NULL);
480 v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), ep);
481 of_node_put(endpoint);
486 static int imx7_csi_link_setup(struct media_entity *entity,
487 const struct media_pad *local,
488 const struct media_pad *remote, u32 flags)
490 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
491 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
492 struct v4l2_subdev *remote_sd;
495 dev_dbg(csi->dev, "link setup %s -> %s\n", remote->entity->name,
496 local->entity->name);
498 mutex_lock(&csi->lock);
500 if (local->flags & MEDIA_PAD_FL_SINK) {
501 if (!is_media_entity_v4l2_subdev(remote->entity)) {
506 remote_sd = media_entity_to_v4l2_subdev(remote->entity);
508 if (flags & MEDIA_LNK_FL_ENABLED) {
513 csi->src_sd = remote_sd;
522 if (flags & MEDIA_LNK_FL_ENABLED) {
527 csi->sink = remote->entity;
529 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
530 v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0);
535 if (csi->sink || csi->src_sd)
536 ret = imx7_csi_init(csi);
538 imx7_csi_deinit(csi);
541 mutex_unlock(&csi->lock);
546 static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd,
547 struct media_link *link,
548 struct v4l2_subdev_format *source_fmt,
549 struct v4l2_subdev_format *sink_fmt)
551 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
552 struct v4l2_fwnode_endpoint upstream_ep = {};
555 ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
559 ret = imx7_csi_get_upstream_endpoint(csi, &upstream_ep, true);
561 v4l2_err(&csi->sd, "failed to find upstream endpoint\n");
565 mutex_lock(&csi->lock);
567 csi->upstream_ep = upstream_ep;
568 csi->is_csi2 = (upstream_ep.bus_type == V4L2_MBUS_CSI2_DPHY);
570 mutex_unlock(&csi->lock);
575 static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t phys,
579 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB2);
581 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB1);
584 static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi)
586 struct imx_media_video_dev *vdev = csi->vdev;
587 struct imx_media_buffer *buf;
588 struct vb2_buffer *vb2_buf;
592 for (i = 0; i < 2; i++) {
593 buf = imx_media_capture_device_next_buf(vdev);
595 csi->active_vb2_buf[i] = buf;
596 vb2_buf = &buf->vbuf.vb2_buf;
597 phys[i] = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
599 csi->active_vb2_buf[i] = NULL;
600 phys[i] = csi->underrun_buf.phys;
603 imx7_csi_update_buf(csi, phys[i], i);
607 static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi,
608 enum vb2_buffer_state return_status)
610 struct imx_media_buffer *buf;
613 /* return any remaining active frames with return_status */
614 for (i = 0; i < 2; i++) {
615 buf = csi->active_vb2_buf[i];
617 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
619 vb->timestamp = ktime_get_ns();
620 vb2_buffer_done(vb, return_status);
625 static void imx7_csi_vb2_buf_done(struct imx7_csi *csi)
627 struct imx_media_video_dev *vdev = csi->vdev;
628 struct imx_media_buffer *done, *next;
629 struct vb2_buffer *vb;
632 done = csi->active_vb2_buf[csi->buf_num];
634 done->vbuf.field = vdev->fmt.fmt.pix.field;
635 done->vbuf.sequence = csi->frame_sequence;
636 vb = &done->vbuf.vb2_buf;
637 vb->timestamp = ktime_get_ns();
638 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
640 csi->frame_sequence++;
642 /* get next queued buffer */
643 next = imx_media_capture_device_next_buf(vdev);
645 phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);
646 csi->active_vb2_buf[csi->buf_num] = next;
648 phys = csi->underrun_buf.phys;
649 csi->active_vb2_buf[csi->buf_num] = NULL;
652 imx7_csi_update_buf(csi, phys, csi->buf_num);
655 static irqreturn_t imx7_csi_irq_handler(int irq, void *data)
657 struct imx7_csi *csi = data;
660 spin_lock(&csi->irqlock);
662 status = imx7_csi_irq_clear(csi);
664 if (status & BIT_RFF_OR_INT) {
665 dev_warn(csi->dev, "Rx fifo overflow\n");
666 imx7_csi_error_recovery(csi);
669 if (status & BIT_HRESP_ERR_INT) {
670 dev_warn(csi->dev, "Hresponse error detected\n");
671 imx7_csi_error_recovery(csi);
674 if (status & BIT_ADDR_CH_ERR_INT) {
675 imx7_csi_hw_disable(csi);
677 imx7_csi_dma_reflash(csi);
679 imx7_csi_hw_enable(csi);
682 if ((status & BIT_DMA_TSF_DONE_FB1) &&
683 (status & BIT_DMA_TSF_DONE_FB2)) {
685 * For both FB1 and FB2 interrupter bits set case,
686 * CSI DMA is work in one of FB1 and FB2 buffer,
687 * but software can not know the state.
688 * Skip it to avoid base address updated
689 * when csi work in field0 and field1 will write to
692 } else if (status & BIT_DMA_TSF_DONE_FB1) {
694 } else if (status & BIT_DMA_TSF_DONE_FB2) {
698 if ((status & BIT_DMA_TSF_DONE_FB1) ||
699 (status & BIT_DMA_TSF_DONE_FB2)) {
700 imx7_csi_vb2_buf_done(csi);
703 complete(&csi->last_eof_completion);
704 csi->last_eof = false;
708 spin_unlock(&csi->irqlock);
713 static int imx7_csi_dma_start(struct imx7_csi *csi)
715 struct imx_media_video_dev *vdev = csi->vdev;
716 struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix;
719 ret = imx_media_alloc_dma_buf(csi->dev, &csi->underrun_buf,
722 v4l2_warn(&csi->sd, "consider increasing the CMA area\n");
726 csi->frame_sequence = 0;
727 csi->last_eof = false;
728 init_completion(&csi->last_eof_completion);
730 imx7_csi_setup_vb2_buf(csi);
735 static void imx7_csi_dma_stop(struct imx7_csi *csi)
737 unsigned long timeout_jiffies;
741 /* mark next EOF interrupt as the last before stream off */
742 spin_lock_irqsave(&csi->irqlock, flags);
743 csi->last_eof = true;
744 spin_unlock_irqrestore(&csi->irqlock, flags);
747 * and then wait for interrupt handler to mark completion.
749 timeout_jiffies = msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT);
750 ret = wait_for_completion_timeout(&csi->last_eof_completion,
753 v4l2_warn(&csi->sd, "wait last EOF timeout\n");
755 imx7_csi_hw_disable_irq(csi);
757 imx7_csi_dma_unsetup_vb2_buf(csi, VB2_BUF_STATE_ERROR);
759 imx_media_free_dma_buf(csi->dev, &csi->underrun_buf);
762 static int imx7_csi_configure(struct imx7_csi *csi)
764 struct imx_media_video_dev *vdev = csi->vdev;
765 struct v4l2_pix_format *out_pix = &vdev->fmt.fmt.pix;
766 __u32 in_code = csi->format_mbus[IMX7_CSI_PAD_SINK].code;
768 int width = out_pix->width;
770 if (out_pix->field == V4L2_FIELD_INTERLACED) {
771 imx7_csi_deinterlace_enable(csi, true);
772 imx7_csi_buf_stride_set(csi, out_pix->width);
774 imx7_csi_deinterlace_enable(csi, false);
775 imx7_csi_buf_stride_set(csi, 0);
778 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
781 if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
782 out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
785 imx7_csi_set_imagpara(csi, width, out_pix->height);
787 cr18 |= (BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
788 BIT_BASEADDR_CHG_ERR_EN);
789 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
794 imx7_csi_set_imagpara(csi, width, out_pix->height);
796 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
797 cr1 &= ~BIT_GCLK_MODE;
799 cr18 &= BIT_MIPI_DATA_FORMAT_MASK;
800 cr18 |= BIT_DATA_FROM_MIPI;
802 switch (out_pix->pixelformat) {
803 case V4L2_PIX_FMT_UYVY:
804 case V4L2_PIX_FMT_YUYV:
805 cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
807 case V4L2_PIX_FMT_SBGGR8:
808 cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
810 case V4L2_PIX_FMT_SBGGR16:
811 if (in_code == MEDIA_BUS_FMT_SBGGR10_1X10)
812 cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
813 else if (in_code == MEDIA_BUS_FMT_SBGGR12_1X12)
814 cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
815 else if (in_code == MEDIA_BUS_FMT_SBGGR14_1X14)
816 cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
817 cr1 |= BIT_PIXEL_BIT;
823 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
824 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
829 static void imx7_csi_enable(struct imx7_csi *csi)
831 imx7_csi_sw_reset(csi);
833 imx7_csi_dmareq_rff_enable(csi);
834 imx7_csi_hw_enable_irq(csi);
835 imx7_csi_hw_enable(csi);
838 static void imx7_csi_disable(struct imx7_csi *csi)
840 imx7_csi_dmareq_rff_disable(csi);
842 imx7_csi_hw_disable_irq(csi);
844 imx7_csi_buf_stride_set(csi, 0);
846 imx7_csi_hw_disable(csi);
849 static int imx7_csi_streaming_start(struct imx7_csi *csi)
853 ret = imx7_csi_dma_start(csi);
857 ret = imx7_csi_configure(csi);
861 imx7_csi_enable(csi);
866 imx7_csi_dma_stop(csi);
871 static int imx7_csi_streaming_stop(struct imx7_csi *csi)
873 imx7_csi_dma_stop(csi);
875 imx7_csi_disable(csi);
880 static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable)
882 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
885 mutex_lock(&csi->lock);
887 if (!csi->src_sd || !csi->sink) {
892 if (csi->is_streaming == !!enable)
896 ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1);
900 ret = imx7_csi_streaming_start(csi);
902 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
906 imx7_csi_streaming_stop(csi);
908 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
911 csi->is_streaming = !!enable;
914 mutex_unlock(&csi->lock);
919 static struct v4l2_mbus_framefmt *
920 imx7_csi_get_format(struct imx7_csi *csi,
921 struct v4l2_subdev_pad_config *cfg,
923 enum v4l2_subdev_format_whence which)
925 if (which == V4L2_SUBDEV_FORMAT_TRY)
926 return v4l2_subdev_get_try_format(&csi->sd, cfg, pad);
928 return &csi->format_mbus[pad];
931 static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,
932 struct v4l2_subdev_pad_config *cfg,
933 struct v4l2_subdev_mbus_code_enum *code)
935 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
936 struct v4l2_mbus_framefmt *in_fmt;
939 mutex_lock(&csi->lock);
941 in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK, code->which);
944 case IMX7_CSI_PAD_SINK:
945 ret = imx_media_enum_mbus_format(&code->code, code->index,
948 case IMX7_CSI_PAD_SRC:
949 if (code->index != 0) {
954 code->code = in_fmt->code;
961 mutex_unlock(&csi->lock);
966 static int imx7_csi_get_fmt(struct v4l2_subdev *sd,
967 struct v4l2_subdev_pad_config *cfg,
968 struct v4l2_subdev_format *sdformat)
970 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
971 struct v4l2_mbus_framefmt *fmt;
974 mutex_lock(&csi->lock);
976 fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which);
982 sdformat->format = *fmt;
985 mutex_unlock(&csi->lock);
990 static int imx7_csi_try_fmt(struct imx7_csi *csi,
991 struct v4l2_subdev_pad_config *cfg,
992 struct v4l2_subdev_format *sdformat,
993 const struct imx_media_pixfmt **cc)
995 const struct imx_media_pixfmt *in_cc;
996 struct v4l2_mbus_framefmt *in_fmt;
999 in_fmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SINK,
1004 switch (sdformat->pad) {
1005 case IMX7_CSI_PAD_SRC:
1006 in_cc = imx_media_find_mbus_format(in_fmt->code, CS_SEL_ANY,
1009 sdformat->format.width = in_fmt->width;
1010 sdformat->format.height = in_fmt->height;
1011 sdformat->format.code = in_fmt->code;
1014 sdformat->format.colorspace = in_fmt->colorspace;
1015 sdformat->format.xfer_func = in_fmt->xfer_func;
1017 case IMX7_CSI_PAD_SINK:
1018 *cc = imx_media_find_mbus_format(sdformat->format.code,
1021 imx_media_enum_mbus_format(&code, 0, CS_SEL_ANY, false);
1022 *cc = imx_media_find_mbus_format(code, CS_SEL_ANY,
1024 sdformat->format.code = (*cc)->codes[0];
1031 imx_media_try_colorimetry(&sdformat->format, false);
1036 static int imx7_csi_set_fmt(struct v4l2_subdev *sd,
1037 struct v4l2_subdev_pad_config *cfg,
1038 struct v4l2_subdev_format *sdformat)
1040 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1041 const struct imx_media_pixfmt *outcc;
1042 struct v4l2_mbus_framefmt *outfmt;
1043 const struct imx_media_pixfmt *cc;
1044 struct v4l2_mbus_framefmt *fmt;
1045 struct v4l2_subdev_format format;
1048 if (sdformat->pad >= IMX7_CSI_PADS_NUM)
1051 mutex_lock(&csi->lock);
1053 if (csi->is_streaming) {
1058 ret = imx7_csi_try_fmt(csi, cfg, sdformat, &cc);
1062 fmt = imx7_csi_get_format(csi, cfg, sdformat->pad, sdformat->which);
1068 *fmt = sdformat->format;
1070 if (sdformat->pad == IMX7_CSI_PAD_SINK) {
1071 /* propagate format to source pads */
1072 format.pad = IMX7_CSI_PAD_SRC;
1073 format.which = sdformat->which;
1074 format.format = sdformat->format;
1075 if (imx7_csi_try_fmt(csi, cfg, &format, &outcc)) {
1079 outfmt = imx7_csi_get_format(csi, cfg, IMX7_CSI_PAD_SRC,
1081 *outfmt = format.format;
1083 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1084 csi->cc[IMX7_CSI_PAD_SRC] = outcc;
1087 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1088 csi->cc[sdformat->pad] = cc;
1091 mutex_unlock(&csi->lock);
1096 static int imx7_csi_registered(struct v4l2_subdev *sd)
1098 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1102 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1103 /* set a default mbus format */
1104 ret = imx_media_init_mbus_fmt(&csi->format_mbus[i],
1105 800, 600, 0, V4L2_FIELD_NONE,
1110 /* init default frame interval */
1111 csi->frame_interval[i].numerator = 1;
1112 csi->frame_interval[i].denominator = 30;
1115 csi->vdev = imx_media_capture_device_init(csi->sd.dev, &csi->sd,
1117 if (IS_ERR(csi->vdev))
1118 return PTR_ERR(csi->vdev);
1120 ret = imx_media_capture_device_register(csi->vdev);
1122 imx_media_capture_device_remove(csi->vdev);
1127 static void imx7_csi_unregistered(struct v4l2_subdev *sd)
1129 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1131 imx_media_capture_device_unregister(csi->vdev);
1132 imx_media_capture_device_remove(csi->vdev);
1135 static int imx7_csi_init_cfg(struct v4l2_subdev *sd,
1136 struct v4l2_subdev_pad_config *cfg)
1138 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1139 struct v4l2_mbus_framefmt *mf;
1143 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1144 mf = v4l2_subdev_get_try_format(sd, cfg, i);
1146 ret = imx_media_init_mbus_fmt(mf, 800, 600, 0, V4L2_FIELD_NONE,
1155 static const struct media_entity_operations imx7_csi_entity_ops = {
1156 .link_setup = imx7_csi_link_setup,
1157 .link_validate = v4l2_subdev_link_validate,
1160 static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {
1161 .s_stream = imx7_csi_s_stream,
1164 static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {
1165 .init_cfg = imx7_csi_init_cfg,
1166 .enum_mbus_code = imx7_csi_enum_mbus_code,
1167 .get_fmt = imx7_csi_get_fmt,
1168 .set_fmt = imx7_csi_set_fmt,
1169 .link_validate = imx7_csi_pad_link_validate,
1172 static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {
1173 .video = &imx7_csi_video_ops,
1174 .pad = &imx7_csi_pad_ops,
1177 static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {
1178 .registered = imx7_csi_registered,
1179 .unregistered = imx7_csi_unregistered,
1182 static int imx7_csi_parse_endpoint(struct device *dev,
1183 struct v4l2_fwnode_endpoint *vep,
1184 struct v4l2_async_subdev *asd)
1186 return fwnode_device_is_available(asd->match.fwnode) ? 0 : -EINVAL;
1189 static int imx7_csi_probe(struct platform_device *pdev)
1191 struct device *dev = &pdev->dev;
1192 struct device_node *node = dev->of_node;
1193 struct imx_media_dev *imxmd;
1194 struct imx7_csi *csi;
1197 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
1203 csi->mclk = devm_clk_get(&pdev->dev, "mclk");
1204 if (IS_ERR(csi->mclk)) {
1205 ret = PTR_ERR(csi->mclk);
1206 dev_err(dev, "Failed to get mclk: %d", ret);
1210 csi->irq = platform_get_irq(pdev, 0);
1214 csi->regbase = devm_platform_ioremap_resource(pdev, 0);
1215 if (IS_ERR(csi->regbase))
1216 return PTR_ERR(csi->regbase);
1218 spin_lock_init(&csi->irqlock);
1219 mutex_init(&csi->lock);
1221 /* install interrupt handler */
1222 ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi",
1225 dev_err(dev, "Request CSI IRQ failed.\n");
1229 /* add media device */
1230 imxmd = imx_media_dev_init(dev, NULL);
1231 if (IS_ERR(imxmd)) {
1232 ret = PTR_ERR(imxmd);
1235 platform_set_drvdata(pdev, &csi->sd);
1237 ret = imx_media_of_add_csi(imxmd, node);
1238 if (ret < 0 && ret != -ENODEV && ret != -EEXIST)
1241 ret = imx_media_dev_notifier_register(imxmd, NULL);
1246 v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops);
1247 v4l2_set_subdevdata(&csi->sd, csi);
1248 csi->sd.internal_ops = &imx7_csi_internal_ops;
1249 csi->sd.entity.ops = &imx7_csi_entity_ops;
1250 csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1251 csi->sd.dev = &pdev->dev;
1252 csi->sd.owner = THIS_MODULE;
1253 csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1254 csi->sd.grp_id = IMX_MEDIA_GRP_ID_CSI;
1255 snprintf(csi->sd.name, sizeof(csi->sd.name), "csi");
1257 v4l2_ctrl_handler_init(&csi->ctrl_hdlr, 0);
1258 csi->sd.ctrl_handler = &csi->ctrl_hdlr;
1260 for (i = 0; i < IMX7_CSI_PADS_NUM; i++)
1261 csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ?
1262 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
1264 ret = media_entity_pads_init(&csi->sd.entity, IMX7_CSI_PADS_NUM,
1269 ret = v4l2_async_register_fwnode_subdev(&csi->sd,
1270 sizeof(struct v4l2_async_subdev),
1272 imx7_csi_parse_endpoint);
1279 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
1282 v4l2_async_notifier_cleanup(&imxmd->notifier);
1283 v4l2_device_unregister(&imxmd->v4l2_dev);
1284 media_device_unregister(&imxmd->md);
1285 media_device_cleanup(&imxmd->md);
1288 mutex_destroy(&csi->lock);
1293 static int imx7_csi_remove(struct platform_device *pdev)
1295 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1296 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1297 struct imx_media_dev *imxmd = csi->imxmd;
1299 v4l2_async_notifier_unregister(&imxmd->notifier);
1300 v4l2_async_notifier_cleanup(&imxmd->notifier);
1302 media_device_unregister(&imxmd->md);
1303 v4l2_device_unregister(&imxmd->v4l2_dev);
1304 media_device_cleanup(&imxmd->md);
1306 v4l2_async_unregister_subdev(sd);
1307 v4l2_ctrl_handler_free(&csi->ctrl_hdlr);
1309 mutex_destroy(&csi->lock);
1314 static const struct of_device_id imx7_csi_of_match[] = {
1315 { .compatible = "fsl,imx7-csi" },
1316 { .compatible = "fsl,imx6ul-csi" },
1319 MODULE_DEVICE_TABLE(of, imx7_csi_of_match);
1321 static struct platform_driver imx7_csi_driver = {
1322 .probe = imx7_csi_probe,
1323 .remove = imx7_csi_remove,
1325 .of_match_table = imx7_csi_of_match,
1329 module_platform_driver(imx7_csi_driver);
1331 MODULE_DESCRIPTION("i.MX7 CSI subdev driver");
1332 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_ALIAS("platform:imx7-csi");