1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hantro VPU codec driver
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
12 #include <linux/interrupt.h>
13 #include <linux/v4l2-controls.h>
14 #include <media/h264-ctrls.h>
15 #include <media/mpeg2-ctrls.h>
16 #include <media/vp8-ctrls.h>
17 #include <media/videobuf2-core.h>
19 #define DEC_8190_ALIGN_MASK 0x07U
24 struct hantro_variant;
27 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
28 * @cpu: CPU pointer to the buffer.
29 * @dma: DMA address of the buffer.
30 * @size: Size of the buffer.
31 * @attrs: Attributes of the DMA mapping.
33 struct hantro_aux_buf {
41 * struct hantro_jpeg_enc_hw_ctx
42 * @bounce_buffer: Bounce buffer
44 struct hantro_jpeg_enc_hw_ctx {
45 struct hantro_aux_buf bounce_buffer;
48 /* Max. number of entries in the DPB (HW limitation). */
49 #define HANTRO_H264_DPB_SIZE 16
52 * struct hantro_h264_dec_ctrls
53 * @decode: Decode params
54 * @scaling: Scaling info
55 * @slice: Slice params
59 struct hantro_h264_dec_ctrls {
60 const struct v4l2_ctrl_h264_decode_params *decode;
61 const struct v4l2_ctrl_h264_scaling_matrix *scaling;
62 const struct v4l2_ctrl_h264_slice_params *slices;
63 const struct v4l2_ctrl_h264_sps *sps;
64 const struct v4l2_ctrl_h264_pps *pps;
68 * struct hantro_h264_dec_reflists
73 struct hantro_h264_dec_reflists {
74 u8 p[HANTRO_H264_DPB_SIZE];
75 u8 b0[HANTRO_H264_DPB_SIZE];
76 u8 b1[HANTRO_H264_DPB_SIZE];
80 * struct hantro_h264_dec_hw_ctx
81 * @priv: Private auxiliary buffer for hardware.
83 * @reflists: P/B0/B1 reflists
84 * @ctrls: V4L2 controls attached to a run
86 struct hantro_h264_dec_hw_ctx {
87 struct hantro_aux_buf priv;
88 struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
89 struct hantro_h264_dec_reflists reflists;
90 struct hantro_h264_dec_ctrls ctrls;
94 * struct hantro_mpeg2_dec_hw_ctx
95 * @qtable: Quantization table
97 struct hantro_mpeg2_dec_hw_ctx {
98 struct hantro_aux_buf qtable;
102 * struct hantro_vp8d_hw_ctx
103 * @segment_map: Segment map buffer.
104 * @prob_tbl: Probability table buffer.
106 struct hantro_vp8_dec_hw_ctx {
107 struct hantro_aux_buf segment_map;
108 struct hantro_aux_buf prob_tbl;
112 * struct hantro_postproc_ctx
114 * @dec_q: References buffers, in decoder format.
116 struct hantro_postproc_ctx {
117 struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
121 * struct hantro_codec_ops - codec mode specific operations
123 * @init: If needed, can be used for initialization.
124 * Optional and called from process context.
125 * @exit: If needed, can be used to undo the .init phase.
126 * Optional and called from process context.
127 * @run: Start single {en,de)coding job. Called from atomic context
128 * to indicate that a pair of buffers is ready and the hardware
129 * should be programmed and started.
130 * @done: Read back processing results and additional data from hardware.
131 * @reset: Reset the hardware in case of a timeout.
133 struct hantro_codec_ops {
134 int (*init)(struct hantro_ctx *ctx);
135 void (*exit)(struct hantro_ctx *ctx);
136 void (*run)(struct hantro_ctx *ctx);
137 void (*done)(struct hantro_ctx *ctx, enum vb2_buffer_state);
138 void (*reset)(struct hantro_ctx *ctx);
142 * enum hantro_enc_fmt - source format ID for hardware registers.
144 enum hantro_enc_fmt {
145 RK3288_VPU_ENC_FMT_YUV420P = 0,
146 RK3288_VPU_ENC_FMT_YUV420SP = 1,
147 RK3288_VPU_ENC_FMT_YUYV422 = 2,
148 RK3288_VPU_ENC_FMT_UYVY422 = 3,
151 extern const struct hantro_variant rk3399_vpu_variant;
152 extern const struct hantro_variant rk3328_vpu_variant;
153 extern const struct hantro_variant rk3288_vpu_variant;
154 extern const struct hantro_variant imx8mq_vpu_variant;
156 extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
158 extern const u32 hantro_vp8_dec_mc_filter[8][6];
160 void hantro_watchdog(struct work_struct *work);
161 void hantro_run(struct hantro_ctx *ctx);
162 void hantro_irq_done(struct hantro_dev *vpu, unsigned int bytesused,
163 enum vb2_buffer_state result);
164 void hantro_start_prepare_run(struct hantro_ctx *ctx);
165 void hantro_end_prepare_run(struct hantro_ctx *ctx);
167 void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
168 void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx);
169 int hantro_jpeg_enc_init(struct hantro_ctx *ctx);
170 void hantro_jpeg_enc_exit(struct hantro_ctx *ctx);
172 dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
173 unsigned int dpb_idx);
174 int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
175 void hantro_g1_h264_dec_run(struct hantro_ctx *ctx);
176 int hantro_h264_dec_init(struct hantro_ctx *ctx);
177 void hantro_h264_dec_exit(struct hantro_ctx *ctx);
179 void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
180 void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx);
181 void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
182 const struct v4l2_ctrl_mpeg2_quantization *ctrl);
183 int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
184 void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
186 void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);
187 void rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx);
188 int hantro_vp8_dec_init(struct hantro_ctx *ctx);
189 void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
190 void hantro_vp8_prob_update(struct hantro_ctx *ctx,
191 const struct v4l2_ctrl_vp8_frame_header *hdr);
193 #endif /* HANTRO_HW_H_ */