drivers/staging/media/allegro-dvt/allegro-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
   4  *
   5  * Allegro DVT video encoder driver
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/firmware.h>
  10 #include <linux/gcd.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/log2.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/sizes.h>
  21 #include <linux/slab.h>
  22 #include <linux/videodev2.h>
  23 #include <media/v4l2-ctrls.h>
  24 #include <media/v4l2-device.h>
  25 #include <media/v4l2-event.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/v4l2-mem2mem.h>
  28 #include <media/videobuf2-dma-contig.h>
  29 #include <media/videobuf2-v4l2.h>
  30
  31 #include "allegro-mail.h"
  32 #include "nal-h264.h"
  33
  34 /*
  35  * Support up to 4k video streams. The hardware actually supports higher
  36  * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
  37  * Codec Unit v1.1) Chapter 3.
  38  */
  39 #define ALLEGRO_WIDTH_MIN 128
  40 #define ALLEGRO_WIDTH_DEFAULT 1920
  41 #define ALLEGRO_WIDTH_MAX 3840
  42 #define ALLEGRO_HEIGHT_MIN 64
  43 #define ALLEGRO_HEIGHT_DEFAULT 1080
  44 #define ALLEGRO_HEIGHT_MAX 2160
  45
  46 #define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
  47
  48 #define ALLEGRO_GOP_SIZE_DEFAULT 25
  49 #define ALLEGRO_GOP_SIZE_MAX 1000
  50
  51 /*
  52  * MCU Control Registers
  53  *
  54  * The Zynq UltraScale+ Devices Register Reference documents the registers
  55  * with an offset of 0x9000, which equals the size of the SRAM and one page
  56  * gap. The driver handles SRAM and registers separately and, therefore, is
  57  * oblivious of the offset.
  58  */
  59 #define AL5_MCU_RESET                   0x0000
  60 #define AL5_MCU_RESET_SOFT              BIT(0)
  61 #define AL5_MCU_RESET_REGS              BIT(1)
  62 #define AL5_MCU_RESET_MODE              0x0004
  63 #define AL5_MCU_RESET_MODE_SLEEP        BIT(0)
  64 #define AL5_MCU_RESET_MODE_HALT         BIT(1)
  65 #define AL5_MCU_STA                     0x0008
  66 #define AL5_MCU_STA_SLEEP               BIT(0)
  67 #define AL5_MCU_WAKEUP                  0x000c
  68
  69 #define AL5_ICACHE_ADDR_OFFSET_MSB      0x0010
  70 #define AL5_ICACHE_ADDR_OFFSET_LSB      0x0014
  71 #define AL5_DCACHE_ADDR_OFFSET_MSB      0x0018
  72 #define AL5_DCACHE_ADDR_OFFSET_LSB      0x001c
  73
  74 #define AL5_MCU_INTERRUPT               0x0100
  75 #define AL5_ITC_CPU_IRQ_MSK             0x0104
  76 #define AL5_ITC_CPU_IRQ_CLR             0x0108
  77 #define AL5_ITC_CPU_IRQ_STA             0x010C
  78 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED   BIT(0)
  79
  80 #define AXI_ADDR_OFFSET_IP              0x0208
  81
  82 /*
  83  * The MCU accesses the system memory with a 2G offset compared to CPU
  84  * physical addresses.
  85  */
  86 #define MCU_CACHE_OFFSET SZ_2G
  87
  88 /*
  89  * The driver needs to reserve some space at the beginning of capture buffers,
  90  * because it needs to write SPS/PPS NAL units. The encoder writes the actual
  91  * frame data after the offset.
  92  */
  93 #define ENCODER_STREAM_OFFSET SZ_64
  94
  95 #define SIZE_MACROBLOCK 16
  96
  97 static int debug;
  98 module_param(debug, int, 0644);
  99 MODULE_PARM_DESC(debug, "Debug level (0-2)");
 100
 101 struct allegro_buffer {
 102         void *vaddr;
 103         dma_addr_t paddr;
 104         size_t size;
 105         struct list_head head;
 106 };
 107
 108 struct allegro_channel;
 109
 110 struct allegro_mbox {
 111         unsigned int head;
 112         unsigned int tail;
 113         unsigned int data;
 114         size_t size;
 115         /* protect mailbox from simultaneous accesses */
 116         struct mutex lock;
 117 };
 118
 119 struct allegro_dev {
 120         struct v4l2_device v4l2_dev;
 121         struct video_device video_dev;
 122         struct v4l2_m2m_dev *m2m_dev;
 123         struct platform_device *plat_dev;
 124
 125         /* mutex protecting vb2_queue structure */
 126         struct mutex lock;
 127
 128         struct regmap *regmap;
 129         struct regmap *sram;
 130
 131         struct allegro_buffer firmware;
 132         struct allegro_buffer suballocator;
 133
 134         struct completion init_complete;
 135
 136         /* The mailbox interface */
 137         struct allegro_mbox mbox_command;
 138         struct allegro_mbox mbox_status;
 139
 140         /*
 141          * The downstream driver limits the users to 64 users, thus I can use
 142          * a bitfield for the user_ids that are in use. See also user_id in
 143          * struct allegro_channel.
 144          */
 145         unsigned long channel_user_ids;
 146         struct list_head channels;
 147 };
 148
 149 static struct regmap_config allegro_regmap_config = {
 150         .name = "regmap",
 151         .reg_bits = 32,
 152         .val_bits = 32,
 153         .reg_stride = 4,
 154         .max_register = 0xfff,
 155         .cache_type = REGCACHE_NONE,
 156 };
 157
 158 static struct regmap_config allegro_sram_config = {
 159         .name = "sram",
 160         .reg_bits = 32,
 161         .val_bits = 32,
 162         .reg_stride = 4,
 163         .max_register = 0x7fff,
 164         .cache_type = REGCACHE_NONE,
 165 };
 166
 167 enum allegro_state {
 168         ALLEGRO_STATE_ENCODING,
 169         ALLEGRO_STATE_DRAIN,
 170         ALLEGRO_STATE_WAIT_FOR_BUFFER,
 171         ALLEGRO_STATE_STOPPED,
 172 };
 173
 174 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
 175
 176 struct allegro_channel {
 177         struct allegro_dev *dev;
 178         struct v4l2_fh fh;
 179         struct v4l2_ctrl_handler ctrl_handler;
 180
 181         unsigned int width;
 182         unsigned int height;
 183         unsigned int stride;
 184         struct v4l2_fract framerate;
 185
 186         enum v4l2_colorspace colorspace;
 187         enum v4l2_ycbcr_encoding ycbcr_enc;
 188         enum v4l2_quantization quantization;
 189         enum v4l2_xfer_func xfer_func;
 190
 191         u32 pixelformat;
 192         unsigned int sizeimage_raw;
 193         unsigned int osequence;
 194
 195         u32 codec;
 196         enum v4l2_mpeg_video_h264_profile profile;
 197         enum v4l2_mpeg_video_h264_level level;
 198         unsigned int sizeimage_encoded;
 199         unsigned int csequence;
 200
 201         bool frame_rc_enable;
 202         unsigned int bitrate;
 203         unsigned int bitrate_peak;
 204         unsigned int cpb_size;
 205         unsigned int gop_size;
 206
 207         struct v4l2_ctrl *mpeg_video_h264_profile;
 208         struct v4l2_ctrl *mpeg_video_h264_level;
 209         struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
 210         struct v4l2_ctrl *mpeg_video_h264_max_qp;
 211         struct v4l2_ctrl *mpeg_video_h264_min_qp;
 212         struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
 213         struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
 214         struct v4l2_ctrl *mpeg_video_frame_rc_enable;
 215         struct { /* video bitrate mode control cluster */
 216                 struct v4l2_ctrl *mpeg_video_bitrate_mode;
 217                 struct v4l2_ctrl *mpeg_video_bitrate;
 218                 struct v4l2_ctrl *mpeg_video_bitrate_peak;
 219         };
 220         struct v4l2_ctrl *mpeg_video_cpb_size;
 221         struct v4l2_ctrl *mpeg_video_gop_size;
 222
 223         /* user_id is used to identify the channel during CREATE_CHANNEL */
 224         /* not sure, what to set here and if this is actually required */
 225         int user_id;
 226         /* channel_id is set by the mcu and used by all later commands */
 227         int mcu_channel_id;
 228
 229         struct list_head buffers_reference;
 230         struct list_head buffers_intermediate;
 231
 232         struct list_head source_shadow_list;
 233         struct list_head stream_shadow_list;
 234         /* protect shadow lists of buffers passed to firmware */
 235         struct mutex shadow_list_lock;
 236
 237         struct list_head list;
 238         struct completion completion;
 239
 240         unsigned int error;
 241         enum allegro_state state;
 242 };
 243
 244 static inline int
 245 allegro_set_state(struct allegro_channel *channel, enum allegro_state state)
 246 {
 247         channel->state = state;
 248
 249         return 0;
 250 }
 251
 252 static inline enum allegro_state
 253 allegro_get_state(struct allegro_channel *channel)
 254 {
 255         return channel->state;
 256 }
 257
 258 struct allegro_m2m_buffer {
 259         struct v4l2_m2m_buffer buf;
 260         struct list_head head;
 261 };
 262
 263 #define to_allegro_m2m_buffer(__buf) \
 264         container_of(__buf, struct allegro_m2m_buffer, buf)
 265
 266 struct fw_info {
 267         unsigned int id;
 268         unsigned int id_codec;
 269         char *version;
 270         unsigned int mailbox_cmd;
 271         unsigned int mailbox_status;
 272         size_t mailbox_size;
 273         size_t suballocator_size;
 274 };
 275
 276 static const struct fw_info supported_firmware[] = {
 277         {
 278                 .id = 18296,
 279                 .id_codec = 96272,
 280                 .version = "v2018.2",
 281                 .mailbox_cmd = 0x7800,
 282                 .mailbox_status = 0x7c00,
 283                 .mailbox_size = 0x400 - 0x8,
 284                 .suballocator_size = SZ_16M,
 285         },
 286 };
 287
 288 static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
 289 {
 290         if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
 291                 v4l2_warn(&dev->v4l2_dev,
 292                           "address %pad is outside mcu window\n", &phys);
 293
 294         return lower_32_bits(phys) | MCU_CACHE_OFFSET;
 295 }
 296
 297 static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
 298 {
 299         return lower_32_bits(size);
 300 }
 301
 302 static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
 303 {
 304         if (upper_32_bits(phys))
 305                 v4l2_warn(&dev->v4l2_dev,
 306                           "address %pad cannot be used by codec\n", &phys);
 307
 308         return lower_32_bits(phys);
 309 }
 310
 311 static inline u64 ptr_to_u64(const void *ptr)
 312 {
 313         return (uintptr_t)ptr;
 314 }
 315
 316 /* Helper functions for channel and user operations */
 317
 318 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
 319 {
 320         if (dev->channel_user_ids == ~0UL)
 321                 return -EBUSY;
 322
 323         return ffz(dev->channel_user_ids);
 324 }
 325
 326 static struct allegro_channel *
 327 allegro_find_channel_by_user_id(struct allegro_dev *dev,
 328                                 unsigned int user_id)
 329 {
 330         struct allegro_channel *channel;
 331
 332         list_for_each_entry(channel, &dev->channels, list) {
 333                 if (channel->user_id == user_id)
 334                         return channel;
 335         }
 336
 337         return ERR_PTR(-EINVAL);
 338 }
 339
 340 static struct allegro_channel *
 341 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
 342                                    unsigned int channel_id)
 343 {
 344         struct allegro_channel *channel;
 345
 346         list_for_each_entry(channel, &dev->channels, list) {
 347                 if (channel->mcu_channel_id == channel_id)
 348                         return channel;
 349         }
 350
 351         return ERR_PTR(-EINVAL);
 352 }
 353
 354 static inline bool channel_exists(struct allegro_channel *channel)
 355 {
 356         return channel->mcu_channel_id != -1;
 357 }
 358
 359 #define AL_ERROR                        0x80
 360 #define AL_ERR_INIT_FAILED              0x81
 361 #define AL_ERR_NO_FRAME_DECODED         0x82
 362 #define AL_ERR_RESOLUTION_CHANGE        0x85
 363 #define AL_ERR_NO_MEMORY                0x87
 364 #define AL_ERR_STREAM_OVERFLOW          0x88
 365 #define AL_ERR_TOO_MANY_SLICES          0x89
 366 #define AL_ERR_BUF_NOT_READY            0x8c
 367 #define AL_ERR_NO_CHANNEL_AVAILABLE     0x8d
 368 #define AL_ERR_RESOURCE_UNAVAILABLE     0x8e
 369 #define AL_ERR_NOT_ENOUGH_CORES         0x8f
 370 #define AL_ERR_REQUEST_MALFORMED        0x90
 371 #define AL_ERR_CMD_NOT_ALLOWED          0x91
 372 #define AL_ERR_INVALID_CMD_VALUE        0x92
 373
 374 static inline const char *allegro_err_to_string(unsigned int err)
 375 {
 376         switch (err) {
 377         case AL_ERR_INIT_FAILED:
 378                 return "initialization failed";
 379         case AL_ERR_NO_FRAME_DECODED:
 380                 return "no frame decoded";
 381         case AL_ERR_RESOLUTION_CHANGE:
 382                 return "resolution change";
 383         case AL_ERR_NO_MEMORY:
 384                 return "out of memory";
 385         case AL_ERR_STREAM_OVERFLOW:
 386                 return "stream buffer overflow";
 387         case AL_ERR_TOO_MANY_SLICES:
 388                 return "too many slices";
 389         case AL_ERR_BUF_NOT_READY:
 390                 return "buffer not ready";
 391         case AL_ERR_NO_CHANNEL_AVAILABLE:
 392                 return "no channel available";
 393         case AL_ERR_RESOURCE_UNAVAILABLE:
 394                 return "resource unavailable";
 395         case AL_ERR_NOT_ENOUGH_CORES:
 396                 return "not enough cores";
 397         case AL_ERR_REQUEST_MALFORMED:
 398                 return "request malformed";
 399         case AL_ERR_CMD_NOT_ALLOWED:
 400                 return "command not allowed";
 401         case AL_ERR_INVALID_CMD_VALUE:
 402                 return "invalid command value";
 403         case AL_ERROR:
 404         default:
 405                 return "unknown error";
 406         }
 407 }
 408
 409 static unsigned int estimate_stream_size(unsigned int width,
 410                                          unsigned int height)
 411 {
 412         unsigned int offset = ENCODER_STREAM_OFFSET;
 413         unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
 414                                         DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 415         unsigned int pcm_size = SZ_256;
 416         unsigned int partition_table = SZ_256;
 417
 418         return round_up(offset + num_blocks * pcm_size + partition_table, 32);
 419 }
 420
 421 static enum v4l2_mpeg_video_h264_level
 422 select_minimum_h264_level(unsigned int width, unsigned int height)
 423 {
 424         unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
 425         unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 426         unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
 427         enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 428
 429         /*
 430          * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
 431          * also specify limits regarding bit rate and CBP size. Only approximate
 432          * the levels using the frame size.
 433          *
 434          * Level 5.1 allows up to 4k video resolution.
 435          */
 436         if (frame_size_in_mb <= 99)
 437                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
 438         else if (frame_size_in_mb <= 396)
 439                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
 440         else if (frame_size_in_mb <= 792)
 441                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
 442         else if (frame_size_in_mb <= 1620)
 443                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
 444         else if (frame_size_in_mb <= 3600)
 445                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
 446         else if (frame_size_in_mb <= 5120)
 447                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
 448         else if (frame_size_in_mb <= 8192)
 449                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 450         else if (frame_size_in_mb <= 8704)
 451                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
 452         else if (frame_size_in_mb <= 22080)
 453                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
 454         else
 455                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
 456
 457         return level;
 458 }
 459
 460 static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
 461 {
 462         switch (level) {
 463         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 464                 return 64000;
 465         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 466                 return 128000;
 467         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 468                 return 192000;
 469         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 470                 return 384000;
 471         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 472                 return 768000;
 473         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 474                 return 2000000;
 475         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 476                 return 4000000;
 477         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 478                 return 4000000;
 479         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 480                 return 10000000;
 481         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 482                 return 14000000;
 483         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 484                 return 20000000;
 485         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 486                 return 20000000;
 487         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 488                 return 50000000;
 489         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 490                 return 50000000;
 491         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 492                 return 135000000;
 493         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 494         default:
 495                 return 240000000;
 496         }
 497 }
 498
 499 static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
 500 {
 501         switch (level) {
 502         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 503                 return 175;
 504         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 505                 return 350;
 506         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 507                 return 500;
 508         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 509                 return 1000;
 510         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 511                 return 2000;
 512         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 513                 return 2000;
 514         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 515                 return 4000;
 516         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 517                 return 4000;
 518         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 519                 return 10000;
 520         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 521                 return 14000;
 522         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 523                 return 20000;
 524         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 525                 return 25000;
 526         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 527                 return 62500;
 528         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 529                 return 62500;
 530         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 531                 return 135000;
 532         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 533         default:
 534                 return 240000;
 535         }
 536 }
 537
 538 static const struct fw_info *
 539 allegro_get_firmware_info(struct allegro_dev *dev,
 540                           const struct firmware *fw,
 541                           const struct firmware *fw_codec)
 542 {
 543         int i;
 544         unsigned int id = fw->size;
 545         unsigned int id_codec = fw_codec->size;
 546
 547         for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
 548                 if (supported_firmware[i].id == id &&
 549                     supported_firmware[i].id_codec == id_codec)
 550                         return &supported_firmware[i];
 551
 552         return NULL;
 553 }
 554
 555 /*
 556  * Buffers that are used internally by the MCU.
 557  */
 558
 559 static int allegro_alloc_buffer(struct allegro_dev *dev,
 560                                 struct allegro_buffer *buffer, size_t size)
 561 {
 562         buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
 563                                            &buffer->paddr, GFP_KERNEL);
 564         if (!buffer->vaddr)
 565                 return -ENOMEM;
 566         buffer->size = size;
 567
 568         return 0;
 569 }
 570
 571 static void allegro_free_buffer(struct allegro_dev *dev,
 572                                 struct allegro_buffer *buffer)
 573 {
 574         if (buffer->vaddr) {
 575                 dma_free_coherent(&dev->plat_dev->dev, buffer->size,
 576                                   buffer->vaddr, buffer->paddr);
 577                 buffer->vaddr = NULL;
 578                 buffer->size = 0;
 579         }
 580 }
 581
 582 /*
 583  * Mailbox interface to send messages to the MCU.
 584  */
 585
 586 static int allegro_mbox_init(struct allegro_dev *dev,
 587                              struct allegro_mbox *mbox,
 588                              unsigned int base, size_t size)
 589 {
 590         if (!mbox)
 591                 return -EINVAL;
 592
 593         mbox->head = base;
 594         mbox->tail = base + 0x4;
 595         mbox->data = base + 0x8;
 596         mbox->size = size;
 597         mutex_init(&mbox->lock);
 598
 599         regmap_write(dev->sram, mbox->head, 0);
 600         regmap_write(dev->sram, mbox->tail, 0);
 601
 602         return 0;
 603 }
 604
 605 static int allegro_mbox_write(struct allegro_dev *dev,
 606                               struct allegro_mbox *mbox, void *src, size_t size)
 607 {
 608         struct mcu_msg_header *header = src;
 609         unsigned int tail;
 610         size_t size_no_wrap;
 611         int err = 0;
 612
 613         if (!src)
 614                 return -EINVAL;
 615
 616         if (size > mbox->size) {
 617                 v4l2_err(&dev->v4l2_dev,
 618                          "message (%zu bytes) too large for mailbox (%zu bytes)\n",
 619                          size, mbox->size);
 620                 return -EINVAL;
 621         }
 622
 623         if (header->length != size - sizeof(*header)) {
 624                 v4l2_err(&dev->v4l2_dev,
 625                          "invalid message length: %u bytes (expected %zu bytes)\n",
 626                          header->length, size - sizeof(*header));
 627                 return -EINVAL;
 628         }
 629
 630         v4l2_dbg(2, debug, &dev->v4l2_dev,
 631                  "write command message: type %s, body length %d\n",
 632                  msg_type_name(header->type), header->length);
 633
 634         mutex_lock(&mbox->lock);
 635         regmap_read(dev->sram, mbox->tail, &tail);
 636         if (tail > mbox->size) {
 637                 v4l2_err(&dev->v4l2_dev,
 638                          "invalid tail (0x%x): must be smaller than mailbox size (0x%zx)\n",
 639                          tail, mbox->size);
 640                 err = -EIO;
 641                 goto out;
 642         }
 643         size_no_wrap = min(size, mbox->size - (size_t)tail);
 644         regmap_bulk_write(dev->sram, mbox->data + tail, src, size_no_wrap / 4);
 645         regmap_bulk_write(dev->sram, mbox->data,
 646                           src + size_no_wrap, (size - size_no_wrap) / 4);
 647         regmap_write(dev->sram, mbox->tail, (tail + size) % mbox->size);
 648
 649 out:
 650         mutex_unlock(&mbox->lock);
 651
 652         return err;
 653 }
 654
 655 static ssize_t allegro_mbox_read(struct allegro_dev *dev,
 656                                  struct allegro_mbox *mbox,
 657                                  void *dst, size_t nbyte)
 658 {
 659         struct mcu_msg_header *header;
 660         unsigned int head;
 661         ssize_t size;
 662         size_t body_no_wrap;
 663
 664         regmap_read(dev->sram, mbox->head, &head);
 665         if (head > mbox->size) {
 666                 v4l2_err(&dev->v4l2_dev,
 667                          "invalid head (0x%x): must be smaller than mailbox size (0x%zx)\n",
 668                          head, mbox->size);
 669                 return -EIO;
 670         }
 671
 672         /* Assume that the header does not wrap. */
 673         regmap_bulk_read(dev->sram, mbox->data + head,
 674                          dst, sizeof(*header) / 4);
 675         header = dst;
 676         size = header->length + sizeof(*header);
 677         if (size > mbox->size || size & 0x3) {
 678                 v4l2_err(&dev->v4l2_dev,
 679                          "invalid message length: %zu bytes (maximum %zu bytes)\n",
 680                          header->length + sizeof(*header), mbox->size);
 681                 return -EIO;
 682         }
 683         if (size > nbyte) {
 684                 v4l2_err(&dev->v4l2_dev,
 685                          "destination buffer too small: %zu bytes (need %zu bytes)\n",
 686                          nbyte, size);
 687                 return -EINVAL;
 688         }
 689
 690         /*
 691          * The message might wrap within the mailbox. If the message does not
 692          * wrap, the first read will read the entire message, otherwise the
 693          * first read will read message until the end of the mailbox and the
 694          * second read will read the remaining bytes from the beginning of the
 695          * mailbox.
 696          *
 697          * Skip the header, as was already read to get the size of the body.
 698          */
 699         body_no_wrap = min((size_t)header->length,
 700                            (size_t)(mbox->size - (head + sizeof(*header))));
 701         regmap_bulk_read(dev->sram, mbox->data + head + sizeof(*header),
 702                          dst + sizeof(*header), body_no_wrap / 4);
 703         regmap_bulk_read(dev->sram, mbox->data,
 704                          dst + sizeof(*header) + body_no_wrap,
 705                          (header->length - body_no_wrap) / 4);
 706
 707         regmap_write(dev->sram, mbox->head, (head + size) % mbox->size);
 708
 709         v4l2_dbg(2, debug, &dev->v4l2_dev,
 710                  "read status message: type %s, body length %d\n",
 711                  msg_type_name(header->type), header->length);
 712
 713         return size;
 714 }
 715
 716 static void allegro_mcu_interrupt(struct allegro_dev *dev)
 717 {
 718         regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
 719 }
 720
 721 static void allegro_mcu_send_init(struct allegro_dev *dev,
 722                                   dma_addr_t suballoc_dma, size_t suballoc_size)
 723 {
 724         struct mcu_msg_init_request msg;
 725
 726         memset(&msg, 0, sizeof(msg));
 727
 728         msg.header.type = MCU_MSG_TYPE_INIT;
 729         msg.header.length = sizeof(msg) - sizeof(msg.header);
 730
 731         msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
 732         msg.suballoc_size = to_mcu_size(dev, suballoc_size);
 733
 734         /* disable L2 cache */
 735         msg.l2_cache[0] = -1;
 736         msg.l2_cache[1] = -1;
 737         msg.l2_cache[2] = -1;
 738
 739         allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
 740         allegro_mcu_interrupt(dev);
 741 }
 742
 743 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
 744 {
 745         switch (pixelformat) {
 746         case V4L2_PIX_FMT_NV12:
 747                 /* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
 748                 return 0x100 | 0x88;
 749         default:
 750                 return -EINVAL;
 751         }
 752 }
 753
 754 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
 755 {
 756         switch (colorspace) {
 757         case V4L2_COLORSPACE_REC709:
 758                 return 2;
 759         case V4L2_COLORSPACE_SMPTE170M:
 760                 return 3;
 761         case V4L2_COLORSPACE_SMPTE240M:
 762                 return 4;
 763         case V4L2_COLORSPACE_SRGB:
 764                 return 7;
 765         default:
 766                 /* UNKNOWN */
 767                 return 0;
 768         }
 769 }
 770
 771 static s8 v4l2_pixelformat_to_mcu_codec(u32 pixelformat)
 772 {
 773         switch (pixelformat) {
 774         case V4L2_PIX_FMT_H264:
 775         default:
 776                 return 1;
 777         }
 778 }
 779
 780 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
 781 {
 782         switch (profile) {
 783         case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
 784         default:
 785                 return 66;
 786         }
 787 }
 788
 789 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
 790 {
 791         switch (level) {
 792         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 793                 return 10;
 794         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 795                 return 11;
 796         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 797                 return 12;
 798         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 799                 return 13;
 800         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 801                 return 20;
 802         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 803                 return 21;
 804         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 805                 return 22;
 806         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 807                 return 30;
 808         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 809                 return 31;
 810         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 811                 return 32;
 812         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 813                 return 40;
 814         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 815                 return 41;
 816         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 817                 return 42;
 818         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 819                 return 50;
 820         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 821         default:
 822                 return 51;
 823         }
 824 }
 825
 826 static u32
 827 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
 828 {
 829         switch (mode) {
 830         case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
 831                 return 2;
 832         case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
 833         default:
 834                 return 1;
 835         }
 836 }
 837
 838 static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
 839 {
 840         unsigned int cpb_size_kbit;
 841         unsigned int bitrate_kbps;
 842
 843         /*
 844          * The mcu expects the CPB size in units of a 90 kHz clock, but the
 845          * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
 846          * the CPB size in kilobytes.
 847          */
 848         cpb_size_kbit = cpb_size * BITS_PER_BYTE;
 849         bitrate_kbps = bitrate / 1000;
 850
 851         return (cpb_size_kbit * 90000) / bitrate_kbps;
 852 }
 853
 854 static s16 get_qp_delta(int minuend, int subtrahend)
 855 {
 856         if (minuend == subtrahend)
 857                 return -1;
 858         else
 859                 return minuend - subtrahend;
 860 }
 861
 862 static int fill_create_channel_param(struct allegro_channel *channel,
 863                                      struct create_channel_param *param)
 864 {
 865         int i_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
 866         int p_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
 867         int b_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
 868         int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
 869
 870         param->width = channel->width;
 871         param->height = channel->height;
 872         param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
 873         param->colorspace =
 874                 v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
 875         param->src_mode = 0x0;
 876         param->profile = v4l2_profile_to_mcu_profile(channel->profile);
 877         param->constraint_set_flags = BIT(1);
 878         param->codec = v4l2_pixelformat_to_mcu_codec(channel->codec);
 879         param->level = v4l2_level_to_mcu_level(channel->level);
 880         param->tier = 0;
 881         param->sps_param = BIT(20) | 0x4a;
 882         param->pps_param = BIT(2);
 883         param->enc_option = AL_OPT_RDO_COST_MODE | AL_OPT_LF_X_TILE |
 884                             AL_OPT_LF_X_SLICE | AL_OPT_LF;
 885         param->beta_offset = -1;
 886         param->tc_offset = -1;
 887         param->num_slices = 1;
 888         param->me_range[0] = 8;
 889         param->me_range[1] = 8;
 890         param->me_range[2] = 16;
 891         param->me_range[3] = 16;
 892         param->max_cu_size = ilog2(SIZE_MACROBLOCK);
 893         param->min_cu_size = ilog2(8);
 894         param->max_tu_size = 2;
 895         param->min_tu_size = 2;
 896         param->max_transfo_depth_intra = 1;
 897         param->max_transfo_depth_inter = 1;
 898
 899         param->prefetch_auto = 0;
 900         param->prefetch_mem_offset = 0;
 901         param->prefetch_mem_size = 0;
 902
 903         param->rate_control_mode = channel->frame_rc_enable ?
 904                 v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
 905
 906         param->cpb_size = v4l2_cpb_size_to_mcu(channel->cpb_size,
 907                                                channel->bitrate_peak);
 908         /* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
 909         param->initial_rem_delay = param->cpb_size;
 910         param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
 911                                         channel->framerate.denominator);
 912         param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
 913         param->target_bitrate = channel->bitrate;
 914         param->max_bitrate = channel->bitrate_peak;
 915         param->initial_qp = i_frame_qp;
 916         param->min_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
 917         param->max_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
 918         param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
 919         param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
 920         param->golden_ref = 0;
 921         param->golden_delta = 2;
 922         param->golden_ref_frequency = 10;
 923         param->rate_control_option = 0x00000000;
 924
 925         param->gop_ctrl_mode = 0x00000000;
 926         param->freq_idr = channel->gop_size;
 927         param->freq_lt = 0;
 928         param->gdr_mode = 0x00000000;
 929         param->gop_length = channel->gop_size;
 930         param->subframe_latency = 0x00000000;
 931
 932         return 0;
 933 }
 934
 935 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
 936                                            struct allegro_channel *channel)
 937 {
 938         struct mcu_msg_create_channel msg;
 939
 940         memset(&msg, 0, sizeof(msg));
 941
 942         msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
 943         msg.header.length = sizeof(msg) - sizeof(msg.header);
 944
 945         msg.user_id = channel->user_id;
 946
 947         fill_create_channel_param(channel, &msg.param);
 948
 949         allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
 950         allegro_mcu_interrupt(dev);
 951
 952         return 0;
 953 }
 954
 955 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
 956                                             struct allegro_channel *channel)
 957 {
 958         struct mcu_msg_destroy_channel msg;
 959
 960         memset(&msg, 0, sizeof(msg));
 961
 962         msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
 963         msg.header.length = sizeof(msg) - sizeof(msg.header);
 964
 965         msg.channel_id = channel->mcu_channel_id;
 966
 967         allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
 968         allegro_mcu_interrupt(dev);
 969
 970         return 0;
 971 }
 972
 973 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
 974                                               struct allegro_channel *channel,
 975                                               dma_addr_t paddr,
 976                                               unsigned long size,
 977                                               u64 stream_id)
 978 {
 979         struct mcu_msg_put_stream_buffer msg;
 980
 981         memset(&msg, 0, sizeof(msg));
 982
 983         msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
 984         msg.header.length = sizeof(msg) - sizeof(msg.header);
 985
 986         msg.channel_id = channel->mcu_channel_id;
 987         msg.dma_addr = to_codec_addr(dev, paddr);
 988         msg.mcu_addr = to_mcu_addr(dev, paddr);
 989         msg.size = size;
 990         msg.offset = ENCODER_STREAM_OFFSET;
 991         /* copied to mcu_msg_encode_frame_response */
 992         msg.stream_id = stream_id;
 993
 994         allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
 995         allegro_mcu_interrupt(dev);
 996
 997         return 0;
 998 }
 999
1000 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1001                                          struct allegro_channel *channel,
1002                                          dma_addr_t src_y, dma_addr_t src_uv,
1003                                          u64 src_handle)
1004 {
1005         struct mcu_msg_encode_frame msg;
1006
1007         memset(&msg, 0, sizeof(msg));
1008
1009         msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1010         msg.header.length = sizeof(msg) - sizeof(msg.header);
1011
1012         msg.channel_id = channel->mcu_channel_id;
1013         msg.encoding_options = AL_OPT_FORCE_LOAD;
1014         msg.pps_qp = 26; /* qp are relative to 26 */
1015         msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1016         /* src_handle is copied to mcu_msg_encode_frame_response */
1017         msg.src_handle = src_handle;
1018         msg.src_y = to_codec_addr(dev, src_y);
1019         msg.src_uv = to_codec_addr(dev, src_uv);
1020         msg.stride = channel->stride;
1021         msg.ep2 = 0x0;
1022         msg.ep2_v = to_mcu_addr(dev, msg.ep2);
1023
1024         allegro_mbox_write(dev, &dev->mbox_command, &msg, sizeof(msg));
1025         allegro_mcu_interrupt(dev);
1026
1027         return 0;
1028 }
1029
1030 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1031                                              unsigned long timeout_ms)
1032 {
1033         unsigned long tmo;
1034
1035         tmo = wait_for_completion_timeout(&dev->init_complete,
1036                                           msecs_to_jiffies(timeout_ms));
1037         if (tmo == 0)
1038                 return -ETIMEDOUT;
1039
1040         reinit_completion(&dev->init_complete);
1041         return 0;
1042 }
1043
1044 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1045                                             enum mcu_msg_type type)
1046 {
1047         struct allegro_dev *dev = channel->dev;
1048         struct mcu_msg_push_buffers_internal *msg;
1049         struct mcu_msg_push_buffers_internal_buffer *buffer;
1050         unsigned int num_buffers = 0;
1051         size_t size;
1052         struct allegro_buffer *al_buffer;
1053         struct list_head *list;
1054         int err;
1055
1056         switch (type) {
1057         case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1058                 list = &channel->buffers_reference;
1059                 break;
1060         case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1061                 list = &channel->buffers_intermediate;
1062                 break;
1063         default:
1064                 return -EINVAL;
1065         }
1066
1067         list_for_each_entry(al_buffer, list, head)
1068                 num_buffers++;
1069         size = struct_size(msg, buffer, num_buffers);
1070
1071         msg = kmalloc(size, GFP_KERNEL);
1072         if (!msg)
1073                 return -ENOMEM;
1074
1075         msg->header.length = size - sizeof(msg->header);
1076         msg->header.type = type;
1077         msg->channel_id = channel->mcu_channel_id;
1078
1079         buffer = msg->buffer;
1080         list_for_each_entry(al_buffer, list, head) {
1081                 buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1082                 buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1083                 buffer->size = to_mcu_size(dev, al_buffer->size);
1084                 buffer++;
1085         }
1086
1087         err = allegro_mbox_write(dev, &dev->mbox_command, msg, size);
1088         if (err)
1089                 goto out;
1090         allegro_mcu_interrupt(dev);
1091
1092 out:
1093         kfree(msg);
1094         return err;
1095 }
1096
1097 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1098 {
1099         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1100
1101         return allegro_mcu_push_buffer_internal(channel, type);
1102 }
1103
1104 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1105 {
1106         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1107
1108         return allegro_mcu_push_buffer_internal(channel, type);
1109 }
1110
1111 static int allocate_buffers_internal(struct allegro_channel *channel,
1112                                      struct list_head *list,
1113                                      size_t n, size_t size)
1114 {
1115         struct allegro_dev *dev = channel->dev;
1116         unsigned int i;
1117         int err;
1118         struct allegro_buffer *buffer, *tmp;
1119
1120         for (i = 0; i < n; i++) {
1121                 buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1122                 if (!buffer) {
1123                         err = -ENOMEM;
1124                         goto err;
1125                 }
1126                 INIT_LIST_HEAD(&buffer->head);
1127
1128                 err = allegro_alloc_buffer(dev, buffer, size);
1129                 if (err)
1130                         goto err;
1131                 list_add(&buffer->head, list);
1132         }
1133
1134         return 0;
1135
1136 err:
1137         list_for_each_entry_safe(buffer, tmp, list, head) {
1138                 list_del(&buffer->head);
1139                 allegro_free_buffer(dev, buffer);
1140                 kfree(buffer);
1141         }
1142         return err;
1143 }
1144
1145 static void destroy_buffers_internal(struct allegro_channel *channel,
1146                                      struct list_head *list)
1147 {
1148         struct allegro_dev *dev = channel->dev;
1149         struct allegro_buffer *buffer, *tmp;
1150
1151         list_for_each_entry_safe(buffer, tmp, list, head) {
1152                 list_del(&buffer->head);
1153                 allegro_free_buffer(dev, buffer);
1154                 kfree(buffer);
1155         }
1156 }
1157
1158 static void destroy_reference_buffers(struct allegro_channel *channel)
1159 {
1160         return destroy_buffers_internal(channel, &channel->buffers_reference);
1161 }
1162
1163 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1164 {
1165         return destroy_buffers_internal(channel,
1166                                         &channel->buffers_intermediate);
1167 }
1168
1169 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1170                                          size_t n, size_t size)
1171 {
1172         return allocate_buffers_internal(channel,
1173                                          &channel->buffers_intermediate,
1174                                          n, size);
1175 }
1176
1177 static int allocate_reference_buffers(struct allegro_channel *channel,
1178                                       size_t n, size_t size)
1179 {
1180         return allocate_buffers_internal(channel,
1181                                          &channel->buffers_reference,
1182                                          n, PAGE_ALIGN(size));
1183 }
1184
1185 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1186                                       void *dest, size_t n)
1187 {
1188         struct allegro_dev *dev = channel->dev;
1189         struct nal_h264_sps *sps;
1190         ssize_t size;
1191         unsigned int size_mb = SIZE_MACROBLOCK;
1192         /* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1193         unsigned int crop_unit_x = 2;
1194         unsigned int crop_unit_y = 2;
1195
1196         sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1197         if (!sps)
1198                 return -ENOMEM;
1199
1200         sps->profile_idc = nal_h264_profile_from_v4l2(channel->profile);
1201         sps->constraint_set0_flag = 0;
1202         sps->constraint_set1_flag = 1;
1203         sps->constraint_set2_flag = 0;
1204         sps->constraint_set3_flag = 0;
1205         sps->constraint_set4_flag = 0;
1206         sps->constraint_set5_flag = 0;
1207         sps->level_idc = nal_h264_level_from_v4l2(channel->level);
1208         sps->seq_parameter_set_id = 0;
1209         sps->log2_max_frame_num_minus4 = 0;
1210         sps->pic_order_cnt_type = 0;
1211         sps->log2_max_pic_order_cnt_lsb_minus4 = 6;
1212         sps->max_num_ref_frames = 3;
1213         sps->gaps_in_frame_num_value_allowed_flag = 0;
1214         sps->pic_width_in_mbs_minus1 =
1215                 DIV_ROUND_UP(channel->width, size_mb) - 1;
1216         sps->pic_height_in_map_units_minus1 =
1217                 DIV_ROUND_UP(channel->height, size_mb) - 1;
1218         sps->frame_mbs_only_flag = 1;
1219         sps->mb_adaptive_frame_field_flag = 0;
1220         sps->direct_8x8_inference_flag = 1;
1221         sps->frame_cropping_flag =
1222                 (channel->width % size_mb) || (channel->height % size_mb);
1223         if (sps->frame_cropping_flag) {
1224                 sps->crop_left = 0;
1225                 sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1226                 sps->crop_top = 0;
1227                 sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1228         }
1229         sps->vui_parameters_present_flag = 1;
1230         sps->vui.aspect_ratio_info_present_flag = 0;
1231         sps->vui.overscan_info_present_flag = 0;
1232         sps->vui.video_signal_type_present_flag = 1;
1233         sps->vui.video_format = 1;
1234         sps->vui.video_full_range_flag = 0;
1235         sps->vui.colour_description_present_flag = 1;
1236         sps->vui.colour_primaries = 5;
1237         sps->vui.transfer_characteristics = 5;
1238         sps->vui.matrix_coefficients = 5;
1239         sps->vui.chroma_loc_info_present_flag = 1;
1240         sps->vui.chroma_sample_loc_type_top_field = 0;
1241         sps->vui.chroma_sample_loc_type_bottom_field = 0;
1242
1243         sps->vui.timing_info_present_flag = 1;
1244         sps->vui.num_units_in_tick = channel->framerate.denominator;
1245         sps->vui.time_scale = 2 * channel->framerate.numerator;
1246
1247         sps->vui.fixed_frame_rate_flag = 1;
1248         sps->vui.nal_hrd_parameters_present_flag = 0;
1249         sps->vui.vcl_hrd_parameters_present_flag = 1;
1250         sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1251         sps->vui.vcl_hrd_parameters.bit_rate_scale = 0;
1252         sps->vui.vcl_hrd_parameters.cpb_size_scale = 1;
1253         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1254         sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1255                 channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1256         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1257         sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1258                 (channel->cpb_size * 1000) / (1 << (4 + sps->vui.vcl_hrd_parameters.cpb_size_scale)) - 1;
1259         sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1260                 !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1261         sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1262         sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1263         sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1264         sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1265         sps->vui.low_delay_hrd_flag = 0;
1266         sps->vui.pic_struct_present_flag = 1;
1267         sps->vui.bitstream_restriction_flag = 0;
1268
1269         size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1270
1271         kfree(sps);
1272
1273         return size;
1274 }
1275
1276 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1277                                       void *dest, size_t n)
1278 {
1279         struct allegro_dev *dev = channel->dev;
1280         struct nal_h264_pps *pps;
1281         ssize_t size;
1282
1283         pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1284         if (!pps)
1285                 return -ENOMEM;
1286
1287         pps->pic_parameter_set_id = 0;
1288         pps->seq_parameter_set_id = 0;
1289         pps->entropy_coding_mode_flag = 0;
1290         pps->bottom_field_pic_order_in_frame_present_flag = 0;
1291         pps->num_slice_groups_minus1 = 0;
1292         pps->num_ref_idx_l0_default_active_minus1 = 2;
1293         pps->num_ref_idx_l1_default_active_minus1 = 2;
1294         pps->weighted_pred_flag = 0;
1295         pps->weighted_bipred_idc = 0;
1296         pps->pic_init_qp_minus26 = 0;
1297         pps->pic_init_qs_minus26 = 0;
1298         pps->chroma_qp_index_offset = 0;
1299         pps->deblocking_filter_control_present_flag = 1;
1300         pps->constrained_intra_pred_flag = 0;
1301         pps->redundant_pic_cnt_present_flag = 0;
1302         pps->transform_8x8_mode_flag = 0;
1303         pps->pic_scaling_matrix_present_flag = 0;
1304         pps->second_chroma_qp_index_offset = 0;
1305
1306         size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1307
1308         kfree(pps);
1309
1310         return size;
1311 }
1312
1313 static bool allegro_channel_is_at_eos(struct allegro_channel *channel)
1314 {
1315         bool is_at_eos = false;
1316
1317         switch (allegro_get_state(channel)) {
1318         case ALLEGRO_STATE_STOPPED:
1319                 is_at_eos = true;
1320                 break;
1321         case ALLEGRO_STATE_DRAIN:
1322         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
1323                 mutex_lock(&channel->shadow_list_lock);
1324                 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) == 0 &&
1325                     list_empty(&channel->source_shadow_list))
1326                         is_at_eos = true;
1327                 mutex_unlock(&channel->shadow_list_lock);
1328                 break;
1329         default:
1330                 break;
1331         }
1332
1333         return is_at_eos;
1334 }
1335
1336 static void allegro_channel_buf_done(struct allegro_channel *channel,
1337                                      struct vb2_v4l2_buffer *buf,
1338                                      enum vb2_buffer_state state)
1339 {
1340         const struct v4l2_event eos_event = {
1341                 .type = V4L2_EVENT_EOS
1342         };
1343
1344         if (allegro_channel_is_at_eos(channel)) {
1345                 buf->flags |= V4L2_BUF_FLAG_LAST;
1346                 v4l2_event_queue_fh(&channel->fh, &eos_event);
1347
1348                 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
1349         }
1350
1351         v4l2_m2m_buf_done(buf, state);
1352 }
1353
1354 static u64 allegro_put_buffer(struct allegro_channel *channel,
1355                               struct list_head *list,
1356                               struct vb2_v4l2_buffer *buffer)
1357 {
1358         struct v4l2_m2m_buffer *b = container_of(buffer,
1359                                                  struct v4l2_m2m_buffer, vb);
1360         struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1361
1362         mutex_lock(&channel->shadow_list_lock);
1363         list_add_tail(&shadow->head, list);
1364         mutex_unlock(&channel->shadow_list_lock);
1365
1366         return ptr_to_u64(buffer);
1367 }
1368
1369 static struct vb2_v4l2_buffer *
1370 allegro_get_buffer(struct allegro_channel *channel,
1371                    struct list_head *list, u64 handle)
1372 {
1373         struct allegro_m2m_buffer *shadow, *tmp;
1374         struct vb2_v4l2_buffer *buffer = NULL;
1375
1376         mutex_lock(&channel->shadow_list_lock);
1377         list_for_each_entry_safe(shadow, tmp, list, head) {
1378                 if (handle == ptr_to_u64(&shadow->buf.vb)) {
1379                         buffer = &shadow->buf.vb;
1380                         list_del_init(&shadow->head);
1381                         break;
1382                 }
1383         }
1384         mutex_unlock(&channel->shadow_list_lock);
1385
1386         return buffer;
1387 }
1388
1389 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1390                 struct mcu_msg_encode_frame_response *msg)
1391 {
1392         struct allegro_dev *dev = channel->dev;
1393         struct vb2_v4l2_buffer *src_buf;
1394         struct vb2_v4l2_buffer *dst_buf;
1395         struct {
1396                 u32 offset;
1397                 u32 size;
1398         } *partition;
1399         enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1400         char *curr;
1401         ssize_t len;
1402         ssize_t free;
1403
1404         src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
1405                                      msg->src_handle);
1406         if (!src_buf)
1407                 v4l2_warn(&dev->v4l2_dev,
1408                           "channel %d: invalid source buffer\n",
1409                           channel->mcu_channel_id);
1410
1411         dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
1412                                      msg->stream_id);
1413         if (!dst_buf)
1414                 v4l2_warn(&dev->v4l2_dev,
1415                           "channel %d: invalid stream buffer\n",
1416                           channel->mcu_channel_id);
1417
1418         if (!src_buf || !dst_buf)
1419                 goto err;
1420
1421         dst_buf->sequence = channel->csequence++;
1422
1423         if (msg->error_code & AL_ERROR) {
1424                 v4l2_err(&dev->v4l2_dev,
1425                          "channel %d: failed to encode frame: %s (%x)\n",
1426                          channel->mcu_channel_id,
1427                          allegro_err_to_string(msg->error_code),
1428                          msg->error_code);
1429                 goto err;
1430         }
1431
1432         if (msg->partition_table_size != 1) {
1433                 v4l2_warn(&dev->v4l2_dev,
1434                           "channel %d: only handling first partition table entry (%d entries)\n",
1435                           channel->mcu_channel_id, msg->partition_table_size);
1436         }
1437
1438         if (msg->partition_table_offset +
1439             msg->partition_table_size * sizeof(*partition) >
1440             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1441                 v4l2_err(&dev->v4l2_dev,
1442                          "channel %d: partition table outside of dst_buf\n",
1443                          channel->mcu_channel_id);
1444                 goto err;
1445         }
1446
1447         partition =
1448             vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
1449         if (partition->offset + partition->size >
1450             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1451                 v4l2_err(&dev->v4l2_dev,
1452                          "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
1453                          channel->mcu_channel_id, partition->offset,
1454                          partition->size);
1455                 goto err;
1456         }
1457
1458         v4l2_dbg(2, debug, &dev->v4l2_dev,
1459                  "channel %d: encoded frame of size %d is at offset 0x%x\n",
1460                  channel->mcu_channel_id, partition->size, partition->offset);
1461
1462         /*
1463          * The payload must include the data before the partition offset,
1464          * because we will put the sps and pps data there.
1465          */
1466         vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1467                               partition->offset + partition->size);
1468
1469         curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
1470         free = partition->offset;
1471         if (msg->is_idr) {
1472                 len = allegro_h264_write_sps(channel, curr, free);
1473                 if (len < 0) {
1474                         v4l2_err(&dev->v4l2_dev,
1475                                  "not enough space for sequence parameter set: %zd left\n",
1476                                  free);
1477                         goto err;
1478                 }
1479                 curr += len;
1480                 free -= len;
1481                 v4l2_dbg(1, debug, &dev->v4l2_dev,
1482                          "channel %d: wrote %zd byte SPS nal unit\n",
1483                          channel->mcu_channel_id, len);
1484         }
1485
1486         if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
1487                 len = allegro_h264_write_pps(channel, curr, free);
1488                 if (len < 0) {
1489                         v4l2_err(&dev->v4l2_dev,
1490                                  "not enough space for picture parameter set: %zd left\n",
1491                                  free);
1492                         goto err;
1493                 }
1494                 curr += len;
1495                 free -= len;
1496                 v4l2_dbg(1, debug, &dev->v4l2_dev,
1497                          "channel %d: wrote %zd byte PPS nal unit\n",
1498                          channel->mcu_channel_id, len);
1499         }
1500
1501         if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
1502                 dst_buf->vb2_buf.planes[0].data_offset = free;
1503                 free = 0;
1504         } else {
1505                 len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
1506                 if (len < 0) {
1507                         v4l2_err(&dev->v4l2_dev,
1508                                  "failed to write %zd filler data\n", free);
1509                         goto err;
1510                 }
1511                 curr += len;
1512                 free -= len;
1513                 v4l2_dbg(2, debug, &dev->v4l2_dev,
1514                          "channel %d: wrote %zd bytes filler nal unit\n",
1515                          channel->mcu_channel_id, len);
1516         }
1517
1518         if (free != 0) {
1519                 v4l2_err(&dev->v4l2_dev,
1520                          "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
1521                          free);
1522                 goto err;
1523         }
1524
1525         state = VB2_BUF_STATE_DONE;
1526
1527         v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
1528         if (msg->is_idr)
1529                 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1530         else
1531                 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1532
1533         v4l2_dbg(1, debug, &dev->v4l2_dev,
1534                  "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
1535                  channel->mcu_channel_id,
1536                  dst_buf->sequence,
1537                  msg->is_idr ? "IDR, " : "",
1538                  msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
1539                  msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
1540                  msg->qp, partition->size);
1541
1542 err:
1543         if (src_buf)
1544                 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1545
1546         if (dst_buf)
1547                 allegro_channel_buf_done(channel, dst_buf, state);
1548 }
1549
1550 static int allegro_handle_init(struct allegro_dev *dev,
1551                                struct mcu_msg_init_response *msg)
1552 {
1553         complete(&dev->init_complete);
1554
1555         return 0;
1556 }
1557
1558 static int
1559 allegro_handle_create_channel(struct allegro_dev *dev,
1560                               struct mcu_msg_create_channel_response *msg)
1561 {
1562         struct allegro_channel *channel;
1563         int err = 0;
1564
1565         if (msg->header.length != sizeof(*msg) - sizeof(msg->header))
1566                 v4l2_warn(&dev->v4l2_dev,
1567                           "received message has %d bytes, but expected %zu\n",
1568                           msg->header.length,
1569                           sizeof(*msg) - sizeof(msg->header));
1570
1571         channel = allegro_find_channel_by_user_id(dev, msg->user_id);
1572         if (IS_ERR(channel)) {
1573                 v4l2_warn(&dev->v4l2_dev,
1574                           "received %s for unknown user %d\n",
1575                           msg_type_name(msg->header.type),
1576                           msg->user_id);
1577                 return -EINVAL;
1578         }
1579
1580         if (msg->error_code) {
1581                 v4l2_err(&dev->v4l2_dev,
1582                          "user %d: mcu failed to create channel: %s (%x)\n",
1583                          channel->user_id,
1584                          allegro_err_to_string(msg->error_code),
1585                          msg->error_code);
1586                 err = -EIO;
1587                 goto out;
1588         }
1589
1590         channel->mcu_channel_id = msg->channel_id;
1591         v4l2_dbg(1, debug, &dev->v4l2_dev,
1592                  "user %d: channel has channel id %d\n",
1593                  channel->user_id, channel->mcu_channel_id);
1594
1595         v4l2_dbg(1, debug, &dev->v4l2_dev,
1596                  "channel %d: intermediate buffers: %d x %d bytes\n",
1597                  channel->mcu_channel_id,
1598                  msg->int_buffers_count, msg->int_buffers_size);
1599         err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
1600                                             msg->int_buffers_size);
1601         if (err) {
1602                 v4l2_err(&dev->v4l2_dev,
1603                          "channel %d: failed to allocate intermediate buffers\n",
1604                          channel->mcu_channel_id);
1605                 goto out;
1606         }
1607         err = allegro_mcu_push_buffer_intermediate(channel);
1608         if (err)
1609                 goto out;
1610
1611         v4l2_dbg(1, debug, &dev->v4l2_dev,
1612                  "channel %d: reference buffers: %d x %d bytes\n",
1613                  channel->mcu_channel_id,
1614                  msg->rec_buffers_count, msg->rec_buffers_size);
1615         err = allocate_reference_buffers(channel, msg->rec_buffers_count,
1616                                          msg->rec_buffers_size);
1617         if (err) {
1618                 v4l2_err(&dev->v4l2_dev,
1619                          "channel %d: failed to allocate reference buffers\n",
1620                          channel->mcu_channel_id);
1621                 goto out;
1622         }
1623         err = allegro_mcu_push_buffer_reference(channel);
1624         if (err)
1625                 goto out;
1626
1627 out:
1628         channel->error = err;
1629         complete(&channel->completion);
1630
1631         /* Handled successfully, error is passed via channel->error */
1632         return 0;
1633 }
1634
1635 static int
1636 allegro_handle_destroy_channel(struct allegro_dev *dev,
1637                                struct mcu_msg_destroy_channel_response *msg)
1638 {
1639         struct allegro_channel *channel;
1640
1641         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1642         if (IS_ERR(channel)) {
1643                 v4l2_err(&dev->v4l2_dev,
1644                          "received %s for unknown channel %d\n",
1645                          msg_type_name(msg->header.type),
1646                          msg->channel_id);
1647                 return -EINVAL;
1648         }
1649
1650         v4l2_dbg(2, debug, &dev->v4l2_dev,
1651                  "user %d: vcu destroyed channel %d\n",
1652                  channel->user_id, channel->mcu_channel_id);
1653         complete(&channel->completion);
1654
1655         return 0;
1656 }
1657
1658 static int
1659 allegro_handle_encode_frame(struct allegro_dev *dev,
1660                             struct mcu_msg_encode_frame_response *msg)
1661 {
1662         struct allegro_channel *channel;
1663
1664         if (msg->header.length != sizeof(*msg) - sizeof(msg->header))
1665                 v4l2_warn(&dev->v4l2_dev,
1666                           "received message has %d bytes, but expected %zu\n",
1667                           msg->header.length,
1668                           sizeof(*msg) - sizeof(msg->header));
1669
1670         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1671         if (IS_ERR(channel)) {
1672                 v4l2_err(&dev->v4l2_dev,
1673                          "received %s for unknown channel %d\n",
1674                          msg_type_name(msg->header.type),
1675                          msg->channel_id);
1676                 return -EINVAL;
1677         }
1678
1679         allegro_channel_finish_frame(channel, msg);
1680
1681         return 0;
1682 }
1683
1684 static int allegro_receive_message(struct allegro_dev *dev)
1685 {
1686         union mcu_msg_response *msg;
1687         ssize_t size;
1688         int err = 0;
1689
1690         msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1691         if (!msg)
1692                 return -ENOMEM;
1693
1694         size = allegro_mbox_read(dev, &dev->mbox_status, msg, sizeof(*msg));
1695         if (size < sizeof(msg->header)) {
1696                 v4l2_err(&dev->v4l2_dev,
1697                          "invalid mbox message (%zd): must be at least %zu\n",
1698                          size, sizeof(msg->header));
1699                 err = -EINVAL;
1700                 goto out;
1701         }
1702
1703         switch (msg->header.type) {
1704         case MCU_MSG_TYPE_INIT:
1705                 err = allegro_handle_init(dev, &msg->init);
1706                 break;
1707         case MCU_MSG_TYPE_CREATE_CHANNEL:
1708                 err = allegro_handle_create_channel(dev, &msg->create_channel);
1709                 break;
1710         case MCU_MSG_TYPE_DESTROY_CHANNEL:
1711                 err = allegro_handle_destroy_channel(dev,
1712                                                      &msg->destroy_channel);
1713                 break;
1714         case MCU_MSG_TYPE_ENCODE_FRAME:
1715                 err = allegro_handle_encode_frame(dev, &msg->encode_frame);
1716                 break;
1717         default:
1718                 v4l2_warn(&dev->v4l2_dev,
1719                           "%s: unknown message %s\n",
1720                           __func__, msg_type_name(msg->header.type));
1721                 err = -EINVAL;
1722                 break;
1723         }
1724
1725 out:
1726         kfree(msg);
1727
1728         return err;
1729 }
1730
1731 static irqreturn_t allegro_hardirq(int irq, void *data)
1732 {
1733         struct allegro_dev *dev = data;
1734         unsigned int status;
1735
1736         regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
1737         if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
1738                 return IRQ_NONE;
1739
1740         regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
1741
1742         return IRQ_WAKE_THREAD;
1743 }
1744
1745 static irqreturn_t allegro_irq_thread(int irq, void *data)
1746 {
1747         struct allegro_dev *dev = data;
1748
1749         allegro_receive_message(dev);
1750
1751         return IRQ_HANDLED;
1752 }
1753
1754 static void allegro_copy_firmware(struct allegro_dev *dev,
1755                                   const u8 * const buf, size_t size)
1756 {
1757         int err = 0;
1758
1759         v4l2_dbg(1, debug, &dev->v4l2_dev,
1760                  "copy mcu firmware (%zu B) to SRAM\n", size);
1761         err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
1762         if (err)
1763                 v4l2_err(&dev->v4l2_dev,
1764                          "failed to copy firmware: %d\n", err);
1765 }
1766
1767 static void allegro_copy_fw_codec(struct allegro_dev *dev,
1768                                   const u8 * const buf, size_t size)
1769 {
1770         int err;
1771         dma_addr_t icache_offset, dcache_offset;
1772
1773         /*
1774          * The downstream allocates 600 KB for the codec firmware to have some
1775          * extra space for "possible extensions." My tests were fine with
1776          * allocating just enough memory for the actual firmware, but I am not
1777          * sure that the firmware really does not use the remaining space.
1778          */
1779         err = allegro_alloc_buffer(dev, &dev->firmware, size);
1780         if (err) {
1781                 v4l2_err(&dev->v4l2_dev,
1782                          "failed to allocate %zu bytes for firmware\n", size);
1783                 return;
1784         }
1785
1786         v4l2_dbg(1, debug, &dev->v4l2_dev,
1787                  "copy codec firmware (%zd B) to phys %pad\n",
1788                  size, &dev->firmware.paddr);
1789         memcpy(dev->firmware.vaddr, buf, size);
1790
1791         regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
1792                      upper_32_bits(dev->firmware.paddr));
1793
1794         icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
1795         v4l2_dbg(2, debug, &dev->v4l2_dev,
1796                  "icache_offset: msb = 0x%x, lsb = 0x%x\n",
1797                  upper_32_bits(icache_offset), lower_32_bits(icache_offset));
1798         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
1799                      upper_32_bits(icache_offset));
1800         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
1801                      lower_32_bits(icache_offset));
1802
1803         dcache_offset =
1804             (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
1805         v4l2_dbg(2, debug, &dev->v4l2_dev,
1806                  "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
1807                  upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
1808         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
1809                      upper_32_bits(dcache_offset));
1810         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
1811                      lower_32_bits(dcache_offset));
1812 }
1813
1814 static void allegro_free_fw_codec(struct allegro_dev *dev)
1815 {
1816         allegro_free_buffer(dev, &dev->firmware);
1817 }
1818
1819 /*
1820  * Control functions for the MCU
1821  */
1822
1823 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
1824 {
1825         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
1826 }
1827
1828 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
1829 {
1830         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
1831 }
1832
1833 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
1834 {
1835         unsigned long timeout;
1836         unsigned int status;
1837
1838         timeout = jiffies + msecs_to_jiffies(100);
1839         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1840                status != AL5_MCU_STA_SLEEP) {
1841                 if (time_after(jiffies, timeout))
1842                         return -ETIMEDOUT;
1843                 cpu_relax();
1844         }
1845
1846         return 0;
1847 }
1848
1849 static int allegro_mcu_start(struct allegro_dev *dev)
1850 {
1851         unsigned long timeout;
1852         unsigned int status;
1853         int err;
1854
1855         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
1856         if (err)
1857                 return err;
1858
1859         timeout = jiffies + msecs_to_jiffies(100);
1860         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1861                status == AL5_MCU_STA_SLEEP) {
1862                 if (time_after(jiffies, timeout))
1863                         return -ETIMEDOUT;
1864                 cpu_relax();
1865         }
1866
1867         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1868         if (err)
1869                 return err;
1870
1871         return 0;
1872 }
1873
1874 static int allegro_mcu_reset(struct allegro_dev *dev)
1875 {
1876         int err;
1877
1878         /*
1879          * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
1880          * does not go to sleep after the reset.
1881          */
1882         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1883         if (err)
1884                 return err;
1885
1886         err = regmap_write(dev->regmap,
1887                            AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
1888         if (err < 0)
1889                 return err;
1890
1891         err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
1892         if (err < 0)
1893                 return err;
1894
1895         return allegro_mcu_wait_for_sleep(dev);
1896 }
1897
1898 static void allegro_destroy_channel(struct allegro_channel *channel)
1899 {
1900         struct allegro_dev *dev = channel->dev;
1901         unsigned long timeout;
1902
1903         if (channel_exists(channel)) {
1904                 reinit_completion(&channel->completion);
1905                 allegro_mcu_send_destroy_channel(dev, channel);
1906                 timeout = wait_for_completion_timeout(&channel->completion,
1907                                                       msecs_to_jiffies(5000));
1908                 if (timeout == 0)
1909                         v4l2_warn(&dev->v4l2_dev,
1910                                   "channel %d: timeout while destroying\n",
1911                                   channel->mcu_channel_id);
1912
1913                 channel->mcu_channel_id = -1;
1914         }
1915
1916         destroy_intermediate_buffers(channel);
1917         destroy_reference_buffers(channel);
1918
1919         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
1920         v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
1921         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
1922         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
1923         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
1924         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
1925         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
1926         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
1927         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
1928         v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
1929         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
1930         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
1931         v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
1932
1933         if (channel->user_id != -1) {
1934                 clear_bit(channel->user_id, &dev->channel_user_ids);
1935                 channel->user_id = -1;
1936         }
1937 }
1938
1939 /*
1940  * Create the MCU channel
1941  *
1942  * After the channel has been created, the picture size, format, colorspace
1943  * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
1944  * changed anymore.
1945  *
1946  * The channel can be created only once. The MCU will accept source buffers
1947  * and stream buffers only after a channel has been created.
1948  */
1949 static int allegro_create_channel(struct allegro_channel *channel)
1950 {
1951         struct allegro_dev *dev = channel->dev;
1952         unsigned long timeout;
1953         enum v4l2_mpeg_video_h264_level min_level;
1954
1955         if (channel_exists(channel)) {
1956                 v4l2_warn(&dev->v4l2_dev,
1957                           "channel already exists\n");
1958                 return 0;
1959         }
1960
1961         channel->user_id = allegro_next_user_id(dev);
1962         if (channel->user_id < 0) {
1963                 v4l2_err(&dev->v4l2_dev,
1964                          "no free channels available\n");
1965                 return -EBUSY;
1966         }
1967         set_bit(channel->user_id, &dev->channel_user_ids);
1968
1969         v4l2_dbg(1, debug, &dev->v4l2_dev,
1970                  "user %d: creating channel (%4.4s, %dx%d@%d)\n",
1971                  channel->user_id,
1972                  (char *)&channel->codec, channel->width, channel->height,
1973                  DIV_ROUND_UP(channel->framerate.numerator,
1974                               channel->framerate.denominator));
1975
1976         min_level = select_minimum_h264_level(channel->width, channel->height);
1977         if (channel->level < min_level) {
1978                 v4l2_warn(&dev->v4l2_dev,
1979                           "user %d: selected Level %s too low: increasing to Level %s\n",
1980                           channel->user_id,
1981                           v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[channel->level],
1982                           v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[min_level]);
1983                 channel->level = min_level;
1984         }
1985
1986         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
1987         v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
1988         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
1989         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
1990         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
1991         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
1992         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
1993         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
1994         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
1995         v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
1996         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
1997         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
1998         v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
1999
2000         reinit_completion(&channel->completion);
2001         allegro_mcu_send_create_channel(dev, channel);
2002         timeout = wait_for_completion_timeout(&channel->completion,
2003                                               msecs_to_jiffies(5000));
2004         if (timeout == 0)
2005                 channel->error = -ETIMEDOUT;
2006         if (channel->error)
2007                 goto err;
2008
2009         v4l2_dbg(1, debug, &dev->v4l2_dev,
2010                  "channel %d: accepting buffers\n",
2011                  channel->mcu_channel_id);
2012
2013         return 0;
2014
2015 err:
2016         allegro_destroy_channel(channel);
2017
2018         return channel->error;
2019 }
2020
2021 static void allegro_set_default_params(struct allegro_channel *channel)
2022 {
2023         channel->width = ALLEGRO_WIDTH_DEFAULT;
2024         channel->height = ALLEGRO_HEIGHT_DEFAULT;
2025         channel->stride = round_up(channel->width, 32);
2026         channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2027
2028         channel->colorspace = V4L2_COLORSPACE_REC709;
2029         channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2030         channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2031         channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2032
2033         channel->pixelformat = V4L2_PIX_FMT_NV12;
2034         channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2035
2036         channel->codec = V4L2_PIX_FMT_H264;
2037         channel->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
2038         channel->level =
2039                 select_minimum_h264_level(channel->width, channel->height);
2040         channel->sizeimage_encoded =
2041                 estimate_stream_size(channel->width, channel->height);
2042
2043         channel->bitrate = maximum_bitrate(channel->level);
2044         channel->bitrate_peak = maximum_bitrate(channel->level);
2045         channel->cpb_size = maximum_cpb_size(channel->level);
2046         channel->gop_size = ALLEGRO_GOP_SIZE_DEFAULT;
2047 }
2048
2049 static int allegro_queue_setup(struct vb2_queue *vq,
2050                                unsigned int *nbuffers, unsigned int *nplanes,
2051                                unsigned int sizes[],
2052                                struct device *alloc_devs[])
2053 {
2054         struct allegro_channel *channel = vb2_get_drv_priv(vq);
2055         struct allegro_dev *dev = channel->dev;
2056
2057         v4l2_dbg(2, debug, &dev->v4l2_dev,
2058                  "%s: queue setup[%s]: nplanes = %d\n",
2059                  V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2060                  *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2061
2062         if (*nplanes != 0) {
2063                 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2064                         if (sizes[0] < channel->sizeimage_raw)
2065                                 return -EINVAL;
2066                 } else {
2067                         if (sizes[0] < channel->sizeimage_encoded)
2068                                 return -EINVAL;
2069                 }
2070         } else {
2071                 *nplanes = 1;
2072                 if (V4L2_TYPE_IS_OUTPUT(vq->type))
2073                         sizes[0] = channel->sizeimage_raw;
2074                 else
2075                         sizes[0] = channel->sizeimage_encoded;
2076         }
2077
2078         return 0;
2079 }
2080
2081 static int allegro_buf_prepare(struct vb2_buffer *vb)
2082 {
2083         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2084         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2085         struct allegro_dev *dev = channel->dev;
2086
2087         if (allegro_get_state(channel) == ALLEGRO_STATE_DRAIN &&
2088             V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
2089                 return -EBUSY;
2090
2091         if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2092                 if (vbuf->field == V4L2_FIELD_ANY)
2093                         vbuf->field = V4L2_FIELD_NONE;
2094                 if (vbuf->field != V4L2_FIELD_NONE) {
2095                         v4l2_err(&dev->v4l2_dev,
2096                                  "channel %d: unsupported field\n",
2097                                  channel->mcu_channel_id);
2098                         return -EINVAL;
2099                 }
2100         }
2101
2102         return 0;
2103 }
2104
2105 static void allegro_buf_queue(struct vb2_buffer *vb)
2106 {
2107         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2108         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2109
2110         if (allegro_get_state(channel) == ALLEGRO_STATE_WAIT_FOR_BUFFER &&
2111             vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2112                 allegro_channel_buf_done(channel, vbuf, VB2_BUF_STATE_DONE);
2113                 return;
2114         }
2115
2116         v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2117 }
2118
2119 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2120 {
2121         struct allegro_channel *channel = vb2_get_drv_priv(q);
2122         struct allegro_dev *dev = channel->dev;
2123
2124         v4l2_dbg(2, debug, &dev->v4l2_dev,
2125                  "%s: start streaming\n",
2126                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2127
2128         if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2129                 channel->osequence = 0;
2130                 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2131         } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2132                 channel->csequence = 0;
2133         }
2134
2135         return 0;
2136 }
2137
2138 static void allegro_stop_streaming(struct vb2_queue *q)
2139 {
2140         struct allegro_channel *channel = vb2_get_drv_priv(q);
2141         struct allegro_dev *dev = channel->dev;
2142         struct vb2_v4l2_buffer *buffer;
2143         struct allegro_m2m_buffer *shadow, *tmp;
2144
2145         v4l2_dbg(2, debug, &dev->v4l2_dev,
2146                  "%s: stop streaming\n",
2147                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2148
2149         if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2150                 mutex_lock(&channel->shadow_list_lock);
2151                 list_for_each_entry_safe(shadow, tmp,
2152                                          &channel->source_shadow_list, head) {
2153                         list_del(&shadow->head);
2154                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2155                 }
2156                 mutex_unlock(&channel->shadow_list_lock);
2157
2158                 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
2159                 while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2160                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2161         } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2162                 mutex_lock(&channel->shadow_list_lock);
2163                 list_for_each_entry_safe(shadow, tmp,
2164                                          &channel->stream_shadow_list, head) {
2165                         list_del(&shadow->head);
2166                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2167                 }
2168                 mutex_unlock(&channel->shadow_list_lock);
2169
2170                 allegro_destroy_channel(channel);
2171                 while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2172                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2173         }
2174 }
2175
2176 static const struct vb2_ops allegro_queue_ops = {
2177         .queue_setup = allegro_queue_setup,
2178         .buf_prepare = allegro_buf_prepare,
2179         .buf_queue = allegro_buf_queue,
2180         .start_streaming = allegro_start_streaming,
2181         .stop_streaming = allegro_stop_streaming,
2182         .wait_prepare = vb2_ops_wait_prepare,
2183         .wait_finish = vb2_ops_wait_finish,
2184 };
2185
2186 static int allegro_queue_init(void *priv,
2187                               struct vb2_queue *src_vq,
2188                               struct vb2_queue *dst_vq)
2189 {
2190         int err;
2191         struct allegro_channel *channel = priv;
2192
2193         src_vq->dev = &channel->dev->plat_dev->dev;
2194         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2195         src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2196         src_vq->mem_ops = &vb2_dma_contig_memops;
2197         src_vq->drv_priv = channel;
2198         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2199         src_vq->ops = &allegro_queue_ops;
2200         src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2201         src_vq->lock = &channel->dev->lock;
2202         err = vb2_queue_init(src_vq);
2203         if (err)
2204                 return err;
2205
2206         dst_vq->dev = &channel->dev->plat_dev->dev;
2207         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2208         dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2209         dst_vq->mem_ops = &vb2_dma_contig_memops;
2210         dst_vq->drv_priv = channel;
2211         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2212         dst_vq->ops = &allegro_queue_ops;
2213         dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2214         dst_vq->lock = &channel->dev->lock;
2215         err = vb2_queue_init(dst_vq);
2216         if (err)
2217                 return err;
2218
2219         return 0;
2220 }
2221
2222 static int allegro_clamp_qp(struct allegro_channel *channel,
2223                             struct v4l2_ctrl *ctrl)
2224 {
2225         struct v4l2_ctrl *next_ctrl;
2226
2227         if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
2228                 next_ctrl = channel->mpeg_video_h264_p_frame_qp;
2229         else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
2230                 next_ctrl = channel->mpeg_video_h264_b_frame_qp;
2231         else
2232                 return 0;
2233
2234         /* Modify range automatically updates the value */
2235         __v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
2236
2237         return allegro_clamp_qp(channel, next_ctrl);
2238 }
2239
2240 static int allegro_clamp_bitrate(struct allegro_channel *channel,
2241                                  struct v4l2_ctrl *ctrl)
2242 {
2243         struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
2244         struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
2245
2246         if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
2247             ctrl_bitrate_peak->val < ctrl_bitrate->val)
2248                 ctrl_bitrate_peak->val = ctrl_bitrate->val;
2249
2250         return 0;
2251 }
2252
2253 static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
2254 {
2255         struct allegro_channel *channel = container_of(ctrl->handler,
2256                                                        struct allegro_channel,
2257                                                        ctrl_handler);
2258
2259         switch (ctrl->id) {
2260         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2261                 allegro_clamp_bitrate(channel, ctrl);
2262                 break;
2263         }
2264
2265         return 0;
2266 }
2267
2268 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2269 {
2270         struct allegro_channel *channel = container_of(ctrl->handler,
2271                                                        struct allegro_channel,
2272                                                        ctrl_handler);
2273         struct allegro_dev *dev = channel->dev;
2274
2275         v4l2_dbg(1, debug, &dev->v4l2_dev,
2276                  "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2277
2278         switch (ctrl->id) {
2279         case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
2280                 channel->level = ctrl->val;
2281                 break;
2282         case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
2283                 channel->frame_rc_enable = ctrl->val;
2284                 break;
2285         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2286                 channel->bitrate = channel->mpeg_video_bitrate->val;
2287                 channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
2288                 v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
2289                                    ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
2290                 break;
2291         case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
2292                 channel->cpb_size = ctrl->val;
2293                 break;
2294         case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
2295                 channel->gop_size = ctrl->val;
2296                 break;
2297         case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
2298         case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
2299         case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
2300                 allegro_clamp_qp(channel, ctrl);
2301                 break;
2302         }
2303
2304         return 0;
2305 }
2306
2307 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
2308         .try_ctrl = allegro_try_ctrl,
2309         .s_ctrl = allegro_s_ctrl,
2310 };
2311
2312 static int allegro_open(struct file *file)
2313 {
2314         struct video_device *vdev = video_devdata(file);
2315         struct allegro_dev *dev = video_get_drvdata(vdev);
2316         struct allegro_channel *channel = NULL;
2317         struct v4l2_ctrl_handler *handler;
2318         u64 mask;
2319         int ret;
2320
2321         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2322         if (!channel)
2323                 return -ENOMEM;
2324
2325         v4l2_fh_init(&channel->fh, vdev);
2326
2327         init_completion(&channel->completion);
2328         INIT_LIST_HEAD(&channel->source_shadow_list);
2329         INIT_LIST_HEAD(&channel->stream_shadow_list);
2330         mutex_init(&channel->shadow_list_lock);
2331
2332         channel->dev = dev;
2333
2334         allegro_set_default_params(channel);
2335
2336         handler = &channel->ctrl_handler;
2337         v4l2_ctrl_handler_init(handler, 0);
2338         channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
2339                         &allegro_ctrl_ops,
2340                         V4L2_CID_MPEG_VIDEO_H264_PROFILE,
2341                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
2342                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
2343         mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
2344         channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
2345                         &allegro_ctrl_ops,
2346                         V4L2_CID_MPEG_VIDEO_H264_LEVEL,
2347                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
2348                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
2349         channel->mpeg_video_h264_i_frame_qp =
2350                 v4l2_ctrl_new_std(handler,
2351                                   &allegro_ctrl_ops,
2352                                   V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
2353                                   0, 51, 1, 30);
2354         channel->mpeg_video_h264_max_qp =
2355                 v4l2_ctrl_new_std(handler,
2356                                   &allegro_ctrl_ops,
2357                                   V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
2358                                   0, 51, 1, 51);
2359         channel->mpeg_video_h264_min_qp =
2360                 v4l2_ctrl_new_std(handler,
2361                                   &allegro_ctrl_ops,
2362                                   V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
2363                                   0, 51, 1, 0);
2364         channel->mpeg_video_h264_p_frame_qp =
2365                 v4l2_ctrl_new_std(handler,
2366                                   &allegro_ctrl_ops,
2367                                   V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
2368                                   0, 51, 1, 30);
2369         channel->mpeg_video_h264_b_frame_qp =
2370                 v4l2_ctrl_new_std(handler,
2371                                   &allegro_ctrl_ops,
2372                                   V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
2373                                   0, 51, 1, 30);
2374         channel->mpeg_video_frame_rc_enable =
2375                 v4l2_ctrl_new_std(handler,
2376                                   &allegro_ctrl_ops,
2377                                   V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
2378                                   false, 0x1,
2379                                   true, false);
2380         channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
2381                         &allegro_ctrl_ops,
2382                         V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
2383                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
2384                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
2385         channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
2386                         &allegro_ctrl_ops,
2387                         V4L2_CID_MPEG_VIDEO_BITRATE,
2388                         0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2389                         1, channel->bitrate);
2390         channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
2391                         &allegro_ctrl_ops,
2392                         V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
2393                         0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2394                         1, channel->bitrate_peak);
2395         channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
2396                         &allegro_ctrl_ops,
2397                         V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
2398                         0, maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2399                         1, channel->cpb_size);
2400         channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
2401                         &allegro_ctrl_ops,
2402                         V4L2_CID_MPEG_VIDEO_GOP_SIZE,
2403                         0, ALLEGRO_GOP_SIZE_MAX,
2404                         1, channel->gop_size);
2405         v4l2_ctrl_new_std(handler,
2406                           &allegro_ctrl_ops,
2407                           V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
2408                           1, 32,
2409                           1, 1);
2410         if (handler->error != 0) {
2411                 ret = handler->error;
2412                 goto error;
2413         }
2414
2415         channel->fh.ctrl_handler = handler;
2416
2417         v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
2418
2419         channel->mcu_channel_id = -1;
2420         channel->user_id = -1;
2421
2422         INIT_LIST_HEAD(&channel->buffers_reference);
2423         INIT_LIST_HEAD(&channel->buffers_intermediate);
2424
2425         list_add(&channel->list, &dev->channels);
2426
2427         channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
2428                                                 allegro_queue_init);
2429
2430         if (IS_ERR(channel->fh.m2m_ctx)) {
2431                 ret = PTR_ERR(channel->fh.m2m_ctx);
2432                 goto error;
2433         }
2434
2435         file->private_data = &channel->fh;
2436         v4l2_fh_add(&channel->fh);
2437
2438         return 0;
2439
2440 error:
2441         v4l2_ctrl_handler_free(handler);
2442         kfree(channel);
2443         return ret;
2444 }
2445
2446 static int allegro_release(struct file *file)
2447 {
2448         struct allegro_channel *channel = fh_to_channel(file->private_data);
2449
2450         v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
2451
2452         list_del(&channel->list);
2453
2454         v4l2_ctrl_handler_free(&channel->ctrl_handler);
2455
2456         v4l2_fh_del(&channel->fh);
2457         v4l2_fh_exit(&channel->fh);
2458
2459         kfree(channel);
2460
2461         return 0;
2462 }
2463
2464 static int allegro_querycap(struct file *file, void *fh,
2465                             struct v4l2_capability *cap)
2466 {
2467         struct video_device *vdev = video_devdata(file);
2468         struct allegro_dev *dev = video_get_drvdata(vdev);
2469
2470         strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
2471         strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
2472         snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
2473                  dev_name(&dev->plat_dev->dev));
2474
2475         return 0;
2476 }
2477
2478 static int allegro_enum_fmt_vid(struct file *file, void *fh,
2479                                 struct v4l2_fmtdesc *f)
2480 {
2481         if (f->index)
2482                 return -EINVAL;
2483         switch (f->type) {
2484         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
2485                 f->pixelformat = V4L2_PIX_FMT_NV12;
2486                 break;
2487         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
2488                 f->pixelformat = V4L2_PIX_FMT_H264;
2489                 break;
2490         default:
2491                 return -EINVAL;
2492         }
2493         return 0;
2494 }
2495
2496 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
2497                                  struct v4l2_format *f)
2498 {
2499         struct allegro_channel *channel = fh_to_channel(fh);
2500
2501         f->fmt.pix.field = V4L2_FIELD_NONE;
2502         f->fmt.pix.width = channel->width;
2503         f->fmt.pix.height = channel->height;
2504
2505         f->fmt.pix.colorspace = channel->colorspace;
2506         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2507         f->fmt.pix.quantization = channel->quantization;
2508         f->fmt.pix.xfer_func = channel->xfer_func;
2509
2510         f->fmt.pix.pixelformat = channel->codec;
2511         f->fmt.pix.bytesperline = 0;
2512         f->fmt.pix.sizeimage = channel->sizeimage_encoded;
2513
2514         return 0;
2515 }
2516
2517 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
2518                                    struct v4l2_format *f)
2519 {
2520         f->fmt.pix.field = V4L2_FIELD_NONE;
2521
2522         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2523                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2524         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2525                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2526
2527         f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
2528         f->fmt.pix.bytesperline = 0;
2529         f->fmt.pix.sizeimage =
2530                 estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
2531
2532         return 0;
2533 }
2534
2535 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
2536                                  struct v4l2_format *f)
2537 {
2538         struct allegro_channel *channel = fh_to_channel(fh);
2539
2540         f->fmt.pix.field = V4L2_FIELD_NONE;
2541
2542         f->fmt.pix.width = channel->width;
2543         f->fmt.pix.height = channel->height;
2544
2545         f->fmt.pix.colorspace = channel->colorspace;
2546         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2547         f->fmt.pix.quantization = channel->quantization;
2548         f->fmt.pix.xfer_func = channel->xfer_func;
2549
2550         f->fmt.pix.pixelformat = channel->pixelformat;
2551         f->fmt.pix.bytesperline = channel->stride;
2552         f->fmt.pix.sizeimage = channel->sizeimage_raw;
2553
2554         return 0;
2555 }
2556
2557 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
2558                                    struct v4l2_format *f)
2559 {
2560         f->fmt.pix.field = V4L2_FIELD_NONE;
2561
2562         /*
2563          * The firmware of the Allegro codec handles the padding internally
2564          * and expects the visual frame size when configuring a channel.
2565          * Therefore, unlike other encoder drivers, this driver does not round
2566          * up the width and height to macroblock alignment and does not
2567          * implement the selection api.
2568          */
2569         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2570                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2571         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2572                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2573
2574         f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
2575         f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
2576         f->fmt.pix.sizeimage =
2577                 f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
2578
2579         return 0;
2580 }
2581
2582 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
2583                                  struct v4l2_format *f)
2584 {
2585         struct allegro_channel *channel = fh_to_channel(fh);
2586         int err;
2587
2588         err = allegro_try_fmt_vid_out(file, fh, f);
2589         if (err)
2590                 return err;
2591
2592         channel->width = f->fmt.pix.width;
2593         channel->height = f->fmt.pix.height;
2594         channel->stride = f->fmt.pix.bytesperline;
2595         channel->sizeimage_raw = f->fmt.pix.sizeimage;
2596
2597         channel->colorspace = f->fmt.pix.colorspace;
2598         channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
2599         channel->quantization = f->fmt.pix.quantization;
2600         channel->xfer_func = f->fmt.pix.xfer_func;
2601
2602         channel->level =
2603                 select_minimum_h264_level(channel->width, channel->height);
2604         channel->sizeimage_encoded =
2605                 estimate_stream_size(channel->width, channel->height);
2606
2607         return 0;
2608 }
2609
2610 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
2611 {
2612         struct allegro_dev *dev = channel->dev;
2613         struct vb2_v4l2_buffer *dst_buf;
2614
2615         switch (allegro_get_state(channel)) {
2616         case ALLEGRO_STATE_DRAIN:
2617         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2618                 return -EBUSY;
2619         case ALLEGRO_STATE_ENCODING:
2620                 allegro_set_state(channel, ALLEGRO_STATE_DRAIN);
2621                 break;
2622         default:
2623                 return 0;
2624         }
2625
2626         /* If there are output buffers, they must be encoded */
2627         if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) != 0) {
2628                 v4l2_dbg(1, debug,  &dev->v4l2_dev,
2629                          "channel %d: CMD_STOP: continue encoding src buffers\n",
2630                          channel->mcu_channel_id);
2631                 return 0;
2632         }
2633
2634         /* If there are capture buffers, use it to signal EOS */
2635         dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2636         if (dst_buf) {
2637                 v4l2_dbg(1, debug,  &dev->v4l2_dev,
2638                          "channel %d: CMD_STOP: signaling EOS\n",
2639                          channel->mcu_channel_id);
2640                 allegro_channel_buf_done(channel, dst_buf, VB2_BUF_STATE_DONE);
2641                 return 0;
2642         }
2643
2644         /*
2645          * If there are no capture buffers, we need to wait for the next
2646          * buffer to signal EOS.
2647          */
2648         v4l2_dbg(1, debug,  &dev->v4l2_dev,
2649                  "channel %d: CMD_STOP: wait for CAPTURE buffer to signal EOS\n",
2650                  channel->mcu_channel_id);
2651         allegro_set_state(channel, ALLEGRO_STATE_WAIT_FOR_BUFFER);
2652
2653         return 0;
2654 }
2655
2656 static int allegro_channel_cmd_start(struct allegro_channel *channel)
2657 {
2658         switch (allegro_get_state(channel)) {
2659         case ALLEGRO_STATE_DRAIN:
2660         case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2661                 return -EBUSY;
2662         case ALLEGRO_STATE_STOPPED:
2663                 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2664                 break;
2665         default:
2666                 return 0;
2667         }
2668
2669         return 0;
2670 }
2671
2672 static int allegro_encoder_cmd(struct file *file, void *fh,
2673                                struct v4l2_encoder_cmd *cmd)
2674 {
2675         struct allegro_channel *channel = fh_to_channel(fh);
2676         int err;
2677
2678         err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
2679         if (err)
2680                 return err;
2681
2682         switch (cmd->cmd) {
2683         case V4L2_ENC_CMD_STOP:
2684                 err = allegro_channel_cmd_stop(channel);
2685                 break;
2686         case V4L2_ENC_CMD_START:
2687                 err = allegro_channel_cmd_start(channel);
2688                 break;
2689         default:
2690                 err = -EINVAL;
2691                 break;
2692         }
2693
2694         return err;
2695 }
2696
2697 static int allegro_enum_framesizes(struct file *file, void *fh,
2698                                    struct v4l2_frmsizeenum *fsize)
2699 {
2700         switch (fsize->pixel_format) {
2701         case V4L2_PIX_FMT_H264:
2702         case V4L2_PIX_FMT_NV12:
2703                 break;
2704         default:
2705                 return -EINVAL;
2706         }
2707
2708         if (fsize->index)
2709                 return -EINVAL;
2710
2711         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
2712         fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
2713         fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
2714         fsize->stepwise.step_width = 1;
2715         fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
2716         fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
2717         fsize->stepwise.step_height = 1;
2718
2719         return 0;
2720 }
2721
2722 static int allegro_ioctl_streamon(struct file *file, void *priv,
2723                                   enum v4l2_buf_type type)
2724 {
2725         struct v4l2_fh *fh = file->private_data;
2726         struct allegro_channel *channel = fh_to_channel(fh);
2727         int err;
2728
2729         if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2730                 err = allegro_create_channel(channel);
2731                 if (err)
2732                         return err;
2733         }
2734
2735         return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
2736 }
2737
2738 static int allegro_g_parm(struct file *file, void *fh,
2739                           struct v4l2_streamparm *a)
2740 {
2741         struct allegro_channel *channel = fh_to_channel(fh);
2742         struct v4l2_fract *timeperframe;
2743
2744         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2745                 return -EINVAL;
2746
2747         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2748         timeperframe = &a->parm.output.timeperframe;
2749         timeperframe->numerator = channel->framerate.denominator;
2750         timeperframe->denominator = channel->framerate.numerator;
2751
2752         return 0;
2753 }
2754
2755 static int allegro_s_parm(struct file *file, void *fh,
2756                           struct v4l2_streamparm *a)
2757 {
2758         struct allegro_channel *channel = fh_to_channel(fh);
2759         struct v4l2_fract *timeperframe;
2760         int div;
2761
2762         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2763                 return -EINVAL;
2764
2765         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2766         timeperframe = &a->parm.output.timeperframe;
2767
2768         if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
2769                 return allegro_g_parm(file, fh, a);
2770
2771         div = gcd(timeperframe->denominator, timeperframe->numerator);
2772         channel->framerate.numerator = timeperframe->denominator / div;
2773         channel->framerate.denominator = timeperframe->numerator / div;
2774
2775         return 0;
2776 }
2777
2778 static int allegro_subscribe_event(struct v4l2_fh *fh,
2779                                    const struct v4l2_event_subscription *sub)
2780 {
2781         switch (sub->type) {
2782         case V4L2_EVENT_EOS:
2783                 return v4l2_event_subscribe(fh, sub, 0, NULL);
2784         default:
2785                 return v4l2_ctrl_subscribe_event(fh, sub);
2786         }
2787 }
2788
2789 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
2790         .vidioc_querycap = allegro_querycap,
2791         .vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
2792         .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
2793         .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
2794         .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
2795         .vidioc_s_fmt_vid_cap = allegro_try_fmt_vid_cap,
2796         .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
2797         .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
2798         .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
2799
2800         .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
2801         .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
2802
2803         .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
2804         .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
2805         .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
2806         .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
2807         .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
2808
2809         .vidioc_streamon = allegro_ioctl_streamon,
2810         .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
2811
2812         .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
2813         .vidioc_encoder_cmd = allegro_encoder_cmd,
2814         .vidioc_enum_framesizes = allegro_enum_framesizes,
2815
2816         .vidioc_g_parm          = allegro_g_parm,
2817         .vidioc_s_parm          = allegro_s_parm,
2818
2819         .vidioc_subscribe_event = allegro_subscribe_event,
2820         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2821 };
2822
2823 static const struct v4l2_file_operations allegro_fops = {
2824         .owner = THIS_MODULE,
2825         .open = allegro_open,
2826         .release = allegro_release,
2827         .poll = v4l2_m2m_fop_poll,
2828         .unlocked_ioctl = video_ioctl2,
2829         .mmap = v4l2_m2m_fop_mmap,
2830 };
2831
2832 static int allegro_register_device(struct allegro_dev *dev)
2833 {
2834         struct video_device *video_dev = &dev->video_dev;
2835
2836         strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
2837         video_dev->fops = &allegro_fops;
2838         video_dev->ioctl_ops = &allegro_ioctl_ops;
2839         video_dev->release = video_device_release_empty;
2840         video_dev->lock = &dev->lock;
2841         video_dev->v4l2_dev = &dev->v4l2_dev;
2842         video_dev->vfl_dir = VFL_DIR_M2M;
2843         video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
2844         video_set_drvdata(video_dev, dev);
2845
2846         return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
2847 }
2848
2849 static void allegro_device_run(void *priv)
2850 {
2851         struct allegro_channel *channel = priv;
2852         struct allegro_dev *dev = channel->dev;
2853         struct vb2_v4l2_buffer *src_buf;
2854         struct vb2_v4l2_buffer *dst_buf;
2855         dma_addr_t src_y;
2856         dma_addr_t src_uv;
2857         dma_addr_t dst_addr;
2858         unsigned long dst_size;
2859         u64 src_handle;
2860         u64 dst_handle;
2861
2862         dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2863         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
2864         dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
2865         dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
2866                                         dst_buf);
2867         allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
2868                                            dst_handle);
2869
2870         src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
2871         src_buf->sequence = channel->osequence++;
2872         src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
2873         src_uv = src_y + (channel->stride * channel->height);
2874         src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
2875                                         src_buf);
2876         allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
2877
2878         v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
2879 }
2880
2881 static const struct v4l2_m2m_ops allegro_m2m_ops = {
2882         .device_run = allegro_device_run,
2883 };
2884
2885 static int allegro_mcu_hw_init(struct allegro_dev *dev,
2886                                const struct fw_info *info)
2887 {
2888         int err;
2889
2890         allegro_mbox_init(dev, &dev->mbox_command,
2891                           info->mailbox_cmd, info->mailbox_size);
2892         allegro_mbox_init(dev, &dev->mbox_status,
2893                           info->mailbox_status, info->mailbox_size);
2894
2895         allegro_mcu_enable_interrupts(dev);
2896
2897         /* The mcu sends INIT after reset. */
2898         allegro_mcu_start(dev);
2899         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2900         if (err < 0) {
2901                 v4l2_err(&dev->v4l2_dev,
2902                          "mcu did not send INIT after reset\n");
2903                 err = -EIO;
2904                 goto err_disable_interrupts;
2905         }
2906
2907         err = allegro_alloc_buffer(dev, &dev->suballocator,
2908                                    info->suballocator_size);
2909         if (err) {
2910                 v4l2_err(&dev->v4l2_dev,
2911                          "failed to allocate %zu bytes for suballocator\n",
2912                          info->suballocator_size);
2913                 goto err_reset_mcu;
2914         }
2915
2916         allegro_mcu_send_init(dev, dev->suballocator.paddr,
2917                               dev->suballocator.size);
2918         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2919         if (err < 0) {
2920                 v4l2_err(&dev->v4l2_dev,
2921                          "mcu failed to configure sub-allocator\n");
2922                 err = -EIO;
2923                 goto err_free_suballocator;
2924         }
2925
2926         return 0;
2927
2928 err_free_suballocator:
2929         allegro_free_buffer(dev, &dev->suballocator);
2930 err_reset_mcu:
2931         allegro_mcu_reset(dev);
2932 err_disable_interrupts:
2933         allegro_mcu_disable_interrupts(dev);
2934
2935         return err;
2936 }
2937
2938 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
2939 {
2940         int err;
2941
2942         err = allegro_mcu_reset(dev);
2943         if (err)
2944                 v4l2_warn(&dev->v4l2_dev,
2945                           "mcu failed to enter sleep state\n");
2946
2947         err = allegro_mcu_disable_interrupts(dev);
2948         if (err)
2949                 v4l2_warn(&dev->v4l2_dev,
2950                           "failed to disable interrupts\n");
2951
2952         allegro_free_buffer(dev, &dev->suballocator);
2953
2954         return 0;
2955 }
2956
2957 static void allegro_fw_callback(const struct firmware *fw, void *context)
2958 {
2959         struct allegro_dev *dev = context;
2960         const char *fw_codec_name = "al5e.fw";
2961         const struct firmware *fw_codec;
2962         int err;
2963         const struct fw_info *info;
2964
2965         if (!fw)
2966                 return;
2967
2968         v4l2_dbg(1, debug, &dev->v4l2_dev,
2969                  "requesting codec firmware '%s'\n", fw_codec_name);
2970         err = request_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
2971         if (err)
2972                 goto err_release_firmware;
2973
2974         info = allegro_get_firmware_info(dev, fw, fw_codec);
2975         if (!info) {
2976                 v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
2977                 goto err_release_firmware_codec;
2978         }
2979
2980         v4l2_info(&dev->v4l2_dev,
2981                   "using mcu firmware version '%s'\n", info->version);
2982
2983         /* Ensure that the mcu is sleeping at the reset vector */
2984         err = allegro_mcu_reset(dev);
2985         if (err) {
2986                 v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
2987                 goto err_release_firmware_codec;
2988         }
2989
2990         allegro_copy_firmware(dev, fw->data, fw->size);
2991         allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
2992
2993         err = allegro_mcu_hw_init(dev, info);
2994         if (err) {
2995                 v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
2996                 goto err_free_fw_codec;
2997         }
2998
2999         dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3000         if (IS_ERR(dev->m2m_dev)) {
3001                 v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3002                 goto err_mcu_hw_deinit;
3003         }
3004
3005         err = allegro_register_device(dev);
3006         if (err) {
3007                 v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3008                 goto err_m2m_release;
3009         }
3010
3011         v4l2_dbg(1, debug, &dev->v4l2_dev,
3012                  "allegro codec registered as /dev/video%d\n",
3013                  dev->video_dev.num);
3014
3015         release_firmware(fw_codec);
3016         release_firmware(fw);
3017
3018         return;
3019
3020 err_m2m_release:
3021         v4l2_m2m_release(dev->m2m_dev);
3022         dev->m2m_dev = NULL;
3023 err_mcu_hw_deinit:
3024         allegro_mcu_hw_deinit(dev);
3025 err_free_fw_codec:
3026         allegro_free_fw_codec(dev);
3027 err_release_firmware_codec:
3028         release_firmware(fw_codec);
3029 err_release_firmware:
3030         release_firmware(fw);
3031 }
3032
3033 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3034 {
3035         const char *fw = "al5e_b.fw";
3036
3037         v4l2_dbg(1, debug, &dev->v4l2_dev,
3038                  "requesting firmware '%s'\n", fw);
3039         return request_firmware_nowait(THIS_MODULE, true, fw,
3040                                        &dev->plat_dev->dev, GFP_KERNEL, dev,
3041                                        allegro_fw_callback);
3042 }
3043
3044 static int allegro_probe(struct platform_device *pdev)
3045 {
3046         struct allegro_dev *dev;
3047         struct resource *res, *sram_res;
3048         int ret;
3049         int irq;
3050         void __iomem *regs, *sram_regs;
3051
3052         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3053         if (!dev)
3054                 return -ENOMEM;
3055         dev->plat_dev = pdev;
3056         init_completion(&dev->init_complete);
3057         INIT_LIST_HEAD(&dev->channels);
3058
3059         mutex_init(&dev->lock);
3060
3061         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3062         if (!res) {
3063                 dev_err(&pdev->dev,
3064                         "regs resource missing from device tree\n");
3065                 return -EINVAL;
3066         }
3067         regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3068         if (IS_ERR(regs)) {
3069                 dev_err(&pdev->dev, "failed to map registers\n");
3070                 return PTR_ERR(regs);
3071         }
3072         dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3073                                             &allegro_regmap_config);
3074         if (IS_ERR(dev->regmap)) {
3075                 dev_err(&pdev->dev, "failed to init regmap\n");
3076                 return PTR_ERR(dev->regmap);
3077         }
3078
3079         sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3080         if (!sram_res) {
3081                 dev_err(&pdev->dev,
3082                         "sram resource missing from device tree\n");
3083                 return -EINVAL;
3084         }
3085         sram_regs = devm_ioremap(&pdev->dev,
3086                                  sram_res->start,
3087                                  resource_size(sram_res));
3088         if (IS_ERR(sram_regs)) {
3089                 dev_err(&pdev->dev, "failed to map sram\n");
3090                 return PTR_ERR(sram_regs);
3091         }
3092         dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3093                                           &allegro_sram_config);
3094         if (IS_ERR(dev->sram)) {
3095                 dev_err(&pdev->dev, "failed to init sram\n");
3096                 return PTR_ERR(dev->sram);
3097         }
3098
3099         irq = platform_get_irq(pdev, 0);
3100         if (irq < 0)
3101                 return irq;
3102         ret = devm_request_threaded_irq(&pdev->dev, irq,
3103                                         allegro_hardirq,
3104                                         allegro_irq_thread,
3105                                         IRQF_SHARED, dev_name(&pdev->dev), dev);
3106         if (ret < 0) {
3107                 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3108                 return ret;
3109         }
3110
3111         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3112         if (ret)
3113                 return ret;
3114
3115         platform_set_drvdata(pdev, dev);
3116
3117         ret = allegro_firmware_request_nowait(dev);
3118         if (ret < 0) {
3119                 v4l2_err(&dev->v4l2_dev,
3120                          "failed to request firmware: %d\n", ret);
3121                 return ret;
3122         }
3123
3124         return 0;
3125 }
3126
3127 static int allegro_remove(struct platform_device *pdev)
3128 {
3129         struct allegro_dev *dev = platform_get_drvdata(pdev);
3130
3131         video_unregister_device(&dev->video_dev);
3132         if (dev->m2m_dev)
3133                 v4l2_m2m_release(dev->m2m_dev);
3134         allegro_mcu_hw_deinit(dev);
3135         allegro_free_fw_codec(dev);
3136
3137         v4l2_device_unregister(&dev->v4l2_dev);
3138
3139         return 0;
3140 }
3141
3142 static const struct of_device_id allegro_dt_ids[] = {
3143         { .compatible = "allegro,al5e-1.1" },
3144         { /* sentinel */ }
3145 };
3146
3147 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
3148
3149 static struct platform_driver allegro_driver = {
3150         .probe = allegro_probe,
3151         .remove = allegro_remove,
3152         .driver = {
3153                 .name = "allegro",
3154                 .of_match_table = of_match_ptr(allegro_dt_ids),
3155         },
3156 };
3157
3158 module_platform_driver(allegro_driver);
3159
3160 MODULE_LICENSE("GPL");
3161 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
3162 MODULE_DESCRIPTION("Allegro DVT encoder driver");