1 // SPDX-License-Identifier: GPL-2.0+
5 * Adapted i2c-i801.c for use with Kadoka hardware.
7 * Copyright (C) 1998 - 2002
8 * Frodo Looijaard <frodol@dds.nl>,
9 * Philip Edelbrock <phil@netroedge.com>,
10 * Mark D. Studebaker <mdsxyz123@yahoo.com>
11 * Copyright (C) 2007 - 2012
12 * Jean Delvare <khali@linux-fr.org>
13 * Copyright (C) 2010 Intel Corporation
14 * David Woodhouse <dwmw2@infradead.org>
15 * Copyright (C) 2014-2018 Daktronics
16 * Matt Sickler <matt.sickler@daktronics.com>,
17 * Jordon Hofer <jordon.hofer@daktronics.com>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/platform_device.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
32 MODULE_LICENSE("GPL");
33 MODULE_AUTHOR("Matt.Sickler@Daktronics.com");
37 struct i2c_adapter adapter;
38 unsigned int features;
41 /*****************************
42 *** Part 1 - i2c Handlers ***
43 *****************************/
47 /* I801 SMBus address offsets */
48 #define SMBHSTSTS(p) ((0 * REG_SIZE) + (p)->smba)
49 #define SMBHSTCNT(p) ((2 * REG_SIZE) + (p)->smba)
50 #define SMBHSTCMD(p) ((3 * REG_SIZE) + (p)->smba)
51 #define SMBHSTADD(p) ((4 * REG_SIZE) + (p)->smba)
52 #define SMBHSTDAT0(p) ((5 * REG_SIZE) + (p)->smba)
53 #define SMBHSTDAT1(p) ((6 * REG_SIZE) + (p)->smba)
54 #define SMBBLKDAT(p) ((7 * REG_SIZE) + (p)->smba)
55 #define SMBPEC(p) ((8 * REG_SIZE) + (p)->smba) /* ICH3 and later */
56 #define SMBAUXSTS(p) ((12 * REG_SIZE) + (p)->smba) /* ICH4 and later */
57 #define SMBAUXCTL(p) ((13 * REG_SIZE) + (p)->smba) /* ICH4 and later */
59 /* PCI Address Constants */
61 #define SMBHSTCFG 0x040
63 /* Host configuration bits for SMBHSTCFG */
64 #define SMBHSTCFG_HST_EN 1
65 #define SMBHSTCFG_SMB_SMI_EN 2
66 #define SMBHSTCFG_I2C_EN 4
68 /* Auxiliary control register bits, ICH4+ only */
69 #define SMBAUXCTL_CRC 1
70 #define SMBAUXCTL_E32B 2
72 /* kill bit for SMBHSTCNT */
73 #define SMBHSTCNT_KILL 2
76 #define MAX_RETRIES 400
77 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
79 /* I801 command constants */
80 #define I801_QUICK 0x00
81 #define I801_BYTE 0x04
82 #define I801_BYTE_DATA 0x08
83 #define I801_WORD_DATA 0x0C
84 #define I801_PROC_CALL 0x10 /* unimplemented */
85 #define I801_BLOCK_DATA 0x14
86 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
87 #define I801_BLOCK_LAST 0x34
88 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
89 #define I801_START 0x40
90 #define I801_PEC_EN 0x80 /* ICH3 and later */
92 /* I801 Hosts Status register bits */
93 #define SMBHSTSTS_BYTE_DONE 0x80
94 #define SMBHSTSTS_INUSE_STS 0x40
95 #define SMBHSTSTS_SMBALERT_STS 0x20
96 #define SMBHSTSTS_FAILED 0x10
97 #define SMBHSTSTS_BUS_ERR 0x08
98 #define SMBHSTSTS_DEV_ERR 0x04
99 #define SMBHSTSTS_INTR 0x02
100 #define SMBHSTSTS_HOST_BUSY 0x01
102 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
103 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTR)
105 /* Older devices have their ID defined in <linux/pci_ids.h> */
106 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
107 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
108 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
109 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
110 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
111 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
112 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
113 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
114 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
115 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
116 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
118 #define FEATURE_SMBUS_PEC BIT(0)
119 #define FEATURE_BLOCK_BUFFER BIT(1)
120 #define FEATURE_BLOCK_PROC BIT(2)
121 #define FEATURE_I2C_BLOCK_READ BIT(3)
122 /* Not really a feature, but it's convenient to handle it as such */
123 #define FEATURE_IDF BIT(15)
127 #define inb_p(a) readq((void __iomem *)a)
129 #define outb_p(d, a) writeq(d, (void __iomem *)a)
131 /* Make sure the SMBus host is ready to start transmitting.
132 * Return 0 if it is, -EBUSY if it is not.
134 static int i801_check_pre(struct kpc_i2c *priv)
138 status = inb_p(SMBHSTSTS(priv));
139 if (status & SMBHSTSTS_HOST_BUSY) {
140 dev_err(&priv->adapter.dev,
141 "SMBus is busy, can't use it! (status=%x)\n", status);
145 status &= STATUS_FLAGS;
147 outb_p(status, SMBHSTSTS(priv));
148 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
150 dev_err(&priv->adapter.dev,
151 "Failed clearing status flags (%02x)\n", status);
158 /* Convert the status register to an error code, and clear it. */
159 static int i801_check_post(struct kpc_i2c *priv, int status, int timeout)
163 /* If the SMBus is still busy, we give up */
165 dev_err(&priv->adapter.dev, "Transaction timeout\n");
166 /* try to stop the current command */
167 dev_dbg(&priv->adapter.dev,
168 "Terminating the current operation\n");
169 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
171 usleep_range(1000, 2000);
172 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
175 /* Check if it worked */
176 status = inb_p(SMBHSTSTS(priv));
177 if ((status & SMBHSTSTS_HOST_BUSY) ||
178 !(status & SMBHSTSTS_FAILED))
179 dev_err(&priv->adapter.dev,
180 "Failed terminating the transaction\n");
181 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
185 if (status & SMBHSTSTS_FAILED) {
187 dev_err(&priv->adapter.dev, "Transaction failed\n");
189 if (status & SMBHSTSTS_DEV_ERR) {
191 dev_dbg(&priv->adapter.dev, "No response\n");
193 if (status & SMBHSTSTS_BUS_ERR) {
195 dev_dbg(&priv->adapter.dev, "Lost arbitration\n");
199 /* Clear error flags */
200 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
201 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
203 dev_warn(&priv->adapter.dev,
204 "Failed clearing status flags at end of transaction (%02x)\n",
211 static int i801_transaction(struct kpc_i2c *priv, int xact)
217 result = i801_check_pre(priv);
220 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
221 * INTREN, SMBSCMD are passed in xact
223 outb_p(xact | I801_START, SMBHSTCNT(priv));
225 /* We will always wait for a fraction of a second! */
227 usleep_range(250, 500);
228 status = inb_p(SMBHSTSTS(priv));
229 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES));
231 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
235 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
239 /* wait for INTR bit as advised by Intel */
240 static void i801_wait_hwpec(struct kpc_i2c *priv)
246 usleep_range(250, 500);
247 status = inb_p(SMBHSTSTS(priv));
248 } while ((!(status & SMBHSTSTS_INTR)) && (timeout++ < MAX_RETRIES));
250 if (timeout > MAX_RETRIES)
251 dev_dbg(&priv->adapter.dev, "PEC Timeout!\n");
253 outb_p(status, SMBHSTSTS(priv));
256 static int i801_block_transaction_by_block(struct kpc_i2c *priv,
257 union i2c_smbus_data *data,
258 char read_write, int hwpec)
263 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
265 /* Use 32-byte buffer to process this transaction */
266 if (read_write == I2C_SMBUS_WRITE) {
267 len = data->block[0];
268 outb_p(len, SMBHSTDAT0(priv));
269 for (i = 0; i < len; i++)
270 outb_p(data->block[i + 1], SMBBLKDAT(priv));
273 status = i801_transaction(priv,
274 I801_BLOCK_DATA | ENABLE_INT9 | I801_PEC_EN * hwpec);
278 if (read_write == I2C_SMBUS_READ) {
279 len = inb_p(SMBHSTDAT0(priv));
280 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
283 data->block[0] = len;
284 for (i = 0; i < len; i++)
285 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
290 static int i801_block_transaction_byte_by_byte(struct kpc_i2c *priv,
291 union i2c_smbus_data *data,
292 char read_write, int command,
301 result = i801_check_pre(priv);
305 len = data->block[0];
307 if (read_write == I2C_SMBUS_WRITE) {
308 outb_p(len, SMBHSTDAT0(priv));
309 outb_p(data->block[1], SMBBLKDAT(priv));
312 for (i = 1; i <= len; i++) {
313 if (i == len && read_write == I2C_SMBUS_READ) {
314 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
315 smbcmd = I801_I2C_BLOCK_LAST;
317 smbcmd = I801_BLOCK_LAST;
319 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
320 read_write == I2C_SMBUS_READ)
321 smbcmd = I801_I2C_BLOCK_DATA;
323 smbcmd = I801_BLOCK_DATA;
325 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
328 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
330 /* We will always wait for a fraction of a second! */
333 usleep_range(250, 500);
334 status = inb_p(SMBHSTSTS(priv));
335 } while (!(status & SMBHSTSTS_BYTE_DONE) &&
336 (timeout++ < MAX_RETRIES));
338 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
341 if (i == 1 && read_write == I2C_SMBUS_READ &&
342 command != I2C_SMBUS_I2C_BLOCK_DATA) {
343 len = inb_p(SMBHSTDAT0(priv));
344 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
345 dev_err(&priv->adapter.dev,
346 "Illegal SMBus block read size %d\n",
349 while (inb_p(SMBHSTSTS(priv)) &
351 outb_p(SMBHSTSTS_BYTE_DONE,
353 outb_p(SMBHSTSTS_INTR,
357 data->block[0] = len;
360 /* Retrieve/store value in SMBBLKDAT */
361 if (read_write == I2C_SMBUS_READ)
362 data->block[i] = inb_p(SMBBLKDAT(priv));
363 if (read_write == I2C_SMBUS_WRITE && i + 1 <= len)
364 outb_p(data->block[i + 1], SMBBLKDAT(priv));
365 /* signals SMBBLKDAT ready */
366 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
372 static int i801_set_block_buffer_mode(struct kpc_i2c *priv)
374 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
375 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
380 /* Block transaction function */
381 static int i801_block_transaction(struct kpc_i2c *priv,
382 union i2c_smbus_data *data, char read_write,
383 int command, int hwpec)
386 //unsigned char hostc;
388 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
389 if (read_write == I2C_SMBUS_WRITE) {
390 /* set I2C_EN bit in configuration register */
391 //TODO: Figure out the right thing to do here...
392 //pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
393 //pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
394 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
395 dev_err(&priv->adapter.dev,
396 "I2C block read is unsupported!\n");
401 if (read_write == I2C_SMBUS_WRITE ||
402 command == I2C_SMBUS_I2C_BLOCK_DATA) {
403 if (data->block[0] < 1)
405 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
406 data->block[0] = I2C_SMBUS_BLOCK_MAX;
408 data->block[0] = 32; /* max for SMBus block reads */
411 /* Experience has shown that the block buffer can only be used for
412 * SMBus (not I2C) block transactions, even though the datasheet
413 * doesn't mention this limitation.
415 if ((priv->features & FEATURE_BLOCK_BUFFER) &&
416 command != I2C_SMBUS_I2C_BLOCK_DATA &&
417 i801_set_block_buffer_mode(priv) == 0) {
418 result = i801_block_transaction_by_block(priv, data,
421 result = i801_block_transaction_byte_by_byte(priv, data,
426 if (result == 0 && hwpec)
427 i801_wait_hwpec(priv);
428 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
429 read_write == I2C_SMBUS_WRITE) {
430 /* restore saved configuration register value */
431 //TODO: Figure out the right thing to do here...
432 //pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
437 /* Return negative errno on error. */
438 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
439 unsigned short flags, char read_write, u8 command,
440 int size, union i2c_smbus_data *data)
445 struct kpc_i2c *priv = i2c_get_adapdata(adap);
447 hwpec = (priv->features & FEATURE_SMBUS_PEC) &&
448 (flags & I2C_CLIENT_PEC) &&
449 size != I2C_SMBUS_QUICK && size != I2C_SMBUS_I2C_BLOCK_DATA;
452 case I2C_SMBUS_QUICK:
453 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_QUICK\n");
454 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
460 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_BYTE\n");
462 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
464 if (read_write == I2C_SMBUS_WRITE)
465 outb_p(command, SMBHSTCMD(priv));
468 case I2C_SMBUS_BYTE_DATA:
469 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_BYTE_DATA\n");
470 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
473 outb_p(command, SMBHSTCMD(priv));
474 if (read_write == I2C_SMBUS_WRITE)
475 outb_p(data->byte, SMBHSTDAT0(priv));
476 xact = I801_BYTE_DATA;
478 case I2C_SMBUS_WORD_DATA:
479 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_WORD_DATA\n");
480 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
483 outb_p(command, SMBHSTCMD(priv));
484 if (read_write == I2C_SMBUS_WRITE) {
485 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
486 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
488 xact = I801_WORD_DATA;
490 case I2C_SMBUS_BLOCK_DATA:
491 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_BLOCK_DATA\n");
492 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
495 outb_p(command, SMBHSTCMD(priv));
498 case I2C_SMBUS_I2C_BLOCK_DATA:
499 dev_dbg(&priv->adapter.dev, " [acc] SMBUS_I2C_BLOCK_DATA\n");
500 /* NB: page 240 of ICH5 datasheet shows that the R/#W
501 * bit should be cleared here, even when reading
503 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
504 if (read_write == I2C_SMBUS_READ) {
505 /* NB: page 240 of ICH5 datasheet also shows
506 * that DATA1 is the cmd field when reading
508 outb_p(command, SMBHSTDAT1(priv));
510 outb_p(command, SMBHSTCMD(priv));
515 dev_dbg(&priv->adapter.dev,
516 " [acc] Unsupported transaction %d\n", size);
520 if (hwpec) { /* enable/disable hardware PEC */
521 dev_dbg(&priv->adapter.dev, " [acc] hwpec: yes\n");
522 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
524 dev_dbg(&priv->adapter.dev, " [acc] hwpec: no\n");
525 outb_p(inb_p(SMBAUXCTL(priv)) &
526 (~SMBAUXCTL_CRC), SMBAUXCTL(priv));
530 dev_dbg(&priv->adapter.dev, " [acc] block: yes\n");
531 ret = i801_block_transaction(priv, data, read_write, size,
534 dev_dbg(&priv->adapter.dev, " [acc] block: no\n");
535 ret = i801_transaction(priv, xact | ENABLE_INT9);
538 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
539 * time, so we forcibly disable it after every transaction. Turn off
540 * E32B for the same reason.
542 if (hwpec || block) {
543 dev_dbg(&priv->adapter.dev, " [acc] hwpec || block\n");
544 outb_p(inb_p(SMBAUXCTL(priv)) & ~(SMBAUXCTL_CRC |
545 SMBAUXCTL_E32B), SMBAUXCTL(priv));
548 dev_dbg(&priv->adapter.dev, " [acc] block\n");
552 dev_dbg(&priv->adapter.dev, " [acc] ret %d\n", ret);
555 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) {
556 dev_dbg(&priv->adapter.dev,
557 " [acc] I2C_SMBUS_WRITE || I801_QUICK -> ret 0\n");
561 switch (xact & 0x7f) {
562 case I801_BYTE: /* Result put in SMBHSTDAT0 */
564 dev_dbg(&priv->adapter.dev,
565 " [acc] I801_BYTE or I801_BYTE_DATA\n");
566 data->byte = inb_p(SMBHSTDAT0(priv));
569 dev_dbg(&priv->adapter.dev, " [acc] I801_WORD_DATA\n");
570 data->word = inb_p(SMBHSTDAT0(priv)) +
571 (inb_p(SMBHSTDAT1(priv)) << 8);
577 #define enable_flag(x) (x)
578 #define disable_flag(x) 0
579 #define enable_flag_if(x, cond) ((cond) ? (x) : 0)
581 static u32 i801_func(struct i2c_adapter *adapter)
583 struct kpc_i2c *priv = i2c_get_adapdata(adapter);
586 * u32 f = I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
587 * I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
588 * I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
589 * ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
590 * ((priv->features & FEATURE_I2C_BLOCK_READ) ?
591 * I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
594 // http://lxr.free-electrons.com/source/include/uapi/linux/i2c.h#L85
597 enable_flag(I2C_FUNC_I2C) | /* 0x00000001(I enabled this one) */
598 disable_flag(I2C_FUNC_10BIT_ADDR) | /* 0x00000002 */
599 disable_flag(I2C_FUNC_PROTOCOL_MANGLING) | /* 0x00000004 */
600 enable_flag_if(I2C_FUNC_SMBUS_PEC,
601 priv->features & FEATURE_SMBUS_PEC) |
603 disable_flag(I2C_FUNC_SMBUS_BLOCK_PROC_CALL) | /* 0x00008000 */
604 enable_flag(I2C_FUNC_SMBUS_QUICK) | /* 0x00010000 */
605 disable_flag(I2C_FUNC_SMBUS_READ_BYTE) | /* 0x00020000 */
606 disable_flag(I2C_FUNC_SMBUS_WRITE_BYTE) | /* 0x00040000 */
607 disable_flag(I2C_FUNC_SMBUS_READ_BYTE_DATA) | /* 0x00080000 */
608 disable_flag(I2C_FUNC_SMBUS_WRITE_BYTE_DATA) | /* 0x00100000 */
609 disable_flag(I2C_FUNC_SMBUS_READ_WORD_DATA) | /* 0x00200000 */
610 disable_flag(I2C_FUNC_SMBUS_WRITE_WORD_DATA) | /* 0x00400000 */
611 disable_flag(I2C_FUNC_SMBUS_PROC_CALL) | /* 0x00800000 */
612 disable_flag(I2C_FUNC_SMBUS_READ_BLOCK_DATA) | /* 0x01000000 */
613 disable_flag(I2C_FUNC_SMBUS_WRITE_BLOCK_DATA) | /* 0x02000000 */
614 enable_flag_if(I2C_FUNC_SMBUS_READ_I2C_BLOCK,
615 priv->features & FEATURE_I2C_BLOCK_READ) |
617 enable_flag(I2C_FUNC_SMBUS_WRITE_I2C_BLOCK) | /* 0x08000000 */
619 enable_flag(I2C_FUNC_SMBUS_BYTE) | /* _READ_BYTE _WRITE_BYTE */
620 enable_flag(I2C_FUNC_SMBUS_BYTE_DATA) | /* _READ_BYTE_DATA
623 enable_flag(I2C_FUNC_SMBUS_WORD_DATA) | /* _READ_WORD_DATA
626 enable_flag(I2C_FUNC_SMBUS_BLOCK_DATA) | /* _READ_BLOCK_DATA
629 disable_flag(I2C_FUNC_SMBUS_I2C_BLOCK) | /* _READ_I2C_BLOCK
632 disable_flag(I2C_FUNC_SMBUS_EMUL); /* _QUICK _BYTE
633 * _BYTE_DATA _WORD_DATA
643 #undef enable_flag_if
645 static const struct i2c_algorithm smbus_algorithm = {
646 .smbus_xfer = i801_access,
647 .functionality = i801_func,
650 /********************************
651 *** Part 2 - Driver Handlers ***
652 ********************************/
653 static int kpc_i2c_probe(struct platform_device *pldev)
656 struct kpc_i2c *priv;
657 struct resource *res;
659 priv = devm_kzalloc(&pldev->dev, sizeof(*priv), GFP_KERNEL);
663 i2c_set_adapdata(&priv->adapter, priv);
664 priv->adapter.owner = THIS_MODULE;
665 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
666 priv->adapter.algo = &smbus_algorithm;
668 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
672 priv->smba = (unsigned long)devm_ioremap(&pldev->dev,
678 platform_set_drvdata(pldev, priv);
680 priv->features |= FEATURE_IDF;
681 priv->features |= FEATURE_I2C_BLOCK_READ;
682 priv->features |= FEATURE_SMBUS_PEC;
683 priv->features |= FEATURE_BLOCK_BUFFER;
685 //init_MUTEX(&lddata->sem);
687 /* set up the sysfs linkage to our parent device */
688 priv->adapter.dev.parent = &pldev->dev;
690 /* Retry up to 3 times on lost arbitration */
691 priv->adapter.retries = 3;
693 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
694 "Fake SMBus I801 adapter");
696 err = i2c_add_adapter(&priv->adapter);
698 dev_err(&priv->adapter.dev, "Failed to add SMBus adapter\n");
705 static int kpc_i2c_remove(struct platform_device *pldev)
707 struct kpc_i2c *lddev;
709 lddev = (struct kpc_i2c *)platform_get_drvdata(pldev);
711 i2c_del_adapter(&lddev->adapter);
713 //TODO: Figure out the right thing to do here...
714 //pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
715 //pci_release_region(dev, SMBBAR);
716 //pci_set_drvdata(dev, NULL);
718 //cdev_del(&lddev->cdev);
723 static struct platform_driver kpc_i2c_driver = {
724 .probe = kpc_i2c_probe,
725 .remove = kpc_i2c_remove,
727 .name = KP_DRIVER_NAME_I2C,
731 module_platform_driver(kpc_i2c_driver);