2 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 * Copyright 2011-2015 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/iio/adc/ad_sigma_delta.h>
31 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
34 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
35 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
36 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
38 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
39 /* (AD7792)/24-bit (AD7192)) */
40 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
41 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
43 /* Communications Register Bit Designations (AD7192_REG_COMM) */
44 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
45 #define AD7192_COMM_WRITE 0 /* Write Operation */
46 #define AD7192_COMM_READ BIT(6) /* Read Operation */
47 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
50 /* Status Register Bit Designations (AD7192_REG_STAT) */
51 #define AD7192_STAT_RDY BIT(7) /* Ready */
52 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
53 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
54 #define AD7192_STAT_PARITY BIT(4) /* Parity */
55 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
56 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
60 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
61 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
62 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
65 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
66 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
67 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
68 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
69 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
70 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
72 /* Mode Register: AD7192_MODE_SEL options */
73 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
74 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
75 #define AD7192_MODE_IDLE 2 /* Idle Mode */
76 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
77 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
80 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
82 /* Mode Register: AD7192_MODE_CLKSRC options */
83 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
84 /* from MCLK1 to MCLK2 */
85 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
86 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
87 /* available at the MCLK2 pin */
88 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
89 /* at the MCLK2 pin */
91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
93 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
105 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
112 #define AD7193_CH_AIN1P_AIN2M 0x000 /* AIN1(+) - AIN2(-) */
113 #define AD7193_CH_AIN3P_AIN4M 0x001 /* AIN3(+) - AIN4(-) */
114 #define AD7193_CH_AIN5P_AIN6M 0x002 /* AIN5(+) - AIN6(-) */
115 #define AD7193_CH_AIN7P_AIN8M 0x004 /* AIN7(+) - AIN8(-) */
116 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
128 /* ID Register Bit Designations (AD7192_REG_ID) */
129 #define ID_AD7190 0x4
130 #define ID_AD7192 0x0
131 #define ID_AD7193 0x2
132 #define ID_AD7195 0x6
133 #define AD7192_ID_MASK 0x0F
135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
137 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
138 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
144 #define AD7192_INT_FREQ_MHZ 4915200
147 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
148 * In order to avoid contentions on the SPI bus, it's therefore necessary
149 * to use spi bus locking.
151 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
154 struct ad7192_state {
155 struct regulator *reg;
161 u32 scale_avail[8][2];
165 struct ad_sigma_delta sd;
168 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
170 return container_of(sd, struct ad7192_state, sd);
173 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
175 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
177 st->conf &= ~AD7192_CONF_CHAN_MASK;
178 st->conf |= AD7192_CONF_CHAN(channel);
180 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
183 static int ad7192_set_mode(struct ad_sigma_delta *sd,
184 enum ad_sigma_delta_mode mode)
186 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
188 st->mode &= ~AD7192_MODE_SEL_MASK;
189 st->mode |= AD7192_MODE_SEL(mode);
191 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
194 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
195 .set_channel = ad7192_set_channel,
196 .set_mode = ad7192_set_mode,
197 .has_registers = true,
202 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
203 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
204 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
205 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
206 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
207 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
208 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
209 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
210 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
213 static int ad7192_calibrate_all(struct ad7192_state *st)
215 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
216 ARRAY_SIZE(ad7192_calib_arr));
219 static int ad7192_setup(struct ad7192_state *st,
220 const struct ad7192_platform_data *pdata)
222 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
223 unsigned long long scale_uv;
227 /* reset the serial interface */
228 memset(&ones, 0xFF, 6);
229 ret = spi_write(st->sd.spi, &ones, 6);
232 usleep_range(500, 1000); /* Wait for at least 500us */
234 /* write/read test for device presence */
235 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
239 id &= AD7192_ID_MASK;
242 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
245 switch (pdata->clock_source_sel) {
246 case AD7192_CLK_EXT_MCLK1_2:
247 case AD7192_CLK_EXT_MCLK2:
248 st->mclk = AD7192_INT_FREQ_MHZ;
251 case AD7192_CLK_INT_CO:
252 if (pdata->ext_clk_hz)
253 st->mclk = pdata->ext_clk_hz;
255 st->mclk = AD7192_INT_FREQ_MHZ;
262 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
263 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
264 AD7192_MODE_RATE(480);
266 st->conf = AD7192_CONF_GAIN(0);
269 st->mode |= AD7192_MODE_REJ60;
272 st->mode |= AD7192_MODE_SINC3;
274 if (pdata->refin2_en && (st->devid != ID_AD7195))
275 st->conf |= AD7192_CONF_REFSEL;
277 if (pdata->chop_en) {
278 st->conf |= AD7192_CONF_CHOP;
280 st->f_order = 3; /* SINC 3rd order */
282 st->f_order = 4; /* SINC 4th order */
288 st->conf |= AD7192_CONF_BUF;
290 if (pdata->unipolar_en)
291 st->conf |= AD7192_CONF_UNIPOLAR;
293 if (pdata->burnout_curr_en)
294 st->conf |= AD7192_CONF_BURN;
296 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
300 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
304 ret = ad7192_calibrate_all(st);
308 /* Populate available ADC input ranges */
309 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
310 scale_uv = ((u64)st->int_vref_mv * 100000000)
311 >> (indio_dev->channels[0].scan_type.realbits -
312 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
315 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
316 st->scale_avail[i][0] = scale_uv;
321 dev_err(&st->sd.spi->dev, "setup failed\n");
325 static ssize_t ad7192_read_frequency(struct device *dev,
326 struct device_attribute *attr,
329 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
330 struct ad7192_state *st = iio_priv(indio_dev);
332 return sprintf(buf, "%d\n", st->mclk /
333 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
336 static ssize_t ad7192_write_frequency(struct device *dev,
337 struct device_attribute *attr,
341 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
342 struct ad7192_state *st = iio_priv(indio_dev);
346 ret = kstrtoul(buf, 10, &lval);
352 ret = iio_device_claim_direct_mode(indio_dev);
356 div = st->mclk / (lval * st->f_order * 1024);
357 if (div < 1 || div > 1023) {
362 st->mode &= ~AD7192_MODE_RATE(-1);
363 st->mode |= AD7192_MODE_RATE(div);
364 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
367 iio_device_release_direct_mode(indio_dev);
369 return ret ? ret : len;
372 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
373 ad7192_read_frequency,
374 ad7192_write_frequency);
377 ad7192_show_scale_available(struct device *dev,
378 struct device_attribute *attr, char *buf)
380 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
381 struct ad7192_state *st = iio_priv(indio_dev);
384 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
385 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
386 st->scale_avail[i][1]);
388 len += sprintf(buf + len, "\n");
393 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
394 in_voltage-voltage_scale_available,
395 S_IRUGO, ad7192_show_scale_available, NULL, 0);
397 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
398 ad7192_show_scale_available, NULL, 0);
400 static ssize_t ad7192_show_ac_excitation(struct device *dev,
401 struct device_attribute *attr,
404 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
405 struct ad7192_state *st = iio_priv(indio_dev);
407 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
410 static ssize_t ad7192_show_bridge_switch(struct device *dev,
411 struct device_attribute *attr,
414 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
415 struct ad7192_state *st = iio_priv(indio_dev);
417 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
420 static ssize_t ad7192_set(struct device *dev,
421 struct device_attribute *attr,
425 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
426 struct ad7192_state *st = iio_priv(indio_dev);
427 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
431 ret = strtobool(buf, &val);
435 ret = iio_device_claim_direct_mode(indio_dev);
439 switch ((u32)this_attr->address) {
440 case AD7192_REG_GPOCON:
442 st->gpocon |= AD7192_GPOCON_BPDSW;
444 st->gpocon &= ~AD7192_GPOCON_BPDSW;
446 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
448 case AD7192_REG_MODE:
450 st->mode |= AD7192_MODE_ACX;
452 st->mode &= ~AD7192_MODE_ACX;
454 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
460 iio_device_release_direct_mode(indio_dev);
462 return ret ? ret : len;
465 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
466 ad7192_show_bridge_switch, ad7192_set,
469 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
470 ad7192_show_ac_excitation, ad7192_set,
473 static struct attribute *ad7192_attributes[] = {
474 &iio_dev_attr_sampling_frequency.dev_attr.attr,
475 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
476 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
477 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
478 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
482 static const struct attribute_group ad7192_attribute_group = {
483 .attrs = ad7192_attributes,
486 static struct attribute *ad7195_attributes[] = {
487 &iio_dev_attr_sampling_frequency.dev_attr.attr,
488 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
489 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
490 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
494 static const struct attribute_group ad7195_attribute_group = {
495 .attrs = ad7195_attributes,
498 static unsigned int ad7192_get_temp_scale(bool unipolar)
500 return unipolar ? 2815 * 2 : 2815;
503 static int ad7192_read_raw(struct iio_dev *indio_dev,
504 struct iio_chan_spec const *chan,
509 struct ad7192_state *st = iio_priv(indio_dev);
510 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
513 case IIO_CHAN_INFO_RAW:
514 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
515 case IIO_CHAN_INFO_SCALE:
516 switch (chan->type) {
518 mutex_lock(&indio_dev->mlock);
519 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
520 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
521 mutex_unlock(&indio_dev->mlock);
522 return IIO_VAL_INT_PLUS_NANO;
525 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
526 return IIO_VAL_INT_PLUS_NANO;
530 case IIO_CHAN_INFO_OFFSET:
532 *val = -(1 << (chan->scan_type.realbits - 1));
535 /* Kelvin to Celsius */
536 if (chan->type == IIO_TEMP)
537 *val -= 273 * ad7192_get_temp_scale(unipolar);
544 static int ad7192_write_raw(struct iio_dev *indio_dev,
545 struct iio_chan_spec const *chan,
550 struct ad7192_state *st = iio_priv(indio_dev);
554 ret = iio_device_claim_direct_mode(indio_dev);
559 case IIO_CHAN_INFO_SCALE:
561 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
562 if (val2 == st->scale_avail[i][1]) {
565 st->conf &= ~AD7192_CONF_GAIN(-1);
566 st->conf |= AD7192_CONF_GAIN(i);
569 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
571 ad7192_calibrate_all(st);
579 iio_device_release_direct_mode(indio_dev);
584 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
585 struct iio_chan_spec const *chan,
588 return IIO_VAL_INT_PLUS_NANO;
591 static const struct iio_info ad7192_info = {
592 .read_raw = &ad7192_read_raw,
593 .write_raw = &ad7192_write_raw,
594 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
595 .attrs = &ad7192_attribute_group,
596 .validate_trigger = ad_sd_validate_trigger,
597 .driver_module = THIS_MODULE,
600 static const struct iio_info ad7195_info = {
601 .read_raw = &ad7192_read_raw,
602 .write_raw = &ad7192_write_raw,
603 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
604 .attrs = &ad7195_attribute_group,
605 .validate_trigger = ad_sd_validate_trigger,
606 .driver_module = THIS_MODULE,
609 static const struct iio_chan_spec ad7192_channels[] = {
610 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
611 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
612 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
613 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
614 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
615 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
616 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
617 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
618 IIO_CHAN_SOFT_TIMESTAMP(8),
621 static const struct iio_chan_spec ad7193_channels[] = {
622 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
623 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
624 AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
625 AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
626 AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
627 AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
628 AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
629 AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
630 AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
631 AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
632 AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
633 AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
634 AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
635 AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
636 IIO_CHAN_SOFT_TIMESTAMP(14),
639 static int ad7192_probe(struct spi_device *spi)
641 const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
642 struct ad7192_state *st;
643 struct iio_dev *indio_dev;
644 int ret, voltage_uv = 0;
647 dev_err(&spi->dev, "no platform data?\n");
652 dev_err(&spi->dev, "no IRQ?\n");
656 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
660 st = iio_priv(indio_dev);
662 st->reg = devm_regulator_get(&spi->dev, "vcc");
663 if (!IS_ERR(st->reg)) {
664 ret = regulator_enable(st->reg);
668 voltage_uv = regulator_get_voltage(st->reg);
672 st->int_vref_mv = pdata->vref_mv;
674 st->int_vref_mv = voltage_uv / 1000;
676 dev_warn(&spi->dev, "reference voltage undefined\n");
678 spi_set_drvdata(spi, indio_dev);
679 st->devid = spi_get_device_id(spi)->driver_data;
680 indio_dev->dev.parent = &spi->dev;
681 indio_dev->name = spi_get_device_id(spi)->name;
682 indio_dev->modes = INDIO_DIRECT_MODE;
686 indio_dev->channels = ad7193_channels;
687 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
690 indio_dev->channels = ad7192_channels;
691 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
695 if (st->devid == ID_AD7195)
696 indio_dev->info = &ad7195_info;
698 indio_dev->info = &ad7192_info;
700 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
702 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
704 goto error_disable_reg;
706 ret = ad7192_setup(st, pdata);
708 goto error_remove_trigger;
710 ret = iio_device_register(indio_dev);
712 goto error_remove_trigger;
715 error_remove_trigger:
716 ad_sd_cleanup_buffer_and_trigger(indio_dev);
718 if (!IS_ERR(st->reg))
719 regulator_disable(st->reg);
724 static int ad7192_remove(struct spi_device *spi)
726 struct iio_dev *indio_dev = spi_get_drvdata(spi);
727 struct ad7192_state *st = iio_priv(indio_dev);
729 iio_device_unregister(indio_dev);
730 ad_sd_cleanup_buffer_and_trigger(indio_dev);
732 if (!IS_ERR(st->reg))
733 regulator_disable(st->reg);
738 static const struct spi_device_id ad7192_id[] = {
739 {"ad7190", ID_AD7190},
740 {"ad7192", ID_AD7192},
741 {"ad7193", ID_AD7193},
742 {"ad7195", ID_AD7195},
745 MODULE_DEVICE_TABLE(spi, ad7192_id);
747 static struct spi_driver ad7192_driver = {
751 .probe = ad7192_probe,
752 .remove = ad7192_remove,
753 .id_table = ad7192_id,
755 module_spi_driver(ad7192_driver);
757 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
758 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
759 MODULE_LICENSE("GPL v2");