drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24 #include <linux/module.h>
  25
  26 #include "../iio.h"
  27 #include "../sysfs.h"
  28 #include "../events.h"
  29 #include "../buffer.h"
  30
  31 #include "lis3l02dq.h"
  32
  33 /* At the moment the spi framework doesn't allow global setting of cs_change.
  34  * It's in the likely to be added comment at the top of spi.h.
  35  * This means that use cannot be made of spi_write etc.
  36  */
  37 /* direct copy of the irq_default_primary_handler */
  38 #ifndef CONFIG_IIO_BUFFER
  39 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  40 {
  41         return IRQ_WAKE_THREAD;
  42 }
  43 #endif
  44
  45 /**
  46  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  47  * @indio_dev: iio_dev for this actual device
  48  * @reg_address: the address of the register to be read
  49  * @val: pass back the resulting value
  50  **/
  51 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  52                              u8 reg_address, u8 *val)
  53 {
  54         struct lis3l02dq_state *st = iio_priv(indio_dev);
  55         struct spi_message msg;
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         spi_message_init(&msg);
  69         spi_message_add_tail(&xfer, &msg);
  70         ret = spi_sync(st->us, &msg);
  71         *val = st->rx[1];
  72         mutex_unlock(&st->buf_lock);
  73
  74         return ret;
  75 }
  76
  77 /**
  78  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  79  * @indio_dev: iio_dev for this device
  80  * @reg_address: the address of the register to be written
  81  * @val: the value to write
  82  **/
  83 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  84                               u8 reg_address,
  85                               u8 val)
  86 {
  87         int ret;
  88         struct lis3l02dq_state *st = iio_priv(indio_dev);
  89
  90         mutex_lock(&st->buf_lock);
  91         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  92         st->tx[1] = val;
  93         ret = spi_write(st->us, st->tx, 2);
  94         mutex_unlock(&st->buf_lock);
  95
  96         return ret;
  97 }
  98
  99 /**
 100  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 101  * @indio_dev: iio_dev for this device
 102  * @lower_reg_address: the address of the lower of the two registers.
 103  *               Second register is assumed to have address one greater.
 104  * @value: value to be written
 105  **/
 106 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 107                                        u8 lower_reg_address,
 108                                        s16 value)
 109 {
 110         int ret;
 111         struct spi_message msg;
 112         struct lis3l02dq_state *st = iio_priv(indio_dev);
 113         struct spi_transfer xfers[] = { {
 114                         .tx_buf = st->tx,
 115                         .bits_per_word = 8,
 116                         .len = 2,
 117                         .cs_change = 1,
 118                 }, {
 119                         .tx_buf = st->tx + 2,
 120                         .bits_per_word = 8,
 121                         .len = 2,
 122                 },
 123         };
 124
 125         mutex_lock(&st->buf_lock);
 126         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 127         st->tx[1] = value & 0xFF;
 128         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 129         st->tx[3] = (value >> 8) & 0xFF;
 130
 131         spi_message_init(&msg);
 132         spi_message_add_tail(&xfers[0], &msg);
 133         spi_message_add_tail(&xfers[1], &msg);
 134         ret = spi_sync(st->us, &msg);
 135         mutex_unlock(&st->buf_lock);
 136
 137         return ret;
 138 }
 139
 140 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 141                                   u8 lower_reg_address,
 142                                   int *val)
 143 {
 144         struct lis3l02dq_state *st = iio_priv(indio_dev);
 145
 146         struct spi_message msg;
 147         int ret;
 148         s16 tempval;
 149         struct spi_transfer xfers[] = { {
 150                         .tx_buf = st->tx,
 151                         .rx_buf = st->rx,
 152                         .bits_per_word = 8,
 153                         .len = 2,
 154                         .cs_change = 1,
 155                 }, {
 156                         .tx_buf = st->tx + 2,
 157                         .rx_buf = st->rx + 2,
 158                         .bits_per_word = 8,
 159                         .len = 2,
 160                 },
 161         };
 162
 163         mutex_lock(&st->buf_lock);
 164         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 165         st->tx[1] = 0;
 166         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 167         st->tx[3] = 0;
 168
 169         spi_message_init(&msg);
 170         spi_message_add_tail(&xfers[0], &msg);
 171         spi_message_add_tail(&xfers[1], &msg);
 172         ret = spi_sync(st->us, &msg);
 173         if (ret) {
 174                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 175                 goto error_ret;
 176         }
 177         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 178
 179         *val = tempval;
 180 error_ret:
 181         mutex_unlock(&st->buf_lock);
 182         return ret;
 183 }
 184
 185 enum lis3l02dq_rm_ind {
 186         LIS3L02DQ_ACCEL,
 187         LIS3L02DQ_GAIN,
 188         LIS3L02DQ_BIAS,
 189 };
 190
 191 static u8 lis3l02dq_axis_map[3][3] = {
 192         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 193                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 194                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 195         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 196                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 197                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 198         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 199                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 200                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 201 };
 202
 203 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 204                                  u64 e,
 205                                  int *val)
 206 {
 207         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 208 }
 209
 210 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 211                                   u64 event_code,
 212                                   int val)
 213 {
 214         u16 value = val;
 215         return lis3l02dq_spi_write_reg_s16(indio_dev,
 216                                            LIS3L02DQ_REG_THS_L_ADDR,
 217                                            value);
 218 }
 219
 220 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 221                                struct iio_chan_spec const *chan,
 222                                int val,
 223                                int val2,
 224                                long mask)
 225 {
 226         int ret = -EINVAL, reg;
 227         u8 uval;
 228         s8 sval;
 229         switch (mask) {
 230         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 231                 if (val > 255 || val < -256)
 232                         return -EINVAL;
 233                 sval = val;
 234                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 235                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 236                 break;
 237         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 238                 if (val & ~0xFF)
 239                         return -EINVAL;
 240                 uval = val;
 241                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 242                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 243                 break;
 244         }
 245         return ret;
 246 }
 247
 248 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 249                               struct iio_chan_spec const *chan,
 250                               int *val,
 251                               int *val2,
 252                               long mask)
 253 {
 254         u8 utemp;
 255         s8 stemp;
 256         ssize_t ret = 0;
 257         u8 reg;
 258
 259         switch (mask) {
 260         case 0:
 261                 /* Take the iio_dev status lock */
 262                 mutex_lock(&indio_dev->mlock);
 263                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
 264                         ret = lis3l02dq_read_accel_from_buffer(indio_dev->
 265                                                                buffer,
 266                                                                chan->scan_index,
 267                                                                val);
 268                 else {
 269                         reg = lis3l02dq_axis_map
 270                                 [LIS3L02DQ_ACCEL][chan->address];
 271                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 272                 }
 273                 mutex_unlock(&indio_dev->mlock);
 274                 return IIO_VAL_INT;
 275         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 276                 *val = 0;
 277                 *val2 = 9580;
 278                 return IIO_VAL_INT_PLUS_MICRO;
 279         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 280                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 281                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 282                 if (ret)
 283                         goto error_ret;
 284                 /* to match with what previous code does */
 285                 *val = utemp;
 286                 return IIO_VAL_INT;
 287
 288         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 289                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 290                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 291                 /* to match with what previous code does */
 292                 *val = stemp;
 293                 return IIO_VAL_INT;
 294         }
 295 error_ret:
 296         return ret;
 297 }
 298
 299 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 300                                         struct device_attribute *attr,
 301                                         char *buf)
 302 {
 303         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 304         int ret, len = 0;
 305         s8 t;
 306         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 307                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 308                                        (u8 *)&t);
 309         if (ret)
 310                 return ret;
 311         t &= LIS3L02DQ_DEC_MASK;
 312         switch (t) {
 313         case LIS3L02DQ_REG_CTRL_1_DF_128:
 314                 len = sprintf(buf, "280\n");
 315                 break;
 316         case LIS3L02DQ_REG_CTRL_1_DF_64:
 317                 len = sprintf(buf, "560\n");
 318                 break;
 319         case LIS3L02DQ_REG_CTRL_1_DF_32:
 320                 len = sprintf(buf, "1120\n");
 321                 break;
 322         case LIS3L02DQ_REG_CTRL_1_DF_8:
 323                 len = sprintf(buf, "4480\n");
 324                 break;
 325         }
 326         return len;
 327 }
 328
 329 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 330                                          struct device_attribute *attr,
 331                                          const char *buf,
 332                                          size_t len)
 333 {
 334         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 335         long val;
 336         int ret;
 337         u8 t;
 338
 339         ret = strict_strtol(buf, 10, &val);
 340         if (ret)
 341                 return ret;
 342
 343         mutex_lock(&indio_dev->mlock);
 344         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 345                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 346                                        &t);
 347         if (ret)
 348                 goto error_ret_mutex;
 349         /* Wipe the bits clean */
 350         t &= ~LIS3L02DQ_DEC_MASK;
 351         switch (val) {
 352         case 280:
 353                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 354                 break;
 355         case 560:
 356                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 357                 break;
 358         case 1120:
 359                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 360                 break;
 361         case 4480:
 362                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 363                 break;
 364         default:
 365                 ret = -EINVAL;
 366                 goto error_ret_mutex;
 367         }
 368
 369         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 370                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 371                                         t);
 372
 373 error_ret_mutex:
 374         mutex_unlock(&indio_dev->mlock);
 375
 376         return ret ? ret : len;
 377 }
 378
 379 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 380 {
 381         struct lis3l02dq_state *st = iio_priv(indio_dev);
 382         int ret;
 383         u8 val, valtest;
 384
 385         st->us->mode = SPI_MODE_3;
 386
 387         spi_setup(st->us);
 388
 389         val = LIS3L02DQ_DEFAULT_CTRL1;
 390         /* Write suitable defaults to ctrl1 */
 391         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 392                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 393                                         val);
 394         if (ret) {
 395                 dev_err(&st->us->dev, "problem with setup control register 1");
 396                 goto err_ret;
 397         }
 398         /* Repeat as sometimes doesn't work first time?*/
 399         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 400                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 401                                         val);
 402         if (ret) {
 403                 dev_err(&st->us->dev, "problem with setup control register 1");
 404                 goto err_ret;
 405         }
 406
 407         /* Read back to check this has worked acts as loose test of correct
 408          * chip */
 409         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 410                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 411                                        &valtest);
 412         if (ret || (valtest != val)) {
 413                 dev_err(&indio_dev->dev,
 414                         "device not playing ball %d %d\n", valtest, val);
 415                 ret = -EINVAL;
 416                 goto err_ret;
 417         }
 418
 419         val = LIS3L02DQ_DEFAULT_CTRL2;
 420         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 421                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 422                                         val);
 423         if (ret) {
 424                 dev_err(&st->us->dev, "problem with setup control register 2");
 425                 goto err_ret;
 426         }
 427
 428         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 429         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 430                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 431                                         val);
 432         if (ret)
 433                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 434 err_ret:
 435
 436         return ret;
 437 }
 438
 439 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 440                               lis3l02dq_read_frequency,
 441                               lis3l02dq_write_frequency);
 442
 443 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 444
 445 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 446 {
 447         struct iio_dev *indio_dev = private;
 448         u8 t;
 449
 450         s64 timestamp = iio_get_time_ns();
 451
 452         lis3l02dq_spi_read_reg_8(indio_dev,
 453                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 454                                  &t);
 455
 456         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 457                 iio_push_event(indio_dev,
 458                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 459                                                   0,
 460                                                   IIO_MOD_Z,
 461                                                   IIO_EV_TYPE_THRESH,
 462                                                   IIO_EV_DIR_RISING),
 463                                timestamp);
 464
 465         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 466                 iio_push_event(indio_dev,
 467                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 468                                                   0,
 469                                                   IIO_MOD_Z,
 470                                                   IIO_EV_TYPE_THRESH,
 471                                                   IIO_EV_DIR_FALLING),
 472                                timestamp);
 473
 474         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 475                 iio_push_event(indio_dev,
 476                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 477                                                   0,
 478                                                   IIO_MOD_Y,
 479                                                   IIO_EV_TYPE_THRESH,
 480                                                   IIO_EV_DIR_RISING),
 481                                timestamp);
 482
 483         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 484                 iio_push_event(indio_dev,
 485                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 486                                                   0,
 487                                                   IIO_MOD_Y,
 488                                                   IIO_EV_TYPE_THRESH,
 489                                                   IIO_EV_DIR_FALLING),
 490                                timestamp);
 491
 492         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 493                 iio_push_event(indio_dev,
 494                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 495                                                   0,
 496                                                   IIO_MOD_X,
 497                                                   IIO_EV_TYPE_THRESH,
 498                                                   IIO_EV_DIR_RISING),
 499                                timestamp);
 500
 501         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 502                 iio_push_event(indio_dev,
 503                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 504                                                   0,
 505                                                   IIO_MOD_X,
 506                                                   IIO_EV_TYPE_THRESH,
 507                                                   IIO_EV_DIR_FALLING),
 508                                timestamp);
 509
 510         /* Ack and allow for new interrupts */
 511         lis3l02dq_spi_read_reg_8(indio_dev,
 512                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 513                                  &t);
 514
 515         return IRQ_HANDLED;
 516 }
 517
 518 #define LIS3L02DQ_INFO_MASK                             \
 519         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 520          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 521          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 522
 523 #define LIS3L02DQ_EVENT_MASK                                    \
 524         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 525          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 526
 527 static struct iio_chan_spec lis3l02dq_channels[] = {
 528         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 529                  0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 530         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 531                  1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 532         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 533                  2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 534         IIO_CHAN_SOFT_TIMESTAMP(3)
 535 };
 536
 537
 538 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 539                                            u64 event_code)
 540 {
 541
 542         u8 val;
 543         int ret;
 544         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 545                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 546                           IIO_EV_DIR_RISING)));
 547         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 548                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 549                                        &val);
 550         if (ret < 0)
 551                 return ret;
 552
 553         return !!(val & mask);
 554 }
 555
 556 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 557 {
 558         int ret;
 559         u8 control, val;
 560
 561         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 562                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 563                                        &control);
 564
 565         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 566         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 567                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 568                                         control);
 569         if (ret)
 570                 goto error_ret;
 571         /* Also for consistency clear the mask */
 572         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 573                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 574                                        &val);
 575         if (ret)
 576                 goto error_ret;
 577         val &= ~0x3f;
 578
 579         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 580                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 581                                         val);
 582         if (ret)
 583                 goto error_ret;
 584
 585         ret = control;
 586 error_ret:
 587         return ret;
 588 }
 589
 590 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 591                                         u64 event_code,
 592                                         int state)
 593 {
 594         int ret = 0;
 595         u8 val, control;
 596         u8 currentlyset;
 597         bool changed = false;
 598         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 599                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 600                           IIO_EV_DIR_RISING)));
 601
 602         mutex_lock(&indio_dev->mlock);
 603         /* read current control */
 604         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 605                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 606                                        &control);
 607         if (ret)
 608                 goto error_ret;
 609         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 610                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 611                                        &val);
 612         if (ret < 0)
 613                 goto error_ret;
 614         currentlyset = val & mask;
 615
 616         if (!currentlyset && state) {
 617                 changed = true;
 618                 val |= mask;
 619         } else if (currentlyset && !state) {
 620                 changed = true;
 621                 val &= ~mask;
 622         }
 623
 624         if (changed) {
 625                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 626                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 627                                                 val);
 628                 if (ret)
 629                         goto error_ret;
 630                 control = val & 0x3f ?
 631                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 632                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 633                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 634                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 635                                                control);
 636                 if (ret)
 637                         goto error_ret;
 638         }
 639
 640 error_ret:
 641         mutex_unlock(&indio_dev->mlock);
 642         return ret;
 643 }
 644
 645 static struct attribute *lis3l02dq_attributes[] = {
 646         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 647         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 648         NULL
 649 };
 650
 651 static const struct attribute_group lis3l02dq_attribute_group = {
 652         .attrs = lis3l02dq_attributes,
 653 };
 654
 655 static const struct iio_info lis3l02dq_info = {
 656         .read_raw = &lis3l02dq_read_raw,
 657         .write_raw = &lis3l02dq_write_raw,
 658         .read_event_value = &lis3l02dq_read_thresh,
 659         .write_event_value = &lis3l02dq_write_thresh,
 660         .write_event_config = &lis3l02dq_write_event_config,
 661         .read_event_config = &lis3l02dq_read_event_config,
 662         .driver_module = THIS_MODULE,
 663         .attrs = &lis3l02dq_attribute_group,
 664 };
 665
 666 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 667 {
 668         int ret;
 669         struct lis3l02dq_state *st;
 670         struct iio_dev *indio_dev;
 671
 672         indio_dev = iio_allocate_device(sizeof *st);
 673         if (indio_dev == NULL) {
 674                 ret = -ENOMEM;
 675                 goto error_ret;
 676         }
 677         st = iio_priv(indio_dev);
 678         /* this is only used tor removal purposes */
 679         spi_set_drvdata(spi, indio_dev);
 680
 681         st->us = spi;
 682         mutex_init(&st->buf_lock);
 683         indio_dev->name = spi->dev.driver->name;
 684         indio_dev->dev.parent = &spi->dev;
 685         indio_dev->info = &lis3l02dq_info;
 686         indio_dev->channels = lis3l02dq_channels;
 687         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 688
 689         indio_dev->modes = INDIO_DIRECT_MODE;
 690
 691         ret = lis3l02dq_configure_buffer(indio_dev);
 692         if (ret)
 693                 goto error_free_dev;
 694
 695         ret = iio_buffer_register(indio_dev,
 696                                   lis3l02dq_channels,
 697                                   ARRAY_SIZE(lis3l02dq_channels));
 698         if (ret) {
 699                 printk(KERN_ERR "failed to initialize the buffer\n");
 700                 goto error_unreg_buffer_funcs;
 701         }
 702
 703         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 704                 ret = request_threaded_irq(st->us->irq,
 705                                            &lis3l02dq_th,
 706                                            &lis3l02dq_event_handler,
 707                                            IRQF_TRIGGER_RISING,
 708                                            "lis3l02dq",
 709                                            indio_dev);
 710                 if (ret)
 711                         goto error_uninitialize_buffer;
 712
 713                 ret = lis3l02dq_probe_trigger(indio_dev);
 714                 if (ret)
 715                         goto error_free_interrupt;
 716         }
 717
 718         /* Get the device into a sane initial state */
 719         ret = lis3l02dq_initial_setup(indio_dev);
 720         if (ret)
 721                 goto error_remove_trigger;
 722
 723         ret = iio_device_register(indio_dev);
 724         if (ret)
 725                 goto error_remove_trigger;
 726
 727         return 0;
 728
 729 error_remove_trigger:
 730         if (indio_dev->modes & INDIO_BUFFER_TRIGGERED)
 731                 lis3l02dq_remove_trigger(indio_dev);
 732 error_free_interrupt:
 733         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 734                 free_irq(st->us->irq, indio_dev);
 735 error_uninitialize_buffer:
 736         iio_buffer_unregister(indio_dev);
 737 error_unreg_buffer_funcs:
 738         lis3l02dq_unconfigure_buffer(indio_dev);
 739 error_free_dev:
 740         iio_free_device(indio_dev);
 741 error_ret:
 742         return ret;
 743 }
 744
 745 /* Power down the device */
 746 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 747 {
 748         int ret;
 749         struct lis3l02dq_state *st = iio_priv(indio_dev);
 750         u8 val = 0;
 751
 752         mutex_lock(&indio_dev->mlock);
 753         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 754                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 755                                         val);
 756         if (ret) {
 757                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 758                 goto err_ret;
 759         }
 760
 761         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 762                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 763                                         val);
 764         if (ret)
 765                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 766 err_ret:
 767         mutex_unlock(&indio_dev->mlock);
 768         return ret;
 769 }
 770
 771 /* fixme, confirm ordering in this function */
 772 static int lis3l02dq_remove(struct spi_device *spi)
 773 {
 774         int ret;
 775         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 776         struct lis3l02dq_state *st = iio_priv(indio_dev);
 777
 778         iio_device_unregister(indio_dev);
 779
 780         ret = lis3l02dq_disable_all_events(indio_dev);
 781         if (ret)
 782                 goto err_ret;
 783
 784         ret = lis3l02dq_stop_device(indio_dev);
 785         if (ret)
 786                 goto err_ret;
 787
 788         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 789                 free_irq(st->us->irq, indio_dev);
 790
 791         lis3l02dq_remove_trigger(indio_dev);
 792         iio_buffer_unregister(indio_dev);
 793         lis3l02dq_unconfigure_buffer(indio_dev);
 794
 795         iio_free_device(indio_dev);
 796 err_ret:
 797         return ret;
 798 }
 799
 800 static struct spi_driver lis3l02dq_driver = {
 801         .driver = {
 802                 .name = "lis3l02dq",
 803                 .owner = THIS_MODULE,
 804         },
 805         .probe = lis3l02dq_probe,
 806         .remove = __devexit_p(lis3l02dq_remove),
 807 };
 808
 809 static __init int lis3l02dq_init(void)
 810 {
 811         return spi_register_driver(&lis3l02dq_driver);
 812 }
 813 module_init(lis3l02dq_init);
 814
 815 static __exit void lis3l02dq_exit(void)
 816 {
 817         spi_unregister_driver(&lis3l02dq_driver);
 818 }
 819 module_exit(lis3l02dq_exit);
 820
 821 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 822 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 823 MODULE_LICENSE("GPL v2");