3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_initpci.c - Routines and data used to register the driver with the
12 * PCI (and PCI Express) subsystem, as well as basic driver
15 *------------------------------------------------------------------------------
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
24 * Copyright © 2005 Agere Systems Inc.
25 * All rights reserved.
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
45 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
60 #include "et131x_version.h"
61 #include "et131x_defs.h"
63 #include <linux/pci.h>
64 #include <linux/init.h>
65 #include <linux/module.h>
66 #include <linux/types.h>
67 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/ptrace.h>
71 #include <linux/ctype.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/interrupt.h>
76 #include <linux/delay.h>
78 #include <linux/bitops.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
86 #include <linux/random.h>
88 #include "et1310_phy.h"
90 #include "et131x_adapter.h"
92 #include "et1310_address_map.h"
93 #include "et1310_tx.h"
94 #include "et1310_rx.h"
97 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
98 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
100 /* Defines for Parameter Default/Min/Max vaules */
101 #define PARM_SPEED_DUPLEX_MIN 0
102 #define PARM_SPEED_DUPLEX_MAX 5
104 /* Module parameter for manual speed setting
105 * Set Link speed and dublex manually (0-5) [0]
106 * 1 : 10Mb Half-Duplex
107 * 2 : 10Mb Full-Duplex
108 * 3 : 100Mb Half-Duplex
109 * 4 : 100Mb Full-Duplex
110 * 5 : 1000Mb Full-Duplex
111 * 0 : Auto Speed Auto Duplex // default
113 static u32 et131x_speed_set;
114 module_param(et131x_speed_set, uint, 0);
115 MODULE_PARM_DESC(et131x_speed_set,
116 "Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
119 * et131x_hwaddr_init - set up the MAC Address on the ET1310
120 * @adapter: pointer to our private adapter structure
122 void et131x_hwaddr_init(struct et131x_adapter *adapter)
124 /* If have our default mac from init and no mac address from
125 * EEPROM then we need to generate the last octet and set it on the
128 if (adapter->PermanentAddress[0] == 0x00 &&
129 adapter->PermanentAddress[1] == 0x00 &&
130 adapter->PermanentAddress[2] == 0x00 &&
131 adapter->PermanentAddress[3] == 0x00 &&
132 adapter->PermanentAddress[4] == 0x00 &&
133 adapter->PermanentAddress[5] == 0x00) {
135 * We need to randomly generate the last octet so we
136 * decrease our chances of setting the mac address to
137 * same as another one of our cards in the system
139 get_random_bytes(&adapter->CurrentAddress[5], 1);
141 * We have the default value in the register we are
142 * working with so we need to copy the current
143 * address into the permanent address
145 memcpy(adapter->PermanentAddress,
146 adapter->CurrentAddress, ETH_ALEN);
148 /* We do not have an override address, so set the
149 * current address to the permanent address and add
152 memcpy(adapter->CurrentAddress,
153 adapter->PermanentAddress, ETH_ALEN);
159 * et131x_pci_init - initial PCI setup
160 * @adapter: pointer to our private adapter structure
161 * @pdev: our PCI device
163 * Perform the initial setup of PCI registers and if possible initialise
164 * the MAC address. At this point the I/O registers have yet to be mapped
167 static int et131x_pci_init(struct et131x_adapter *adapter,
168 struct pci_dev *pdev)
174 if (et131x_init_eeprom(adapter) < 0)
177 /* Let's set up the PORT LOGIC Register. First we need to know what
178 * the max_payload_size is
180 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
182 "Could not read PCI config space for Max Payload Size\n");
186 /* Program the Ack/Nak latency and replay timers */
187 max_payload &= 0x07; /* Only the lower 3 bits are valid */
189 if (max_payload < 2) {
190 static const u16 AckNak[2] = { 0x76, 0xD0 };
191 static const u16 Replay[2] = { 0x1E0, 0x2ED };
193 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
194 AckNak[max_payload])) {
196 "Could not write PCI config space for ACK/NAK\n");
199 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
200 Replay[max_payload])) {
202 "Could not write PCI config space for Replay Timer\n");
207 /* l0s and l1 latency timers. We are using default values.
208 * Representing 001 for L0s and 010 for L1
210 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
212 "Could not write PCI config space for Latency Timers\n");
216 /* Change the max read size to 2k */
217 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
219 "Could not read PCI config space for Max read size\n");
223 read_size_reg &= 0x8f;
224 read_size_reg |= 0x40;
226 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
228 "Could not write PCI config space for Max read size\n");
232 /* Get MAC address from config space if an eeprom exists, otherwise
233 * the MAC address there will not be valid
235 if (!adapter->has_eeprom) {
236 et131x_hwaddr_init(adapter);
240 for (i = 0; i < ETH_ALEN; i++) {
241 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
242 adapter->PermanentAddress + i)) {
243 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
247 memcpy(adapter->CurrentAddress, adapter->PermanentAddress, ETH_ALEN);
252 * et131x_error_timer_handler
253 * @data: timer-specific variable; here a pointer to our adapter structure
255 * The routine called when the error timer expires, to track the number of
258 void et131x_error_timer_handler(unsigned long data)
260 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
263 pm_csr = readl(&etdev->regs->global.pm_csr);
265 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
266 UpdateMacStatHostCounters(etdev);
268 dev_err(&etdev->pdev->dev,
269 "No interrupts, in PHY coma, pm_csr = 0x%x\n", pm_csr);
271 if (!etdev->Bmsr.bits.link_status &&
272 etdev->RegistryPhyComa &&
273 etdev->PoMgmt.TransPhyComaModeOnBoot < 11) {
274 etdev->PoMgmt.TransPhyComaModeOnBoot++;
277 if (etdev->PoMgmt.TransPhyComaModeOnBoot == 10) {
278 if (!etdev->Bmsr.bits.link_status
279 && etdev->RegistryPhyComa) {
280 if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
281 /* NOTE - This was originally a 'sync with
282 * interrupt'. How to do that under Linux?
284 et131x_enable_interrupts(etdev);
285 EnablePhyComa(etdev);
290 /* This is a periodic timer, so reschedule */
291 mod_timer(&etdev->ErrorTimer, jiffies +
292 TX_ERROR_PERIOD * HZ / 1000);
296 * et131x_link_detection_handler
298 * Timer function for link up at driver load time
300 void et131x_link_detection_handler(unsigned long data)
302 struct et131x_adapter *etdev = (struct et131x_adapter *) data;
305 if (etdev->MediaState == 0) {
306 spin_lock_irqsave(&etdev->Lock, flags);
308 etdev->MediaState = NETIF_STATUS_MEDIA_DISCONNECT;
309 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
311 spin_unlock_irqrestore(&etdev->Lock, flags);
313 netif_carrier_off(etdev->netdev);
318 * et131x_configure_global_regs - configure JAGCore global regs
319 * @etdev: pointer to our adapter structure
321 * Used to configure the global registers on the JAGCore
323 void ConfigGlobalRegs(struct et131x_adapter *etdev)
325 struct global_regs __iomem *regs = &etdev->regs->global;
327 writel(0, ®s->rxq_start_addr);
328 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
330 if (etdev->RegistryJumboPacket < 2048) {
331 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
332 * block of RAM that the driver can split between Tx
333 * and Rx as it desires. Our default is to split it
336 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
337 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
338 } else if (etdev->RegistryJumboPacket < 8192) {
339 /* For jumbo packets > 2k but < 8k, split 50-50. */
340 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
341 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
343 /* 9216 is the only packet size greater than 8k that
344 * is available. The Tx buffer has to be big enough
345 * for one whole packet on the Tx side. We'll make
346 * the Tx 9408, and give the rest to Rx
348 writel(0x01b3, ®s->rxq_end_addr);
349 writel(0x01b4, ®s->txq_start_addr);
352 /* Initialize the loopback register. Disable all loopbacks. */
353 writel(0, ®s->loopback);
356 writel(0, ®s->msi_config);
358 /* By default, disable the watchdog timer. It will be enabled when
359 * a packet is queued.
361 writel(0, ®s->watchdog_timer);
366 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
367 * @adapter: pointer to our private adapter structure
369 * Returns 0 on success, errno on failure (as defined in errno.h)
371 int et131x_adapter_setup(struct et131x_adapter *etdev)
375 /* Configure the JAGCore */
376 ConfigGlobalRegs(etdev);
378 ConfigMACRegs1(etdev);
380 /* Configure the MMC registers */
381 /* All we need to do is initialize the Memory Control Register */
382 writel(ET_MMC_ENABLE, &etdev->regs->mmc.mmc_ctrl);
384 ConfigRxMacRegs(etdev);
385 ConfigTxMacRegs(etdev);
387 ConfigRxDmaRegs(etdev);
388 ConfigTxDmaRegs(etdev);
390 ConfigMacStatRegs(etdev);
392 /* Move the following code to Timer function?? */
393 status = et131x_xcvr_find(etdev);
396 dev_warn(&etdev->pdev->dev, "Could not find the xcvr\n");
398 /* Prepare the TRUEPHY library. */
399 ET1310_PhyInit(etdev);
401 /* Reset the phy now so changes take place */
402 ET1310_PhyReset(etdev);
405 ET1310_PhyPowerDown(etdev, 1);
408 * We need to turn off 1000 base half dulplex, the mac does not
409 * support it. For the 10/100 part, turn off all gig advertisement
411 if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
412 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
414 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
417 ET1310_PhyPowerDown(etdev, 0);
419 et131x_setphy_normal(etdev);
424 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
425 * @adapter: pointer to our private adapter structure
427 void et131x_soft_reset(struct et131x_adapter *adapter)
429 /* Disable MAC Core */
430 writel(0xc00f0000, &adapter->regs->mac.cfg1);
432 /* Set everything to a reset value */
433 writel(0x7F, &adapter->regs->global.sw_reset);
434 writel(0x000f0000, &adapter->regs->mac.cfg1);
435 writel(0x00000000, &adapter->regs->mac.cfg1);
439 * et131x_align_allocated_memory - Align allocated memory on a given boundary
440 * @adapter: pointer to our adapter structure
441 * @phys_addr: pointer to Physical address
442 * @offset: pointer to the offset variable
443 * @mask: correct mask
445 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
447 uint64_t *offset, uint64_t mask)
453 new_addr = *phys_addr & ~mask;
455 if (new_addr != *phys_addr) {
456 /* Move to next aligned block */
457 new_addr += mask + 1;
458 /* Return offset for adjusting virt addr */
459 *offset = new_addr - *phys_addr;
460 /* Return new physical address */
461 *phys_addr = new_addr;
466 * et131x_adapter_memory_alloc
467 * @adapter: pointer to our private adapter structure
469 * Returns 0 on success, errno on failure (as defined in errno.h).
471 * Allocate all the memory blocks for send, receive and others.
473 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
477 /* Allocate memory for the Tx Ring */
478 status = et131x_tx_dma_memory_alloc(adapter);
480 dev_err(&adapter->pdev->dev,
481 "et131x_tx_dma_memory_alloc FAILED\n");
484 /* Receive buffer memory allocation */
485 status = et131x_rx_dma_memory_alloc(adapter);
487 dev_err(&adapter->pdev->dev,
488 "et131x_rx_dma_memory_alloc FAILED\n");
489 et131x_tx_dma_memory_free(adapter);
493 /* Init receive data structures */
494 status = et131x_init_recv(adapter);
496 dev_err(&adapter->pdev->dev,
497 "et131x_init_recv FAILED\n");
498 et131x_tx_dma_memory_free(adapter);
499 et131x_rx_dma_memory_free(adapter);
505 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
506 * @adapter: pointer to our private adapter structure
508 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
510 /* Free DMA memory */
511 et131x_tx_dma_memory_free(adapter);
512 et131x_rx_dma_memory_free(adapter);
518 * et131x_adapter_init
519 * @etdev: pointer to the private adapter struct
520 * @pdev: pointer to the PCI device
522 * Initialize the data structures for the et131x_adapter object and link
523 * them together with the platform provided device structures.
527 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
528 struct pci_dev *pdev)
530 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
531 static const u8 duplex[] = { 0, 1, 2, 1, 2, 2 };
532 static const u16 speed[] = { 0, 10, 10, 100, 100, 1000 };
534 struct et131x_adapter *etdev;
536 /* Setup the fundamental net_device and private adapter structure elements */
537 SET_NETDEV_DEV(netdev, &pdev->dev);
539 /* Allocate private adapter struct and copy in relevant information */
540 etdev = netdev_priv(netdev);
541 etdev->pdev = pci_dev_get(pdev);
542 etdev->netdev = netdev;
544 /* Do the same for the netdev struct */
545 netdev->irq = pdev->irq;
546 netdev->base_addr = pci_resource_start(pdev, 0);
548 /* Initialize spinlocks here */
549 spin_lock_init(&etdev->Lock);
550 spin_lock_init(&etdev->TCBSendQLock);
551 spin_lock_init(&etdev->TCBReadyQLock);
552 spin_lock_init(&etdev->SendHWLock);
553 spin_lock_init(&etdev->RcvLock);
554 spin_lock_init(&etdev->RcvPendLock);
555 spin_lock_init(&etdev->FbrLock);
556 spin_lock_init(&etdev->PHYLock);
558 /* Parse configuration parameters into the private adapter struct */
559 if (et131x_speed_set)
560 dev_info(&etdev->pdev->dev,
561 "Speed set manually to : %d \n", et131x_speed_set);
563 etdev->SpeedDuplex = et131x_speed_set;
564 etdev->RegistryJumboPacket = 1514; /* 1514-9216 */
566 /* Set the MAC address to a default */
567 memcpy(etdev->CurrentAddress, default_mac, ETH_ALEN);
569 /* Decode SpeedDuplex
571 * Set up as if we are auto negotiating always and then change if we
574 * If we are the 10/100 device, and gigabit is somehow requested then
575 * knock it down to 100 full.
577 if (etdev->pdev->device == ET131X_PCI_DEVICE_ID_FAST &&
578 etdev->SpeedDuplex == 5)
579 etdev->SpeedDuplex = 4;
581 etdev->AiForceSpeed = speed[etdev->SpeedDuplex];
582 etdev->AiForceDpx = duplex[etdev->SpeedDuplex]; /* Auto FDX */
588 * et131x_pci_setup - Perform device initialization
589 * @pdev: a pointer to the device's pci_dev structure
590 * @ent: this device's entry in the pci_device_id table
592 * Returns 0 on success, errno on failure (as defined in errno.h)
594 * Registered in the pci_driver structure, this function is called when the
595 * PCI subsystem finds a new PCI device which matches the information
596 * contained in the pci_device_id table. This routine is the equivalent to
597 * a device insertion routine.
600 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
601 const struct pci_device_id *ent)
606 struct net_device *netdev;
607 struct et131x_adapter *adapter;
609 /* Enable the device via the PCI subsystem */
610 if (pci_enable_device(pdev) != 0) {
612 "pci_enable_device() failed\n");
616 /* Perform some basic PCI checks */
617 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
619 "Can't find PCI device's base address\n");
623 if (pci_request_regions(pdev, DRIVER_NAME)) {
625 "Can't get PCI resources\n");
629 /* Enable PCI bus mastering */
630 pci_set_master(pdev);
632 /* Query PCI for Power Mgmt Capabilities
634 * NOTE: Now reading PowerMgmt in another location; is this still
637 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
640 "Cannot find Power Management capabilities\n");
642 goto err_release_res;
645 /* Check the DMA addressing support of this device */
646 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
647 pci_using_dac = true;
649 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
652 "Unable to obtain 64 bit DMA for consistent allocations\n");
653 goto err_release_res;
655 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
656 pci_using_dac = false;
659 "No usable DMA addressing method\n");
661 goto err_release_res;
664 /* Allocate netdev and private adapter structs */
665 netdev = et131x_device_alloc();
666 if (netdev == NULL) {
667 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
669 goto err_release_res;
671 adapter = et131x_adapter_init(netdev, pdev);
672 /* Initialise the PCI setup for the device */
673 et131x_pci_init(adapter, pdev);
675 /* Map the bus-relative registers to system virtual memory */
676 adapter->regs = pci_ioremap_bar(pdev, 0);
677 if (adapter->regs == NULL) {
678 dev_err(&pdev->dev, "Cannot map device registers\n");
683 /* If Phy COMA mode was enabled when we went down, disable it here. */
684 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
686 /* Issue a global reset to the et1310 */
687 et131x_soft_reset(adapter);
689 /* Disable all interrupts (paranoid) */
690 et131x_disable_interrupts(adapter);
692 /* Allocate DMA memory */
693 result = et131x_adapter_memory_alloc(adapter);
695 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
699 /* Init send data structures */
700 et131x_init_send(adapter);
703 * Set up the task structure for the ISR's deferred handler
705 INIT_WORK(&adapter->task, et131x_isr_handler);
707 /* Copy address into the net_device struct */
708 memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
710 /* Setup et1310 as per the documentation */
711 et131x_adapter_setup(adapter);
713 /* Create a timer to count errors received by the NIC */
714 init_timer(&adapter->ErrorTimer);
716 adapter->ErrorTimer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
717 adapter->ErrorTimer.function = et131x_error_timer_handler;
718 adapter->ErrorTimer.data = (unsigned long)adapter;
720 /* Initialize link state */
721 et131x_link_detection_handler((unsigned long)adapter);
723 /* Intialize variable for counting how long we do not have
725 adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
727 /* We can enable interrupts now
729 * NOTE - Because registration of interrupt handler is done in the
730 * device's open(), defer enabling device interrupts to that
734 /* Register the net_device struct with the Linux network layer */
735 result = register_netdev(netdev);
737 dev_err(&pdev->dev, "register_netdev() failed\n");
741 /* Register the net_device struct with the PCI subsystem. Save a copy
742 * of the PCI config space for this device now that the device has
743 * been initialized, just in case it needs to be quickly restored.
745 pci_set_drvdata(pdev, netdev);
746 pci_save_state(adapter->pdev);
750 et131x_adapter_memory_free(adapter);
752 iounmap(adapter->regs);
757 pci_release_regions(pdev);
759 pci_disable_device(pdev);
765 * @pdev: a pointer to the device's pci_dev structure
767 * Registered in the pci_driver structure, this function is called when the
768 * PCI subsystem detects that a PCI device which matches the information
769 * contained in the pci_device_id table has been removed.
772 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
774 struct net_device *netdev;
775 struct et131x_adapter *adapter;
777 /* Retrieve the net_device pointer from the pci_dev struct, as well
778 * as the private adapter struct
780 netdev = (struct net_device *) pci_get_drvdata(pdev);
781 adapter = netdev_priv(netdev);
783 /* Perform device cleanup */
784 unregister_netdev(netdev);
785 et131x_adapter_memory_free(adapter);
786 iounmap(adapter->regs);
787 pci_dev_put(adapter->pdev);
789 pci_release_regions(pdev);
790 pci_disable_device(pdev);
793 static struct pci_device_id et131x_pci_table[] __devinitdata = {
794 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
795 PCI_ANY_ID, 0, 0, 0UL},
796 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
797 PCI_ANY_ID, 0, 0, 0UL},
801 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
803 static struct pci_driver et131x_driver = {
805 .id_table = et131x_pci_table,
806 .probe = et131x_pci_setup,
807 .remove = __devexit_p(et131x_pci_remove),
808 .suspend = NULL, /* et131x_pci_suspend */
809 .resume = NULL, /* et131x_pci_resume */
814 * et131x_init_module - The "main" entry point called on driver initialization
816 * Returns 0 on success, errno on failure (as defined in errno.h)
818 static int __init et131x_init_module(void)
820 if (et131x_speed_set < PARM_SPEED_DUPLEX_MIN ||
821 et131x_speed_set > PARM_SPEED_DUPLEX_MAX) {
822 printk(KERN_WARNING "et131x: invalid speed setting ignored.\n");
823 et131x_speed_set = 0;
825 return pci_register_driver(&et131x_driver);
829 * et131x_cleanup_module - The entry point called on driver cleanup
831 static void __exit et131x_cleanup_module(void)
833 pci_unregister_driver(&et131x_driver);
836 module_init(et131x_init_module);
837 module_exit(et131x_cleanup_module);
839 /* Modinfo parameters (filled out using defines from et131x_version.h) */
840 MODULE_AUTHOR(DRIVER_AUTHOR);
841 MODULE_DESCRIPTION(DRIVER_INFO);
842 MODULE_LICENSE(DRIVER_LICENSE);