2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 * Copyright © 2005 Agere Systems Inc.
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
10 *------------------------------------------------------------------------------
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/pci.h>
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/kernel.h>
61 #include <linux/sched.h>
62 #include <linux/ptrace.h>
63 #include <linux/slab.h>
64 #include <linux/ctype.h>
65 #include <linux/string.h>
66 #include <linux/timer.h>
67 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/bitops.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_arp.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/random.h>
80 #include <linux/phy.h>
84 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
85 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
86 MODULE_LICENSE("Dual BSD/GPL");
87 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
90 #define MAX_NUM_REGISTER_POLLS 1000
91 #define MAX_NUM_WRITE_RETRIES 2
94 #define COUNTER_WRAP_16_BIT 0x10000
95 #define COUNTER_WRAP_12_BIT 0x1000
98 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
99 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
102 /* For interrupts, normal running is:
103 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
104 * watchdog_interrupt & txdma_xfer_done
106 * In both cases, when flow control is enabled for either Tx or bi-direction,
107 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
108 * buffer rings are running low.
110 #define INT_MASK_DISABLE 0xffffffff
112 /* NOTE: Masking out MAC_STAT Interrupt for now...
113 * #define INT_MASK_ENABLE 0xfff6bf17
114 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
116 #define INT_MASK_ENABLE 0xfffebf17
117 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
119 /* General defines */
120 /* Packet and header sizes */
121 #define NIC_MIN_PACKET_SIZE 60
123 /* Multicast list size */
124 #define NIC_MAX_MCAST_LIST 128
126 /* Supported Filters */
127 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
128 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
129 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
130 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
131 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
134 #define ET131X_TX_TIMEOUT (1 * HZ)
135 #define NIC_SEND_HANG_THRESHOLD 0
138 #define FMP_DEST_MULTI 0x00000001
139 #define FMP_DEST_BROAD 0x00000002
141 /* MP_ADAPTER flags */
142 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
144 /* MP_SHARED flags */
145 #define FMP_ADAPTER_LOWER_POWER 0x00200000
147 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
148 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
150 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
152 /* Some offsets in PCI config space that are actually used. */
153 #define ET1310_PCI_MAC_ADDRESS 0xA4
154 #define ET1310_PCI_EEPROM_STATUS 0xB2
155 #define ET1310_PCI_ACK_NACK 0xC0
156 #define ET1310_PCI_REPLAY 0xC2
157 #define ET1310_PCI_L0L1LATENCY 0xCF
159 /* PCI Product IDs */
160 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
161 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
163 /* Define order of magnitude converter */
164 #define NANO_IN_A_MICRO 1000
166 #define PARM_RX_NUM_BUFS_DEF 4
167 #define PARM_RX_TIME_INT_DEF 10
168 #define PARM_RX_MEM_END_DEF 0x2bc
169 #define PARM_TX_TIME_INT_DEF 40
170 #define PARM_TX_NUM_BUFS_DEF 4
171 #define PARM_DMA_CACHE_DEF 0
174 #define FBR_CHUNKS 32
175 #define MAX_DESC_PER_RING_RX 1024
177 /* number of RFDs - default and min */
178 #define RFD_LOW_WATER_MARK 40
179 #define NIC_DEFAULT_NUM_RFD 1024
182 #define NUM_PACKETS_HANDLED 256
184 #define ALCATEL_MULTICAST_PKT 0x01000000
185 #define ALCATEL_BROADCAST_PKT 0x02000000
187 /* typedefs for Free Buffer Descriptors */
191 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
194 /* Packet Status Ring Descriptors
198 * top 16 bits are from the Alcatel Status Word as enumerated in
199 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
202 * 1: ipa IP checksum assist
203 * 2: ipp IP checksum pass
204 * 3: tcpa TCP checksum assist
205 * 4: tcpp TCP checksum pass
207 * 6: rxmac_error RXMAC Error Indicator
208 * 7: drop Drop packet
209 * 8: ft Frame Truncated
213 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
214 * 17: asw_RX_DV_event short receive event detected
215 * 18: asw_false_carrier_event bad carrier since last good packet
216 * 19: asw_code_err one or more nibbles signalled as errors
217 * 20: asw_CRC_err CRC error
218 * 21: asw_len_chk_err frame length field incorrect
219 * 22: asw_too_long frame length > 1518 bytes
220 * 23: asw_OK valid CRC + no code error
221 * 24: asw_multicast has a multicast address
222 * 25: asw_broadcast has a broadcast address
223 * 26: asw_dribble_nibble spurious bits after EOP
224 * 27: asw_control_frame is a control frame
225 * 28: asw_pause_frame is a pause frame
226 * 29: asw_unsupported_op unsupported OP code
227 * 30: asw_VLAN_tag VLAN tag detected
228 * 31: asw_long_evt Rx long event
231 * 0-15: length length in bytes
232 * 16-25: bi Buffer Index
233 * 26-27: ri Ring Index
237 struct pkt_stat_desc {
242 /* Typedefs for the RX DMA status word */
244 /* rx status word 0 holds part of the status bits of the Rx DMA engine
245 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
246 * which contains the Free Buffer ring 0 and 1 available offset.
248 * bit 0-9 FBR1 offset
249 * bit 10 Wrap flag for FBR1
250 * bit 16-25 FBR0 offset
251 * bit 26 Wrap flag for FBR0
254 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
255 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
256 * which contains the Packet Status Ring available offset.
259 * bit 16-27 PSRoffset
264 /* struct rx_status_block is a structure representing the status of the Rx
265 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
267 struct rx_status_block {
272 /* Structure for look-up table holding free buffer ring pointers, addresses
276 void *virt[MAX_DESC_PER_RING_RX];
277 u32 bus_high[MAX_DESC_PER_RING_RX];
278 u32 bus_low[MAX_DESC_PER_RING_RX];
280 dma_addr_t ring_physaddr;
281 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
282 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
288 /* struct rx_ring is the structure representing the adaptor's local
289 * reference(s) to the rings
292 struct fbr_lookup *fbr[NUM_FBRS];
293 void *ps_ring_virtaddr;
294 dma_addr_t ps_ring_physaddr;
298 struct rx_status_block *rx_status_block;
299 dma_addr_t rx_status_bus;
302 struct list_head recv_list;
307 bool unfinished_receives;
311 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
313 * 0-15: length of packet
316 * 29-31: VLAN priority
318 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
320 * 0: last packet in the sequence
321 * 1: first packet in the sequence
322 * 2: interrupt the processor when this pkt sent
323 * 3: Control word - no packet data
324 * 4: Issue half-duplex backpressure : XON/XOFF
325 * 5: send pause frame
326 * 6: Tx frame has error
330 * 10: Packet is a Huge packet
331 * 11: append VLAN tag
332 * 12: IP checksum assist
333 * 13: TCP checksum assist
334 * 14: UDP checksum assist
337 #define TXDESC_FLAG_LASTPKT 0x0001
338 #define TXDESC_FLAG_FIRSTPKT 0x0002
339 #define TXDESC_FLAG_INTPROC 0x0004
341 /* struct tx_desc represents each descriptor on the ring */
345 u32 len_vlan; /* control words how to xmit the */
346 u32 flags; /* data (detailed above) */
349 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
350 * by 0x101c / 0x1020. This is a DMA10 type
353 /* TCB (Transmit Control Block: Host Side) */
355 struct tcb *next; /* Next entry in ring */
356 u32 flags; /* Our flags for the packet */
357 u32 count; /* Used to spot stuck/lost packets */
358 u32 stale; /* Used to spot stuck/lost packets */
359 struct sk_buff *skb; /* Network skb we are tied to */
360 u32 index; /* Ring indexes */
364 /* Structure representing our local reference(s) to the ring */
366 /* TCB (Transmit Control Block) memory and lists */
367 struct tcb *tcb_ring;
369 /* List of TCBs that are ready to be used */
370 struct tcb *tcb_qhead;
371 struct tcb *tcb_qtail;
373 /* list of TCBs that are currently being sent. NOTE that access to all
374 * three of these (including used) are controlled via the
375 * TCBSendQLock. This lock should be secured prior to incementing /
376 * decrementing used, or any queue manipulation on send_head /
379 struct tcb *send_head;
380 struct tcb *send_tail;
383 /* The actual descriptor ring */
384 struct tx_desc *tx_desc_ring;
385 dma_addr_t tx_desc_ring_pa;
387 /* send_idx indicates where we last wrote to in the descriptor ring. */
390 /* The location of the write-back status block */
392 dma_addr_t tx_status_pa;
394 /* Packets since the last IRQ: used for interrupt coalescing */
398 /* Do not change these values: if changed, then change also in respective
399 * TXdma and Rxdma engines
401 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
404 /* These values are all superseded by registry entries to facilitate tuning.
405 * Once the desired performance has been achieved, the optimal registry values
406 * should be re-populated to these #defines:
408 #define TX_ERROR_PERIOD 1000
410 #define LO_MARK_PERCENT_FOR_PSR 15
411 #define LO_MARK_PERCENT_FOR_RX 15
413 /* RFD (Receive Frame Descriptor) */
415 struct list_head list_node;
417 u32 len; /* total size of receive frame */
424 #define FLOW_TXONLY 1
425 #define FLOW_RXONLY 2
428 /* Struct to define some device statistics */
432 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
433 * MUST have 32, then we'll need another way to perform atomic
436 u32 unicast_pkts_rcvd;
437 atomic_t unicast_pkts_xmtd;
438 u32 multicast_pkts_rcvd;
439 atomic_t multicast_pkts_xmtd;
440 u32 broadcast_pkts_rcvd;
441 atomic_t broadcast_pkts_xmtd;
442 u32 rcvd_pkts_dropped;
448 u32 tx_excessive_collisions;
449 u32 tx_first_collisions;
450 u32 tx_late_collisions;
460 u32 rx_code_violations;
463 u32 synchronous_iterations;
464 u32 interrupt_status;
467 /* The private adapter structure */
468 struct et131x_adapter {
469 struct net_device *netdev;
470 struct pci_dev *pdev;
471 struct mii_bus *mii_bus;
472 struct phy_device *phydev;
473 struct work_struct task;
475 /* Flags that indicate current state of the adapter */
478 /* local link state, to determine if a state change has occurred */
482 u8 rom_addr[ETH_ALEN];
488 spinlock_t tcb_send_qlock;
489 spinlock_t tcb_ready_qlock;
490 spinlock_t send_hw_lock;
495 /* Packet Filter and look ahead size */
499 u32 multicast_addr_count;
500 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
502 /* Pointer to the device's PCI register space */
503 struct address_map __iomem *regs;
505 /* Registry parameters */
506 u8 wanted_flow; /* Flow we want for 802.3x flow control */
507 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
509 /* Derived from the registry: */
510 u8 flowcontrol; /* flow control validated by the far-end */
512 /* Minimize init-time */
513 struct timer_list error_timer;
515 /* variable putting the phy into coma mode when boot up with no cable
516 * plugged in after 5 seconds
520 /* Next two used to save power information at power down. This
521 * information will be used during power up to set up parts of Power
522 * Management in JAGCore
527 /* Tx Memory Variables */
528 struct tx_ring tx_ring;
530 /* Rx Memory Variables */
531 struct rx_ring rx_ring;
534 struct ce_stats stats;
537 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
542 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
543 * bits 7,1:0 both equal to 1, at least once after reset.
544 * Subsequent operations need only to check that bits 1:0 are equal
545 * to 1 prior to starting a single byte read/write
548 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
549 /* Read registers grouped in DWORD1 */
550 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
553 /* I2C idle and Phy Queue Avail both true */
554 if ((reg & 0x3000) == 0x3000) {
563 /* eeprom_write - Write a byte to the ET1310's EEPROM
564 * @adapter: pointer to our private adapter structure
565 * @addr: the address to write
566 * @data: the value to write
568 * Returns 1 for a successful write.
570 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
572 struct pci_dev *pdev = adapter->pdev;
581 /* For an EEPROM, an I2C single byte write is defined as a START
582 * condition followed by the device address, EEPROM address, one byte
583 * of data and a STOP condition. The STOP condition will trigger the
584 * EEPROM's internally timed write cycle to the nonvolatile memory.
585 * All inputs are disabled during this write cycle and the EEPROM will
586 * not respond to any access until the internal write is complete.
589 err = eeprom_wait_ready(pdev, NULL);
593 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
594 * and bits 1:0 both =0. Bit 5 should be set according to the
595 * type of EEPROM being accessed (1=two byte addressing, 0=one
598 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
599 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
604 /* Prepare EEPROM address for Step 3 */
606 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
607 /* Write the address to the LBCIF Address Register */
608 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
610 /* Write the data to the LBCIF Data Register (the I2C write
613 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
615 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
616 * 1:0 are both equal to 1, the I2C write has completed and the
617 * internal write cycle of the EEPROM is about to start.
618 * (bits 1:0 = 01 is a legal state while waiting from both
619 * equal to 1, but bits 1:0 = 10 is invalid and implies that
620 * something is broken).
622 err = eeprom_wait_ready(pdev, &status);
626 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
627 * an error has occurred.Don't break here if we are revision
628 * 1, this is so we do a blind write for load bug.
630 if ((status & LBCIF_STATUS_GENERAL_ERROR)
631 && adapter->pdev->revision == 0)
634 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
635 * ACK error has occurred on the address phase of the write.
636 * This could be due to an actual hardware failure or the
637 * EEPROM may still be in its internal write cycle from a
638 * previous write. This write operation was ignored and must be
641 if (status & LBCIF_STATUS_ACK_ERROR) {
642 /* This could be due to an actual hardware failure
643 * or the EEPROM may still be in its internal write
644 * cycle from a previous write. This write operation
645 * was ignored and must be repeated later.
655 /* Set bit 6 of the LBCIF Control Register = 0.
660 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
661 LBCIF_CONTROL_LBCIF_ENABLE))
664 /* Do read until internal ACK_ERROR goes away meaning write
668 pci_write_config_dword(pdev,
669 LBCIF_ADDRESS_REGISTER,
672 pci_read_config_dword(pdev,
673 LBCIF_DATA_REGISTER, &val);
674 } while ((val & 0x00010000) == 0);
675 } while (val & 0x00040000);
677 if ((val & 0xFF00) != 0xC000 || index == 10000)
681 return writeok ? 0 : -EIO;
684 /* eeprom_read - Read a byte from the ET1310's EEPROM
685 * @adapter: pointer to our private adapter structure
686 * @addr: the address from which to read
687 * @pdata: a pointer to a byte in which to store the value of the read
688 * @eeprom_id: the ID of the EEPROM
689 * @addrmode: how the EEPROM is to be accessed
691 * Returns 1 for a successful read
693 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
695 struct pci_dev *pdev = adapter->pdev;
699 /* A single byte read is similar to the single byte write, with the
700 * exception of the data flow:
703 err = eeprom_wait_ready(pdev, NULL);
706 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
707 * and bits 1:0 both =0. Bit 5 should be set according to the type
708 * of EEPROM being accessed (1=two byte addressing, 0=one byte
711 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
712 LBCIF_CONTROL_LBCIF_ENABLE))
714 /* Write the address to the LBCIF Address Register (I2C read will
717 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
719 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
720 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
723 err = eeprom_wait_ready(pdev, &status);
726 /* Regardless of error status, read data byte from LBCIF Data
730 /* Check bit 2 of the LBCIF Status Register. If = 1,
731 * then an error has occurred.
733 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
736 static int et131x_init_eeprom(struct et131x_adapter *adapter)
738 struct pci_dev *pdev = adapter->pdev;
741 /* We first need to check the EEPROM Status code located at offset
742 * 0xB2 of config space
744 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
746 /* THIS IS A WORKAROUND:
747 * I need to call this function twice to get my card in a
748 * LG M1 Express Dual running. I tried also a msleep before this
749 * function, because I thought there could be some time conditions
750 * but it didn't work. Call the whole function twice also work.
752 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
754 "Could not read PCI config space for EEPROM Status\n");
758 /* Determine if the error(s) we care about are present. If they are
759 * present we need to fail.
761 if (eestatus & 0x4C) {
762 int write_failed = 0;
764 if (pdev->revision == 0x01) {
766 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
768 /* Re-write the first 4 bytes if we have an eeprom
769 * present and the revision id is 1, this fixes the
770 * corruption seen with 1310 B Silicon
772 for (i = 0; i < 3; i++)
773 if (eeprom_write(adapter, i, eedata[i]) < 0)
776 if (pdev->revision != 0x01 || write_failed) {
778 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
780 /* This error could mean that there was an error
781 * reading the eeprom or that the eeprom doesn't exist.
782 * We will treat each case the same and not try to
783 * gather additional information that normally would
784 * come from the eeprom, like MAC Address
786 adapter->has_eeprom = 0;
790 adapter->has_eeprom = 1;
792 /* Read the EEPROM for information regarding LED behavior. Refer to
793 * ET1310_phy.c, et131x_xcvr_init(), for its use.
795 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
796 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
798 if (adapter->eeprom_data[0] != 0xcd)
799 /* Disable all optional features */
800 adapter->eeprom_data[1] = 0x00;
805 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
806 * @adapter: pointer to our adapter structure
808 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
810 /* Setup the receive dma configuration register for normal operation */
811 u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
812 struct rx_ring *rx_ring = &adapter->rx_ring;
814 if (rx_ring->fbr[1]->buffsize == 4096)
815 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
816 else if (rx_ring->fbr[1]->buffsize == 8192)
817 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
818 else if (rx_ring->fbr[1]->buffsize == 16384)
819 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
821 csr |= ET_RXDMA_CSR_FBR0_ENABLE;
822 if (rx_ring->fbr[0]->buffsize == 256)
823 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
824 else if (rx_ring->fbr[0]->buffsize == 512)
825 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
826 else if (rx_ring->fbr[0]->buffsize == 1024)
827 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
828 writel(csr, &adapter->regs->rxdma.csr);
830 csr = readl(&adapter->regs->rxdma.csr);
831 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
833 csr = readl(&adapter->regs->rxdma.csr);
834 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
835 dev_err(&adapter->pdev->dev,
836 "RX Dma failed to exit halt state. CSR 0x%08x\n",
842 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
843 * @adapter: pointer to our adapter structure
845 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
848 /* Setup the receive dma configuration register */
849 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
850 &adapter->regs->rxdma.csr);
851 csr = readl(&adapter->regs->rxdma.csr);
852 if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
854 csr = readl(&adapter->regs->rxdma.csr);
855 if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
856 dev_err(&adapter->pdev->dev,
857 "RX Dma failed to enter halt state. CSR 0x%08x\n",
862 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
863 * @adapter: pointer to our adapter structure
865 * Mainly used after a return to the D0 (full-power) state from a lower state.
867 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
869 /* Setup the transmit dma configuration register for normal
872 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
873 &adapter->regs->txdma.csr);
876 static inline void add_10bit(u32 *v, int n)
878 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
881 static inline void add_12bit(u32 *v, int n)
883 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
886 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
887 * @adapter: pointer to our adapter structure
889 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
891 struct mac_regs __iomem *macregs = &adapter->regs->mac;
896 /* First we need to reset everything. Write to MAC configuration
897 * register 1 to perform reset.
899 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
900 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
901 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
904 /* Next lets configure the MAC Inter-packet gap register */
905 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
906 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
907 writel(ipg, ¯egs->ipg);
909 /* Next lets configure the MAC Half Duplex register */
910 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
911 writel(0x00A1F037, ¯egs->hfdp);
913 /* Next lets configure the MAC Interface Control register */
914 writel(0, ¯egs->if_ctrl);
916 /* Let's move on to setting up the mii management configuration */
917 writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
919 /* Next lets configure the MAC Station Address register. These
920 * values are read from the EEPROM during initialization and stored
921 * in the adapter structure. We write what is stored in the adapter
922 * structure to the MAC Station Address registers high and low. This
923 * station address is used for generating and checking pause control
926 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
927 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
928 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
929 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
930 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
932 writel(station1, ¯egs->station_addr_1);
933 writel(station2, ¯egs->station_addr_2);
935 /* Max ethernet packet in bytes that will be passed by the mac without
936 * being truncated. Allow the MAC to pass 4 more than our max packet
937 * size. This is 4 for the Ethernet CRC.
939 * Packets larger than (registry_jumbo_packet) that do not contain a
940 * VLAN ID will be dropped by the Rx function.
942 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
944 /* clear out MAC config reset */
945 writel(0, ¯egs->cfg1);
948 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
949 * @adapter: pointer to our adapter structure
951 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
954 struct mac_regs __iomem *mac = &adapter->regs->mac;
955 struct phy_device *phydev = adapter->phydev;
961 ctl = readl(&adapter->regs->txmac.ctl);
962 cfg1 = readl(&mac->cfg1);
963 cfg2 = readl(&mac->cfg2);
964 ifctrl = readl(&mac->if_ctrl);
966 /* Set up the if mode bits */
967 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
968 if (phydev->speed == SPEED_1000) {
969 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
971 ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
973 cfg2 |= ET_MAC_CFG2_IFMODE_100;
974 ifctrl |= ET_MAC_IFCTRL_PHYMODE;
977 /* We need to enable Rx/Tx */
978 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
980 /* Initialize loop back to off */
981 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
982 if (adapter->flowcontrol == FLOW_RXONLY ||
983 adapter->flowcontrol == FLOW_BOTH)
984 cfg1 |= ET_MAC_CFG1_RX_FLOW;
985 writel(cfg1, &mac->cfg1);
987 /* Now we need to initialize the MAC Configuration 2 register */
988 /* preamble 7, check length, huge frame off, pad crc, crc enable
991 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
992 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
993 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
994 cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
995 cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
996 cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
998 /* Turn on duplex if needed */
999 if (phydev->duplex == DUPLEX_FULL)
1000 cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
1002 ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
1003 if (phydev->duplex == DUPLEX_HALF)
1004 ifctrl |= ET_MAC_IFCTRL_GHDMODE;
1006 writel(ifctrl, &mac->if_ctrl);
1007 writel(cfg2, &mac->cfg2);
1012 cfg1 = readl(&mac->cfg1);
1013 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
1016 dev_warn(&adapter->pdev->dev,
1017 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1022 ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
1023 writel(ctl, &adapter->regs->txmac.ctl);
1025 /* Ready to start the RXDMA/TXDMA engine */
1026 if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
1027 et131x_rx_dma_enable(adapter);
1028 et131x_tx_dma_enable(adapter);
1032 /* et1310_in_phy_coma - check if the device is in phy coma
1033 * @adapter: pointer to our adapter structure
1035 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1037 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1039 u32 pmcsr = readl(&adapter->regs->global.pm_csr);
1041 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1044 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1046 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1053 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1054 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1055 * specified) then we should pass NO multi-cast addresses to the
1058 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1061 /* Loop through our multicast array and set up the device */
1062 for (i = 0; i < adapter->multicast_addr_count; i++) {
1065 result = ether_crc(6, adapter->multicast_list[i]);
1067 result = (result & 0x3F800000) >> 23;
1070 hash1 |= (1 << result);
1071 } else if ((31 < result) && (result < 64)) {
1073 hash2 |= (1 << result);
1074 } else if ((63 < result) && (result < 96)) {
1076 hash3 |= (1 << result);
1079 hash4 |= (1 << result);
1084 /* Write out the new hash to the device */
1085 pm_csr = readl(&adapter->regs->global.pm_csr);
1086 if (!et1310_in_phy_coma(adapter)) {
1087 writel(hash1, &rxmac->multi_hash1);
1088 writel(hash2, &rxmac->multi_hash2);
1089 writel(hash3, &rxmac->multi_hash3);
1090 writel(hash4, &rxmac->multi_hash4);
1094 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1096 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1102 /* Set up unicast packet filter reg 3 to be the first two octets of
1103 * the MAC address for both address
1105 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1106 * MAC address for second address
1108 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1109 * MAC address for first address
1111 uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
1112 (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
1113 (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
1116 uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
1117 (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
1118 (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
1121 uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
1122 (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
1123 (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
1126 pm_csr = readl(&adapter->regs->global.pm_csr);
1127 if (!et1310_in_phy_coma(adapter)) {
1128 writel(uni_pf1, &rxmac->uni_pf_addr1);
1129 writel(uni_pf2, &rxmac->uni_pf_addr2);
1130 writel(uni_pf3, &rxmac->uni_pf_addr3);
1134 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1136 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1137 struct phy_device *phydev = adapter->phydev;
1142 /* Disable the MAC while it is being configured (also disable WOL) */
1143 writel(0x8, &rxmac->ctrl);
1145 /* Initialize WOL to disabled. */
1146 writel(0, &rxmac->crc0);
1147 writel(0, &rxmac->crc12);
1148 writel(0, &rxmac->crc34);
1150 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1151 * its default Values of 0x00000000 because there are not WOL masks
1154 writel(0, &rxmac->mask0_word0);
1155 writel(0, &rxmac->mask0_word1);
1156 writel(0, &rxmac->mask0_word2);
1157 writel(0, &rxmac->mask0_word3);
1159 writel(0, &rxmac->mask1_word0);
1160 writel(0, &rxmac->mask1_word1);
1161 writel(0, &rxmac->mask1_word2);
1162 writel(0, &rxmac->mask1_word3);
1164 writel(0, &rxmac->mask2_word0);
1165 writel(0, &rxmac->mask2_word1);
1166 writel(0, &rxmac->mask2_word2);
1167 writel(0, &rxmac->mask2_word3);
1169 writel(0, &rxmac->mask3_word0);
1170 writel(0, &rxmac->mask3_word1);
1171 writel(0, &rxmac->mask3_word2);
1172 writel(0, &rxmac->mask3_word3);
1174 writel(0, &rxmac->mask4_word0);
1175 writel(0, &rxmac->mask4_word1);
1176 writel(0, &rxmac->mask4_word2);
1177 writel(0, &rxmac->mask4_word3);
1179 /* Lets setup the WOL Source Address */
1180 sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
1181 (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
1182 (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
1184 writel(sa_lo, &rxmac->sa_lo);
1186 sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
1188 writel(sa_hi, &rxmac->sa_hi);
1190 /* Disable all Packet Filtering */
1191 writel(0, &rxmac->pf_ctrl);
1193 /* Let's initialize the Unicast Packet filtering address */
1194 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1195 et1310_setup_device_for_unicast(adapter);
1196 pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
1198 writel(0, &rxmac->uni_pf_addr1);
1199 writel(0, &rxmac->uni_pf_addr2);
1200 writel(0, &rxmac->uni_pf_addr3);
1203 /* Let's initialize the Multicast hash */
1204 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1205 pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
1206 et1310_setup_device_for_multicast(adapter);
1209 /* Runt packet filtering. Didn't work in version A silicon. */
1210 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
1211 pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
1213 if (adapter->registry_jumbo_packet > 8192)
1214 /* In order to transmit jumbo packets greater than 8k, the
1215 * FIFO between RxMAC and RxDMA needs to be reduced in size
1216 * to (16k - Jumbo packet size). In order to implement this,
1217 * we must use "cut through" mode in the RxMAC, which chops
1218 * packets down into segments which are (max_size * 16). In
1219 * this case we selected 256 bytes, since this is the size of
1220 * the PCI-Express TLP's that the 1310 uses.
1222 * seg_en on, fc_en off, size 0x10
1224 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1226 writel(0, &rxmac->mcif_ctrl_max_seg);
1228 /* Initialize the MCIF water marks */
1229 writel(0, &rxmac->mcif_water_mark);
1231 /* Initialize the MIF control */
1232 writel(0, &rxmac->mif_ctrl);
1234 /* Initialize the Space Available Register */
1235 writel(0, &rxmac->space_avail);
1237 /* Initialize the the mif_ctrl register
1238 * bit 3: Receive code error. One or more nibbles were signaled as
1239 * errors during the reception of the packet. Clear this
1240 * bit in Gigabit, set it in 100Mbit. This was derived
1241 * experimentally at UNH.
1242 * bit 4: Receive CRC error. The packet's CRC did not match the
1243 * internally generated CRC.
1244 * bit 5: Receive length check error. Indicates that frame length
1245 * field value in the packet does not match the actual data
1246 * byte length and is not a type field.
1247 * bit 16: Receive frame truncated.
1248 * bit 17: Drop packet enable
1250 if (phydev && phydev->speed == SPEED_100)
1251 writel(0x30038, &rxmac->mif_ctrl);
1253 writel(0x30030, &rxmac->mif_ctrl);
1255 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1256 * filter is always enabled since it is where the runt packets are
1257 * supposed to be dropped. For version A silicon, runt packet
1258 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1259 * but we still leave the packet filter on.
1261 writel(pf_ctrl, &rxmac->pf_ctrl);
1262 writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
1265 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1267 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1269 /* We need to update the Control Frame Parameters
1270 * cfpt - control frame pause timer set to 64 (0x40)
1271 * cfep - control frame extended pause timer set to 0x0
1273 if (adapter->flowcontrol == FLOW_NONE)
1274 writel(0, &txmac->cf_param);
1276 writel(0x40, &txmac->cf_param);
1279 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1281 struct macstat_regs __iomem *macstat =
1282 &adapter->regs->macstat;
1284 /* Next we need to initialize all the macstat registers to zero on
1287 writel(0, &macstat->txrx_0_64_byte_frames);
1288 writel(0, &macstat->txrx_65_127_byte_frames);
1289 writel(0, &macstat->txrx_128_255_byte_frames);
1290 writel(0, &macstat->txrx_256_511_byte_frames);
1291 writel(0, &macstat->txrx_512_1023_byte_frames);
1292 writel(0, &macstat->txrx_1024_1518_byte_frames);
1293 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1295 writel(0, &macstat->rx_bytes);
1296 writel(0, &macstat->rx_packets);
1297 writel(0, &macstat->rx_fcs_errs);
1298 writel(0, &macstat->rx_multicast_packets);
1299 writel(0, &macstat->rx_broadcast_packets);
1300 writel(0, &macstat->rx_control_frames);
1301 writel(0, &macstat->rx_pause_frames);
1302 writel(0, &macstat->rx_unknown_opcodes);
1303 writel(0, &macstat->rx_align_errs);
1304 writel(0, &macstat->rx_frame_len_errs);
1305 writel(0, &macstat->rx_code_errs);
1306 writel(0, &macstat->rx_carrier_sense_errs);
1307 writel(0, &macstat->rx_undersize_packets);
1308 writel(0, &macstat->rx_oversize_packets);
1309 writel(0, &macstat->rx_fragment_packets);
1310 writel(0, &macstat->rx_jabbers);
1311 writel(0, &macstat->rx_drops);
1313 writel(0, &macstat->tx_bytes);
1314 writel(0, &macstat->tx_packets);
1315 writel(0, &macstat->tx_multicast_packets);
1316 writel(0, &macstat->tx_broadcast_packets);
1317 writel(0, &macstat->tx_pause_frames);
1318 writel(0, &macstat->tx_deferred);
1319 writel(0, &macstat->tx_excessive_deferred);
1320 writel(0, &macstat->tx_single_collisions);
1321 writel(0, &macstat->tx_multiple_collisions);
1322 writel(0, &macstat->tx_late_collisions);
1323 writel(0, &macstat->tx_excessive_collisions);
1324 writel(0, &macstat->tx_total_collisions);
1325 writel(0, &macstat->tx_pause_honored_frames);
1326 writel(0, &macstat->tx_drops);
1327 writel(0, &macstat->tx_jabbers);
1328 writel(0, &macstat->tx_fcs_errs);
1329 writel(0, &macstat->tx_control_frames);
1330 writel(0, &macstat->tx_oversize_frames);
1331 writel(0, &macstat->tx_undersize_frames);
1332 writel(0, &macstat->tx_fragments);
1333 writel(0, &macstat->carry_reg1);
1334 writel(0, &macstat->carry_reg2);
1336 /* Unmask any counters that we want to track the overflow of.
1337 * Initially this will be all counters. It may become clear later
1338 * that we do not need to track all counters.
1340 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1341 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1344 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1345 * @adapter: pointer to our private adapter structure
1346 * @addr: the address of the transceiver
1347 * @reg: the register to read
1348 * @value: pointer to a 16-bit value in which the value will be stored
1350 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1353 struct mac_regs __iomem *mac = &adapter->regs->mac;
1360 /* Save a local copy of the registers we are dealing with so we can
1363 mii_addr = readl(&mac->mii_mgmt_addr);
1364 mii_cmd = readl(&mac->mii_mgmt_cmd);
1366 /* Stop the current operation */
1367 writel(0, &mac->mii_mgmt_cmd);
1369 /* Set up the register we need to read from on the correct PHY */
1370 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1372 writel(0x1, &mac->mii_mgmt_cmd);
1377 mii_indicator = readl(&mac->mii_mgmt_indicator);
1378 } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
1380 /* If we hit the max delay, we could not read the register */
1382 dev_warn(&adapter->pdev->dev,
1383 "reg 0x%08x could not be read\n", reg);
1384 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1391 /* If we hit here we were able to read the register and we need to
1392 * return the value to the caller
1394 *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
1397 /* Stop the read operation */
1398 writel(0, &mac->mii_mgmt_cmd);
1400 /* set the registers we touched back to the state at which we entered
1403 writel(mii_addr, &mac->mii_mgmt_addr);
1404 writel(mii_cmd, &mac->mii_mgmt_cmd);
1409 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1411 struct phy_device *phydev = adapter->phydev;
1416 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1419 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1420 * @adapter: pointer to our private adapter structure
1421 * @reg: the register to read
1422 * @value: 16-bit value to write
1424 static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1426 struct mac_regs __iomem *mac = &adapter->regs->mac;
1427 struct phy_device *phydev = adapter->phydev;
1438 addr = phydev->addr;
1440 /* Save a local copy of the registers we are dealing with so we can
1443 mii_addr = readl(&mac->mii_mgmt_addr);
1444 mii_cmd = readl(&mac->mii_mgmt_cmd);
1446 /* Stop the current operation */
1447 writel(0, &mac->mii_mgmt_cmd);
1449 /* Set up the register we need to write to on the correct PHY */
1450 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1452 /* Add the value to write to the registers to the mac */
1453 writel(value, &mac->mii_mgmt_ctrl);
1458 mii_indicator = readl(&mac->mii_mgmt_indicator);
1459 } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
1461 /* If we hit the max delay, we could not write the register */
1465 dev_warn(&adapter->pdev->dev,
1466 "reg 0x%08x could not be written", reg);
1467 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1469 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1470 readl(&mac->mii_mgmt_cmd));
1472 et131x_mii_read(adapter, reg, &tmp);
1476 /* Stop the write operation */
1477 writel(0, &mac->mii_mgmt_cmd);
1479 /* set the registers we touched back to the state at which we entered
1482 writel(mii_addr, &mac->mii_mgmt_addr);
1483 writel(mii_cmd, &mac->mii_mgmt_cmd);
1488 static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
1494 u16 mask = 1 << bitnum;
1496 /* Read the requested register */
1497 et131x_mii_read(adapter, regnum, ®);
1499 *value = (reg & mask) >> bitnum;
1502 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1504 struct phy_device *phydev = adapter->phydev;
1506 if (phydev->duplex == DUPLEX_HALF) {
1507 adapter->flowcontrol = FLOW_NONE;
1509 char remote_pause, remote_async_pause;
1511 et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
1512 et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
1514 if (remote_pause && remote_async_pause) {
1515 adapter->flowcontrol = adapter->wanted_flow;
1516 } else if (remote_pause && !remote_async_pause) {
1517 if (adapter->wanted_flow == FLOW_BOTH)
1518 adapter->flowcontrol = FLOW_BOTH;
1520 adapter->flowcontrol = FLOW_NONE;
1521 } else if (!remote_pause && !remote_async_pause) {
1522 adapter->flowcontrol = FLOW_NONE;
1524 if (adapter->wanted_flow == FLOW_BOTH)
1525 adapter->flowcontrol = FLOW_RXONLY;
1527 adapter->flowcontrol = FLOW_NONE;
1532 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1533 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1535 struct ce_stats *stats = &adapter->stats;
1536 struct macstat_regs __iomem *macstat =
1537 &adapter->regs->macstat;
1539 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1540 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1541 stats->tx_deferred += readl(&macstat->tx_deferred);
1542 stats->tx_excessive_collisions +=
1543 readl(&macstat->tx_multiple_collisions);
1544 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1545 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1546 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1548 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1549 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1550 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1551 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1552 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1553 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1554 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1557 /* et1310_handle_macstat_interrupt
1559 * One of the MACSTAT counters has wrapped. Update the local copy of
1560 * the statistics held in the adapter structure, checking the "wrap"
1561 * bit for each counter.
1563 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1568 /* Read the interrupt bits from the register(s). These are Clear On
1571 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1572 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1574 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1575 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1577 /* We need to do update the host copy of all the MAC_STAT counters.
1578 * For each counter, check it's overflow bit. If the overflow bit is
1579 * set, then increment the host version of the count by one complete
1580 * revolution of the counter. This routine is called when the counter
1581 * block indicates that one of the counters has wrapped.
1583 if (carry_reg1 & (1 << 14))
1584 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1585 if (carry_reg1 & (1 << 8))
1586 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1587 if (carry_reg1 & (1 << 7))
1588 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1589 if (carry_reg1 & (1 << 2))
1590 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1591 if (carry_reg1 & (1 << 6))
1592 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1593 if (carry_reg1 & (1 << 3))
1594 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1595 if (carry_reg1 & (1 << 0))
1596 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1597 if (carry_reg2 & (1 << 16))
1598 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1599 if (carry_reg2 & (1 << 15))
1600 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1601 if (carry_reg2 & (1 << 6))
1602 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1603 if (carry_reg2 & (1 << 8))
1604 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1605 if (carry_reg2 & (1 << 5))
1606 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1607 if (carry_reg2 & (1 << 4))
1608 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1609 if (carry_reg2 & (1 << 2))
1610 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1613 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1615 struct net_device *netdev = bus->priv;
1616 struct et131x_adapter *adapter = netdev_priv(netdev);
1620 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1628 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1631 struct net_device *netdev = bus->priv;
1632 struct et131x_adapter *adapter = netdev_priv(netdev);
1634 return et131x_mii_write(adapter, reg, value);
1637 static int et131x_mdio_reset(struct mii_bus *bus)
1639 struct net_device *netdev = bus->priv;
1640 struct et131x_adapter *adapter = netdev_priv(netdev);
1642 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1647 /* et1310_phy_power_switch - PHY power control
1648 * @adapter: device to control
1649 * @down: true for off/false for back on
1651 * one hundred, ten, one thousand megs
1652 * How would you like to have your LAN accessed
1653 * Can't you see that this code processed
1654 * Phy power, phy power..
1656 static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
1660 et131x_mii_read(adapter, MII_BMCR, &data);
1661 data &= ~BMCR_PDOWN;
1664 et131x_mii_write(adapter, MII_BMCR, data);
1667 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1668 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1672 /* Set the LED behavior such that LED 1 indicates speed (off =
1673 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1674 * link and activity (on for link, blink off for activity).
1676 * NOTE: Some customizations have been added here for specific
1677 * vendors; The LED behavior is now determined by vendor data in the
1678 * EEPROM. However, the above description is the default.
1680 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1681 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1683 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1684 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1686 if ((adapter->eeprom_data[1] & 0x8) == 0)
1687 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1689 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1691 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1695 /* et131x_configure_global_regs - configure JAGCore global regs
1697 * Used to configure the global registers on the JAGCore
1699 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1701 struct global_regs __iomem *regs = &adapter->regs->global;
1703 writel(0, ®s->rxq_start_addr);
1704 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
1706 if (adapter->registry_jumbo_packet < 2048) {
1707 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1708 * block of RAM that the driver can split between Tx
1709 * and Rx as it desires. Our default is to split it
1712 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
1713 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
1714 } else if (adapter->registry_jumbo_packet < 8192) {
1715 /* For jumbo packets > 2k but < 8k, split 50-50. */
1716 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
1717 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
1719 /* 9216 is the only packet size greater than 8k that
1720 * is available. The Tx buffer has to be big enough
1721 * for one whole packet on the Tx side. We'll make
1722 * the Tx 9408, and give the rest to Rx
1724 writel(0x01b3, ®s->rxq_end_addr);
1725 writel(0x01b4, ®s->txq_start_addr);
1728 /* Initialize the loopback register. Disable all loopbacks. */
1729 writel(0, ®s->loopback);
1732 writel(0, ®s->msi_config);
1734 /* By default, disable the watchdog timer. It will be enabled when
1735 * a packet is queued.
1737 writel(0, ®s->watchdog_timer);
1740 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1741 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1743 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1744 struct rx_ring *rx_local = &adapter->rx_ring;
1745 struct fbr_desc *fbr_entry;
1748 unsigned long flags;
1751 /* Halt RXDMA to perform the reconfigure. */
1752 et131x_rx_dma_disable(adapter);
1754 /* Load the completion writeback physical address */
1755 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1756 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1758 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1760 /* Set the address and parameters of the packet status ring into the
1763 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1764 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1765 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1766 writel(0, &rx_dma->psr_full_offset);
1768 psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
1769 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1770 &rx_dma->psr_min_des);
1772 spin_lock_irqsave(&adapter->rcv_lock, flags);
1774 /* These local variables track the PSR in the adapter structure */
1775 rx_local->local_psr_full = 0;
1777 for (id = 0; id < NUM_FBRS; id++) {
1778 u32 __iomem *num_des;
1779 u32 __iomem *full_offset;
1780 u32 __iomem *min_des;
1781 u32 __iomem *base_hi;
1782 u32 __iomem *base_lo;
1783 struct fbr_lookup *fbr = rx_local->fbr[id];
1786 num_des = &rx_dma->fbr0_num_des;
1787 full_offset = &rx_dma->fbr0_full_offset;
1788 min_des = &rx_dma->fbr0_min_des;
1789 base_hi = &rx_dma->fbr0_base_hi;
1790 base_lo = &rx_dma->fbr0_base_lo;
1792 num_des = &rx_dma->fbr1_num_des;
1793 full_offset = &rx_dma->fbr1_full_offset;
1794 min_des = &rx_dma->fbr1_min_des;
1795 base_hi = &rx_dma->fbr1_base_hi;
1796 base_lo = &rx_dma->fbr1_base_lo;
1799 /* Now's the best time to initialize FBR contents */
1800 fbr_entry = fbr->ring_virtaddr;
1801 for (entry = 0; entry < fbr->num_entries; entry++) {
1802 fbr_entry->addr_hi = fbr->bus_high[entry];
1803 fbr_entry->addr_lo = fbr->bus_low[entry];
1804 fbr_entry->word2 = entry;
1808 /* Set the address and parameters of Free buffer ring 1 and 0
1809 * into the 1310's registers
1811 writel(upper_32_bits(fbr->ring_physaddr), base_hi);
1812 writel(lower_32_bits(fbr->ring_physaddr), base_lo);
1813 writel(fbr->num_entries - 1, num_des);
1814 writel(ET_DMA10_WRAP, full_offset);
1816 /* This variable tracks the free buffer ring 1 full position,
1817 * so it has to match the above.
1819 fbr->local_full = ET_DMA10_WRAP;
1820 writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1824 /* Program the number of packets we will receive before generating an
1826 * For version B silicon, this value gets updated once autoneg is
1829 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1831 /* The "time_done" is not working correctly to coalesce interrupts
1832 * after a given time period, but rather is giving us an interrupt
1833 * regardless of whether we have received packets.
1834 * This value gets updated once autoneg is complete.
1836 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1838 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1841 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1843 * Configure the transmit engine with the ring buffers we have created
1844 * and prepare it for use.
1846 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1848 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1849 struct tx_ring *tx_ring = &adapter->tx_ring;
1851 /* Load the hardware with the start of the transmit descriptor ring. */
1852 writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
1853 writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
1855 /* Initialise the transmit DMA engine */
1856 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1858 /* Load the completion writeback physical address */
1859 writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
1860 writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
1862 *tx_ring->tx_status = 0;
1864 writel(0, &txdma->service_request);
1865 tx_ring->send_idx = 0;
1868 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1869 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1871 /* Configure the JAGCore */
1872 et131x_configure_global_regs(adapter);
1874 et1310_config_mac_regs1(adapter);
1876 /* Configure the MMC registers */
1877 /* All we need to do is initialize the Memory Control Register */
1878 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1880 et1310_config_rxmac_regs(adapter);
1881 et1310_config_txmac_regs(adapter);
1883 et131x_config_rx_dma_regs(adapter);
1884 et131x_config_tx_dma_regs(adapter);
1886 et1310_config_macstat_regs(adapter);
1888 et1310_phy_power_switch(adapter, 0);
1889 et131x_xcvr_init(adapter);
1892 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1893 static void et131x_soft_reset(struct et131x_adapter *adapter)
1897 /* Disable MAC Core */
1898 reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
1899 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1900 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1901 writel(reg, &adapter->regs->mac.cfg1);
1904 writel(reg, &adapter->regs->global.sw_reset);
1906 reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1907 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1908 writel(reg, &adapter->regs->mac.cfg1);
1909 writel(0, &adapter->regs->mac.cfg1);
1912 /* et131x_enable_interrupts - enable interrupt
1914 * Enable the appropriate interrupts on the ET131x according to our
1917 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
1921 /* Enable all global interrupts */
1922 if (adapter->flowcontrol == FLOW_TXONLY ||
1923 adapter->flowcontrol == FLOW_BOTH)
1924 mask = INT_MASK_ENABLE;
1926 mask = INT_MASK_ENABLE_NO_FLOW;
1928 writel(mask, &adapter->regs->global.int_mask);
1931 /* et131x_disable_interrupts - interrupt disable
1933 * Block all interrupts from the et131x device at the device itself
1935 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
1937 /* Disable all global interrupts */
1938 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
1941 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1942 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
1944 /* Setup the transmit dma configuration register */
1945 writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
1946 &adapter->regs->txdma.csr);
1949 /* et131x_enable_txrx - Enable tx/rx queues */
1950 static void et131x_enable_txrx(struct net_device *netdev)
1952 struct et131x_adapter *adapter = netdev_priv(netdev);
1954 /* Enable the Tx and Rx DMA engines (if not already enabled) */
1955 et131x_rx_dma_enable(adapter);
1956 et131x_tx_dma_enable(adapter);
1958 /* Enable device interrupts */
1959 if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
1960 et131x_enable_interrupts(adapter);
1962 /* We're ready to move some data, so start the queue */
1963 netif_start_queue(netdev);
1966 /* et131x_disable_txrx - Disable tx/rx queues */
1967 static void et131x_disable_txrx(struct net_device *netdev)
1969 struct et131x_adapter *adapter = netdev_priv(netdev);
1971 /* First thing is to stop the queue */
1972 netif_stop_queue(netdev);
1974 /* Stop the Tx and Rx DMA engines */
1975 et131x_rx_dma_disable(adapter);
1976 et131x_tx_dma_disable(adapter);
1978 /* Disable device interrupts */
1979 et131x_disable_interrupts(adapter);
1982 /* et131x_init_send - Initialize send data structures */
1983 static void et131x_init_send(struct et131x_adapter *adapter)
1986 struct tx_ring *tx_ring = &adapter->tx_ring;
1987 struct tcb *tcb = tx_ring->tcb_ring;
1989 tx_ring->tcb_qhead = tcb;
1991 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
1993 /* Go through and set up each TCB */
1994 for (ct = 0; ct++ < NUM_TCB; tcb++)
1995 /* Set the link pointer in HW TCB to the next TCB in the
1998 tcb->next = tcb + 1;
2000 /* Set the tail pointer */
2002 tx_ring->tcb_qtail = tcb;
2004 /* Curr send queue should now be empty */
2005 tx_ring->send_head = NULL;
2006 tx_ring->send_tail = NULL;
2009 /* et1310_enable_phy_coma - called when network cable is unplugged
2011 * driver receive an phy status change interrupt while in D0 and check that
2012 * phy_status is down.
2014 * -- gate off JAGCore;
2015 * -- set gigE PHY in Coma mode
2016 * -- wake on phy_interrupt; Perform software reset JAGCore,
2017 * re-initialize jagcore and gigE PHY
2019 * Add D0-ASPM-PhyLinkDown Support:
2020 * -- while in D0, when there is a phy_interrupt indicating phy link
2021 * down status, call the MPSetPhyComa routine to enter this active
2022 * state power saving mode
2023 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2024 * indicating linkup status, call the MPDisablePhyComa routine to
2025 * restore JAGCore and gigE PHY
2027 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2029 unsigned long flags;
2032 pmcsr = readl(&adapter->regs->global.pm_csr);
2034 /* Save the GbE PHY speed and duplex modes. Need to restore this
2035 * when cable is plugged back in
2038 /* Stop sending packets. */
2039 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2040 adapter->flags |= FMP_ADAPTER_LOWER_POWER;
2041 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2043 /* Wait for outstanding Receive packets */
2045 et131x_disable_txrx(adapter->netdev);
2047 /* Gate off JAGCore 3 clock domains */
2048 pmcsr &= ~ET_PMCSR_INIT;
2049 writel(pmcsr, &adapter->regs->global.pm_csr);
2051 /* Program gigE PHY in to Coma mode */
2052 pmcsr |= ET_PM_PHY_SW_COMA;
2053 writel(pmcsr, &adapter->regs->global.pm_csr);
2056 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
2057 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2061 pmcsr = readl(&adapter->regs->global.pm_csr);
2063 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2064 pmcsr |= ET_PMCSR_INIT;
2065 pmcsr &= ~ET_PM_PHY_SW_COMA;
2066 writel(pmcsr, &adapter->regs->global.pm_csr);
2068 /* Restore the GbE PHY speed and duplex modes;
2069 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2072 /* Re-initialize the send structures */
2073 et131x_init_send(adapter);
2075 /* Bring the device back to the state it was during init prior to
2076 * autonegotiation being complete. This way, when we get the auto-neg
2077 * complete interrupt, we can complete init by calling ConfigMacREGS2.
2079 et131x_soft_reset(adapter);
2081 /* setup et1310 as per the documentation ?? */
2082 et131x_adapter_setup(adapter);
2084 /* Allow Tx to restart */
2085 adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
2087 et131x_enable_txrx(adapter->netdev);
2090 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2092 u32 tmp_free_buff_ring = *free_buff_ring;
2094 tmp_free_buff_ring++;
2095 /* This works for all cases where limit < 1024. The 1023 case
2096 * works because 1023++ is 1024 which means the if condition is not
2097 * taken but the carry of the bit into the wrap bit toggles the wrap
2100 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2101 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2102 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2104 /* For the 1023 case */
2105 tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
2106 *free_buff_ring = tmp_free_buff_ring;
2107 return tmp_free_buff_ring;
2110 /* et131x_rx_dma_memory_alloc
2112 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2113 * and the Packet Status Ring.
2115 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2120 u32 pktstat_ringsize;
2122 struct rx_ring *rx_ring = &adapter->rx_ring;
2123 struct fbr_lookup *fbr;
2125 /* Alloc memory for the lookup table */
2126 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2127 if (rx_ring->fbr[0] == NULL)
2129 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2130 if (rx_ring->fbr[1] == NULL)
2133 /* The first thing we will do is configure the sizes of the buffer
2134 * rings. These will change based on jumbo packet support. Larger
2135 * jumbo packets increases the size of each entry in FBR0, and the
2136 * number of entries in FBR0, while at the same time decreasing the
2137 * number of entries in FBR1.
2139 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2140 * entries are huge in order to accommodate a "jumbo" frame, then it
2141 * will have less entries. Conversely, FBR1 will now be relied upon
2142 * to carry more "normal" frames, thus it's entry size also increases
2143 * and the number of entries goes up too (since it now carries
2144 * "small" + "regular" packets.
2146 * In this scheme, we try to maintain 512 entries between the two
2147 * rings. Also, FBR1 remains a constant size - when it's size doubles
2148 * the number of entries halves. FBR0 increases in size, however.
2151 if (adapter->registry_jumbo_packet < 2048) {
2152 rx_ring->fbr[0]->buffsize = 256;
2153 rx_ring->fbr[0]->num_entries = 512;
2154 rx_ring->fbr[1]->buffsize = 2048;
2155 rx_ring->fbr[1]->num_entries = 512;
2156 } else if (adapter->registry_jumbo_packet < 4096) {
2157 rx_ring->fbr[0]->buffsize = 512;
2158 rx_ring->fbr[0]->num_entries = 1024;
2159 rx_ring->fbr[1]->buffsize = 4096;
2160 rx_ring->fbr[1]->num_entries = 512;
2162 rx_ring->fbr[0]->buffsize = 1024;
2163 rx_ring->fbr[0]->num_entries = 768;
2164 rx_ring->fbr[1]->buffsize = 16384;
2165 rx_ring->fbr[1]->num_entries = 128;
2168 rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries +
2169 rx_ring->fbr[1]->num_entries;
2171 for (id = 0; id < NUM_FBRS; id++) {
2172 fbr = rx_ring->fbr[id];
2173 /* Allocate an area of memory for Free Buffer Ring */
2174 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2175 fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2177 &fbr->ring_physaddr,
2179 if (!fbr->ring_virtaddr) {
2180 dev_err(&adapter->pdev->dev,
2181 "Cannot alloc memory for Free Buffer Ring %d\n", id);
2186 for (id = 0; id < NUM_FBRS; id++) {
2187 fbr = rx_ring->fbr[id];
2188 fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
2190 for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
2191 dma_addr_t fbr_tmp_physaddr;
2193 fbr->mem_virtaddrs[i] = dma_alloc_coherent(
2194 &adapter->pdev->dev, fbr_chunksize,
2195 &fbr->mem_physaddrs[i],
2198 if (!fbr->mem_virtaddrs[i]) {
2199 dev_err(&adapter->pdev->dev,
2200 "Could not alloc memory\n");
2204 /* See NOTE in "Save Physical Address" comment above */
2205 fbr_tmp_physaddr = fbr->mem_physaddrs[i];
2207 for (j = 0; j < FBR_CHUNKS; j++) {
2208 u32 index = (i * FBR_CHUNKS) + j;
2210 /* Save the Virtual address of this index for
2211 * quick access later
2213 fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] +
2214 (j * fbr->buffsize);
2216 /* now store the physical address in the
2217 * descriptor so the device can access it
2219 fbr->bus_high[index] =
2220 upper_32_bits(fbr_tmp_physaddr);
2221 fbr->bus_low[index] =
2222 lower_32_bits(fbr_tmp_physaddr);
2224 fbr_tmp_physaddr += fbr->buffsize;
2229 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2231 sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries;
2233 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2235 &rx_ring->ps_ring_physaddr,
2238 if (!rx_ring->ps_ring_virtaddr) {
2239 dev_err(&adapter->pdev->dev,
2240 "Cannot alloc memory for Packet Status Ring\n");
2244 /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2245 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2246 * are ever returned, make sure the high part is retrieved here before
2247 * storing the adjusted address.
2250 /* Allocate an area of memory for writeback of status information */
2251 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2252 sizeof(struct rx_status_block),
2253 &rx_ring->rx_status_bus,
2255 if (!rx_ring->rx_status_block) {
2256 dev_err(&adapter->pdev->dev,
2257 "Cannot alloc memory for Status Block\n");
2260 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2262 /* The RFDs are going to be put on lists later on, so initialize the
2265 INIT_LIST_HEAD(&rx_ring->recv_list);
2269 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2270 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2275 u32 pktstat_ringsize;
2277 struct rx_ring *rx_ring = &adapter->rx_ring;
2278 struct fbr_lookup *fbr;
2280 /* Free RFDs and associated packet descriptors */
2281 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2283 while (!list_empty(&rx_ring->recv_list)) {
2284 rfd = list_entry(rx_ring->recv_list.next,
2285 struct rfd, list_node);
2287 list_del(&rfd->list_node);
2292 /* Free Free Buffer Rings */
2293 for (id = 0; id < NUM_FBRS; id++) {
2294 fbr = rx_ring->fbr[id];
2296 if (!fbr || !fbr->ring_virtaddr)
2299 /* First the packet memory */
2301 index < fbr->num_entries / FBR_CHUNKS;
2303 if (fbr->mem_virtaddrs[index]) {
2304 bufsize = fbr->buffsize * FBR_CHUNKS;
2306 dma_free_coherent(&adapter->pdev->dev,
2308 fbr->mem_virtaddrs[index],
2309 fbr->mem_physaddrs[index]);
2311 fbr->mem_virtaddrs[index] = NULL;
2315 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2317 dma_free_coherent(&adapter->pdev->dev,
2320 fbr->ring_physaddr);
2322 fbr->ring_virtaddr = NULL;
2325 /* Free Packet Status Ring */
2326 if (rx_ring->ps_ring_virtaddr) {
2327 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2328 rx_ring->psr_num_entries;
2330 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2331 rx_ring->ps_ring_virtaddr,
2332 rx_ring->ps_ring_physaddr);
2334 rx_ring->ps_ring_virtaddr = NULL;
2337 /* Free area of memory for the writeback of status information */
2338 if (rx_ring->rx_status_block) {
2339 dma_free_coherent(&adapter->pdev->dev,
2340 sizeof(struct rx_status_block),
2341 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2342 rx_ring->rx_status_block = NULL;
2345 /* Free the FBR Lookup Table */
2346 kfree(rx_ring->fbr[0]);
2347 kfree(rx_ring->fbr[1]);
2349 /* Reset Counters */
2350 rx_ring->num_ready_recv = 0;
2353 /* et131x_init_recv - Initialize receive data structures */
2354 static int et131x_init_recv(struct et131x_adapter *adapter)
2358 struct rx_ring *rx_ring = &adapter->rx_ring;
2360 /* Setup each RFD */
2361 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2362 rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA);
2368 /* Add this RFD to the recv_list */
2369 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2371 /* Increment the available RFD's */
2372 rx_ring->num_ready_recv++;
2378 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2379 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2381 struct phy_device *phydev = adapter->phydev;
2383 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2384 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2386 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2387 writel(0, &adapter->regs->rxdma.max_pkt_time);
2388 writel(1, &adapter->regs->rxdma.num_pkt_done);
2392 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2393 * @adapter: pointer to our adapter
2394 * @rfd: pointer to the RFD
2396 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2398 struct rx_ring *rx_local = &adapter->rx_ring;
2399 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2400 u16 buff_index = rfd->bufferindex;
2401 u8 ring_index = rfd->ringindex;
2402 unsigned long flags;
2403 struct fbr_lookup *fbr = rx_local->fbr[ring_index];
2405 /* We don't use any of the OOB data besides status. Otherwise, we
2406 * need to clean up OOB data
2408 if (buff_index < fbr->num_entries) {
2410 u32 __iomem *offset;
2411 struct fbr_desc *next;
2413 spin_lock_irqsave(&adapter->fbr_lock, flags);
2415 if (ring_index == 0)
2416 offset = &rx_dma->fbr0_full_offset;
2418 offset = &rx_dma->fbr1_full_offset;
2420 next = (struct fbr_desc *)(fbr->ring_virtaddr) +
2421 INDEX10(fbr->local_full);
2423 /* Handle the Free Buffer Ring advancement here. Write
2424 * the PA / Buffer Index for the returned buffer into
2425 * the oldest (next to be freed)FBR entry
2427 next->addr_hi = fbr->bus_high[buff_index];
2428 next->addr_lo = fbr->bus_low[buff_index];
2429 next->word2 = buff_index;
2431 free_buff_ring = bump_free_buff_ring(&fbr->local_full,
2432 fbr->num_entries - 1);
2433 writel(free_buff_ring, offset);
2435 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2437 dev_err(&adapter->pdev->dev,
2438 "%s illegal Buffer Index returned\n", __func__);
2441 /* The processing on this RFD is done, so put it back on the tail of
2444 spin_lock_irqsave(&adapter->rcv_lock, flags);
2445 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2446 rx_local->num_ready_recv++;
2447 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2449 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2452 /* nic_rx_pkts - Checks the hardware for available packets
2454 * Returns rfd, a pointer to our MPRFD.
2456 * Checks the hardware for available packets, using completion ring
2457 * If packets are available, it gets an RFD from the recv_list, attaches
2458 * the packet to it, puts the RFD in the RecvPendList, and also returns
2459 * the pointer to the RFD.
2461 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2463 struct rx_ring *rx_local = &adapter->rx_ring;
2464 struct rx_status_block *status;
2465 struct pkt_stat_desc *psr;
2469 unsigned long flags;
2470 struct list_head *element;
2476 struct sk_buff *skb;
2477 struct fbr_lookup *fbr;
2479 /* RX Status block is written by the DMA engine prior to every
2480 * interrupt. It contains the next to be used entry in the Packet
2481 * Status Ring, and also the two Free Buffer rings.
2483 status = rx_local->rx_status_block;
2484 word1 = status->word1 >> 16; /* Get the useful bits */
2486 /* Check the PSR and wrap bits do not match */
2487 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2488 return NULL; /* Looks like this ring is not updated yet */
2490 /* The packet status ring indicates that data is available. */
2491 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2492 (rx_local->local_psr_full & 0xFFF);
2494 /* Grab any information that is required once the PSR is advanced,
2495 * since we can no longer rely on the memory being accurate
2497 len = psr->word1 & 0xFFFF;
2498 ring_index = (psr->word1 >> 26) & 0x03;
2499 fbr = rx_local->fbr[ring_index];
2500 buff_index = (psr->word1 >> 16) & 0x3FF;
2503 /* Indicate that we have used this PSR entry. */
2505 add_12bit(&rx_local->local_psr_full, 1);
2507 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2508 /* Clear psr full and toggle the wrap bit */
2509 rx_local->local_psr_full &= ~0xFFF;
2510 rx_local->local_psr_full ^= 0x1000;
2513 writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2515 if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
2516 /* Illegal buffer or ring index cannot be used by S/W*/
2517 dev_err(&adapter->pdev->dev,
2518 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2519 rx_local->local_psr_full & 0xFFF, len, buff_index);
2523 /* Get and fill the RFD. */
2524 spin_lock_irqsave(&adapter->rcv_lock, flags);
2526 element = rx_local->recv_list.next;
2527 rfd = list_entry(element, struct rfd, list_node);
2530 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2534 list_del(&rfd->list_node);
2535 rx_local->num_ready_recv--;
2537 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2539 rfd->bufferindex = buff_index;
2540 rfd->ringindex = ring_index;
2542 /* In V1 silicon, there is a bug which screws up filtering of runt
2543 * packets. Therefore runt packet filtering is disabled in the MAC and
2544 * the packets are dropped here. They are also counted here.
2546 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2547 adapter->stats.rx_other_errs++;
2556 /* Determine if this is a multicast packet coming in */
2557 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2558 !(word0 & ALCATEL_BROADCAST_PKT)) {
2559 /* Promiscuous mode and Multicast mode are not mutually
2560 * exclusive as was first thought. I guess Promiscuous is just
2561 * considered a super-set of the other filters. Generally filter
2562 * is 0x2b when in promiscuous mode.
2564 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2565 && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2566 && !(adapter->packet_filter &
2567 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2568 buf = fbr->virt[buff_index];
2570 /* Loop through our list to see if the destination
2571 * address of this packet matches one in our list.
2573 for (i = 0; i < adapter->multicast_addr_count; i++) {
2574 if (buf[0] == adapter->multicast_list[i][0]
2575 && buf[1] == adapter->multicast_list[i][1]
2576 && buf[2] == adapter->multicast_list[i][2]
2577 && buf[3] == adapter->multicast_list[i][3]
2578 && buf[4] == adapter->multicast_list[i][4]
2579 && buf[5] == adapter->multicast_list[i][5]) {
2584 /* If our index is equal to the number of Multicast
2585 * address we have, then this means we did not find this
2586 * packet's matching address in our list. Set the len to
2587 * zero, so we free our RFD when we return from this
2590 if (i == adapter->multicast_addr_count)
2595 adapter->stats.multicast_pkts_rcvd++;
2596 } else if (word0 & ALCATEL_BROADCAST_PKT) {
2597 adapter->stats.broadcast_pkts_rcvd++;
2599 /* Not sure what this counter measures in promiscuous mode.
2600 * Perhaps we should check the MAC address to see if it is
2601 * directed to us in promiscuous mode.
2603 adapter->stats.unicast_pkts_rcvd++;
2613 skb = dev_alloc_skb(rfd->len + 2);
2615 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2619 adapter->netdev->stats.rx_bytes += rfd->len;
2621 memcpy(skb_put(skb, rfd->len), fbr->virt[buff_index], rfd->len);
2623 skb->protocol = eth_type_trans(skb, adapter->netdev);
2624 skb->ip_summed = CHECKSUM_NONE;
2628 nic_return_rfd(adapter, rfd);
2632 /* et131x_handle_recv_interrupt - Interrupt handler for receive processing
2634 * Assumption, Rcv spinlock has been acquired.
2636 static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2638 struct rfd *rfd = NULL;
2641 struct rx_ring *rx_ring = &adapter->rx_ring;
2643 /* Process up to available RFD's */
2644 while (count < NUM_PACKETS_HANDLED) {
2645 if (list_empty(&rx_ring->recv_list)) {
2646 WARN_ON(rx_ring->num_ready_recv != 0);
2651 rfd = nic_rx_pkts(adapter);
2656 /* Do not receive any packets until a filter has been set.
2657 * Do not receive any packets until we have link.
2658 * If length is zero, return the RFD in order to advance the
2661 if (!adapter->packet_filter ||
2662 !netif_carrier_ok(adapter->netdev) ||
2666 /* Increment the number of packets we received */
2667 adapter->netdev->stats.rx_packets++;
2669 /* Set the status on the packet, either resources or success */
2670 if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
2671 dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
2676 if (count == NUM_PACKETS_HANDLED || !done) {
2677 rx_ring->unfinished_receives = true;
2678 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2679 &adapter->regs->global.watchdog_timer);
2681 /* Watchdog timer will disable itself if appropriate. */
2682 rx_ring->unfinished_receives = false;
2685 /* et131x_tx_dma_memory_alloc
2687 * Allocates memory that will be visible both to the device and to the CPU.
2688 * The OS will pass us packets, pointers to which we will insert in the Tx
2689 * Descriptor queue. The device will read this queue to find the packets in
2690 * memory. The device will update the "status" in memory each time it xmits a
2693 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2696 struct tx_ring *tx_ring = &adapter->tx_ring;
2698 /* Allocate memory for the TCB's (Transmit Control Block) */
2699 tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
2700 GFP_ATOMIC | GFP_DMA);
2701 if (!tx_ring->tcb_ring)
2704 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2705 tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
2707 &tx_ring->tx_desc_ring_pa,
2709 if (!tx_ring->tx_desc_ring) {
2710 dev_err(&adapter->pdev->dev,
2711 "Cannot alloc memory for Tx Ring\n");
2715 /* Save physical address
2717 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2718 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2719 * are ever returned, make sure the high part is retrieved here before
2720 * storing the adjusted address.
2722 /* Allocate memory for the Tx status block */
2723 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2725 &tx_ring->tx_status_pa,
2727 if (!tx_ring->tx_status_pa) {
2728 dev_err(&adapter->pdev->dev,
2729 "Cannot alloc memory for Tx status block\n");
2735 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2736 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2739 struct tx_ring *tx_ring = &adapter->tx_ring;
2741 if (tx_ring->tx_desc_ring) {
2742 /* Free memory relating to Tx rings here */
2743 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2744 dma_free_coherent(&adapter->pdev->dev,
2746 tx_ring->tx_desc_ring,
2747 tx_ring->tx_desc_ring_pa);
2748 tx_ring->tx_desc_ring = NULL;
2751 /* Free memory for the Tx status block */
2752 if (tx_ring->tx_status) {
2753 dma_free_coherent(&adapter->pdev->dev,
2756 tx_ring->tx_status_pa);
2758 tx_ring->tx_status = NULL;
2760 /* Free the memory for the tcb structures */
2761 kfree(tx_ring->tcb_ring);
2764 /* nic_send_packet - NIC specific send handler for version B silicon.
2765 * @adapter: pointer to our adapter
2766 * @tcb: pointer to struct tcb
2768 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2771 struct tx_desc desc[24]; /* 24 x 16 byte */
2773 u32 thiscopy, remainder;
2774 struct sk_buff *skb = tcb->skb;
2775 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2776 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2777 unsigned long flags;
2778 struct phy_device *phydev = adapter->phydev;
2779 dma_addr_t dma_addr;
2780 struct tx_ring *tx_ring = &adapter->tx_ring;
2782 /* Part of the optimizations of this send routine restrict us to
2783 * sending 24 fragments at a pass. In practice we should never see
2784 * more than 5 fragments.
2786 * NOTE: The older version of this function (below) can handle any
2787 * number of fragments. If needed, we can call this function,
2788 * although it is less efficient.
2791 /* nr_frags should be no more than 18. */
2792 BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
2794 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2796 for (i = 0; i < nr_frags; i++) {
2797 /* If there is something in this element, lets get a
2798 * descriptor from the ring and get the necessary data
2801 /* If the fragments are smaller than a standard MTU,
2802 * then map them to a single descriptor in the Tx
2803 * Desc ring. However, if they're larger, as is
2804 * possible with support for jumbo packets, then
2805 * split them each across 2 descriptors.
2807 * This will work until we determine why the hardware
2808 * doesn't seem to like large fragments.
2810 if (skb_headlen(skb) <= 1514) {
2811 /* Low 16bits are length, high is vlan and
2812 * unused currently so zero
2814 desc[frag].len_vlan = skb_headlen(skb);
2815 dma_addr = dma_map_single(&adapter->pdev->dev,
2819 desc[frag].addr_lo = lower_32_bits(dma_addr);
2820 desc[frag].addr_hi = upper_32_bits(dma_addr);
2823 desc[frag].len_vlan = skb_headlen(skb) / 2;
2824 dma_addr = dma_map_single(&adapter->pdev->dev,
2826 (skb_headlen(skb) / 2),
2828 desc[frag].addr_lo = lower_32_bits(dma_addr);
2829 desc[frag].addr_hi = upper_32_bits(dma_addr);
2832 desc[frag].len_vlan = skb_headlen(skb) / 2;
2833 dma_addr = dma_map_single(&adapter->pdev->dev,
2835 (skb_headlen(skb) / 2),
2836 (skb_headlen(skb) / 2),
2838 desc[frag].addr_lo = lower_32_bits(dma_addr);
2839 desc[frag].addr_hi = upper_32_bits(dma_addr);
2843 desc[frag].len_vlan = frags[i - 1].size;
2844 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
2849 desc[frag].addr_lo = lower_32_bits(dma_addr);
2850 desc[frag].addr_hi = upper_32_bits(dma_addr);
2855 if (phydev && phydev->speed == SPEED_1000) {
2856 if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
2857 /* Last element & Interrupt flag */
2858 desc[frag - 1].flags =
2859 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2860 tx_ring->since_irq = 0;
2861 } else { /* Last element */
2862 desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
2865 desc[frag - 1].flags =
2866 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2868 desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
2870 tcb->index_start = tx_ring->send_idx;
2873 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2875 thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
2877 if (thiscopy >= frag) {
2881 remainder = frag - thiscopy;
2884 memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
2886 sizeof(struct tx_desc) * thiscopy);
2888 add_10bit(&tx_ring->send_idx, thiscopy);
2890 if (INDEX10(tx_ring->send_idx) == 0 ||
2891 INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
2892 tx_ring->send_idx &= ~ET_DMA10_MASK;
2893 tx_ring->send_idx ^= ET_DMA10_WRAP;
2897 memcpy(tx_ring->tx_desc_ring,
2899 sizeof(struct tx_desc) * remainder);
2901 add_10bit(&tx_ring->send_idx, remainder);
2904 if (INDEX10(tx_ring->send_idx) == 0) {
2905 if (tx_ring->send_idx)
2906 tcb->index = NUM_DESC_PER_RING_TX - 1;
2908 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2910 tcb->index = tx_ring->send_idx - 1;
2912 spin_lock(&adapter->tcb_send_qlock);
2914 if (tx_ring->send_tail)
2915 tx_ring->send_tail->next = tcb;
2917 tx_ring->send_head = tcb;
2919 tx_ring->send_tail = tcb;
2921 WARN_ON(tcb->next != NULL);
2925 spin_unlock(&adapter->tcb_send_qlock);
2927 /* Write the new write pointer back to the device. */
2928 writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
2930 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2931 * timer to wake us up if this packet isn't followed by N more.
2933 if (phydev && phydev->speed == SPEED_1000) {
2934 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2935 &adapter->regs->global.watchdog_timer);
2937 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2942 /* send_packet - Do the work to send a packet
2944 * Assumption: Send spinlock has been acquired
2946 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2951 unsigned long flags;
2952 struct tx_ring *tx_ring = &adapter->tx_ring;
2954 /* All packets must have at least a MAC address and a protocol type */
2955 if (skb->len < ETH_HLEN)
2958 /* Get a TCB for this packet */
2959 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2961 tcb = tx_ring->tcb_qhead;
2964 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2968 tx_ring->tcb_qhead = tcb->next;
2970 if (tx_ring->tcb_qhead == NULL)
2971 tx_ring->tcb_qtail = NULL;
2973 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2977 if (skb->data != NULL && skb_headlen(skb) >= 6) {
2978 shbufva = (u16 *) skb->data;
2980 if ((shbufva[0] == 0xffff) &&
2981 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff))
2982 tcb->flags |= FMP_DEST_BROAD;
2983 else if ((shbufva[0] & 0x3) == 0x0001)
2984 tcb->flags |= FMP_DEST_MULTI;
2989 /* Call the NIC specific send handler. */
2990 status = nic_send_packet(adapter, tcb);
2993 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2995 if (tx_ring->tcb_qtail)
2996 tx_ring->tcb_qtail->next = tcb;
2998 /* Apparently ready Q is empty. */
2999 tx_ring->tcb_qhead = tcb;
3001 tx_ring->tcb_qtail = tcb;
3002 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3005 WARN_ON(tx_ring->used > NUM_TCB);
3009 /* et131x_send_packets - This function is called by the OS to send packets */
3010 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3013 struct et131x_adapter *adapter = netdev_priv(netdev);
3014 struct tx_ring *tx_ring = &adapter->tx_ring;
3016 /* Send these packets
3018 * NOTE: The Linux Tx entry point is only given one packet at a time
3019 * to Tx, so the PacketCount and it's array used makes no sense here
3022 /* TCB is not available */
3023 if (tx_ring->used >= NUM_TCB) {
3024 /* NOTE: If there's an error on send, no need to queue the
3025 * packet under Linux; if we just send an error up to the
3026 * netif layer, it will resend the skb to us.
3030 /* We need to see if the link is up; if it's not, make the
3031 * netif layer think we're good and drop the packet
3033 if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
3034 !netif_carrier_ok(netdev)) {
3035 dev_kfree_skb_any(skb);
3038 adapter->netdev->stats.tx_dropped++;
3040 status = send_packet(skb, adapter);
3041 if (status != 0 && status != -ENOMEM) {
3042 /* On any other error, make netif think we're
3043 * OK and drop the packet
3045 dev_kfree_skb_any(skb);
3047 adapter->netdev->stats.tx_dropped++;
3054 /* free_send_packet - Recycle a struct tcb
3055 * @adapter: pointer to our adapter
3056 * @tcb: pointer to struct tcb
3058 * Complete the packet if necessary
3059 * Assumption - Send spinlock has been acquired
3061 static inline void free_send_packet(struct et131x_adapter *adapter,
3064 unsigned long flags;
3065 struct tx_desc *desc = NULL;
3066 struct net_device_stats *stats = &adapter->netdev->stats;
3067 struct tx_ring *tx_ring = &adapter->tx_ring;
3070 if (tcb->flags & FMP_DEST_BROAD)
3071 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3072 else if (tcb->flags & FMP_DEST_MULTI)
3073 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3075 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3078 stats->tx_bytes += tcb->skb->len;
3080 /* Iterate through the TX descriptors on the ring
3081 * corresponding to this packet and umap the fragments
3085 desc = tx_ring->tx_desc_ring +
3086 INDEX10(tcb->index_start);
3088 dma_addr = desc->addr_lo;
3089 dma_addr |= (u64)desc->addr_hi << 32;
3091 dma_unmap_single(&adapter->pdev->dev,
3093 desc->len_vlan, DMA_TO_DEVICE);
3095 add_10bit(&tcb->index_start, 1);
3096 if (INDEX10(tcb->index_start) >=
3097 NUM_DESC_PER_RING_TX) {
3098 tcb->index_start &= ~ET_DMA10_MASK;
3099 tcb->index_start ^= ET_DMA10_WRAP;
3101 } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
3103 dev_kfree_skb_any(tcb->skb);
3106 memset(tcb, 0, sizeof(struct tcb));
3108 /* Add the TCB to the Ready Q */
3109 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3111 stats->tx_packets++;
3113 if (tx_ring->tcb_qtail)
3114 tx_ring->tcb_qtail->next = tcb;
3116 /* Apparently ready Q is empty. */
3117 tx_ring->tcb_qhead = tcb;
3119 tx_ring->tcb_qtail = tcb;
3121 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3122 WARN_ON(tx_ring->used < 0);
3125 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
3127 * Assumption - Send spinlock has been acquired
3129 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3132 unsigned long flags;
3134 struct tx_ring *tx_ring = &adapter->tx_ring;
3136 /* Any packets being sent? Check the first TCB on the send list */
3137 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3139 tcb = tx_ring->send_head;
3141 while (tcb != NULL && freed < NUM_TCB) {
3142 struct tcb *next = tcb->next;
3144 tx_ring->send_head = next;
3147 tx_ring->send_tail = NULL;
3151 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3154 free_send_packet(adapter, tcb);
3156 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3158 tcb = tx_ring->send_head;
3161 WARN_ON(freed == NUM_TCB);
3163 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3168 /* et131x_handle_send_interrupt - Interrupt handler for sending processing
3170 * Re-claim the send resources, complete sends and get more to send from
3171 * the send wait queue.
3173 * Assumption - Send spinlock has been acquired
3175 static void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3177 unsigned long flags;
3181 struct tx_ring *tx_ring = &adapter->tx_ring;
3183 serviced = readl(&adapter->regs->txdma.new_service_complete);
3184 index = INDEX10(serviced);
3186 /* Has the ring wrapped? Process any descriptors that do not have
3187 * the same "wrap" indicator as the current completion indicator
3189 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3191 tcb = tx_ring->send_head;
3194 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3195 index < INDEX10(tcb->index)) {
3197 tx_ring->send_head = tcb->next;
3198 if (tcb->next == NULL)
3199 tx_ring->send_tail = NULL;
3201 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3202 free_send_packet(adapter, tcb);
3203 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3205 /* Goto the next packet */
3206 tcb = tx_ring->send_head;
3209 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3210 && index > (tcb->index & ET_DMA10_MASK)) {
3212 tx_ring->send_head = tcb->next;
3213 if (tcb->next == NULL)
3214 tx_ring->send_tail = NULL;
3216 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3217 free_send_packet(adapter, tcb);
3218 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3220 /* Goto the next packet */
3221 tcb = tx_ring->send_head;
3224 /* Wake up the queue when we hit a low-water mark */
3225 if (tx_ring->used <= NUM_TCB / 3)
3226 netif_wake_queue(adapter->netdev);
3228 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3231 static int et131x_get_settings(struct net_device *netdev,
3232 struct ethtool_cmd *cmd)
3234 struct et131x_adapter *adapter = netdev_priv(netdev);
3236 return phy_ethtool_gset(adapter->phydev, cmd);
3239 static int et131x_set_settings(struct net_device *netdev,
3240 struct ethtool_cmd *cmd)
3242 struct et131x_adapter *adapter = netdev_priv(netdev);
3244 return phy_ethtool_sset(adapter->phydev, cmd);
3247 static int et131x_get_regs_len(struct net_device *netdev)
3249 #define ET131X_REGS_LEN 256
3250 return ET131X_REGS_LEN * sizeof(u32);
3253 static void et131x_get_regs(struct net_device *netdev,
3254 struct ethtool_regs *regs, void *regs_data)
3256 struct et131x_adapter *adapter = netdev_priv(netdev);
3257 struct address_map __iomem *aregs = adapter->regs;
3258 u32 *regs_buff = regs_data;
3262 memset(regs_data, 0, et131x_get_regs_len(netdev));
3264 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3265 adapter->pdev->device;
3268 et131x_mii_read(adapter, MII_BMCR, &tmp);
3269 regs_buff[num++] = tmp;
3270 et131x_mii_read(adapter, MII_BMSR, &tmp);
3271 regs_buff[num++] = tmp;
3272 et131x_mii_read(adapter, MII_PHYSID1, &tmp);
3273 regs_buff[num++] = tmp;
3274 et131x_mii_read(adapter, MII_PHYSID2, &tmp);
3275 regs_buff[num++] = tmp;
3276 et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
3277 regs_buff[num++] = tmp;
3278 et131x_mii_read(adapter, MII_LPA, &tmp);
3279 regs_buff[num++] = tmp;
3280 et131x_mii_read(adapter, MII_EXPANSION, &tmp);
3281 regs_buff[num++] = tmp;
3282 /* Autoneg next page transmit reg */
3283 et131x_mii_read(adapter, 0x07, &tmp);
3284 regs_buff[num++] = tmp;
3285 /* Link partner next page reg */
3286 et131x_mii_read(adapter, 0x08, &tmp);
3287 regs_buff[num++] = tmp;
3288 et131x_mii_read(adapter, MII_CTRL1000, &tmp);
3289 regs_buff[num++] = tmp;
3290 et131x_mii_read(adapter, MII_STAT1000, &tmp);
3291 regs_buff[num++] = tmp;
3292 et131x_mii_read(adapter, 0x0b, &tmp);
3293 regs_buff[num++] = tmp;
3294 et131x_mii_read(adapter, 0x0c, &tmp);
3295 regs_buff[num++] = tmp;
3296 et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
3297 regs_buff[num++] = tmp;
3298 et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
3299 regs_buff[num++] = tmp;
3300 et131x_mii_read(adapter, MII_ESTATUS, &tmp);
3301 regs_buff[num++] = tmp;
3303 et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
3304 regs_buff[num++] = tmp;
3305 et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
3306 regs_buff[num++] = tmp;
3307 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
3308 regs_buff[num++] = tmp;
3309 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
3310 regs_buff[num++] = tmp;
3311 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
3312 regs_buff[num++] = tmp;
3314 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
3315 regs_buff[num++] = tmp;
3316 et131x_mii_read(adapter, PHY_CONFIG, &tmp);
3317 regs_buff[num++] = tmp;
3318 et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
3319 regs_buff[num++] = tmp;
3320 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
3321 regs_buff[num++] = tmp;
3322 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
3323 regs_buff[num++] = tmp;
3324 et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
3325 regs_buff[num++] = tmp;
3326 et131x_mii_read(adapter, PHY_LED_1, &tmp);
3327 regs_buff[num++] = tmp;
3328 et131x_mii_read(adapter, PHY_LED_2, &tmp);
3329 regs_buff[num++] = tmp;
3332 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3333 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3334 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3335 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3336 regs_buff[num++] = readl(&aregs->global.pm_csr);
3337 regs_buff[num++] = adapter->stats.interrupt_status;
3338 regs_buff[num++] = readl(&aregs->global.int_mask);
3339 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3340 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3341 regs_buff[num++] = readl(&aregs->global.sw_reset);
3342 regs_buff[num++] = readl(&aregs->global.slv_timer);
3343 regs_buff[num++] = readl(&aregs->global.msi_config);
3344 regs_buff[num++] = readl(&aregs->global.loopback);
3345 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3348 regs_buff[num++] = readl(&aregs->txdma.csr);
3349 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3350 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3351 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3352 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3353 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3354 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3355 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3356 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3357 regs_buff[num++] = readl(&aregs->txdma.service_request);
3358 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3359 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3360 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3361 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3362 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3363 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3364 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3365 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3366 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3367 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3368 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3369 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3370 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3371 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3372 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3373 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3376 regs_buff[num++] = readl(&aregs->rxdma.csr);
3377 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3378 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3379 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3380 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3381 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3382 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3383 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3384 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3385 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3386 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3387 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3388 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3389 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3390 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3391 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3392 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3393 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3394 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3395 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3396 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3397 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3398 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3399 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3400 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3401 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3402 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3403 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3404 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3407 static void et131x_get_drvinfo(struct net_device *netdev,
3408 struct ethtool_drvinfo *info)
3410 struct et131x_adapter *adapter = netdev_priv(netdev);
3412 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
3413 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3414 strlcpy(info->bus_info, pci_name(adapter->pdev),
3415 sizeof(info->bus_info));
3418 static struct ethtool_ops et131x_ethtool_ops = {
3419 .get_settings = et131x_get_settings,
3420 .set_settings = et131x_set_settings,
3421 .get_drvinfo = et131x_get_drvinfo,
3422 .get_regs_len = et131x_get_regs_len,
3423 .get_regs = et131x_get_regs,
3424 .get_link = ethtool_op_get_link,
3427 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3428 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3430 /* If have our default mac from init and no mac address from
3431 * EEPROM then we need to generate the last octet and set it on the
3434 if (is_zero_ether_addr(adapter->rom_addr)) {
3435 /* We need to randomly generate the last octet so we
3436 * decrease our chances of setting the mac address to
3437 * same as another one of our cards in the system
3439 get_random_bytes(&adapter->addr[5], 1);
3440 /* We have the default value in the register we are
3441 * working with so we need to copy the current
3442 * address into the permanent address
3444 memcpy(adapter->rom_addr,
3445 adapter->addr, ETH_ALEN);
3447 /* We do not have an override address, so set the
3448 * current address to the permanent address and add
3451 memcpy(adapter->addr,
3452 adapter->rom_addr, ETH_ALEN);
3456 /* et131x_pci_init - initial PCI setup
3458 * Perform the initial setup of PCI registers and if possible initialise
3459 * the MAC address. At this point the I/O registers have yet to be mapped
3461 static int et131x_pci_init(struct et131x_adapter *adapter,
3462 struct pci_dev *pdev)
3467 rc = et131x_init_eeprom(adapter);
3471 if (!pci_is_pcie(pdev)) {
3472 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3476 /* Let's set up the PORT LOGIC Register. */
3478 /* Program the Ack/Nak latency and replay timers */
3479 max_payload = pdev->pcie_mpss;
3481 if (max_payload < 2) {
3482 static const u16 acknak[2] = { 0x76, 0xD0 };
3483 static const u16 replay[2] = { 0x1E0, 0x2ED };
3485 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3486 acknak[max_payload])) {
3488 "Could not write PCI config space for ACK/NAK\n");
3491 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3492 replay[max_payload])) {
3494 "Could not write PCI config space for Replay Timer\n");
3499 /* l0s and l1 latency timers. We are using default values.
3500 * Representing 001 for L0s and 010 for L1
3502 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3504 "Could not write PCI config space for Latency Timers\n");
3508 /* Change the max read size to 2k */
3509 if (pcie_set_readrq(pdev, 2048)) {
3511 "Couldn't change PCI config space for Max read size\n");
3515 /* Get MAC address from config space if an eeprom exists, otherwise
3516 * the MAC address there will not be valid
3518 if (!adapter->has_eeprom) {
3519 et131x_hwaddr_init(adapter);
3523 for (i = 0; i < ETH_ALEN; i++) {
3524 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3525 adapter->rom_addr + i)) {
3526 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3530 ether_addr_copy(adapter->addr, adapter->rom_addr);
3538 /* et131x_error_timer_handler
3539 * @data: timer-specific variable; here a pointer to our adapter structure
3541 * The routine called when the error timer expires, to track the number of
3544 static void et131x_error_timer_handler(unsigned long data)
3546 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3547 struct phy_device *phydev = adapter->phydev;
3549 if (et1310_in_phy_coma(adapter)) {
3550 /* Bring the device immediately out of coma, to
3551 * prevent it from sleeping indefinitely, this
3552 * mechanism could be improved!
3554 et1310_disable_phy_coma(adapter);
3555 adapter->boot_coma = 20;
3557 et1310_update_macstat_host_counters(adapter);
3560 if (!phydev->link && adapter->boot_coma < 11)
3561 adapter->boot_coma++;
3563 if (adapter->boot_coma == 10) {
3564 if (!phydev->link) {
3565 if (!et1310_in_phy_coma(adapter)) {
3566 /* NOTE - This was originally a 'sync with
3567 * interrupt'. How to do that under Linux?
3569 et131x_enable_interrupts(adapter);
3570 et1310_enable_phy_coma(adapter);
3575 /* This is a periodic timer, so reschedule */
3576 mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3579 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3580 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3582 et131x_tx_dma_memory_free(adapter);
3583 et131x_rx_dma_memory_free(adapter);
3586 /* et131x_adapter_memory_alloc
3587 * Allocate all the memory blocks for send, receive and others.
3589 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3593 /* Allocate memory for the Tx Ring */
3594 status = et131x_tx_dma_memory_alloc(adapter);
3596 dev_err(&adapter->pdev->dev,
3597 "et131x_tx_dma_memory_alloc FAILED\n");
3598 et131x_tx_dma_memory_free(adapter);
3601 /* Receive buffer memory allocation */
3602 status = et131x_rx_dma_memory_alloc(adapter);
3604 dev_err(&adapter->pdev->dev,
3605 "et131x_rx_dma_memory_alloc FAILED\n");
3606 et131x_adapter_memory_free(adapter);
3610 /* Init receive data structures */
3611 status = et131x_init_recv(adapter);
3613 dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
3614 et131x_adapter_memory_free(adapter);
3619 static void et131x_adjust_link(struct net_device *netdev)
3621 struct et131x_adapter *adapter = netdev_priv(netdev);
3622 struct phy_device *phydev = adapter->phydev;
3626 if (phydev->link == adapter->link)
3629 /* Check to see if we are in coma mode and if
3630 * so, disable it because we will not be able
3631 * to read PHY values until we are out.
3633 if (et1310_in_phy_coma(adapter))
3634 et1310_disable_phy_coma(adapter);
3636 adapter->link = phydev->link;
3637 phy_print_status(phydev);
3640 adapter->boot_coma = 20;
3641 if (phydev->speed == SPEED_10) {
3644 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3646 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3648 et131x_mii_write(adapter, PHY_INDEX_REG,
3649 register18 | 0x8402);
3650 et131x_mii_write(adapter, PHY_DATA_REG,
3652 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3656 et1310_config_flow_control(adapter);
3658 if (phydev->speed == SPEED_1000 &&
3659 adapter->registry_jumbo_packet > 2048) {
3662 et131x_mii_read(adapter, PHY_CONFIG, ®);
3663 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3664 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3665 et131x_mii_write(adapter, PHY_CONFIG, reg);
3668 et131x_set_rx_dma_timer(adapter);
3669 et1310_config_mac_regs2(adapter);
3671 adapter->boot_coma = 0;
3673 if (phydev->speed == SPEED_10) {
3676 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3678 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3680 et131x_mii_write(adapter, PHY_INDEX_REG,
3681 register18 | 0x8402);
3682 et131x_mii_write(adapter, PHY_DATA_REG,
3684 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3688 /* Free the packets being actively sent & stopped */
3689 et131x_free_busy_send_packets(adapter);
3691 /* Re-initialize the send structures */
3692 et131x_init_send(adapter);
3694 /* Bring the device back to the state it was during
3695 * init prior to autonegotiation being complete. This
3696 * way, when we get the auto-neg complete interrupt,
3697 * we can complete init by calling config_mac_regs2.
3699 et131x_soft_reset(adapter);
3701 /* Setup ET1310 as per the documentation */
3702 et131x_adapter_setup(adapter);
3704 /* perform reset of tx/rx */
3705 et131x_disable_txrx(netdev);
3706 et131x_enable_txrx(netdev);
3710 static int et131x_mii_probe(struct net_device *netdev)
3712 struct et131x_adapter *adapter = netdev_priv(netdev);
3713 struct phy_device *phydev = NULL;
3715 phydev = phy_find_first(adapter->mii_bus);
3717 dev_err(&adapter->pdev->dev, "no PHY found\n");
3721 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3722 &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
3724 if (IS_ERR(phydev)) {
3725 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3726 return PTR_ERR(phydev);
3729 phydev->supported &= (SUPPORTED_10baseT_Half
3730 | SUPPORTED_10baseT_Full
3731 | SUPPORTED_100baseT_Half
3732 | SUPPORTED_100baseT_Full
3737 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3738 phydev->supported |= SUPPORTED_1000baseT_Full;
3740 phydev->advertising = phydev->supported;
3741 adapter->phydev = phydev;
3743 dev_info(&adapter->pdev->dev,
3744 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3745 phydev->drv->name, dev_name(&phydev->dev));
3750 /* et131x_adapter_init
3752 * Initialize the data structures for the et131x_adapter object and link
3753 * them together with the platform provided device structures.
3755 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3756 struct pci_dev *pdev)
3758 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3760 struct et131x_adapter *adapter;
3762 /* Allocate private adapter struct and copy in relevant information */
3763 adapter = netdev_priv(netdev);
3764 adapter->pdev = pci_dev_get(pdev);
3765 adapter->netdev = netdev;
3767 /* Initialize spinlocks here */
3768 spin_lock_init(&adapter->tcb_send_qlock);
3769 spin_lock_init(&adapter->tcb_ready_qlock);
3770 spin_lock_init(&adapter->send_hw_lock);
3771 spin_lock_init(&adapter->rcv_lock);
3772 spin_lock_init(&adapter->fbr_lock);
3774 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
3776 /* Set the MAC address to a default */
3777 ether_addr_copy(adapter->addr, default_mac);
3782 /* et131x_pci_remove
3784 * Registered in the pci_driver structure, this function is called when the
3785 * PCI subsystem detects that a PCI device which matches the information
3786 * contained in the pci_device_id table has been removed.
3788 static void et131x_pci_remove(struct pci_dev *pdev)
3790 struct net_device *netdev = pci_get_drvdata(pdev);
3791 struct et131x_adapter *adapter = netdev_priv(netdev);
3793 unregister_netdev(netdev);
3794 phy_disconnect(adapter->phydev);
3795 mdiobus_unregister(adapter->mii_bus);
3796 cancel_work_sync(&adapter->task);
3797 kfree(adapter->mii_bus->irq);
3798 mdiobus_free(adapter->mii_bus);
3800 et131x_adapter_memory_free(adapter);
3801 iounmap(adapter->regs);
3804 free_netdev(netdev);
3805 pci_release_regions(pdev);
3806 pci_disable_device(pdev);
3809 /* et131x_up - Bring up a device for use. */
3810 static void et131x_up(struct net_device *netdev)
3812 struct et131x_adapter *adapter = netdev_priv(netdev);
3814 et131x_enable_txrx(netdev);
3815 phy_start(adapter->phydev);
3818 /* et131x_down - Bring down the device */
3819 static void et131x_down(struct net_device *netdev)
3821 struct et131x_adapter *adapter = netdev_priv(netdev);
3823 /* Save the timestamp for the TX watchdog, prevent a timeout */
3824 netdev->trans_start = jiffies;
3826 phy_stop(adapter->phydev);
3827 et131x_disable_txrx(netdev);
3830 #ifdef CONFIG_PM_SLEEP
3831 static int et131x_suspend(struct device *dev)
3833 struct pci_dev *pdev = to_pci_dev(dev);
3834 struct net_device *netdev = pci_get_drvdata(pdev);
3836 if (netif_running(netdev)) {
3837 netif_device_detach(netdev);
3838 et131x_down(netdev);
3839 pci_save_state(pdev);
3845 static int et131x_resume(struct device *dev)
3847 struct pci_dev *pdev = to_pci_dev(dev);
3848 struct net_device *netdev = pci_get_drvdata(pdev);
3850 if (netif_running(netdev)) {
3851 pci_restore_state(pdev);
3853 netif_device_attach(netdev);
3859 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
3860 #define ET131X_PM_OPS (&et131x_pm_ops)
3862 #define ET131X_PM_OPS NULL
3865 /* et131x_isr - The Interrupt Service Routine for the driver.
3866 * @irq: the IRQ on which the interrupt was received.
3867 * @dev_id: device-specific info (here a pointer to a net_device struct)
3869 * Returns a value indicating if the interrupt was handled.
3871 static irqreturn_t et131x_isr(int irq, void *dev_id)
3873 bool handled = true;
3874 struct net_device *netdev = (struct net_device *)dev_id;
3875 struct et131x_adapter *adapter = netdev_priv(netdev);
3876 struct rx_ring *rx_ring = &adapter->rx_ring;
3877 struct tx_ring *tx_ring = &adapter->tx_ring;
3880 if (!netif_device_present(netdev)) {
3885 /* If the adapter is in low power state, then it should not
3886 * recognize any interrupt
3889 /* Disable Device Interrupts */
3890 et131x_disable_interrupts(adapter);
3892 /* Get a copy of the value in the interrupt status register
3893 * so we can process the interrupting section
3895 status = readl(&adapter->regs->global.int_status);
3897 if (adapter->flowcontrol == FLOW_TXONLY ||
3898 adapter->flowcontrol == FLOW_BOTH) {
3899 status &= ~INT_MASK_ENABLE;
3901 status &= ~INT_MASK_ENABLE_NO_FLOW;
3904 /* Make sure this is our interrupt */
3907 et131x_enable_interrupts(adapter);
3911 /* This is our interrupt, so process accordingly */
3913 if (status & ET_INTR_WATCHDOG) {
3914 struct tcb *tcb = tx_ring->send_head;
3917 if (++tcb->stale > 1)
3918 status |= ET_INTR_TXDMA_ISR;
3920 if (rx_ring->unfinished_receives)
3921 status |= ET_INTR_RXDMA_XFR_DONE;
3922 else if (tcb == NULL)
3923 writel(0, &adapter->regs->global.watchdog_timer);
3925 status &= ~ET_INTR_WATCHDOG;
3929 /* This interrupt has in some way been "handled" by
3930 * the ISR. Either it was a spurious Rx interrupt, or
3931 * it was a Tx interrupt that has been filtered by
3934 et131x_enable_interrupts(adapter);
3938 /* We need to save the interrupt status value for use in our
3939 * DPC. We will clear the software copy of that in that
3942 adapter->stats.interrupt_status = status;
3944 /* Schedule the ISR handler as a bottom-half task in the
3945 * kernel's tq_immediate queue, and mark the queue for
3948 schedule_work(&adapter->task);
3950 return IRQ_RETVAL(handled);
3953 /* et131x_isr_handler - The ISR handler
3955 * scheduled to run in a deferred context by the ISR. This is where the ISR's
3956 * work actually gets done.
3958 static void et131x_isr_handler(struct work_struct *work)
3960 struct et131x_adapter *adapter =
3961 container_of(work, struct et131x_adapter, task);
3962 u32 status = adapter->stats.interrupt_status;
3963 struct address_map __iomem *iomem = adapter->regs;
3965 /* These first two are by far the most common. Once handled, we clear
3966 * their two bits in the status word. If the word is now zero, we
3969 /* Handle all the completed Transmit interrupts */
3970 if (status & ET_INTR_TXDMA_ISR)
3971 et131x_handle_send_interrupt(adapter);
3973 /* Handle all the completed Receives interrupts */
3974 if (status & ET_INTR_RXDMA_XFR_DONE)
3975 et131x_handle_recv_interrupt(adapter);
3977 status &= ~(ET_INTR_TXDMA_ERR | ET_INTR_RXDMA_XFR_DONE);
3982 /* Handle the TXDMA Error interrupt */
3983 if (status & ET_INTR_TXDMA_ERR) {
3984 /* Following read also clears the register (COR) */
3985 u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
3987 dev_warn(&adapter->pdev->dev,
3988 "TXDMA_ERR interrupt, error = %d\n",
3992 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
3993 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
3994 /* This indicates the number of unused buffers in RXDMA free
3995 * buffer ring 0 is <= the limit you programmed. Free buffer
3996 * resources need to be returned. Free buffers are consumed as
3997 * packets are passed from the network to the host. The host
3998 * becomes aware of the packets from the contents of the packet
3999 * status ring. This ring is queried when the packet done
4000 * interrupt occurs. Packets are then passed to the OS. When
4001 * the OS is done with the packets the resources can be
4002 * returned to the ET1310 for re-use. This interrupt is one
4003 * method of returning resources.
4006 /* If the user has flow control on, then we will
4007 * send a pause packet, otherwise just exit
4009 if (adapter->flowcontrol == FLOW_TXONLY ||
4010 adapter->flowcontrol == FLOW_BOTH) {
4013 /* Tell the device to send a pause packet via the back
4014 * pressure register (bp req and bp xon/xoff)
4016 pm_csr = readl(&iomem->global.pm_csr);
4017 if (!et1310_in_phy_coma(adapter))
4018 writel(3, &iomem->txmac.bp_ctrl);
4022 /* Handle Packet Status Ring Low Interrupt */
4023 if (status & ET_INTR_RXDMA_STAT_LOW) {
4024 /* Same idea as with the two Free Buffer Rings. Packets going
4025 * from the network to the host each consume a free buffer
4026 * resource and a packet status resource. These resources are
4027 * passed to the OS. When the OS is done with the resources,
4028 * they need to be returned to the ET1310. This is one method
4029 * of returning the resources.
4033 /* Handle RXDMA Error Interrupt */
4034 if (status & ET_INTR_RXDMA_ERR) {
4035 /* The rxdma_error interrupt is sent when a time-out on a
4036 * request issued by the JAGCore has occurred or a completion is
4037 * returned with an un-successful status. In both cases the
4038 * request is considered complete. The JAGCore will
4039 * automatically re-try the request in question. Normally
4040 * information on events like these are sent to the host using
4041 * the "Advanced Error Reporting" capability. This interrupt is
4042 * another way of getting similar information. The only thing
4043 * required is to clear the interrupt by reading the ISR in the
4044 * global resources. The JAGCore will do a re-try on the
4045 * request. Normally you should never see this interrupt. If
4046 * you start to see this interrupt occurring frequently then
4047 * something bad has occurred. A reset might be the thing to do.
4051 dev_warn(&adapter->pdev->dev,
4052 "RxDMA_ERR interrupt, error %x\n",
4053 readl(&iomem->txmac.tx_test));
4056 /* Handle the Wake on LAN Event */
4057 if (status & ET_INTR_WOL) {
4058 /* This is a secondary interrupt for wake on LAN. The driver
4059 * should never see this, if it does, something serious is
4060 * wrong. We will TRAP the message when we are in DBG mode,
4061 * otherwise we will ignore it.
4063 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4066 /* Let's move on to the TxMac */
4067 if (status & ET_INTR_TXMAC) {
4068 u32 err = readl(&iomem->txmac.err);
4070 /* When any of the errors occur and TXMAC generates an
4071 * interrupt to report these errors, it usually means that
4072 * TXMAC has detected an error in the data stream retrieved
4073 * from the on-chip Tx Q. All of these errors are catastrophic
4074 * and TXMAC won't be able to recover data when these errors
4075 * occur. In a nutshell, the whole Tx path will have to be reset
4076 * and re-configured afterwards.
4078 dev_warn(&adapter->pdev->dev,
4079 "TXMAC interrupt, error 0x%08x\n",
4082 /* If we are debugging, we want to see this error, otherwise we
4083 * just want the device to be reset and continue
4087 /* Handle RXMAC Interrupt */
4088 if (status & ET_INTR_RXMAC) {
4089 /* These interrupts are catastrophic to the device, what we need
4090 * to do is disable the interrupts and set the flag to cause us
4091 * to reset so we can solve this issue.
4093 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
4095 dev_warn(&adapter->pdev->dev,
4096 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4097 readl(&iomem->rxmac.err_reg));
4099 dev_warn(&adapter->pdev->dev,
4100 "Enable 0x%08x, Diag 0x%08x\n",
4101 readl(&iomem->rxmac.ctrl),
4102 readl(&iomem->rxmac.rxq_diag));
4104 /* If we are debugging, we want to see this error, otherwise we
4105 * just want the device to be reset and continue
4109 /* Handle MAC_STAT Interrupt */
4110 if (status & ET_INTR_MAC_STAT) {
4111 /* This means at least one of the un-masked counters in the
4112 * MAC_STAT block has rolled over. Use this to maintain the top,
4113 * software managed bits of the counter(s).
4115 et1310_handle_macstat_interrupt(adapter);
4118 /* Handle SLV Timeout Interrupt */
4119 if (status & ET_INTR_SLV_TIMEOUT) {
4120 /* This means a timeout has occurred on a read or write request
4121 * to one of the JAGCore registers. The Global Resources block
4122 * has terminated the request and on a read request, returned a
4123 * "fake" value. The most likely reasons are: Bad Address or the
4124 * addressed module is in a power-down state and can't respond.
4128 et131x_enable_interrupts(adapter);
4131 /* et131x_stats - Return the current device statistics */
4132 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4134 struct et131x_adapter *adapter = netdev_priv(netdev);
4135 struct net_device_stats *stats = &adapter->netdev->stats;
4136 struct ce_stats *devstat = &adapter->stats;
4138 stats->rx_errors = devstat->rx_length_errs +
4139 devstat->rx_align_errs +
4140 devstat->rx_crc_errs +
4141 devstat->rx_code_violations +
4142 devstat->rx_other_errs;
4143 stats->tx_errors = devstat->tx_max_pkt_errs;
4144 stats->multicast = devstat->multicast_pkts_rcvd;
4145 stats->collisions = devstat->tx_collisions;
4147 stats->rx_length_errors = devstat->rx_length_errs;
4148 stats->rx_over_errors = devstat->rx_overflows;
4149 stats->rx_crc_errors = devstat->rx_crc_errs;
4151 /* NOTE: These stats don't have corresponding values in CE_STATS,
4152 * so we're going to have to update these directly from within the
4155 /* stats->rx_bytes = 20; devstat->; */
4156 /* stats->tx_bytes = 20; devstat->; */
4157 /* stats->rx_dropped = devstat->; */
4158 /* stats->tx_dropped = devstat->; */
4160 /* NOTE: Not used, can't find analogous statistics */
4161 /* stats->rx_frame_errors = devstat->; */
4162 /* stats->rx_fifo_errors = devstat->; */
4163 /* stats->rx_missed_errors = devstat->; */
4165 /* stats->tx_aborted_errors = devstat->; */
4166 /* stats->tx_carrier_errors = devstat->; */
4167 /* stats->tx_fifo_errors = devstat->; */
4168 /* stats->tx_heartbeat_errors = devstat->; */
4169 /* stats->tx_window_errors = devstat->; */
4173 /* et131x_open - Open the device for use. */
4174 static int et131x_open(struct net_device *netdev)
4176 struct et131x_adapter *adapter = netdev_priv(netdev);
4177 struct pci_dev *pdev = adapter->pdev;
4178 unsigned int irq = pdev->irq;
4181 /* Start the timer to track NIC errors */
4182 init_timer(&adapter->error_timer);
4183 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4184 adapter->error_timer.function = et131x_error_timer_handler;
4185 adapter->error_timer.data = (unsigned long)adapter;
4186 add_timer(&adapter->error_timer);
4188 result = request_irq(irq, et131x_isr,
4189 IRQF_SHARED, netdev->name, netdev);
4191 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4195 adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
4202 /* et131x_close - Close the device */
4203 static int et131x_close(struct net_device *netdev)
4205 struct et131x_adapter *adapter = netdev_priv(netdev);
4207 et131x_down(netdev);
4209 adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
4210 free_irq(adapter->pdev->irq, netdev);
4212 /* Stop the error timer */
4213 return del_timer_sync(&adapter->error_timer);
4216 /* et131x_ioctl - The I/O Control handler for the driver
4217 * @netdev: device on which the control request is being made
4218 * @reqbuf: a pointer to the IOCTL request buffer
4219 * @cmd: the IOCTL command code
4221 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4224 struct et131x_adapter *adapter = netdev_priv(netdev);
4226 if (!adapter->phydev)
4229 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4232 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4233 * @adapter: pointer to our private adapter structure
4235 * FIXME: lot of dups with MAC code
4237 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4239 int filter = adapter->packet_filter;
4243 ctrl = readl(&adapter->regs->rxmac.ctrl);
4244 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4246 /* Default to disabled packet filtering. Enable it in the individual
4247 * case statements that require the device to filter something
4251 /* Set us to be in promiscuous mode so we receive everything, this
4252 * is also true when we get a packet filter of 0
4254 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4255 pf_ctrl &= ~7; /* Clear filter bits */
4257 /* Set us up with Multicast packet filtering. Three cases are
4258 * possible - (1) we have a multi-cast list, (2) we receive ALL
4259 * multicast entries or (3) we receive none.
4261 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4262 pf_ctrl &= ~2; /* Multicast filter bit */
4264 et1310_setup_device_for_multicast(adapter);
4269 /* Set us up with Unicast packet filtering */
4270 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4271 et1310_setup_device_for_unicast(adapter);
4276 /* Set us up with Broadcast packet filtering */
4277 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4278 pf_ctrl |= 1; /* Broadcast filter bit */
4283 /* Setup the receive mac configuration registers - Packet
4284 * Filter control + the enable / disable for packet filter
4285 * in the control reg.
4287 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4288 writel(ctrl, &adapter->regs->rxmac.ctrl);
4293 /* et131x_multicast - The handler to configure multicasting on the interface */
4294 static void et131x_multicast(struct net_device *netdev)
4296 struct et131x_adapter *adapter = netdev_priv(netdev);
4298 struct netdev_hw_addr *ha;
4301 /* Before we modify the platform-independent filter flags, store them
4302 * locally. This allows us to determine if anything's changed and if
4303 * we even need to bother the hardware
4305 packet_filter = adapter->packet_filter;
4307 /* Clear the 'multicast' flag locally; because we only have a single
4308 * flag to check multicast, and multiple multicast addresses can be
4309 * set, this is the easiest way to determine if more than one
4310 * multicast address is being set.
4312 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4314 /* Check the net_device flags and set the device independent flags
4318 if (netdev->flags & IFF_PROMISC)
4319 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4321 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4323 if (netdev->flags & IFF_ALLMULTI)
4324 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4326 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4327 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4329 if (netdev_mc_count(netdev) < 1) {
4330 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4331 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4333 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4335 /* Set values in the private adapter struct */
4337 netdev_for_each_mc_addr(ha, netdev) {
4338 if (i == NIC_MAX_MCAST_LIST)
4340 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4342 adapter->multicast_addr_count = i;
4344 /* Are the new flags different from the previous ones? If not, then no
4345 * action is required
4347 * NOTE - This block will always update the multicast_list with the
4348 * hardware, even if the addresses aren't the same.
4350 if (packet_filter != adapter->packet_filter)
4351 et131x_set_packet_filter(adapter);
4354 /* et131x_tx - The handler to tx a packet on the device */
4355 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4358 struct et131x_adapter *adapter = netdev_priv(netdev);
4359 struct tx_ring *tx_ring = &adapter->tx_ring;
4361 /* stop the queue if it's getting full */
4362 if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
4363 netif_stop_queue(netdev);
4365 /* Save the timestamp for the TX timeout watchdog */
4366 netdev->trans_start = jiffies;
4368 /* Call the device-specific data Tx routine */
4369 status = et131x_send_packets(skb, netdev);
4371 /* Check status and manage the netif queue if necessary */
4373 if (status == -ENOMEM)
4374 status = NETDEV_TX_BUSY;
4376 status = NETDEV_TX_OK;
4381 /* et131x_tx_timeout - Timeout handler
4383 * The handler called when a Tx request times out. The timeout period is
4384 * specified by the 'tx_timeo" element in the net_device structure (see
4385 * et131x_alloc_device() to see how this value is set).
4387 static void et131x_tx_timeout(struct net_device *netdev)
4389 struct et131x_adapter *adapter = netdev_priv(netdev);
4390 struct tx_ring *tx_ring = &adapter->tx_ring;
4392 unsigned long flags;
4394 /* If the device is closed, ignore the timeout */
4395 if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
4398 /* Any nonrecoverable hardware error?
4399 * Checks adapter->flags for any failure in phy reading
4401 if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
4404 /* Hardware failure? */
4405 if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
4406 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4410 /* Is send stuck? */
4411 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4413 tcb = tx_ring->send_head;
4418 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4419 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4422 dev_warn(&adapter->pdev->dev,
4423 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4427 adapter->netdev->stats.tx_errors++;
4429 /* perform reset of tx/rx */
4430 et131x_disable_txrx(netdev);
4431 et131x_enable_txrx(netdev);
4436 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4439 /* et131x_change_mtu - The handler called to change the MTU for the device */
4440 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4443 struct et131x_adapter *adapter = netdev_priv(netdev);
4445 /* Make sure the requested MTU is valid */
4446 if (new_mtu < 64 || new_mtu > 9216)
4449 et131x_disable_txrx(netdev);
4450 et131x_handle_send_interrupt(adapter);
4451 et131x_handle_recv_interrupt(adapter);
4453 /* Set the new MTU */
4454 netdev->mtu = new_mtu;
4456 /* Free Rx DMA memory */
4457 et131x_adapter_memory_free(adapter);
4459 /* Set the config parameter for Jumbo Packet support */
4460 adapter->registry_jumbo_packet = new_mtu + 14;
4461 et131x_soft_reset(adapter);
4463 /* Alloc and init Rx DMA memory */
4464 result = et131x_adapter_memory_alloc(adapter);
4466 dev_warn(&adapter->pdev->dev,
4467 "Change MTU failed; couldn't re-alloc DMA memory\n");
4471 et131x_init_send(adapter);
4473 et131x_hwaddr_init(adapter);
4474 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4476 /* Init the device with the new settings */
4477 et131x_adapter_setup(adapter);
4479 et131x_enable_txrx(netdev);
4484 /* et131x_set_mac_addr - handler to change the MAC address for the device */
4485 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
4488 struct et131x_adapter *adapter = netdev_priv(netdev);
4489 struct sockaddr *address = new_mac;
4491 if (adapter == NULL)
4494 /* Make sure the requested MAC is valid */
4495 if (!is_valid_ether_addr(address->sa_data))
4496 return -EADDRNOTAVAIL;
4498 et131x_disable_txrx(netdev);
4499 et131x_handle_send_interrupt(adapter);
4500 et131x_handle_recv_interrupt(adapter);
4502 /* Set the new MAC */
4503 /* netdev->set_mac_address = &new_mac; */
4505 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
4507 netdev_info(netdev, "Setting MAC address to %pM\n",
4510 /* Free Rx DMA memory */
4511 et131x_adapter_memory_free(adapter);
4513 et131x_soft_reset(adapter);
4515 /* Alloc and init Rx DMA memory */
4516 result = et131x_adapter_memory_alloc(adapter);
4518 dev_err(&adapter->pdev->dev,
4519 "Change MAC failed; couldn't re-alloc DMA memory\n");
4523 et131x_init_send(adapter);
4525 et131x_hwaddr_init(adapter);
4527 /* Init the device with the new settings */
4528 et131x_adapter_setup(adapter);
4530 et131x_enable_txrx(netdev);
4535 static const struct net_device_ops et131x_netdev_ops = {
4536 .ndo_open = et131x_open,
4537 .ndo_stop = et131x_close,
4538 .ndo_start_xmit = et131x_tx,
4539 .ndo_set_rx_mode = et131x_multicast,
4540 .ndo_tx_timeout = et131x_tx_timeout,
4541 .ndo_change_mtu = et131x_change_mtu,
4542 .ndo_set_mac_address = et131x_set_mac_addr,
4543 .ndo_validate_addr = eth_validate_addr,
4544 .ndo_get_stats = et131x_stats,
4545 .ndo_do_ioctl = et131x_ioctl,
4548 /* et131x_pci_setup - Perform device initialization
4549 * @pdev: a pointer to the device's pci_dev structure
4550 * @ent: this device's entry in the pci_device_id table
4552 * Registered in the pci_driver structure, this function is called when the
4553 * PCI subsystem finds a new PCI device which matches the information
4554 * contained in the pci_device_id table. This routine is the equivalent to
4555 * a device insertion routine.
4557 static int et131x_pci_setup(struct pci_dev *pdev,
4558 const struct pci_device_id *ent)
4560 struct net_device *netdev;
4561 struct et131x_adapter *adapter;
4565 rc = pci_enable_device(pdev);
4567 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4571 /* Perform some basic PCI checks */
4572 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4573 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4578 rc = pci_request_regions(pdev, DRIVER_NAME);
4580 dev_err(&pdev->dev, "Can't get PCI resources\n");
4584 pci_set_master(pdev);
4586 /* Check the DMA addressing support of this device */
4587 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
4588 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
4589 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4591 goto err_release_res;
4594 /* Allocate netdev and private adapter structs */
4595 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4597 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4599 goto err_release_res;
4602 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4603 netdev->netdev_ops = &et131x_netdev_ops;
4605 SET_NETDEV_DEV(netdev, &pdev->dev);
4606 netdev->ethtool_ops = &et131x_ethtool_ops;
4608 adapter = et131x_adapter_init(netdev, pdev);
4610 rc = et131x_pci_init(adapter, pdev);
4614 /* Map the bus-relative registers to system virtual memory */
4615 adapter->regs = pci_ioremap_bar(pdev, 0);
4616 if (!adapter->regs) {
4617 dev_err(&pdev->dev, "Cannot map device registers\n");
4622 /* If Phy COMA mode was enabled when we went down, disable it here. */
4623 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4625 /* Issue a global reset to the et1310 */
4626 et131x_soft_reset(adapter);
4628 /* Disable all interrupts (paranoid) */
4629 et131x_disable_interrupts(adapter);
4631 /* Allocate DMA memory */
4632 rc = et131x_adapter_memory_alloc(adapter);
4634 dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
4638 /* Init send data structures */
4639 et131x_init_send(adapter);
4641 /* Set up the task structure for the ISR's deferred handler */
4642 INIT_WORK(&adapter->task, et131x_isr_handler);
4644 /* Copy address into the net_device struct */
4645 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4647 /* Init variable for counting how long we do not have link status */
4648 adapter->boot_coma = 0;
4649 et1310_disable_phy_coma(adapter);
4653 /* Setup the mii_bus struct */
4654 adapter->mii_bus = mdiobus_alloc();
4655 if (!adapter->mii_bus) {
4656 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4660 adapter->mii_bus->name = "et131x_eth_mii";
4661 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4662 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4663 adapter->mii_bus->priv = netdev;
4664 adapter->mii_bus->read = et131x_mdio_read;
4665 adapter->mii_bus->write = et131x_mdio_write;
4666 adapter->mii_bus->reset = et131x_mdio_reset;
4667 adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
4669 if (!adapter->mii_bus->irq)
4672 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4673 adapter->mii_bus->irq[ii] = PHY_POLL;
4675 rc = mdiobus_register(adapter->mii_bus);
4677 dev_err(&pdev->dev, "failed to register MII bus\n");
4678 goto err_mdio_free_irq;
4681 rc = et131x_mii_probe(netdev);
4683 dev_err(&pdev->dev, "failed to probe MII bus\n");
4684 goto err_mdio_unregister;
4687 /* Setup et1310 as per the documentation */
4688 et131x_adapter_setup(adapter);
4690 /* We can enable interrupts now
4692 * NOTE - Because registration of interrupt handler is done in the
4693 * device's open(), defer enabling device interrupts to that
4697 /* Register the net_device struct with the Linux network layer */
4698 rc = register_netdev(netdev);
4700 dev_err(&pdev->dev, "register_netdev() failed\n");
4701 goto err_phy_disconnect;
4704 /* Register the net_device struct with the PCI subsystem. Save a copy
4705 * of the PCI config space for this device now that the device has
4706 * been initialized, just in case it needs to be quickly restored.
4708 pci_set_drvdata(pdev, netdev);
4713 phy_disconnect(adapter->phydev);
4714 err_mdio_unregister:
4715 mdiobus_unregister(adapter->mii_bus);
4717 kfree(adapter->mii_bus->irq);
4719 mdiobus_free(adapter->mii_bus);
4721 et131x_adapter_memory_free(adapter);
4723 iounmap(adapter->regs);
4726 free_netdev(netdev);
4728 pci_release_regions(pdev);
4730 pci_disable_device(pdev);
4734 static const struct pci_device_id et131x_pci_table[] = {
4735 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
4736 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
4739 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4741 static struct pci_driver et131x_driver = {
4742 .name = DRIVER_NAME,
4743 .id_table = et131x_pci_table,
4744 .probe = et131x_pci_setup,
4745 .remove = et131x_pci_remove,
4746 .driver.pm = ET131X_PM_OPS,
4749 module_pci_driver(et131x_driver);