3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_address_map.h - Contains the register mapping for the ET1310
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
92 * Interrupt status reg at address 0x0018
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
115 * Same masks as above
119 * Software reset reg at address 0x0028
125 * 5: mac_stat_sw_reset
131 * SLV Timer reg at address 0x002C (low 24 bits)
135 * MSI Configuration reg at address 0x0030
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
142 * Loopback reg located at address 0x0034
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
152 typedef struct _GLOBAL_t { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
168 } GLOBAL_t, *PGLOBAL_t;
170 /* END OF GLOBAL REGISTER ADDRESS MAP */
173 /* START OF TXDMA REGISTER ADDRESS MAP */
176 * txdma control status reg at address 0x1000
179 #define ET_TXDMA_CSR_HALT 0x00000001
180 #define ET_TXDMA_DROP_TLP 0x00000002
181 #define ET_TXDMA_CACHE_THRS 0x000000F0
182 #define ET_TXDMA_CACHE_SHIFT 4
183 #define ET_TXDMA_SNGL_EPKT 0x00000100
184 #define ET_TXDMA_CLASS 0x00001E00
187 * structure for txdma packet ring base address hi reg in txdma address map
188 * located at address 0x1004
189 * Defined earlier (u32)
193 * structure for txdma packet ring base address low reg in txdma address map
194 * located at address 0x1008
195 * Defined earlier (u32)
199 * structure for txdma packet ring number of descriptor reg in txdma address
200 * map. Located at address 0x100C
206 #define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x400
208 #define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x010
211 #define INDEX10(x) ((x) & ET_DMA10_MASK)
212 #define INDEX4(x) ((x) & ET_DMA4_MASK)
214 extern inline void add_10bit(u32 *v, int n)
216 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
220 * 10bit DMA with wrap
221 * txdma tx queue write address reg in txdma address map at 0x1010
222 * txdma tx queue write address external reg in txdma address map at 0x1014
223 * txdma tx queue read address reg in txdma address map at 0x1018
226 * txdma status writeback address hi reg in txdma address map at0x101C
227 * txdma status writeback address lo reg in txdma address map at 0x1020
229 * 10bit DMA with wrap
230 * txdma service request reg in txdma address map at 0x1024
231 * structure for txdma service complete reg in txdma address map at 0x1028
234 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
235 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
237 * txdma error reg in txdma address map at address 0x1034
247 * Tx DMA Module of JAGCore Address Mapping
248 * Located at address 0x1000
250 typedef struct _TXDMA_t { /* Location: */
251 u32 csr; /* 0x1000 */
252 u32 pr_base_hi; /* 0x1004 */
253 u32 pr_base_lo; /* 0x1008 */
254 u32 pr_num_des; /* 0x100C */
255 u32 txq_wr_addr; /* 0x1010 */
256 u32 txq_wr_addr_ext; /* 0x1014 */
257 u32 txq_rd_addr; /* 0x1018 */
258 u32 dma_wb_base_hi; /* 0x101C */
259 u32 dma_wb_base_lo; /* 0x1020 */
260 u32 service_request; /* 0x1024 */
261 u32 service_complete; /* 0x1028 */
262 u32 cache_rd_index; /* 0x102C */
263 u32 cache_wr_index; /* 0x1030 */
264 u32 TxDmaError; /* 0x1034 */
265 u32 DescAbortCount; /* 0x1038 */
266 u32 PayloadAbortCnt; /* 0x103c */
267 u32 WriteBackAbortCnt; /* 0x1040 */
268 u32 DescTimeoutCnt; /* 0x1044 */
269 u32 PayloadTimeoutCnt; /* 0x1048 */
270 u32 WriteBackTimeoutCnt; /* 0x104c */
271 u32 DescErrorCount; /* 0x1050 */
272 u32 PayloadErrorCnt; /* 0x1054 */
273 u32 WriteBackErrorCnt; /* 0x1058 */
274 u32 DroppedTLPCount; /* 0x105c */
275 u32 NewServiceComplete; /* 0x1060 */
276 u32 EthernetPacketCount; /* 0x1064 */
277 } TXDMA_t, *PTXDMA_t;
279 /* END OF TXDMA REGISTER ADDRESS MAP */
282 /* START OF RXDMA REGISTER ADDRESS MAP */
285 * structure for control status reg in rxdma address map
286 * Located at address 0x2000
288 typedef union _RXDMA_CSR_t {
291 #ifdef _BIT_FIELDS_HTOL
292 u32 unused2:14; /* bits 18-31 */
293 u32 halt_status:1; /* bit 17 */
294 u32 pkt_done_flush:1; /* bit 16 */
295 u32 pkt_drop_disable:1; /* bit 15 */
296 u32 unused1:1; /* bit 14 */
297 u32 fbr1_enable:1; /* bit 13 */
298 u32 fbr1_size:2; /* bits 11-12 */
299 u32 fbr0_enable:1; /* bit 10 */
300 u32 fbr0_size:2; /* bits 8-9 */
301 u32 dma_big_endian:1; /* bit 7 */
302 u32 pkt_big_endian:1; /* bit 6 */
303 u32 psr_big_endian:1; /* bit 5 */
304 u32 fbr_big_endian:1; /* bit 4 */
305 u32 tc:3; /* bits 1-3 */
306 u32 halt:1; /* bit 0 */
308 u32 halt:1; /* bit 0 */
309 u32 tc:3; /* bits 1-3 */
310 u32 fbr_big_endian:1; /* bit 4 */
311 u32 psr_big_endian:1; /* bit 5 */
312 u32 pkt_big_endian:1; /* bit 6 */
313 u32 dma_big_endian:1; /* bit 7 */
314 u32 fbr0_size:2; /* bits 8-9 */
315 u32 fbr0_enable:1; /* bit 10 */
316 u32 fbr1_size:2; /* bits 11-12 */
317 u32 fbr1_enable:1; /* bit 13 */
318 u32 unused1:1; /* bit 14 */
319 u32 pkt_drop_disable:1; /* bit 15 */
320 u32 pkt_done_flush:1; /* bit 16 */
321 u32 halt_status:1; /* bit 17 */
322 u32 unused2:14; /* bits 18-31 */
325 } RXDMA_CSR_t, *PRXDMA_CSR_t;
328 * structure for dma writeback lo reg in rxdma address map
329 * located at address 0x2004
330 * Defined earlier (u32)
334 * structure for dma writeback hi reg in rxdma address map
335 * located at address 0x2008
336 * Defined earlier (u32)
340 * structure for number of packets done reg in rxdma address map
341 * located at address 0x200C
348 * structure for max packet time reg in rxdma address map
349 * located at address 0x2010
356 * structure for rx queue read address reg in rxdma address map
357 * located at address 0x2014
358 * Defined earlier (u32)
362 * structure for rx queue read address external reg in rxdma address map
363 * located at address 0x2018
364 * Defined earlier (u32)
368 * structure for rx queue write address reg in rxdma address map
369 * located at address 0x201C
370 * Defined earlier (u32)
374 * structure for packet status ring base address lo reg in rxdma address map
375 * located at address 0x2020
376 * Defined earlier (u32)
380 * structure for packet status ring base address hi reg in rxdma address map
381 * located at address 0x2024
382 * Defined earlier (u32)
386 * structure for packet status ring number of descriptors reg in rxdma address
387 * map. Located at address 0x2028
394 * structure for packet status ring available offset reg in rxdma address map
395 * located at address 0x202C
403 * structure for packet status ring full offset reg in rxdma address map
404 * located at address 0x2030
412 * structure for packet status ring access index reg in rxdma address map
413 * located at address 0x2034
420 * structure for packet status ring minimum descriptors reg in rxdma address
421 * map. Located at address 0x2038
428 * structure for free buffer ring base lo address reg in rxdma address map
429 * located at address 0x203C
430 * Defined earlier (u32)
434 * structure for free buffer ring base hi address reg in rxdma address map
435 * located at address 0x2040
436 * Defined earlier (u32)
440 * structure for free buffer ring number of descriptors reg in rxdma address
441 * map. Located at address 0x2044
446 typedef union _RXDMA_FBR_NUM_DES_t {
449 #ifdef _BIT_FIELDS_HTOL
450 u32 unused:22; /* bits 10-31 */
451 u32 fbr_ndesc:10; /* bits 0-9 */
453 u32 fbr_ndesc:10; /* bits 0-9 */
454 u32 unused:22; /* bits 10-31 */
457 } RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
460 * structure for free buffer ring 0 available offset reg in rxdma address map
461 * located at address 0x2048
462 * Defined earlier (u32)
466 * structure for free buffer ring 0 full offset reg in rxdma address map
467 * located at address 0x204C
468 * Defined earlier (u32)
472 * structure for free buffer cache 0 full offset reg in rxdma address map
473 * located at address 0x2050
480 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
481 * located at address 0x2054
488 * structure for free buffer ring 1 base address lo reg in rxdma address map
489 * located at address 0x2058 - 0x205C
490 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
494 * structure for free buffer ring 1 number of descriptors reg in rxdma address
495 * map. Located at address 0x2060
496 * Defined earlier (RXDMA_FBR_NUM_DES_t)
500 * structure for free buffer ring 1 available offset reg in rxdma address map
501 * located at address 0x2064
502 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
506 * structure for free buffer ring 1 full offset reg in rxdma address map
507 * located at address 0x2068
508 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
512 * structure for free buffer cache 1 read index reg in rxdma address map
513 * located at address 0x206C
514 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
518 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
519 * located at address 0x2070
520 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
524 * Rx DMA Module of JAGCore Address Mapping
525 * Located at address 0x2000
527 typedef struct _RXDMA_t { /* Location: */
528 RXDMA_CSR_t csr; /* 0x2000 */
529 u32 dma_wb_base_lo; /* 0x2004 */
530 u32 dma_wb_base_hi; /* 0x2008 */
531 u32 num_pkt_done; /* 0x200C */
532 u32 max_pkt_time; /* 0x2010 */
533 u32 rxq_rd_addr; /* 0x2014 */
534 u32 rxq_rd_addr_ext; /* 0x2018 */
535 u32 rxq_wr_addr; /* 0x201C */
536 u32 psr_base_lo; /* 0x2020 */
537 u32 psr_base_hi; /* 0x2024 */
538 u32 psr_num_des; /* 0x2028 */
539 u32 psr_avail_offset; /* 0x202C */
540 u32 psr_full_offset; /* 0x2030 */
541 u32 psr_access_index; /* 0x2034 */
542 u32 psr_min_des; /* 0x2038 */
543 u32 fbr0_base_lo; /* 0x203C */
544 u32 fbr0_base_hi; /* 0x2040 */
545 u32 fbr0_num_des; /* 0x2044 */
546 u32 fbr0_avail_offset; /* 0x2048 */
547 u32 fbr0_full_offset; /* 0x204C */
548 u32 fbr0_rd_index; /* 0x2050 */
549 u32 fbr0_min_des; /* 0x2054 */
550 u32 fbr1_base_lo; /* 0x2058 */
551 u32 fbr1_base_hi; /* 0x205C */
552 u32 fbr1_num_des; /* 0x2060 */
553 u32 fbr1_avail_offset; /* 0x2064 */
554 u32 fbr1_full_offset; /* 0x2068 */
555 u32 fbr1_rd_index; /* 0x206C */
556 u32 fbr1_min_des; /* 0x2070 */
557 } RXDMA_t, *PRXDMA_t;
559 /* END OF RXDMA REGISTER ADDRESS MAP */
562 /* START OF TXMAC REGISTER ADDRESS MAP */
565 * structure for control reg in txmac address map
566 * located at address 0x3000
568 typedef union _TXMAC_CTL_t {
571 #ifdef _BIT_FIELDS_HTOL
572 u32 unused:24; /* bits 8-31 */
573 u32 cklseg_diable:1; /* bit 7 */
574 u32 ckbcnt_disable:1; /* bit 6 */
575 u32 cksegnum:1; /* bit 5 */
576 u32 async_disable:1; /* bit 4 */
577 u32 fc_disable:1; /* bit 3 */
578 u32 mcif_disable:1; /* bit 2 */
579 u32 mif_disable:1; /* bit 1 */
580 u32 txmac_en:1; /* bit 0 */
582 u32 txmac_en:1; /* bit 0 */
583 u32 mif_disable:1; /* bit 1 mac interface */
584 u32 mcif_disable:1; /* bit 2 mem. contr. interface */
585 u32 fc_disable:1; /* bit 3 */
586 u32 async_disable:1; /* bit 4 */
587 u32 cksegnum:1; /* bit 5 */
588 u32 ckbcnt_disable:1; /* bit 6 */
589 u32 cklseg_diable:1; /* bit 7 */
590 u32 unused:24; /* bits 8-31 */
593 } TXMAC_CTL_t, *PTXMAC_CTL_t;
596 * structure for shadow pointer reg in txmac address map
597 * located at address 0x3004
605 * structure for error count reg in txmac address map
606 * located at address 0x3008
608 typedef union _TXMAC_ERR_CNT_t {
611 #ifdef _BIT_FIELDS_HTOL
612 u32 unused:20; /* bits 12-31 */
613 u32 reserved:4; /* bits 8-11 */
614 u32 txq_underrun:4; /* bits 4-7 */
615 u32 fifo_underrun:4; /* bits 0-3 */
617 u32 fifo_underrun:4; /* bits 0-3 */
618 u32 txq_underrun:4; /* bits 4-7 */
619 u32 reserved:4; /* bits 8-11 */
620 u32 unused:20; /* bits 12-31 */
623 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
626 * structure for max fill reg in txmac address map
627 * located at address 0x300C
633 * structure for cf parameter reg in txmac address map
634 * located at address 0x3010
640 * structure for tx test reg in txmac address map
641 * located at address 0x3014
646 * 10-0: txq test pointer
650 * structure for error reg in txmac address map
651 * located at address 0x3018
653 typedef union _TXMAC_ERR_t {
656 #ifdef _BIT_FIELDS_HTOL
657 u32 unused2:23; /* bits 9-31 */
658 u32 fifo_underrun:1; /* bit 8 */
659 u32 unused1:2; /* bits 6-7 */
660 u32 ctrl2_err:1; /* bit 5 */
661 u32 txq_underrun:1; /* bit 4 */
662 u32 bcnt_err:1; /* bit 3 */
663 u32 lseg_err:1; /* bit 2 */
664 u32 segnum_err:1; /* bit 1 */
665 u32 seg0_err:1; /* bit 0 */
667 u32 seg0_err:1; /* bit 0 */
668 u32 segnum_err:1; /* bit 1 */
669 u32 lseg_err:1; /* bit 2 */
670 u32 bcnt_err:1; /* bit 3 */
671 u32 txq_underrun:1; /* bit 4 */
672 u32 ctrl2_err:1; /* bit 5 */
673 u32 unused1:2; /* bits 6-7 */
674 u32 fifo_underrun:1; /* bit 8 */
675 u32 unused2:23; /* bits 9-31 */
678 } TXMAC_ERR_t, *PTXMAC_ERR_t;
681 * structure for error interrupt reg in txmac address map
682 * located at address 0x301C
684 typedef union _TXMAC_ERR_INT_t {
687 #ifdef _BIT_FIELDS_HTOL
688 u32 unused2:23; /* bits 9-31 */
689 u32 fifo_underrun:1; /* bit 8 */
690 u32 unused1:2; /* bits 6-7 */
691 u32 ctrl2_err:1; /* bit 5 */
692 u32 txq_underrun:1; /* bit 4 */
693 u32 bcnt_err:1; /* bit 3 */
694 u32 lseg_err:1; /* bit 2 */
695 u32 segnum_err:1; /* bit 1 */
696 u32 seg0_err:1; /* bit 0 */
698 u32 seg0_err:1; /* bit 0 */
699 u32 segnum_err:1; /* bit 1 */
700 u32 lseg_err:1; /* bit 2 */
701 u32 bcnt_err:1; /* bit 3 */
702 u32 txq_underrun:1; /* bit 4 */
703 u32 ctrl2_err:1; /* bit 5 */
704 u32 unused1:2; /* bits 6-7 */
705 u32 fifo_underrun:1; /* bit 8 */
706 u32 unused2:23; /* bits 9-31 */
709 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
712 * structure for error interrupt reg in txmac address map
713 * located at address 0x3020
721 * Tx MAC Module of JAGCore Address Mapping
723 typedef struct _TXMAC_t { /* Location: */
724 TXMAC_CTL_t ctl; /* 0x3000 */
725 u32 shadow_ptr; /* 0x3004 */
726 TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */
727 u32 max_fill; /* 0x300C */
728 u32 cf_param; /* 0x3010 */
729 u32 tx_test; /* 0x3014 */
730 TXMAC_ERR_t err; /* 0x3018 */
731 TXMAC_ERR_INT_t err_int; /* 0x301C */
732 u32 bp_ctrl; /* 0x3020 */
733 } TXMAC_t, *PTXMAC_t;
735 /* END OF TXMAC REGISTER ADDRESS MAP */
737 /* START OF RXMAC REGISTER ADDRESS MAP */
740 * structure for rxmac control reg in rxmac address map
741 * located at address 0x4000
743 typedef union _RXMAC_CTRL_t {
746 #ifdef _BIT_FIELDS_HTOL
747 u32 reserved:25; /* bits 7-31 */
748 u32 rxmac_int_disable:1; /* bit 6 */
749 u32 async_disable:1; /* bit 5 */
750 u32 mif_disable:1; /* bit 4 */
751 u32 wol_disable:1; /* bit 3 */
752 u32 pkt_filter_disable:1; /* bit 2 */
753 u32 mcif_disable:1; /* bit 1 */
754 u32 rxmac_en:1; /* bit 0 */
756 u32 rxmac_en:1; /* bit 0 */
757 u32 mcif_disable:1; /* bit 1 */
758 u32 pkt_filter_disable:1; /* bit 2 */
759 u32 wol_disable:1; /* bit 3 */
760 u32 mif_disable:1; /* bit 4 */
761 u32 async_disable:1; /* bit 5 */
762 u32 rxmac_int_disable:1; /* bit 6 */
763 u32 reserved:25; /* bits 7-31 */
766 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
769 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
770 * located at address 0x4004
772 typedef union _RXMAC_WOL_CTL_CRC0_t {
775 #ifdef _BIT_FIELDS_HTOL
776 u32 crc0:16; /* bits 16-31 */
777 u32 reserve:4; /* bits 12-15 */
778 u32 ignore_pp:1; /* bit 11 */
779 u32 ignore_mp:1; /* bit 10 */
780 u32 clr_intr:1; /* bit 9 */
781 u32 ignore_link_chg:1; /* bit 8 */
782 u32 ignore_uni:1; /* bit 7 */
783 u32 ignore_multi:1; /* bit 6 */
784 u32 ignore_broad:1; /* bit 5 */
785 u32 valid_crc4:1; /* bit 4 */
786 u32 valid_crc3:1; /* bit 3 */
787 u32 valid_crc2:1; /* bit 2 */
788 u32 valid_crc1:1; /* bit 1 */
789 u32 valid_crc0:1; /* bit 0 */
791 u32 valid_crc0:1; /* bit 0 */
792 u32 valid_crc1:1; /* bit 1 */
793 u32 valid_crc2:1; /* bit 2 */
794 u32 valid_crc3:1; /* bit 3 */
795 u32 valid_crc4:1; /* bit 4 */
796 u32 ignore_broad:1; /* bit 5 */
797 u32 ignore_multi:1; /* bit 6 */
798 u32 ignore_uni:1; /* bit 7 */
799 u32 ignore_link_chg:1; /* bit 8 */
800 u32 clr_intr:1; /* bit 9 */
801 u32 ignore_mp:1; /* bit 10 */
802 u32 ignore_pp:1; /* bit 11 */
803 u32 reserve:4; /* bits 12-15 */
804 u32 crc0:16; /* bits 16-31 */
807 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
810 * structure for CRC 1 and CRC 2 reg in rxmac address map
811 * located at address 0x4008
813 typedef union _RXMAC_WOL_CRC12_t {
816 #ifdef _BIT_FIELDS_HTOL
817 u32 crc2:16; /* bits 16-31 */
818 u32 crc1:16; /* bits 0-15 */
820 u32 crc1:16; /* bits 0-15 */
821 u32 crc2:16; /* bits 16-31 */
824 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
827 * structure for CRC 3 and CRC 4 reg in rxmac address map
828 * located at address 0x400C
830 typedef union _RXMAC_WOL_CRC34_t {
833 #ifdef _BIT_FIELDS_HTOL
834 u32 crc4:16; /* bits 16-31 */
835 u32 crc3:16; /* bits 0-15 */
837 u32 crc3:16; /* bits 0-15 */
838 u32 crc4:16; /* bits 16-31 */
841 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
844 * structure for Wake On Lan Source Address Lo reg in rxmac address map
845 * located at address 0x4010
847 typedef union _RXMAC_WOL_SA_LO_t {
850 #ifdef _BIT_FIELDS_HTOL
851 u32 sa3:8; /* bits 24-31 */
852 u32 sa4:8; /* bits 16-23 */
853 u32 sa5:8; /* bits 8-15 */
854 u32 sa6:8; /* bits 0-7 */
856 u32 sa6:8; /* bits 0-7 */
857 u32 sa5:8; /* bits 8-15 */
858 u32 sa4:8; /* bits 16-23 */
859 u32 sa3:8; /* bits 24-31 */
862 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
865 * structure for Wake On Lan Source Address Hi reg in rxmac address map
866 * located at address 0x4014
868 typedef union _RXMAC_WOL_SA_HI_t {
871 #ifdef _BIT_FIELDS_HTOL
872 u32 reserved:16; /* bits 16-31 */
873 u32 sa1:8; /* bits 8-15 */
874 u32 sa2:8; /* bits 0-7 */
876 u32 sa2:8; /* bits 0-7 */
877 u32 sa1:8; /* bits 8-15 */
878 u32 reserved:16; /* bits 16-31 */
881 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
884 * structure for Wake On Lan mask reg in rxmac address map
885 * located at address 0x4018 - 0x4064
886 * Defined earlier (u32)
890 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
891 * located at address 0x4068
893 typedef union _RXMAC_UNI_PF_ADDR1_t {
896 #ifdef _BIT_FIELDS_HTOL
897 u32 addr1_3:8; /* bits 24-31 */
898 u32 addr1_4:8; /* bits 16-23 */
899 u32 addr1_5:8; /* bits 8-15 */
900 u32 addr1_6:8; /* bits 0-7 */
902 u32 addr1_6:8; /* bits 0-7 */
903 u32 addr1_5:8; /* bits 8-15 */
904 u32 addr1_4:8; /* bits 16-23 */
905 u32 addr1_3:8; /* bits 24-31 */
908 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
911 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
912 * located at address 0x406C
914 typedef union _RXMAC_UNI_PF_ADDR2_t {
917 #ifdef _BIT_FIELDS_HTOL
918 u32 addr2_3:8; /* bits 24-31 */
919 u32 addr2_4:8; /* bits 16-23 */
920 u32 addr2_5:8; /* bits 8-15 */
921 u32 addr2_6:8; /* bits 0-7 */
923 u32 addr2_6:8; /* bits 0-7 */
924 u32 addr2_5:8; /* bits 8-15 */
925 u32 addr2_4:8; /* bits 16-23 */
926 u32 addr2_3:8; /* bits 24-31 */
929 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
932 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
933 * located at address 0x4070
935 typedef union _RXMAC_UNI_PF_ADDR3_t {
938 #ifdef _BIT_FIELDS_HTOL
939 u32 addr2_1:8; /* bits 24-31 */
940 u32 addr2_2:8; /* bits 16-23 */
941 u32 addr1_1:8; /* bits 8-15 */
942 u32 addr1_2:8; /* bits 0-7 */
944 u32 addr1_2:8; /* bits 0-7 */
945 u32 addr1_1:8; /* bits 8-15 */
946 u32 addr2_2:8; /* bits 16-23 */
947 u32 addr2_1:8; /* bits 24-31 */
950 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
953 * structure for Multicast Hash reg in rxmac address map
954 * located at address 0x4074 - 0x4080
955 * Defined earlier (u32)
959 * structure for Packet Filter Control reg in rxmac address map
960 * located at address 0x4084
962 typedef union _RXMAC_PF_CTRL_t {
965 #ifdef _BIT_FIELDS_HTOL
966 u32 unused2:9; /* bits 23-31 */
967 u32 min_pkt_size:7; /* bits 16-22 */
968 u32 unused1:12; /* bits 4-15 */
969 u32 filter_frag_en:1; /* bit 3 */
970 u32 filter_uni_en:1; /* bit 2 */
971 u32 filter_multi_en:1; /* bit 1 */
972 u32 filter_broad_en:1; /* bit 0 */
974 u32 filter_broad_en:1; /* bit 0 */
975 u32 filter_multi_en:1; /* bit 1 */
976 u32 filter_uni_en:1; /* bit 2 */
977 u32 filter_frag_en:1; /* bit 3 */
978 u32 unused1:12; /* bits 4-15 */
979 u32 min_pkt_size:7; /* bits 16-22 */
980 u32 unused2:9; /* bits 23-31 */
983 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
986 * structure for Memory Controller Interface Control Max Segment reg in rxmac
987 * address map. Located at address 0x4088
989 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
992 #ifdef _BIT_FIELDS_HTOL
993 u32 reserved:22; /* bits 10-31 */
994 u32 max_size:8; /* bits 2-9 */
995 u32 fc_en:1; /* bit 1 */
996 u32 seg_en:1; /* bit 0 */
998 u32 seg_en:1; /* bit 0 */
999 u32 fc_en:1; /* bit 1 */
1000 u32 max_size:8; /* bits 2-9 */
1001 u32 reserved:22; /* bits 10-31 */
1004 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1007 * structure for Memory Controller Interface Water Mark reg in rxmac address
1008 * map. Located at address 0x408C
1010 typedef union _RXMAC_MCIF_WATER_MARK_t {
1013 #ifdef _BIT_FIELDS_HTOL
1014 u32 reserved2:6; /* bits 26-31 */
1015 u32 mark_hi:10; /* bits 16-25 */
1016 u32 reserved1:6; /* bits 10-15 */
1017 u32 mark_lo:10; /* bits 0-9 */
1019 u32 mark_lo:10; /* bits 0-9 */
1020 u32 reserved1:6; /* bits 10-15 */
1021 u32 mark_hi:10; /* bits 16-25 */
1022 u32 reserved2:6; /* bits 26-31 */
1025 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1028 * structure for Rx Queue Dialog reg in rxmac address map.
1029 * located at address 0x4090
1031 typedef union _RXMAC_RXQ_DIAG_t {
1034 #ifdef _BIT_FIELDS_HTOL
1035 u32 reserved2:6; /* bits 26-31 */
1036 u32 rd_ptr:10; /* bits 16-25 */
1037 u32 reserved1:6; /* bits 10-15 */
1038 u32 wr_ptr:10; /* bits 0-9 */
1040 u32 wr_ptr:10; /* bits 0-9 */
1041 u32 reserved1:6; /* bits 10-15 */
1042 u32 rd_ptr:10; /* bits 16-25 */
1043 u32 reserved2:6; /* bits 26-31 */
1046 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1049 * structure for space availiable reg in rxmac address map.
1050 * located at address 0x4094
1052 typedef union _RXMAC_SPACE_AVAIL_t {
1055 #ifdef _BIT_FIELDS_HTOL
1056 u32 reserved2:15; /* bits 17-31 */
1057 u32 space_avail_en:1; /* bit 16 */
1058 u32 reserved1:6; /* bits 10-15 */
1059 u32 space_avail:10; /* bits 0-9 */
1061 u32 space_avail:10; /* bits 0-9 */
1062 u32 reserved1:6; /* bits 10-15 */
1063 u32 space_avail_en:1; /* bit 16 */
1064 u32 reserved2:15; /* bits 17-31 */
1067 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1070 * structure for management interface reg in rxmac address map.
1071 * located at address 0x4098
1073 typedef union _RXMAC_MIF_CTL_t {
1076 #ifdef _BIT_FIELDS_HTOL
1077 u32 reserve:14; /* bits 18-31 */
1078 u32 drop_pkt_en:1; /* bit 17 */
1079 u32 drop_pkt_mask:17; /* bits 0-16 */
1081 u32 drop_pkt_mask:17; /* bits 0-16 */
1082 u32 drop_pkt_en:1; /* bit 17 */
1083 u32 reserve:14; /* bits 18-31 */
1086 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1089 * structure for Error reg in rxmac address map.
1090 * located at address 0x409C
1092 typedef union _RXMAC_ERROR_REG_t {
1095 #ifdef _BIT_FIELDS_HTOL
1096 u32 reserve:28; /* bits 4-31 */
1097 u32 mif:1; /* bit 3 */
1098 u32 async:1; /* bit 2 */
1099 u32 pkt_filter:1; /* bit 1 */
1100 u32 mcif:1; /* bit 0 */
1102 u32 mcif:1; /* bit 0 */
1103 u32 pkt_filter:1; /* bit 1 */
1104 u32 async:1; /* bit 2 */
1105 u32 mif:1; /* bit 3 */
1106 u32 reserve:28; /* bits 4-31 */
1109 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1112 * Rx MAC Module of JAGCore Address Mapping
1114 typedef struct _RXMAC_t { /* Location: */
1115 RXMAC_CTRL_t ctrl; /* 0x4000 */
1116 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1117 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1118 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1119 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1120 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1121 u32 mask0_word0; /* 0x4018 */
1122 u32 mask0_word1; /* 0x401C */
1123 u32 mask0_word2; /* 0x4020 */
1124 u32 mask0_word3; /* 0x4024 */
1125 u32 mask1_word0; /* 0x4028 */
1126 u32 mask1_word1; /* 0x402C */
1127 u32 mask1_word2; /* 0x4030 */
1128 u32 mask1_word3; /* 0x4034 */
1129 u32 mask2_word0; /* 0x4038 */
1130 u32 mask2_word1; /* 0x403C */
1131 u32 mask2_word2; /* 0x4040 */
1132 u32 mask2_word3; /* 0x4044 */
1133 u32 mask3_word0; /* 0x4048 */
1134 u32 mask3_word1; /* 0x404C */
1135 u32 mask3_word2; /* 0x4050 */
1136 u32 mask3_word3; /* 0x4054 */
1137 u32 mask4_word0; /* 0x4058 */
1138 u32 mask4_word1; /* 0x405C */
1139 u32 mask4_word2; /* 0x4060 */
1140 u32 mask4_word3; /* 0x4064 */
1141 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1142 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1143 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1144 u32 multi_hash1; /* 0x4074 */
1145 u32 multi_hash2; /* 0x4078 */
1146 u32 multi_hash3; /* 0x407C */
1147 u32 multi_hash4; /* 0x4080 */
1148 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1149 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1150 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1151 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1152 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1154 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1155 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1156 } RXMAC_t, *PRXMAC_t;
1158 /* END OF TXMAC REGISTER ADDRESS MAP */
1161 /* START OF MAC REGISTER ADDRESS MAP */
1164 * structure for configuration #1 reg in mac address map.
1165 * located at address 0x5000
1185 #define CFG1_LOOPBACK 0x00000100
1186 #define CFG1_RX_FLOW 0x00000020
1187 #define CFG1_TX_FLOW 0x00000010
1188 #define CFG1_RX_ENABLE 0x00000004
1189 #define CFG1_TX_ENABLE 0x00000001
1190 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1193 * structure for configuration #2 reg in mac address map.
1194 * located at address 0x5004
1210 * structure for Interpacket gap reg in mac address map.
1211 * located at address 0x5008
1214 * 30-24: non B2B ipg 1
1216 * 22-16: non B2B ipg 2
1217 * 15-8: Min ifg enforce
1220 * structure for half duplex reg in mac address map.
1221 * located at address 0x500C
1223 * 23-20: Alt BEB trunc
1224 * 19: Alt BEB enable
1228 * 15-12: re-xmit max
1230 * 9-0: collision window
1234 * structure for Maximum Frame Length reg in mac address map.
1235 * located at address 0x5010: bits 0-15 hold the length.
1239 * structure for Reserve 1 reg in mac address map.
1240 * located at address 0x5014 - 0x5018
1241 * Defined earlier (u32)
1245 * structure for Test reg in mac address map.
1246 * located at address 0x501C
1247 * test: bits 0-2, rest unused
1251 * structure for MII Management Configuration reg in mac address map.
1252 * located at address 0x5020
1254 * 31: reset MII mgmt
1256 * 5: scan auto increment
1257 * 4: preamble supress
1259 * 2-0: mgmt clock reset
1263 * structure for MII Management Command reg in mac address map.
1264 * located at address 0x5024
1270 * structure for MII Management Address reg in mac address map.
1271 * located at address 0x5028
1278 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1281 * structure for MII Management Control reg in mac address map.
1282 * located at address 0x502C
1288 * structure for MII Management Status reg in mac address map.
1289 * located at address 0x5030
1295 * structure for MII Management Indicators reg in mac address map.
1296 * located at address 0x5034
1303 #define MGMT_BUSY 0x00000001 /* busy */
1304 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1307 * structure for Interface Control reg in mac address map.
1308 * located at address 0x5038
1310 * 31: reset if module
1323 * 8: disable link fail
1326 * 0: enable jabber protection
1330 * structure for Interface Status reg in mac address map.
1331 * located at address 0x503C
1333 typedef union _MAC_IF_STAT_t {
1336 #ifdef _BIT_FIELDS_HTOL
1337 u32 reserved:22; /* bits 10-31 */
1338 u32 excess_defer:1; /* bit 9 */
1339 u32 clash:1; /* bit 8 */
1340 u32 phy_jabber:1; /* bit 7 */
1341 u32 phy_link_ok:1; /* bit 6 */
1342 u32 phy_full_duplex:1; /* bit 5 */
1343 u32 phy_speed:1; /* bit 4 */
1344 u32 pe100x_link_fail:1; /* bit 3 */
1345 u32 pe10t_loss_carrie:1; /* bit 2 */
1346 u32 pe10t_sqe_error:1; /* bit 1 */
1347 u32 pe10t_jabber:1; /* bit 0 */
1349 u32 pe10t_jabber:1; /* bit 0 */
1350 u32 pe10t_sqe_error:1; /* bit 1 */
1351 u32 pe10t_loss_carrie:1; /* bit 2 */
1352 u32 pe100x_link_fail:1; /* bit 3 */
1353 u32 phy_speed:1; /* bit 4 */
1354 u32 phy_full_duplex:1; /* bit 5 */
1355 u32 phy_link_ok:1; /* bit 6 */
1356 u32 phy_jabber:1; /* bit 7 */
1357 u32 clash:1; /* bit 8 */
1358 u32 excess_defer:1; /* bit 9 */
1359 u32 reserved:22; /* bits 10-31 */
1362 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1365 * structure for Mac Station Address, Part 1 reg in mac address map.
1366 * located at address 0x5040
1368 typedef union _MAC_STATION_ADDR1_t {
1371 #ifdef _BIT_FIELDS_HTOL
1372 u32 Octet6:8; /* bits 24-31 */
1373 u32 Octet5:8; /* bits 16-23 */
1374 u32 Octet4:8; /* bits 8-15 */
1375 u32 Octet3:8; /* bits 0-7 */
1377 u32 Octet3:8; /* bits 0-7 */
1378 u32 Octet4:8; /* bits 8-15 */
1379 u32 Octet5:8; /* bits 16-23 */
1380 u32 Octet6:8; /* bits 24-31 */
1383 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1386 * structure for Mac Station Address, Part 2 reg in mac address map.
1387 * located at address 0x5044
1389 typedef union _MAC_STATION_ADDR2_t {
1392 #ifdef _BIT_FIELDS_HTOL
1393 u32 Octet2:8; /* bits 24-31 */
1394 u32 Octet1:8; /* bits 16-23 */
1395 u32 reserved:16; /* bits 0-15 */
1397 u32 reserved:16; /* bit 0-15 */
1398 u32 Octet1:8; /* bits 16-23 */
1399 u32 Octet2:8; /* bits 24-31 */
1402 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1405 * MAC Module of JAGCore Address Mapping
1407 typedef struct _MAC_t { /* Location: */
1408 u32 cfg1; /* 0x5000 */
1409 u32 cfg2; /* 0x5004 */
1410 u32 ipg; /* 0x5008 */
1411 u32 hfdp; /* 0x500C */
1412 u32 max_fm_len; /* 0x5010 */
1413 u32 rsv1; /* 0x5014 */
1414 u32 rsv2; /* 0x5018 */
1415 u32 mac_test; /* 0x501C */
1416 u32 mii_mgmt_cfg; /* 0x5020 */
1417 u32 mii_mgmt_cmd; /* 0x5024 */
1418 u32 mii_mgmt_addr; /* 0x5028 */
1419 u32 mii_mgmt_ctrl; /* 0x502C */
1420 u32 mii_mgmt_stat; /* 0x5030 */
1421 u32 mii_mgmt_indicator; /* 0x5034 */
1422 u32 if_ctrl; /* 0x5038 */
1423 MAC_IF_STAT_t if_stat; /* 0x503C */
1424 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1425 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1428 /* END OF MAC REGISTER ADDRESS MAP */
1430 /* START OF MAC STAT REGISTER ADDRESS MAP */
1433 * structure for Carry Register One and it's Mask Register reg located in mac
1434 * stat address map address 0x6130 and 0x6138.
1464 * structure for Carry Register Two Mask Register reg in mac stat address map.
1465 * located at address 0x613C
1491 * MAC STATS Module of JAGCore Address Mapping
1493 typedef struct _MAC_STAT_t { /* Location: */
1494 u32 pad[32]; /* 0x6000 - 607C */
1496 /* Tx/Rx 0-64 Byte Frame Counter */
1497 u32 TR64; /* 0x6080 */
1499 /* Tx/Rx 65-127 Byte Frame Counter */
1500 u32 TR127; /* 0x6084 */
1502 /* Tx/Rx 128-255 Byte Frame Counter */
1503 u32 TR255; /* 0x6088 */
1505 /* Tx/Rx 256-511 Byte Frame Counter */
1506 u32 TR511; /* 0x608C */
1508 /* Tx/Rx 512-1023 Byte Frame Counter */
1509 u32 TR1K; /* 0x6090 */
1511 /* Tx/Rx 1024-1518 Byte Frame Counter */
1512 u32 TRMax; /* 0x6094 */
1514 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1515 u32 TRMgv; /* 0x6098 */
1517 /* Rx Byte Counter */
1518 u32 RByt; /* 0x609C */
1520 /* Rx Packet Counter */
1521 u32 RPkt; /* 0x60A0 */
1523 /* Rx FCS Error Counter */
1524 u32 RFcs; /* 0x60A4 */
1526 /* Rx Multicast Packet Counter */
1527 u32 RMca; /* 0x60A8 */
1529 /* Rx Broadcast Packet Counter */
1530 u32 RBca; /* 0x60AC */
1532 /* Rx Control Frame Packet Counter */
1533 u32 RxCf; /* 0x60B0 */
1535 /* Rx Pause Frame Packet Counter */
1536 u32 RxPf; /* 0x60B4 */
1538 /* Rx Unknown OP Code Counter */
1539 u32 RxUo; /* 0x60B8 */
1541 /* Rx Alignment Error Counter */
1542 u32 RAln; /* 0x60BC */
1544 /* Rx Frame Length Error Counter */
1545 u32 RFlr; /* 0x60C0 */
1547 /* Rx Code Error Counter */
1548 u32 RCde; /* 0x60C4 */
1550 /* Rx Carrier Sense Error Counter */
1551 u32 RCse; /* 0x60C8 */
1553 /* Rx Undersize Packet Counter */
1554 u32 RUnd; /* 0x60CC */
1556 /* Rx Oversize Packet Counter */
1557 u32 ROvr; /* 0x60D0 */
1559 /* Rx Fragment Counter */
1560 u32 RFrg; /* 0x60D4 */
1562 /* Rx Jabber Counter */
1563 u32 RJbr; /* 0x60D8 */
1566 u32 RDrp; /* 0x60DC */
1568 /* Tx Byte Counter */
1569 u32 TByt; /* 0x60E0 */
1571 /* Tx Packet Counter */
1572 u32 TPkt; /* 0x60E4 */
1574 /* Tx Multicast Packet Counter */
1575 u32 TMca; /* 0x60E8 */
1577 /* Tx Broadcast Packet Counter */
1578 u32 TBca; /* 0x60EC */
1580 /* Tx Pause Control Frame Counter */
1581 u32 TxPf; /* 0x60F0 */
1583 /* Tx Deferral Packet Counter */
1584 u32 TDfr; /* 0x60F4 */
1586 /* Tx Excessive Deferral Packet Counter */
1587 u32 TEdf; /* 0x60F8 */
1589 /* Tx Single Collision Packet Counter */
1590 u32 TScl; /* 0x60FC */
1592 /* Tx Multiple Collision Packet Counter */
1593 u32 TMcl; /* 0x6100 */
1595 /* Tx Late Collision Packet Counter */
1596 u32 TLcl; /* 0x6104 */
1598 /* Tx Excessive Collision Packet Counter */
1599 u32 TXcl; /* 0x6108 */
1601 /* Tx Total Collision Packet Counter */
1602 u32 TNcl; /* 0x610C */
1604 /* Tx Pause Frame Honored Counter */
1605 u32 TPfh; /* 0x6110 */
1607 /* Tx Drop Frame Counter */
1608 u32 TDrp; /* 0x6114 */
1610 /* Tx Jabber Frame Counter */
1611 u32 TJbr; /* 0x6118 */
1613 /* Tx FCS Error Counter */
1614 u32 TFcs; /* 0x611C */
1616 /* Tx Control Frame Counter */
1617 u32 TxCf; /* 0x6120 */
1619 /* Tx Oversize Frame Counter */
1620 u32 TOvr; /* 0x6124 */
1622 /* Tx Undersize Frame Counter */
1623 u32 TUnd; /* 0x6128 */
1625 /* Tx Fragments Frame Counter */
1626 u32 TFrg; /* 0x612C */
1628 /* Carry Register One Register */
1629 u32 Carry1; /* 0x6130 */
1631 /* Carry Register Two Register */
1632 u32 Carry2; /* 0x6134 */
1634 /* Carry Register One Mask Register */
1635 u32 Carry1M; /* 0x6138 */
1637 /* Carry Register Two Mask Register */
1638 u32 Carry2M; /* 0x613C */
1639 } MAC_STAT_t, *PMAC_STAT_t;
1641 /* END OF MAC STAT REGISTER ADDRESS MAP */
1644 /* START OF MMC REGISTER ADDRESS MAP */
1647 * Main Memory Controller Control reg in mmc address map.
1648 * located at address 0x7000
1651 #define ET_MMC_ENABLE 1
1652 #define ET_MMC_ARB_DISABLE 2
1653 #define ET_MMC_RXMAC_DISABLE 4
1654 #define ET_MMC_TXMAC_DISABLE 8
1655 #define ET_MMC_TXDMA_DISABLE 16
1656 #define ET_MMC_RXDMA_DISABLE 32
1657 #define ET_MMC_FORCE_CE 64
1660 * Main Memory Controller Host Memory Access Address reg in mmc
1661 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1664 #define ET_SRAM_REQ_ACCESS 1
1665 #define ET_SRAM_WR_ACCESS 2
1666 #define ET_SRAM_IS_CTRL 4
1669 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1670 * address map. Located at address 0x7008 - 0x7014
1671 * Defined earlier (u32)
1675 * Memory Control Module of JAGCore Address Mapping
1677 typedef struct _MMC_t { /* Location: */
1678 u32 mmc_ctrl; /* 0x7000 */
1679 u32 sram_access; /* 0x7004 */
1680 u32 sram_word1; /* 0x7008 */
1681 u32 sram_word2; /* 0x700C */
1682 u32 sram_word3; /* 0x7010 */
1683 u32 sram_word4; /* 0x7014 */
1686 /* END OF MMC REGISTER ADDRESS MAP */
1689 /* START OF EXP ROM REGISTER ADDRESS MAP */
1692 * Expansion ROM Module of JAGCore Address Mapping
1695 /* Take this out until it is not empty */
1697 typedef struct _EXP_ROM_t {
1699 } EXP_ROM_t, *PEXP_ROM_t;
1702 /* END OF EXP ROM REGISTER ADDRESS MAP */
1706 * JAGCore Address Mapping
1708 typedef struct _ADDRESS_MAP_t {
1710 /* unused section of global address map */
1711 u8 unused_global[4096 - sizeof(GLOBAL_t)];
1713 /* unused section of txdma address map */
1714 u8 unused_txdma[4096 - sizeof(TXDMA_t)];
1716 /* unused section of rxdma address map */
1717 u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
1719 /* unused section of txmac address map */
1720 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1722 /* unused section of rxmac address map */
1723 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1725 /* unused section of mac address map */
1726 u8 unused_mac[4096 - sizeof(MAC_t)];
1728 /* unused section of mac stat address map */
1729 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1731 /* unused section of mmc address map */
1732 u8 unused_mmc[4096 - sizeof(MMC_t)];
1733 /* unused section of address map */
1734 u8 unused_[1015808];
1736 /* Take this out until it is not empty */
1741 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1742 u8 unused__[524288]; /* unused section of address map */
1743 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1745 #endif /* _ET1310_ADDRESS_MAP_H_ */