1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2003 Digi International (www.digi.com)
4 * Scott H Kilau <Scott_Kilau at digi dot com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14 * PURPOSE. See the GNU General Public License for more details.
21 * struct cls_uart_struct - Per channel/port Classic UART.
23 * key - W = read write
27 * @txrx: (WR) Holding Register.
28 * @ier: (WR) Interrupt Enable Register.
29 * @isr_fcr: (WR) Interrupt Status Register/Fifo Control Register.
30 * @lcr: (WR) Line Control Register.
31 * @mcr: (WR) Modem Control Register.
32 * @lsr: (WR) Line Status Register.
33 * @msr: (WR) Modem Status Register.
34 * @spr: (WR) Scratch Pad Register.
36 struct cls_uart_struct {
47 /* Where to read the interrupt register (8bits) */
48 #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
50 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
52 #define UART_16654_FCR_TXTRIGGER_16 0x10
53 #define UART_16654_FCR_RXTRIGGER_16 0x40
54 #define UART_16654_FCR_RXTRIGGER_56 0x80
56 /* Received CTS/RTS change of state */
57 #define UART_IIR_CTSRTS 0x20
59 /* Receiver data TIMEOUT */
60 #define UART_IIR_RDI_TIMEOUT 0x0C
63 * These are the EXTENDED definitions for the Exar 654's Interrupt
66 #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
67 #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
68 #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
69 #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
70 #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow Control Enable */
71 #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
72 #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
73 #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
75 extern struct board_ops dgnc_cls_ops;
77 #endif /* _DGNC_CLS_H */