2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
32 #include <linux/kernel.h>
33 #include <linux/sched.h> /* For jiffies, task states */
34 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
35 #include <linux/delay.h> /* For udelay */
36 #include <asm/io.h> /* For read[bwl]/write[bwl] */
37 #include <linux/serial.h> /* For struct async_serial */
38 #include <linux/serial_reg.h> /* For the various UART offsets */
39 #include <linux/pci.h>
41 #include "dgnc_driver.h" /* Driver main header file */
44 #include "dgnc_trace.h"
46 static inline void cls_parse_isr(struct board_t *brd, uint port);
47 static inline void cls_clear_break(struct channel_t *ch, int force);
48 static inline void cls_set_cts_flow_control(struct channel_t *ch);
49 static inline void cls_set_rts_flow_control(struct channel_t *ch);
50 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
51 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
52 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
53 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
54 static void cls_parse_modem(struct channel_t *ch, uchar signals);
55 static void cls_tasklet(unsigned long data);
56 static void cls_vpd(struct board_t *brd);
57 static void cls_uart_init(struct channel_t *ch);
58 static void cls_uart_off(struct channel_t *ch);
59 static int cls_drain(struct tty_struct *tty, uint seconds);
60 static void cls_param(struct tty_struct *tty);
61 static void cls_assert_modem_signals(struct channel_t *ch);
62 static void cls_flush_uart_write(struct channel_t *ch);
63 static void cls_flush_uart_read(struct channel_t *ch);
64 static void cls_disable_receiver(struct channel_t *ch);
65 static void cls_enable_receiver(struct channel_t *ch);
66 static void cls_send_break(struct channel_t *ch, int msecs);
67 static void cls_send_start_character(struct channel_t *ch);
68 static void cls_send_stop_character(struct channel_t *ch);
69 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
70 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
71 static uint cls_get_uart_bytes_left(struct channel_t *ch);
72 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
73 static irqreturn_t cls_intr(int irq, void *voidbrd);
75 struct board_ops dgnc_cls_ops = {
76 .tasklet = cls_tasklet,
78 .uart_init = cls_uart_init,
79 .uart_off = cls_uart_off,
83 .assert_modem_signals = cls_assert_modem_signals,
84 .flush_uart_write = cls_flush_uart_write,
85 .flush_uart_read = cls_flush_uart_read,
86 .disable_receiver = cls_disable_receiver,
87 .enable_receiver = cls_enable_receiver,
88 .send_break = cls_send_break,
89 .send_start_character = cls_send_start_character,
90 .send_stop_character = cls_send_stop_character,
91 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
92 .get_uart_bytes_left = cls_get_uart_bytes_left,
93 .send_immediate_char = cls_send_immediate_char
97 static inline void cls_set_cts_flow_control(struct channel_t *ch)
99 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
100 uchar ier = readb(&ch->ch_cls_uart->ier);
103 DPR_PARAM(("Setting CTSFLOW\n"));
106 * The Enhanced Register Set may only be accessed when
107 * the Line Control Register is set to 0xBFh.
109 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
111 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
113 /* Turn on CTS flow control, turn off IXON flow control */
114 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
115 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
117 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
119 /* Write old LCR value back out, which turns enhanced access off */
120 writeb(lcrb, &ch->ch_cls_uart->lcr);
122 /* Enable interrupts for CTS flow, turn off interrupts for received XOFF chars */
123 ier |= (UART_EXAR654_IER_CTSDSR);
124 ier &= ~(UART_EXAR654_IER_XOFF);
125 writeb(ier, &ch->ch_cls_uart->ier);
127 /* Set the usual FIFO values */
128 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
130 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
131 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
132 &ch->ch_cls_uart->isr_fcr);
134 ch->ch_t_tlevel = 16;
139 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
141 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
142 uchar ier = readb(&ch->ch_cls_uart->ier);
145 DPR_PARAM(("Setting IXON FLOW\n"));
148 * The Enhanced Register Set may only be accessed when
149 * the Line Control Register is set to 0xBFh.
151 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
153 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
155 /* Turn on IXON flow control, turn off CTS flow control */
156 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
157 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
159 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
161 /* Now set our current start/stop chars while in enhanced mode */
162 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
163 writeb(0, &ch->ch_cls_uart->lsr);
164 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
165 writeb(0, &ch->ch_cls_uart->spr);
167 /* Write old LCR value back out, which turns enhanced access off */
168 writeb(lcrb, &ch->ch_cls_uart->lcr);
170 /* Disable interrupts for CTS flow, turn on interrupts for received XOFF chars */
171 ier &= ~(UART_EXAR654_IER_CTSDSR);
172 ier |= (UART_EXAR654_IER_XOFF);
173 writeb(ier, &ch->ch_cls_uart->ier);
175 /* Set the usual FIFO values */
176 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
178 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
179 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
180 &ch->ch_cls_uart->isr_fcr);
185 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
187 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
188 uchar ier = readb(&ch->ch_cls_uart->ier);
191 DPR_PARAM(("Unsetting Output FLOW\n"));
194 * The Enhanced Register Set may only be accessed when
195 * the Line Control Register is set to 0xBFh.
197 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
199 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
201 /* Turn off IXON flow control, turn off CTS flow control */
202 isr_fcr |= (UART_EXAR654_EFR_ECB);
203 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
205 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
207 /* Write old LCR value back out, which turns enhanced access off */
208 writeb(lcrb, &ch->ch_cls_uart->lcr);
210 /* Disable interrupts for CTS flow, turn off interrupts for received XOFF chars */
211 ier &= ~(UART_EXAR654_IER_CTSDSR);
212 ier &= ~(UART_EXAR654_IER_XOFF);
213 writeb(ier, &ch->ch_cls_uart->ier);
215 /* Set the usual FIFO values */
216 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
218 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
219 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
220 &ch->ch_cls_uart->isr_fcr);
222 ch->ch_r_watermark = 0;
223 ch->ch_t_tlevel = 16;
224 ch->ch_r_tlevel = 16;
229 static inline void cls_set_rts_flow_control(struct channel_t *ch)
231 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
232 uchar ier = readb(&ch->ch_cls_uart->ier);
235 DPR_PARAM(("Setting RTSFLOW\n"));
238 * The Enhanced Register Set may only be accessed when
239 * the Line Control Register is set to 0xBFh.
241 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
243 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
245 /* Turn on RTS flow control, turn off IXOFF flow control */
246 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
247 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
249 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
251 /* Write old LCR value back out, which turns enhanced access off */
252 writeb(lcrb, &ch->ch_cls_uart->lcr);
254 /* Enable interrupts for RTS flow */
255 ier |= (UART_EXAR654_IER_RTSDTR);
256 writeb(ier, &ch->ch_cls_uart->ier);
258 /* Set the usual FIFO values */
259 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
261 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
262 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
263 &ch->ch_cls_uart->isr_fcr);
266 ch->ch_r_watermark = 4;
272 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
274 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
275 uchar ier = readb(&ch->ch_cls_uart->ier);
278 DPR_PARAM(("Setting IXOFF FLOW\n"));
281 * The Enhanced Register Set may only be accessed when
282 * the Line Control Register is set to 0xBFh.
284 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
286 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
288 /* Turn on IXOFF flow control, turn off RTS flow control */
289 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
290 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
292 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
294 /* Now set our current start/stop chars while in enhanced mode */
295 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
296 writeb(0, &ch->ch_cls_uart->lsr);
297 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
298 writeb(0, &ch->ch_cls_uart->spr);
300 /* Write old LCR value back out, which turns enhanced access off */
301 writeb(lcrb, &ch->ch_cls_uart->lcr);
303 /* Disable interrupts for RTS flow */
304 ier &= ~(UART_EXAR654_IER_RTSDTR);
305 writeb(ier, &ch->ch_cls_uart->ier);
307 /* Set the usual FIFO values */
308 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
310 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
311 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
312 &ch->ch_cls_uart->isr_fcr);
317 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
319 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
320 uchar ier = readb(&ch->ch_cls_uart->ier);
323 DPR_PARAM(("Unsetting Input FLOW\n"));
326 * The Enhanced Register Set may only be accessed when
327 * the Line Control Register is set to 0xBFh.
329 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
331 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
333 /* Turn off IXOFF flow control, turn off RTS flow control */
334 isr_fcr |= (UART_EXAR654_EFR_ECB);
335 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
337 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
339 /* Write old LCR value back out, which turns enhanced access off */
340 writeb(lcrb, &ch->ch_cls_uart->lcr);
342 /* Disable interrupts for RTS flow */
343 ier &= ~(UART_EXAR654_IER_RTSDTR);
344 writeb(ier, &ch->ch_cls_uart->ier);
346 /* Set the usual FIFO values */
347 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
349 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
350 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
351 &ch->ch_cls_uart->isr_fcr);
353 ch->ch_t_tlevel = 16;
354 ch->ch_r_tlevel = 16;
361 * Determines whether its time to shut off break condition.
363 * No locks are assumed to be held when calling this function.
364 * channel lock is held and released in this function.
366 static inline void cls_clear_break(struct channel_t *ch, int force)
370 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
373 DGNC_LOCK(ch->ch_lock, lock_flags);
375 /* Bail if we aren't currently sending a break. */
376 if (!ch->ch_stop_sending_break) {
377 DGNC_UNLOCK(ch->ch_lock, lock_flags);
381 /* Turn break off, and unset some variables */
382 if (ch->ch_flags & CH_BREAK_SENDING) {
383 if ((jiffies >= ch->ch_stop_sending_break) || force) {
384 uchar temp = readb(&ch->ch_cls_uart->lcr);
385 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
386 ch->ch_flags &= ~(CH_BREAK_SENDING);
387 ch->ch_stop_sending_break = 0;
388 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
391 DGNC_UNLOCK(ch->ch_lock, lock_flags);
395 /* Parse the ISR register for the specific port */
396 static inline void cls_parse_isr(struct board_t *brd, uint port)
398 struct channel_t *ch;
403 * No need to verify board pointer, it was already
404 * verified in the interrupt routine.
407 if (port > brd->nasync)
410 ch = brd->channels[port];
411 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
414 /* Here we try to figure out what caused the interrupt to happen */
417 isr = readb(&ch->ch_cls_uart->isr_fcr);
419 /* Bail if no pending interrupt on port */
420 if (isr & UART_IIR_NO_INT) {
424 DPR_INTR(("%s:%d port: %x isr: %x\n", __FILE__, __LINE__, port, isr));
426 /* Receive Interrupt pending */
427 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
428 /* Read data from uart -> queue */
431 cls_copy_data_from_uart_to_queue(ch);
432 dgnc_check_queue_flow_control(ch);
435 /* Transmit Hold register empty pending */
436 if (isr & UART_IIR_THRI) {
437 /* Transfer data (if any) from Write Queue -> UART. */
438 DGNC_LOCK(ch->ch_lock, lock_flags);
439 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
442 DGNC_UNLOCK(ch->ch_lock, lock_flags);
443 cls_copy_data_from_queue_to_uart(ch);
446 /* Received Xoff signal/Special character */
447 if (isr & UART_IIR_XOFF) {
451 /* CTS/RTS change of state */
452 if (isr & UART_IIR_CTSRTS) {
456 * Don't need to do anything, the cls_parse_modem
457 * below will grab the updated modem signals.
461 /* Parse any modem signal changes */
462 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
463 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
470 * Send any/all changes to the line to the UART.
472 static void cls_param(struct tty_struct *tty)
481 struct channel_t *ch;
484 if (!tty || tty->magic != TTY_MAGIC) {
488 un = (struct un_t *) tty->driver_data;
489 if (!un || un->magic != DGNC_UNIT_MAGIC) {
494 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
499 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
503 DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
504 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag, ch->ch_c_iflag));
507 * If baud rate is zero, flush queues, and set mval to drop DTR.
509 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
510 ch->ch_r_head = ch->ch_r_tail = 0;
511 ch->ch_e_head = ch->ch_e_tail = 0;
512 ch->ch_w_head = ch->ch_w_tail = 0;
514 cls_flush_uart_write(ch);
515 cls_flush_uart_read(ch);
517 /* The baudrate is B0 so all modem lines are to be dropped. */
518 ch->ch_flags |= (CH_BAUD0);
519 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
520 cls_assert_modem_signals(ch);
523 } else if (ch->ch_custom_speed) {
525 baud = ch->ch_custom_speed;
526 /* Handle transition from B0 */
527 if (ch->ch_flags & CH_BAUD0) {
528 ch->ch_flags &= ~(CH_BAUD0);
531 * Bring back up RTS and DTR...
532 * Also handle RTS or DTR toggle if set.
534 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
535 ch->ch_mostat |= (UART_MCR_RTS);
536 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
537 ch->ch_mostat |= (UART_MCR_DTR);
544 ulong bauds[4][16] = {
548 600, 1200, 1800, 2400,
549 4800, 9600, 19200, 38400 },
550 { /* slowbaud & CBAUDEX */
551 0, 57600, 115200, 230400,
552 460800, 150, 200, 921600,
553 600, 1200, 1800, 2400,
554 4800, 9600, 19200, 38400 },
556 0, 57600, 76800, 115200,
557 131657, 153600, 230400, 460800,
558 921600, 1200, 1800, 2400,
559 4800, 9600, 19200, 38400 },
560 { /* fastbaud & CBAUDEX */
561 0, 57600, 115200, 230400,
562 460800, 150, 200, 921600,
563 600, 1200, 1800, 2400,
564 4800, 9600, 19200, 38400 }
567 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
568 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
569 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
571 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
573 if (ch->ch_c_cflag & CBAUDEX)
576 if (ch->ch_digi.digi_flags & DIGI_FAST)
581 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
582 baud = bauds[iindex][jindex];
584 DPR_IOCTL(("baud indices were out of range (%d)(%d)",
592 /* Handle transition from B0 */
593 if (ch->ch_flags & CH_BAUD0) {
594 ch->ch_flags &= ~(CH_BAUD0);
597 * Bring back up RTS and DTR...
598 * Also handle RTS or DTR toggle if set.
600 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
601 ch->ch_mostat |= (UART_MCR_RTS);
602 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
603 ch->ch_mostat |= (UART_MCR_DTR);
607 if (ch->ch_c_cflag & PARENB) {
608 lcr |= UART_LCR_PARITY;
611 if (!(ch->ch_c_cflag & PARODD)) {
612 lcr |= UART_LCR_EPAR;
616 * Not all platforms support mark/space parity,
617 * so this will hide behind an ifdef.
620 if (ch->ch_c_cflag & CMSPAR)
621 lcr |= UART_LCR_SPAR;
624 if (ch->ch_c_cflag & CSTOPB)
625 lcr |= UART_LCR_STOP;
627 switch (ch->ch_c_cflag & CSIZE) {
629 lcr |= UART_LCR_WLEN5;
632 lcr |= UART_LCR_WLEN6;
635 lcr |= UART_LCR_WLEN7;
639 lcr |= UART_LCR_WLEN8;
643 ier = uart_ier = readb(&ch->ch_cls_uart->ier);
644 uart_lcr = readb(&ch->ch_cls_uart->lcr);
649 quot = ch->ch_bd->bd_dividend / baud;
651 if (quot != 0 && ch->ch_old_baud != baud) {
652 ch->ch_old_baud = baud;
653 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
654 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
655 writeb((quot >> 8), &ch->ch_cls_uart->ier);
656 writeb(lcr, &ch->ch_cls_uart->lcr);
660 writeb(lcr, &ch->ch_cls_uart->lcr);
662 if (ch->ch_c_cflag & CREAD) {
663 ier |= (UART_IER_RDI | UART_IER_RLSI);
666 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
670 * Have the UART interrupt on modem signal changes ONLY when
671 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
673 if ((ch->ch_digi.digi_flags & CTSPACE) || (ch->ch_digi.digi_flags & RTSPACE) ||
674 (ch->ch_c_cflag & CRTSCTS) || !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
675 !(ch->ch_c_cflag & CLOCAL))
680 ier &= ~UART_IER_MSI;
683 ier |= UART_IER_THRI;
686 writeb(ier, &ch->ch_cls_uart->ier);
688 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
689 cls_set_cts_flow_control(ch);
691 else if (ch->ch_c_iflag & IXON) {
692 /* If start/stop is set to disable, then we should disable flow control */
693 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
694 cls_set_no_output_flow_control(ch);
696 cls_set_ixon_flow_control(ch);
699 cls_set_no_output_flow_control(ch);
702 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
703 cls_set_rts_flow_control(ch);
705 else if (ch->ch_c_iflag & IXOFF) {
706 /* If start/stop is set to disable, then we should disable flow control */
707 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
708 cls_set_no_input_flow_control(ch);
710 cls_set_ixoff_flow_control(ch);
713 cls_set_no_input_flow_control(ch);
716 cls_assert_modem_signals(ch);
718 /* Get current status of the modem signals now */
719 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
724 * Our board poller function.
726 static void cls_tasklet(unsigned long data)
728 struct board_t *bd = (struct board_t *) data;
729 struct channel_t *ch;
735 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
736 APR(("poll_tasklet() - NULL or bad bd.\n"));
740 /* Cache a couple board values */
741 DGNC_LOCK(bd->bd_lock, lock_flags);
744 DGNC_UNLOCK(bd->bd_lock, lock_flags);
747 * Do NOT allow the interrupt routine to read the intr registers
748 * Until we release this lock.
750 DGNC_LOCK(bd->bd_intr_lock, lock_flags);
753 * If board is ready, parse deeper to see if there is anything to do.
755 if ((state == BOARD_READY) && (ports > 0)) {
757 /* Loop on each port */
758 for (i = 0; i < ports; i++) {
759 ch = bd->channels[i];
764 * NOTE: Remember you CANNOT hold any channel
765 * locks when calling input.
766 * During input processing, its possible we
767 * will call ld, which might do callbacks back
773 * Channel lock is grabbed and then released
774 * inside this routine.
776 cls_copy_data_from_queue_to_uart(ch);
777 dgnc_wakeup_writes(ch);
780 * Check carrier function.
785 * The timing check of turning off the break is done
786 * inside clear_break()
788 if (ch->ch_stop_sending_break)
789 cls_clear_break(ch, 0);
793 DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
801 * Classic specific interrupt handler.
803 static irqreturn_t cls_intr(int irq, void *voidbrd)
805 struct board_t *brd = (struct board_t *) voidbrd;
808 unsigned long lock_flags;
811 APR(("Received interrupt (%d) with null board associated\n", irq));
816 * Check to make sure its for us.
818 if (brd->magic != DGNC_BOARD_MAGIC) {
819 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq));
823 DGNC_LOCK(brd->bd_intr_lock, lock_flags);
828 * Check the board's global interrupt offset to see if we
829 * we actually do have an interrupt pending for us.
831 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
833 /* If 0, no interrupts pending */
835 DPR_INTR(("Kernel interrupted to me, but no pending interrupts...\n"));
836 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
840 DPR_INTR(("%s:%d poll_reg: %x\n", __FILE__, __LINE__, poll_reg));
842 /* Parse each port to find out what caused the interrupt */
843 for (i = 0; i < brd->nasync; i++) {
844 cls_parse_isr(brd, i);
848 * Schedule tasklet to more in-depth servicing at a better time.
850 tasklet_schedule(&brd->helper_tasklet);
852 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
854 DPR_INTR(("dgnc_intr finish.\n"));
859 static void cls_disable_receiver(struct channel_t *ch)
861 uchar tmp = readb(&ch->ch_cls_uart->ier);
862 tmp &= ~(UART_IER_RDI);
863 writeb(tmp, &ch->ch_cls_uart->ier);
867 static void cls_enable_receiver(struct channel_t *ch)
869 uchar tmp = readb(&ch->ch_cls_uart->ier);
870 tmp |= (UART_IER_RDI);
871 writeb(tmp, &ch->ch_cls_uart->ier);
875 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
878 uchar linestatus = 0;
879 uchar error_mask = 0;
884 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
887 DGNC_LOCK(ch->ch_lock, lock_flags);
889 /* cache head and tail of queue */
890 head = ch->ch_r_head;
891 tail = ch->ch_r_tail;
893 /* Store how much space we have left in the queue */
894 if ((qleft = tail - head - 1) < 0)
895 qleft += RQUEUEMASK + 1;
898 * Create a mask to determine whether we should
899 * insert the character (if any) into our queue.
901 if (ch->ch_c_iflag & IGNBRK)
902 error_mask |= UART_LSR_BI;
905 linestatus = readb(&ch->ch_cls_uart->lsr);
907 if (!(linestatus & (UART_LSR_DR)))
911 * Discard character if we are ignoring the error mask.
913 if (linestatus & error_mask) {
916 discard = readb(&ch->ch_cls_uart->txrx);
921 * If our queue is full, we have no choice but to drop some data.
922 * The assumption is that HWFLOW or SWFLOW should have stopped
923 * things way way before we got to this point.
925 * I decided that I wanted to ditch the oldest data first,
926 * I hope thats okay with everyone? Yes? Good.
929 DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
930 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
932 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
933 ch->ch_err_overrun++;
937 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE | UART_LSR_FE);
938 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
939 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1);
943 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]));
945 if (ch->ch_equeue[head] & UART_LSR_PE)
947 if (ch->ch_equeue[head] & UART_LSR_BI)
949 if (ch->ch_equeue[head] & UART_LSR_FE)
952 /* Add to, and flip head if needed */
953 head = (head + 1) & RQUEUEMASK;
958 * Write new final heads to channel structure.
960 ch->ch_r_head = head & RQUEUEMASK;
961 ch->ch_e_head = head & EQUEUEMASK;
963 DGNC_UNLOCK(ch->ch_lock, lock_flags);
968 * This function basically goes to sleep for secs, or until
969 * it gets signalled that the port has fully drained.
971 static int cls_drain(struct tty_struct *tty, uint seconds)
974 struct channel_t *ch;
978 if (!tty || tty->magic != TTY_MAGIC) {
982 un = (struct un_t *) tty->driver_data;
983 if (!un || un->magic != DGNC_UNIT_MAGIC) {
988 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
992 DGNC_LOCK(ch->ch_lock, lock_flags);
993 un->un_flags |= UN_EMPTY;
994 DGNC_UNLOCK(ch->ch_lock, lock_flags);
997 * NOTE: Do something with time passed in.
999 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1001 /* If ret is non-zero, user ctrl-c'ed us */
1003 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1009 /* Channel lock MUST be held before calling this function! */
1010 static void cls_flush_uart_write(struct channel_t *ch)
1012 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1016 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_cls_uart->isr_fcr);
1019 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1023 /* Channel lock MUST be held before calling this function! */
1024 static void cls_flush_uart_read(struct channel_t *ch)
1026 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1031 * For complete POSIX compatibility, we should be purging the
1032 * read FIFO in the UART here.
1034 * However, doing the statement below also incorrectly flushes
1035 * write data as well as just basically trashing the FIFO.
1037 * I believe this is a BUG in this UART.
1038 * So for now, we will leave the code #ifdef'ed out...
1041 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_cls_uart->isr_fcr);
1047 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1053 uint len_written = 0;
1056 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1059 DGNC_LOCK(ch->ch_lock, lock_flags);
1061 /* No data to write to the UART */
1062 if (ch->ch_w_tail == ch->ch_w_head) {
1063 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1067 /* If port is "stopped", don't send any data to the UART */
1068 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
1069 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1073 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1074 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1080 /* cache head and tail of queue */
1081 head = ch->ch_w_head & WQUEUEMASK;
1082 tail = ch->ch_w_tail & WQUEUEMASK;
1083 qlen = (head - tail) & WQUEUEMASK;
1085 /* Find minimum of the FIFO space, versus queue length */
1091 * If RTS Toggle mode is on, turn on RTS now if not already set,
1092 * and make sure we get an event when the data transfer has completed.
1094 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1095 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1096 ch->ch_mostat |= (UART_MCR_RTS);
1097 cls_assert_modem_signals(ch);
1099 ch->ch_tun.un_flags |= (UN_EMPTY);
1103 * If DTR Toggle mode is on, turn on DTR now if not already set,
1104 * and make sure we get an event when the data transfer has completed.
1106 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1107 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1108 ch->ch_mostat |= (UART_MCR_DTR);
1109 cls_assert_modem_signals(ch);
1111 ch->ch_tun.un_flags |= (UN_EMPTY);
1113 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1114 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + ch->ch_w_tail, 1);
1115 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_tail]));
1117 ch->ch_w_tail &= WQUEUEMASK;
1123 if (len_written > 0)
1124 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1126 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1132 static void cls_parse_modem(struct channel_t *ch, uchar signals)
1134 volatile uchar msignals = signals;
1136 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1139 DPR_MSIGS(("cls_parse_modem: port: %d signals: %d\n", ch->ch_portnum, msignals));
1142 * Do altpin switching. Altpin switches DCD and DSR.
1143 * This prolly breaks DSRPACE, so we should be more clever here.
1145 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1146 uchar mswap = signals;
1147 if (mswap & UART_MSR_DDCD) {
1148 msignals &= ~UART_MSR_DDCD;
1149 msignals |= UART_MSR_DDSR;
1151 if (mswap & UART_MSR_DDSR) {
1152 msignals &= ~UART_MSR_DDSR;
1153 msignals |= UART_MSR_DDCD;
1155 if (mswap & UART_MSR_DCD) {
1156 msignals &= ~UART_MSR_DCD;
1157 msignals |= UART_MSR_DSR;
1159 if (mswap & UART_MSR_DSR) {
1160 msignals &= ~UART_MSR_DSR;
1161 msignals |= UART_MSR_DCD;
1165 /* Scrub off lower bits. They signify delta's, which I don't care about */
1168 if (msignals & UART_MSR_DCD)
1169 ch->ch_mistat |= UART_MSR_DCD;
1171 ch->ch_mistat &= ~UART_MSR_DCD;
1173 if (msignals & UART_MSR_DSR)
1174 ch->ch_mistat |= UART_MSR_DSR;
1176 ch->ch_mistat &= ~UART_MSR_DSR;
1178 if (msignals & UART_MSR_RI)
1179 ch->ch_mistat |= UART_MSR_RI;
1181 ch->ch_mistat &= ~UART_MSR_RI;
1183 if (msignals & UART_MSR_CTS)
1184 ch->ch_mistat |= UART_MSR_CTS;
1186 ch->ch_mistat &= ~UART_MSR_CTS;
1189 DPR_MSIGS(("Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1191 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1192 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1193 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1194 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1195 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1196 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1200 /* Make the UART raise any of the output signals we want up */
1201 static void cls_assert_modem_signals(struct channel_t *ch)
1205 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1208 out = ch->ch_mostat;
1210 if (ch->ch_flags & CH_LOOPBACK)
1211 out |= UART_MCR_LOOP;
1213 writeb(out, &ch->ch_cls_uart->mcr);
1215 /* Give time for the UART to actually drop the signals */
1220 static void cls_send_start_character(struct channel_t *ch)
1222 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1225 if (ch->ch_startc != _POSIX_VDISABLE) {
1227 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1232 static void cls_send_stop_character(struct channel_t *ch)
1234 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1237 if (ch->ch_stopc != _POSIX_VDISABLE) {
1238 ch->ch_xoff_sends++;
1239 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1245 static void cls_uart_init(struct channel_t *ch)
1247 uchar lcrb = readb(&ch->ch_cls_uart->lcr);
1250 writeb(0, &ch->ch_cls_uart->ier);
1253 * The Enhanced Register Set may only be accessed when
1254 * the Line Control Register is set to 0xBFh.
1256 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1258 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1260 /* Turn on Enhanced/Extended controls */
1261 isr_fcr |= (UART_EXAR654_EFR_ECB);
1263 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1265 /* Write old LCR value back out, which turns enhanced access off */
1266 writeb(lcrb, &ch->ch_cls_uart->lcr);
1268 /* Clear out UART and FIFO */
1269 readb(&ch->ch_cls_uart->txrx);
1271 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_cls_uart->isr_fcr);
1274 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1276 readb(&ch->ch_cls_uart->lsr);
1277 readb(&ch->ch_cls_uart->msr);
1284 static void cls_uart_off(struct channel_t *ch)
1286 writeb(0, &ch->ch_cls_uart->ier);
1291 * cls_get_uarts_bytes_left.
1292 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1294 * The channel lock MUST be held by the calling function.
1296 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1301 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1304 lsr = readb(&ch->ch_cls_uart->lsr);
1306 /* Determine whether the Transmitter is empty or not */
1307 if (!(lsr & UART_LSR_TEMT)) {
1308 if (ch->ch_flags & CH_TX_FIFO_EMPTY) {
1309 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1314 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1324 * Starts sending a break thru the UART.
1326 * The channel lock MUST be held by the calling function.
1328 static void cls_send_break(struct channel_t *ch, int msecs)
1330 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1334 * If we receive a time of 0, this means turn off the break.
1337 /* Turn break off, and unset some variables */
1338 if (ch->ch_flags & CH_BREAK_SENDING) {
1339 uchar temp = readb(&ch->ch_cls_uart->lcr);
1340 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1341 ch->ch_flags &= ~(CH_BREAK_SENDING);
1342 ch->ch_stop_sending_break = 0;
1343 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
1349 * Set the time we should stop sending the break.
1350 * If we are already sending a break, toss away the existing
1351 * time to stop, and use this new value instead.
1353 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1355 /* Tell the UART to start sending the break */
1356 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1357 uchar temp = readb(&ch->ch_cls_uart->lcr);
1358 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1359 ch->ch_flags |= (CH_BREAK_SENDING);
1360 DPR_IOCTL(("Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1361 ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1367 * cls_send_immediate_char.
1368 * Sends a specific character as soon as possible to the UART,
1369 * jumping over any bytes that might be in the write queue.
1371 * The channel lock MUST be held by the calling function.
1373 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1375 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1378 writeb(c, &ch->ch_cls_uart->txrx);
1381 static void cls_vpd(struct board_t *brd)
1383 ulong vpdbase; /* Start of io base of the card */
1384 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
1388 vpdbase = pci_resource_start(brd->pdev, 3);
1394 re_map_vpdbase = ioremap(vpdbase, 0x400);
1396 if (!re_map_vpdbase)
1399 /* Store the VPD into our buffer */
1400 for (i = 0; i < 0x40; i++) {
1401 brd->vpd[i] = readb(re_map_vpdbase + i);
1402 printk("%x ", brd->vpd[i]);
1407 iounmap(re_map_vpdbase);