2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
109 #define DRV_NAME "rtd520"
111 /*======================================================================
112 Driver specific stuff (tunable)
113 ======================================================================*/
114 /* Enable this to test the new DMA support. You may get hard lock ups */
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
130 /* tuning for ai/ao instruction done polling */
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
144 /*======================================================================
146 ======================================================================*/
149 #define PCI_VENDOR_ID_RTD 0x1435
151 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
152 Las1 has the data and can be burst DMAed 32bits at a time.
154 #define LCFG_PCIINDEX 0
155 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
156 #define LAS0_PCIINDEX 2 /* PCI memory resources */
157 #define LAS1_PCIINDEX 3
158 #define LCFG_PCISIZE 0x100
159 #define LAS0_PCISIZE 0x200
160 #define LAS1_PCISIZE 0x10
162 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
163 #define RTD_CLOCK_BASE 125 /* clock period in ns */
165 /* Note: these speed are slower than the spec, but fit the counter resolution*/
166 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
167 /* max speed if we don't have to wait for settling */
168 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
170 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
171 /* min speed when only 1 channel (no burst counter) */
172 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
177 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
178 #define DMA_MODE_BITS (\
179 PLX_LOCAL_BUS_16_WIDE_BITS \
180 | PLX_DMA_EN_READYIN_BIT \
181 | PLX_DMA_LOCAL_BURST_EN_BIT \
183 | PLX_DMA_INTR_PCI_BIT \
184 | PLX_LOCAL_ADDR_CONST_BIT \
185 | PLX_DEMAND_MODE_BIT)
187 #define DMA_TRANSFER_BITS (\
188 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
189 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
190 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
192 /*======================================================================
193 Comedi specific stuff
194 ======================================================================*/
197 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
199 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
200 /* +-5V input range gain steps */
209 /* +-10V input range gain steps */
221 /* +10V input range gain steps */
237 /* PCI4520 has two more gains (6 more entries) */
238 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
239 /* +-5V input range gain steps */
252 /* +-10V input range gain steps */
268 /* +10V input range gain steps */
287 /* Table order matches range values */
288 static const struct comedi_lrange rtd_ao_range = { 4, {
300 const char *name; /* must be first */
305 int range10Start; /* start of +-10V range */
306 int rangeUniStart; /* start of +10V range */
309 static const struct rtdBoard rtd520Boards[] = {
331 * Useful for shorthand access to the particular board structure
333 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
336 This structure is for data unique to this hardware driver.
337 This is also unique for each board in the system.
340 /* memory mapped board structures */
345 unsigned long intCount; /* interrupt count */
346 long aiCount; /* total transfer size (samples) */
347 int transCount; /* # to transfer data. 0->1/2FIFO */
348 int flags; /* flag event modes */
350 /* PCI device info */
351 struct pci_dev *pci_dev;
352 int got_regions; /* non-zero if PCI regions owned */
354 /* channel list info */
355 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
356 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
359 unsigned int aoValue[2]; /* Used for AO read back */
361 /* timer gate (when enabled) */
362 u8 utcGate[4]; /* 1 extra allows simple range check */
364 /* shadow registers affect other registers, but can't be read back */
365 /* The macros below update these on writes */
366 u16 intMask; /* interrupt mask */
367 u16 intClearMask; /* interrupt clear mask */
368 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
369 u8 dioStatus; /* could be read back (dio0Ctrl) */
372 * Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that
373 * size. After transferring, interrupt processes 1/2 FIFO and
376 s16 dma0Offset; /* current processing offset (0, 1/2) */
377 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
378 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
379 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
380 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
381 /* shadow registers */
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
393 /* Macros for accessing channel list bit array */
394 #define CHAN_ARRAY_TEST(array, index) \
395 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
396 #define CHAN_ARRAY_SET(array, index) \
397 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
398 #define CHAN_ARRAY_CLEAR(array, index) \
399 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
402 * most drivers define the following macro to make it easy to
403 * access the private structure.
405 #define devpriv ((struct rtdPrivate *)dev->private)
407 /* Macros to access registers */
409 /* Set Pacer start source select (write only) */
410 #define RtdPacerStartSource(dev, v) \
411 writel(v, devpriv->las0+LAS0_PACER_START)
413 /* Set Pacer stop source select (write only) */
414 #define RtdPacerStopSource(dev, v) \
415 writel(v, devpriv->las0+LAS0_PACER_STOP)
417 /* Set Pacer clock source select (write only) 0=external 1=internal */
418 #define RtdPacerClockSource(dev, v) \
419 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
421 /* Set sample counter source select (write only) */
422 #define RtdAdcSampleCounterSource(dev, v) \
423 writel(v, devpriv->las0+LAS0_ADC_SCNT_SRC)
425 /* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
426 #define RtdPacerTriggerMode(dev, v) \
427 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
429 /* Set About counter stop enable (write only) */
430 #define RtdAboutStopEnable(dev, v) \
431 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
433 /* Set external trigger polarity (write only) 0=positive edge, 1=negative */
434 #define RtdTriggerPolarity(dev, v) \
435 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
437 /* Start single ADC conversion */
438 #define RtdAdcStart(dev) \
439 writew(0, devpriv->las0+LAS0_ADC)
441 /* Read one ADC data value (12bit (with sign extend) as 16bit) */
442 /* Note: matches what DMA would get. Actual value >> 3 */
443 #define RtdAdcFifoGet(dev) \
444 readw(devpriv->las1+LAS1_ADC_FIFO)
446 /* Read two ADC data values (DOESN'T WORK) */
447 #define RtdAdcFifoGet2(dev) \
448 readl(devpriv->las1+LAS1_ADC_FIFO)
451 #define RtdFifoStatus(dev) \
452 readl(devpriv->las0+LAS0_ADC)
454 /* pacer start/stop read=start, write=stop*/
455 #define RtdPacerStart(dev) \
456 readl(devpriv->las0+LAS0_PACER)
457 #define RtdPacerStop(dev) \
458 writel(0, devpriv->las0+LAS0_PACER)
460 /* Interrupt status */
461 #define RtdInterruptStatus(dev) \
462 readw(devpriv->las0+LAS0_IT)
465 #define RtdInterruptMask(dev, v) \
466 writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
468 /* Interrupt status clear (only bits set in mask) */
469 #define RtdInterruptClear(dev) \
470 readw(devpriv->las0+LAS0_CLEAR)
472 /* Interrupt clear mask */
473 #define RtdInterruptClearMask(dev, v) \
474 writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
476 /* Interrupt overrun status */
477 #define RtdInterruptOverrunStatus(dev) \
478 readl(devpriv->las0+LAS0_OVERRUN)
480 /* Interrupt overrun clear */
481 #define RtdInterruptOverrunClear(dev) \
482 writel(0, devpriv->las0+LAS0_OVERRUN)
484 /* Pacer counter, 24bit */
485 #define RtdPacerCount(dev) \
486 readl(devpriv->las0+LAS0_PCLK)
487 #define RtdPacerCounter(dev, v) \
488 writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
490 /* Burst counter, 10bit */
491 #define RtdBurstCount(dev) \
492 readl(devpriv->las0+LAS0_BCLK)
493 #define RtdBurstCounter(dev, v) \
494 writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
496 /* Delay counter, 16bit */
497 #define RtdDelayCount(dev) \
498 readl(devpriv->las0+LAS0_DCLK)
499 #define RtdDelayCounter(dev, v) \
500 writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
502 /* About counter, 16bit */
503 #define RtdAboutCount(dev) \
504 readl(devpriv->las0+LAS0_ACNT)
505 #define RtdAboutCounter(dev, v) \
506 writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
508 /* ADC sample counter, 10bit */
509 #define RtdAdcSampleCount(dev) \
510 readl(devpriv->las0+LAS0_ADC_SCNT)
511 #define RtdAdcSampleCounter(dev, v) \
512 writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
514 /* User Timer/Counter (8254) */
515 #define RtdUtcCounterGet(dev, n) \
516 readb(devpriv->las0 \
517 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
519 #define RtdUtcCounterPut(dev, n, v) \
520 writeb((v) & 0xff, devpriv->las0 \
521 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
523 /* Set UTC (8254) control byte */
524 #define RtdUtcCtrlPut(dev, n, v) \
525 writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
526 devpriv->las0 + LAS0_UTC_CTRL)
528 /* Set UTCn clock source (write only) */
529 #define RtdUtcClockSource(dev, n, v) \
530 writew(v, devpriv->las0 \
531 + ((n <= 0) ? LAS0_UTC0_CLOCK : \
532 ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
534 /* Set UTCn gate source (write only) */
535 #define RtdUtcGateSource(dev, n, v) \
536 writew(v, devpriv->las0 \
537 + ((n <= 0) ? LAS0_UTC0_GATE : \
538 ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
540 /* User output N source select (write only) */
541 #define RtdUsrOutSource(dev, n, v) \
542 writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : \
546 #define RtdDio0Read(dev) \
547 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
548 #define RtdDio0Write(dev, v) \
549 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
551 #define RtdDio1Read(dev) \
552 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
553 #define RtdDio1Write(dev, v) \
554 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
556 #define RtdDioStatusRead(dev) \
557 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
558 #define RtdDioStatusWrite(dev, v) \
559 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
561 #define RtdDio0CtrlRead(dev) \
562 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
563 #define RtdDio0CtrlWrite(dev, v) \
564 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
566 /* Digital to Analog converter */
567 /* Write one data value (sign + 12bit + marker bits) */
568 /* Note: matches what DMA would put. Actual value << 3 */
569 #define RtdDacFifoPut(dev, n, v) \
570 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
573 /* Start single DAC conversion */
574 #define RtdDacUpdate(dev, n) \
575 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
577 /* Start single DAC conversion on both DACs */
578 #define RtdDacBothUpdate(dev) \
579 writew(0, devpriv->las0+LAS0_DAC)
581 /* Set DAC output type and range */
582 #define RtdDacRange(dev, n, v) \
583 writew((v) & 7, devpriv->las0 \
584 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
587 #define RtdDacClearFifo(dev, n) \
588 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
591 /* Set source for DMA 0 (write only, shadow?) */
592 #define RtdDma0Source(dev, n) \
593 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
595 /* Set source for DMA 1 (write only, shadow?) */
596 #define RtdDma1Source(dev, n) \
597 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
599 /* Reset board state for DMA 0 */
600 #define RtdDma0Reset(dev) \
601 writel(0, devpriv->las0+LAS0_DMA0_RESET)
603 /* Reset board state for DMA 1 */
604 #define RtdDma1Reset(dev) \
605 writel(0, devpriv->las0+LAS0_DMA1_SRC)
607 /* PLX9080 interrupt mask and status */
608 #define RtdPlxInterruptRead(dev) \
609 readl(devpriv->lcfg+LCFG_ITCSR)
610 #define RtdPlxInterruptWrite(dev, v) \
611 writel(v, devpriv->lcfg+LCFG_ITCSR)
613 /* Set mode for DMA 0 */
614 #define RtdDma0Mode(dev, m) \
615 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
617 /* Set PCI address for DMA 0 */
618 #define RtdDma0PciAddr(dev, a) \
619 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
621 /* Set local address for DMA 0 */
622 #define RtdDma0LocalAddr(dev, a) \
623 writel((a), devpriv->lcfg+LCFG_DMALADR0)
625 /* Set byte count for DMA 0 */
626 #define RtdDma0Count(dev, c) \
627 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
629 /* Set next descriptor for DMA 0 */
630 #define RtdDma0Next(dev, a) \
631 writel((a), devpriv->lcfg+LCFG_DMADPR0)
633 /* Set mode for DMA 1 */
634 #define RtdDma1Mode(dev, m) \
635 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
637 /* Set PCI address for DMA 1 */
638 #define RtdDma1PciAddr(dev, a) \
639 writel((a), devpriv->lcfg+LCFG_DMAADR1)
641 /* Set local address for DMA 1 */
642 #define RtdDma1LocalAddr(dev, a) \
643 writel((a), devpriv->lcfg+LCFG_DMALADR1)
645 /* Set byte count for DMA 1 */
646 #define RtdDma1Count(dev, c) \
647 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
649 /* Set next descriptor for DMA 1 */
650 #define RtdDma1Next(dev, a) \
651 writel((a), devpriv->lcfg+LCFG_DMADPR1)
653 /* Set control for DMA 0 (write only, shadow?) */
654 #define RtdDma0Control(dev, n) \
655 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
657 /* Get status for DMA 0 */
658 #define RtdDma0Status(dev) \
659 readb(devpriv->lcfg+LCFG_DMACSR0)
661 /* Set control for DMA 1 (write only, shadow?) */
662 #define RtdDma1Control(dev, n) \
663 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
665 /* Get status for DMA 1 */
666 #define RtdDma1Status(dev) \
667 readb(devpriv->lcfg+LCFG_DMACSR1)
670 Given a desired period and the clock period (both in ns),
671 return the proper counter value (divider-1).
672 Sets the original period to be the true value.
673 Note: you have to check if the value is larger than the counter range!
675 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
676 int round_mode, int base)
677 { /* clock period (in ns) */
680 switch (round_mode) {
681 case TRIG_ROUND_NEAREST:
683 divider = (*nanosec + base / 2) / base;
685 case TRIG_ROUND_DOWN:
686 divider = (*nanosec) / base;
689 divider = (*nanosec + base - 1) / base;
693 divider = 2; /* min is divide by 2 */
695 /* Note: we don't check for max, because different timers
696 have different ranges */
698 *nanosec = base * divider;
699 return divider - 1; /* countdown is divisor+1 */
703 Given a desired period (in ns),
704 return the proper counter value (divider-1) for the internal clock.
705 Sets the original period to be the true value.
707 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
709 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
713 Convert a single comedi channel-gain entry to a RTD520 table entry
715 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
716 unsigned int comediChan, int chanIndex)
717 { /* index in channel list */
718 unsigned int chan, range, aref;
719 unsigned short r = 0;
721 chan = CR_CHAN(comediChan);
722 range = CR_RANGE(comediChan);
723 aref = CR_AREF(comediChan);
727 /* Note: we also setup the channel list bipolar flag array */
728 if (range < thisboard->range10Start) { /* first batch are +-5 */
729 r |= 0x000; /* +-5 range */
730 r |= (range & 0x7) << 4; /* gain */
731 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
732 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
733 r |= 0x100; /* +-10 range */
735 r |= ((range - thisboard->range10Start) & 0x7) << 4;
736 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
737 } else { /* last batch is +10 */
738 r |= 0x200; /* +10 range */
740 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
741 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
745 case AREF_GROUND: /* on-board ground */
749 r |= 0x80; /* ref external analog common */
753 r |= 0x400; /* differential inputs */
756 case AREF_OTHER: /* ??? */
759 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
760 chan, range, aref, r); */
765 Setup the channel-gain table from a comedi list
767 static void rtd_load_channelgain_list(struct comedi_device *dev,
768 unsigned int n_chan, unsigned int *list)
770 if (n_chan > 1) { /* setup channel gain table */
773 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
774 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
775 for (ii = 0; ii < n_chan; ii++) {
776 writel(rtdConvertChanGain(dev, list[ii], ii),
777 devpriv->las0 + LAS0_CGT_WRITE);
779 } else { /* just use the channel gain latch */
780 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
781 writel(rtdConvertChanGain(dev, list[0], 0),
782 devpriv->las0 + LAS0_CGL_WRITE);
786 /* determine fifo size by doing adc conversions until the fifo half
787 empty status flag clears */
788 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
790 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
792 static const unsigned limit = 0x2000;
793 unsigned fifo_size = 0;
795 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
796 rtd_load_channelgain_list(dev, 1, &chanspec);
797 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
798 /* convert samples */
799 for (i = 0; i < limit; ++i) {
800 unsigned fifo_status;
801 /* trigger conversion */
804 fifo_status = RtdFifoStatus(dev);
805 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
811 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
815 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
816 if (fifo_size != 0x400 && fifo_size != 0x2000) {
818 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
819 DRV_NAME, fifo_size);
826 "instructions" read/write data in "one-shot" or "software-triggered"
827 mode (simplest case).
828 This doesn't use interrupts.
830 Note, we don't do any settling delays. Use a instruction list to
831 select, delay, then read.
833 static int rtd_ai_rinsn(struct comedi_device *dev,
834 struct comedi_subdevice *s, struct comedi_insn *insn,
840 /* clear any old fifo data */
841 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
843 /* write channel to multiplexer and clear channel gain table */
844 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
846 /* set conversion source */
847 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
849 /* convert n samples */
850 for (n = 0; n < insn->n; n++) {
852 /* trigger conversion */
855 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
856 stat = RtdFifoStatus(dev);
857 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
861 if (ii >= RTD_ADC_TIMEOUT) {
863 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
869 d = RtdAdcFifoGet(dev); /* get 2s comp value */
870 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
871 d = d >> 3; /* low 3 bits are marker lines */
872 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
873 /* convert to comedi unsigned data */
879 /* return the number of samples read/written */
884 Get what we know is there.... Fast!
885 This uses 1/2 the bus cycles of read_dregs (below).
887 The manual claims that we can do a lword read, but it doesn't work here.
889 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
894 for (ii = 0; ii < count; ii++) {
898 if (0 == devpriv->aiCount) { /* done */
899 d = RtdAdcFifoGet(dev); /* Read N and discard */
903 if (0 == (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY)) { /* DEBUG */
904 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
909 d = RtdAdcFifoGet(dev); /* get 2s comp value */
911 d = d >> 3; /* low 3 bits are marker lines */
912 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
913 /* convert to comedi unsigned data */
918 if (!comedi_buf_put(s->async, sample))
921 if (devpriv->aiCount > 0) /* < 0, means read forever */
928 unknown amout of data is waiting in fifo.
930 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
932 while (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
934 s16 d = RtdAdcFifoGet(dev); /* get 2s comp value */
936 if (0 == devpriv->aiCount) { /* done */
937 continue; /* read rest */
940 d = d >> 3; /* low 3 bits are marker lines */
941 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
942 /* convert to comedi unsigned data */
947 if (!comedi_buf_put(s->async, sample))
950 if (devpriv->aiCount > 0) /* < 0, means read forever */
958 Terminate a DMA transfer and wait for everything to quiet down
960 void abort_dma(struct comedi_device *dev, unsigned int channel)
961 { /* DMA channel 0, 1 */
962 unsigned long dma_cs_addr; /* the control/status register */
965 /* unsigned long flags; */
967 dma_cs_addr = (unsigned long)devpriv->lcfg
968 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
970 /* spinlock for plx dma control/status reg */
971 /* spin_lock_irqsave( &dev->spinlock, flags ); */
973 /* abort dma transfer if necessary */
974 status = readb(dma_cs_addr);
975 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
976 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
981 /* wait to make sure done bit is zero (needed?) */
982 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
984 status = readb(dma_cs_addr);
986 if (status & PLX_DMA_DONE_BIT) {
987 printk("rtd520: Timeout waiting for dma %i done clear\n",
992 /* disable channel (required) */
993 writeb(0, dma_cs_addr);
994 udelay(1); /* needed?? */
995 /* set abort bit for channel */
996 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
998 /* wait for dma done bit to be set */
999 status = readb(dma_cs_addr);
1001 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
1002 status = readb(dma_cs_addr);
1005 if ((status & PLX_DMA_DONE_BIT) == 0) {
1006 printk("rtd520: Timeout waiting for dma %i done set\n",
1011 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
1015 Process what is in the DMA transfer buffer and pass to comedi
1016 Note: this is not re-entrant
1018 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
1023 if (devpriv->aiCount == 0) /* transfer already complete */
1026 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1027 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
1030 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
1031 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
1033 sample = *dp >> 3; /* low 3 bits are marker lines */
1035 *dp++ = sample; /* put processed value back */
1037 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
1038 s->async->cur_chan = 0;
1040 ++ii; /* number ready to transfer */
1041 if (devpriv->aiCount > 0) { /* < 0, means read forever */
1042 if (--devpriv->aiCount == 0) { /* done */
1043 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
1049 /* now pass the whole array to the comedi buffer */
1050 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1051 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
1052 if (n < (ii * sizeof(s16))) { /* any residual is an error */
1053 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
1054 ii - (n / sizeof(s16)));
1055 s->async->events |= COMEDI_CB_ERROR;
1058 comedi_buf_memcpy_to(s->async, 0, dp, n);
1059 comedi_buf_write_free(s->async, n);
1062 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
1064 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1066 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
1067 devpriv->dma0Offset = 0;
1071 #endif /* USE_DMA */
1074 Handle all rtd520 interrupts.
1075 Runs atomically and is never re-entered.
1076 This is a "slow handler"; other interrupts may be active.
1077 The data conversion may someday happen in a "bottom half".
1079 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
1081 { /* our data *//* cpu context (ignored) */
1082 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
1085 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
1090 devpriv->intCount++; /* DEBUG statistics */
1092 fifoStatus = RtdFifoStatus(dev);
1093 /* check for FIFO full, this automatically halts the ADC! */
1094 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
1095 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1099 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
1100 u32 istatus = RtdPlxInterruptRead(dev);
1102 if (istatus & ICS_DMA0_A) {
1103 if (ai_process_dma(dev, s) < 0) {
1105 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
1108 (devpriv->dma0Control &
1110 | PLX_CLEAR_DMA_INTR_BIT);
1114 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
1115 devpriv->aiCount, istatus); */
1118 dma0Control & ~PLX_DMA_START_BIT)
1119 | PLX_CLEAR_DMA_INTR_BIT);
1120 if (0 == devpriv->aiCount) { /* counted down */
1121 DPRINTK("rtd520: Samples Done (DMA).\n");
1124 comedi_event(dev, s);
1126 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
1129 /* Fall through and check for other interrupt sources */
1130 #endif /* USE_DMA */
1132 status = RtdInterruptStatus(dev);
1133 /* if interrupt was not caused by our board, or handled above */
1137 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1138 /* since the priority interrupt controller may have queued a sample
1139 counter interrupt, even though we have already finished,
1140 we must handle the possibility that there is no data here */
1141 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1142 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1143 (fifoStatus ^ 0x6666) & 0x7777); */
1144 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1146 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1150 if (0 == devpriv->aiCount) { /* counted down */
1151 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1154 comedi_event(dev, s);
1155 } else if (devpriv->transCount > 0) { /* read often */
1156 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1157 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1158 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1159 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1161 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1165 if (0 == devpriv->aiCount) { /* counted down */
1167 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1168 (fifoStatus ^ 0x6666) & 0x7777);
1171 comedi_event(dev, s);
1173 } else { /* wait for 1/2 FIFO (old) */
1175 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1176 (fifoStatus ^ 0x6666) & 0x7777);
1179 DPRINTK("rtd520: unknown interrupt source!\n");
1182 if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
1184 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1185 devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
1189 /* clear the interrupt */
1190 RtdInterruptClearMask(dev, status);
1191 RtdInterruptClear(dev);
1195 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1196 s->async->events |= COMEDI_CB_ERROR;
1197 devpriv->aiCount = 0; /* stop and don't transfer any more */
1198 /* fall into transferDone */
1201 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1202 RtdPacerStop(dev); /* Stop PACER */
1203 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1204 RtdInterruptMask(dev, 0); /* mask out SAMPLE */
1206 if (devpriv->flags & DMA0_ACTIVE) {
1207 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1208 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1210 devpriv->flags &= ~DMA0_ACTIVE;
1211 /* if Using DMA, then we should have read everything by now */
1212 if (devpriv->aiCount > 0) {
1213 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1217 #endif /* USE_DMA */
1219 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1220 fifoStatus = RtdFifoStatus(dev);
1221 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1222 ai_read_dregs(dev, s); /* read anything left in FIFO */
1225 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1226 comedi_event(dev, s);
1228 /* clear the interrupt */
1229 status = RtdInterruptStatus(dev);
1230 RtdInterruptClearMask(dev, status);
1231 RtdInterruptClear(dev);
1233 fifoStatus = RtdFifoStatus(dev); /* DEBUG */
1235 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1236 devpriv->intCount, status,
1237 0xffff & RtdInterruptOverrunStatus(dev));
1244 return the number of samples available
1246 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1248 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1249 /* Not sure what to do if DMA is active */
1250 return s->async->buf_write_count - s->async->buf_read_count;
1255 cmdtest tests a particular command to see if it is valid.
1256 Using the cmdtest ioctl, a user can create a valid cmd
1257 and then have it executed by the cmd ioctl (asyncronously).
1259 cmdtest returns 1,2,3,4 or 0, depending on which tests
1263 static int rtd_ai_cmdtest(struct comedi_device *dev,
1264 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1269 /* step 1: make sure trigger sources are trivially valid */
1271 tmp = cmd->start_src;
1272 cmd->start_src &= TRIG_NOW;
1273 if (!cmd->start_src || tmp != cmd->start_src)
1276 tmp = cmd->scan_begin_src;
1277 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1278 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1282 tmp = cmd->convert_src;
1283 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1284 if (!cmd->convert_src || tmp != cmd->convert_src)
1288 tmp = cmd->scan_end_src;
1289 cmd->scan_end_src &= TRIG_COUNT;
1290 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1294 tmp = cmd->stop_src;
1295 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1296 if (!cmd->stop_src || tmp != cmd->stop_src)
1303 /* step 2: make sure trigger sources are unique
1304 and mutually compatible */
1305 /* note that mutual compatibility is not an issue here */
1306 if (cmd->scan_begin_src != TRIG_TIMER &&
1307 cmd->scan_begin_src != TRIG_EXT) {
1310 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1313 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1319 /* step 3: make sure arguments are trivially compatible */
1321 if (cmd->start_arg != 0) {
1326 if (cmd->scan_begin_src == TRIG_TIMER) {
1327 /* Note: these are time periods, not actual rates */
1328 if (1 == cmd->chanlist_len) { /* no scanning */
1329 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1330 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1331 rtd_ns_to_timer(&cmd->scan_begin_arg,
1335 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1336 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1337 rtd_ns_to_timer(&cmd->scan_begin_arg,
1342 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1343 cmd->scan_begin_arg = RTD_MAX_SPEED;
1344 rtd_ns_to_timer(&cmd->scan_begin_arg,
1348 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1349 cmd->scan_begin_arg = RTD_MIN_SPEED;
1350 rtd_ns_to_timer(&cmd->scan_begin_arg,
1356 /* external trigger */
1357 /* should be level/edge, hi/lo specification here */
1358 /* should specify multiple external triggers */
1359 if (cmd->scan_begin_arg > 9) {
1360 cmd->scan_begin_arg = 9;
1364 if (cmd->convert_src == TRIG_TIMER) {
1365 if (1 == cmd->chanlist_len) { /* no scanning */
1366 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1367 cmd->convert_arg = RTD_MAX_SPEED_1;
1368 rtd_ns_to_timer(&cmd->convert_arg,
1372 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1373 cmd->convert_arg = RTD_MIN_SPEED_1;
1374 rtd_ns_to_timer(&cmd->convert_arg,
1379 if (cmd->convert_arg < RTD_MAX_SPEED) {
1380 cmd->convert_arg = RTD_MAX_SPEED;
1381 rtd_ns_to_timer(&cmd->convert_arg,
1385 if (cmd->convert_arg > RTD_MIN_SPEED) {
1386 cmd->convert_arg = RTD_MIN_SPEED;
1387 rtd_ns_to_timer(&cmd->convert_arg,
1393 /* external trigger */
1395 if (cmd->convert_arg > 9) {
1396 cmd->convert_arg = 9;
1402 if (cmd->scan_end_arg != cmd->chanlist_len) {
1403 cmd->scan_end_arg = cmd->chanlist_len;
1407 if (cmd->stop_src == TRIG_COUNT) {
1408 /* TODO check for rounding error due to counter wrap */
1412 if (cmd->stop_arg != 0) {
1422 /* step 4: fix up any arguments */
1424 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1425 cmd->chanlist_len = RTD_MAX_CHANLIST;
1428 if (cmd->scan_begin_src == TRIG_TIMER) {
1429 tmp = cmd->scan_begin_arg;
1430 rtd_ns_to_timer(&cmd->scan_begin_arg,
1431 cmd->flags & TRIG_ROUND_MASK);
1432 if (tmp != cmd->scan_begin_arg)
1436 if (cmd->convert_src == TRIG_TIMER) {
1437 tmp = cmd->convert_arg;
1438 rtd_ns_to_timer(&cmd->convert_arg,
1439 cmd->flags & TRIG_ROUND_MASK);
1440 if (tmp != cmd->convert_arg)
1443 if (cmd->scan_begin_src == TRIG_TIMER
1444 && (cmd->scan_begin_arg
1445 < (cmd->convert_arg * cmd->scan_end_arg))) {
1446 cmd->scan_begin_arg =
1447 cmd->convert_arg * cmd->scan_end_arg;
1459 Execute a analog in command with many possible triggering options.
1460 The data get stored in the async structure of the subdevice.
1461 This is usually done by an interrupt handler.
1462 Userland gets to the data using read calls.
1464 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1466 struct comedi_cmd *cmd = &s->async->cmd;
1469 /* stop anything currently running */
1470 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1471 RtdPacerStop(dev); /* make sure PACER is stopped */
1472 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1473 RtdInterruptMask(dev, 0);
1475 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1476 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1477 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1479 devpriv->flags &= ~DMA0_ACTIVE;
1480 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1481 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1484 RtdDma0Reset(dev); /* reset onboard state */
1485 #endif /* USE_DMA */
1486 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1487 RtdInterruptOverrunClear(dev);
1488 devpriv->intCount = 0;
1490 if (!dev->irq) { /* we need interrupts for this */
1491 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1495 /* start configuration */
1496 /* load channel list and reset CGT */
1497 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1499 /* setup the common case and override if needed */
1500 if (cmd->chanlist_len > 1) {
1501 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1502 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1503 writel(1, devpriv->las0 + LAS0_BURST_START);
1504 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
1505 } else { /* single channel */
1506 /*DPRINTK ("rtd520: single channel setup\n"); */
1507 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1508 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
1510 RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
1512 if (TRIG_TIMER == cmd->scan_begin_src) {
1513 /* scan_begin_arg is in nanoseconds */
1514 /* find out how many samples to wait before transferring */
1515 if (cmd->flags & TRIG_WAKE_EOS) {
1516 /* this may generate un-sustainable interrupt rates */
1517 /* the application is responsible for doing the right thing */
1518 devpriv->transCount = cmd->chanlist_len;
1519 devpriv->flags |= SEND_EOS;
1521 /* arrange to transfer data periodically */
1524 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1525 cmd->scan_begin_arg;
1526 if (devpriv->transCount < cmd->chanlist_len) {
1527 /* transfer after each scan (and avoid 0) */
1528 devpriv->transCount = cmd->chanlist_len;
1529 } else { /* make a multiple of scan length */
1530 devpriv->transCount =
1531 (devpriv->transCount +
1532 cmd->chanlist_len - 1)
1533 / cmd->chanlist_len;
1534 devpriv->transCount *= cmd->chanlist_len;
1536 devpriv->flags |= SEND_EOS;
1538 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
1539 /* out of counter range, use 1/2 fifo instead */
1540 devpriv->transCount = 0;
1541 devpriv->flags &= ~SEND_EOS;
1543 /* interrupt for each transfer */
1544 RtdAboutCounter(dev, devpriv->transCount - 1);
1548 ("rtd520: scanLen=%d transferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
1549 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
1550 cmd->scan_begin_arg, devpriv->flags);
1551 } else { /* unknown timing, just use 1/2 FIFO */
1552 devpriv->transCount = 0;
1553 devpriv->flags &= ~SEND_EOS;
1555 RtdPacerClockSource(dev, 1); /* use INTERNAL 8Mhz clock source */
1556 RtdAboutStopEnable(dev, 1); /* just interrupt, dont stop */
1558 /* BUG??? these look like enumerated values, but they are bit fields */
1560 /* First, setup when to stop */
1561 switch (cmd->stop_src) {
1562 case TRIG_COUNT: /* stop after N scans */
1563 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
1564 if ((devpriv->transCount > 0)
1565 && (devpriv->transCount > devpriv->aiCount)) {
1566 devpriv->transCount = devpriv->aiCount;
1570 case TRIG_NONE: /* stop when cancel is called */
1571 devpriv->aiCount = -1; /* read forever */
1575 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
1580 switch (cmd->scan_begin_src) {
1581 case TRIG_TIMER: /* periodic scanning */
1582 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1583 TRIG_ROUND_NEAREST);
1584 /* set PACER clock */
1585 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
1586 RtdPacerCounter(dev, timer);
1591 RtdPacerStartSource(dev, 1); /* EXTERNALy trigger pacer */
1595 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
1596 cmd->scan_begin_src);
1599 /* Sample timing within a scan */
1600 switch (cmd->convert_src) {
1601 case TRIG_TIMER: /* periodic */
1602 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
1603 timer = rtd_ns_to_timer(&cmd->convert_arg,
1604 TRIG_ROUND_NEAREST);
1605 /* setup BURST clock */
1606 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
1607 RtdBurstCounter(dev, timer);
1612 case TRIG_EXT: /* external */
1613 writel(2, devpriv->las0 + LAS0_BURST_START);
1617 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
1620 /* end configuration */
1622 /* This doesn't seem to work. There is no way to clear an interrupt
1623 that the priority controller has queued! */
1624 RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
1625 RtdInterruptClear(dev);
1627 /* TODO: allow multiple interrupt sources */
1628 if (devpriv->transCount > 0) { /* transfer every N samples */
1629 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1630 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
1631 } else { /* 1/2 FIFO transfers */
1633 devpriv->flags |= DMA0_ACTIVE;
1635 /* point to first transfer in ring */
1636 devpriv->dma0Offset = 0;
1637 RtdDma0Mode(dev, DMA_MODE_BITS);
1638 RtdDma0Next(dev, /* point to first block */
1639 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
1640 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1642 RtdPlxInterruptWrite(dev, /* enable interrupt */
1643 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
1644 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
1645 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
1646 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
1647 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
1648 RtdPlxInterruptRead(dev), devpriv->intMask);
1650 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1651 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
1652 #endif /* USE_DMA */
1655 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1656 /* BUG? it seems like things are running before the "start" */
1657 RtdPacerStart(dev); /* Start PACER */
1662 Stop a running data acquisition.
1664 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1668 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1669 RtdPacerStop(dev); /* Stop PACER */
1670 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1671 RtdInterruptMask(dev, 0);
1672 devpriv->aiCount = 0; /* stop and don't transfer any more */
1674 if (devpriv->flags & DMA0_ACTIVE) {
1675 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1676 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1678 devpriv->flags &= ~DMA0_ACTIVE;
1680 #endif /* USE_DMA */
1681 status = RtdInterruptStatus(dev);
1683 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
1684 devpriv->intCount, status,
1685 0xffff & RtdInterruptOverrunStatus(dev));
1690 Output one (or more) analog values to a single port as fast as possible.
1692 static int rtd_ao_winsn(struct comedi_device *dev,
1693 struct comedi_subdevice *s, struct comedi_insn *insn,
1697 int chan = CR_CHAN(insn->chanspec);
1698 int range = CR_RANGE(insn->chanspec);
1700 /* Configure the output range (table index matches the range values) */
1701 RtdDacRange(dev, chan, range);
1703 /* Writing a list of values to an AO channel is probably not
1704 * very useful, but that's how the interface is defined. */
1705 for (i = 0; i < insn->n; ++i) {
1706 int val = data[i] << 3;
1707 int stat = 0; /* initialize to avoid bogus warning */
1710 /* VERIFY: comedi range and offset conversions */
1712 if ((range > 1) /* bipolar */
1713 && (data[i] < 2048)) {
1714 /* offset and sign extend */
1715 val = (((int)data[i]) - 2048) << 3;
1716 } else { /* unipolor */
1721 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
1722 chan, range, data[i], val);
1724 /* a typical programming sequence */
1725 RtdDacFifoPut(dev, chan, val); /* put the value in */
1726 RtdDacUpdate(dev, chan); /* trigger the conversion */
1728 devpriv->aoValue[chan] = data[i]; /* save for read back */
1730 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1731 stat = RtdFifoStatus(dev);
1732 /* 1 -> not empty */
1733 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1738 if (ii >= RTD_DAC_TIMEOUT) {
1740 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
1746 /* return the number of samples read/written */
1750 /* AO subdevices should have a read insn as well as a write insn.
1751 * Usually this means copying a value stored in devpriv. */
1752 static int rtd_ao_rinsn(struct comedi_device *dev,
1753 struct comedi_subdevice *s, struct comedi_insn *insn,
1757 int chan = CR_CHAN(insn->chanspec);
1759 for (i = 0; i < insn->n; i++)
1760 data[i] = devpriv->aoValue[chan];
1767 Write a masked set of bits and the read back the port.
1768 We track what the bits should be (i.e. we don't read the port first).
1770 DIO devices are slightly special. Although it is possible to
1771 * implement the insn_read/insn_write interface, it is much more
1772 * useful to applications if you implement the insn_bits interface.
1773 * This allows packed reading/writing of the DIO channels. The
1774 * comedi core can convert between insn_bits and insn_read/write
1776 static int rtd_dio_insn_bits(struct comedi_device *dev,
1777 struct comedi_subdevice *s,
1778 struct comedi_insn *insn, unsigned int *data)
1780 /* The insn data is a mask in data[0] and the new data
1781 * in data[1], each channel cooresponding to a bit. */
1783 s->state &= ~data[0];
1784 s->state |= data[0] & data[1];
1786 /* Write out the new digital output lines */
1787 RtdDio0Write(dev, s->state);
1789 /* on return, data[1] contains the value of the digital
1791 data[1] = RtdDio0Read(dev);
1793 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
1799 Configure one bit on a IO port as Input or Output (hence the name :-).
1801 static int rtd_dio_insn_config(struct comedi_device *dev,
1802 struct comedi_subdevice *s,
1803 struct comedi_insn *insn, unsigned int *data)
1805 int chan = CR_CHAN(insn->chanspec);
1807 /* The input or output configuration of each digital line is
1808 * configured by a special insn_config instruction. chanspec
1809 * contains the channel to be changed, and data[0] contains the
1810 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1812 case INSN_CONFIG_DIO_OUTPUT:
1813 s->io_bits |= 1 << chan; /* 1 means Out */
1815 case INSN_CONFIG_DIO_INPUT:
1816 s->io_bits &= ~(1 << chan);
1818 case INSN_CONFIG_DIO_QUERY:
1820 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1827 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
1828 /* TODO support digital match interrupts and strobes */
1829 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
1830 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
1831 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
1833 /* port1 can only be all input or all output */
1835 /* there are also 2 user input lines and 2 user output lines */
1840 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1841 { /* board name and options flags */
1842 struct comedi_subdevice *s;
1843 struct pci_dev *pcidev;
1845 resource_size_t physLas0; /* configuration */
1846 resource_size_t physLas1; /* data area */
1847 resource_size_t physLcfg; /* PLX9080 */
1852 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
1854 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
1855 /* You can set this a load time: modprobe comedi comedi_debug=1 */
1856 if (0 == comedi_debug) /* force DMA debug printks */
1861 * Allocate the private structure area. alloc_private() is a
1862 * convenient macro defined in comedidev.h.
1864 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
1868 * Probe the device to determine what device in the series it is.
1870 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
1872 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
1875 if (it->options[0] || it->options[1]) {
1876 if (pcidev->bus->number != it->options[0]
1877 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
1881 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
1882 if (pcidev->device == rtd520Boards[i].device_id) {
1883 dev->board_ptr = &rtd520Boards[i];
1888 break; /* found one */
1891 if (it->options[0] && it->options[1]) {
1892 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
1893 it->options[0], it->options[1]);
1895 printk(KERN_INFO "No RTD card found.\n");
1899 devpriv->pci_dev = pcidev;
1900 dev->board_name = thisboard->name;
1902 ret = comedi_pci_enable(pcidev, DRV_NAME);
1904 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
1907 devpriv->got_regions = 1;
1910 * Initialize base addresses
1912 /* Get the physical address from PCI config */
1913 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
1914 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
1915 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
1916 /* Now have the kernel map this into memory */
1917 /* ASSUME page aligned */
1918 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
1919 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
1920 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
1922 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1926 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
1927 (unsigned long long)physLas0, (unsigned long long)physLas1,
1928 (unsigned long long)physLcfg);
1929 { /* The RTD driver does this */
1930 unsigned char pci_latency;
1932 /*uint32_t epld_version; */
1934 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
1936 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
1938 pci_read_config_byte(devpriv->pci_dev,
1939 PCI_LATENCY_TIMER, &pci_latency);
1940 if (pci_latency < 32) {
1941 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
1942 dev->board_name, pci_latency, 32);
1943 pci_write_config_byte(devpriv->pci_dev,
1944 PCI_LATENCY_TIMER, 32);
1946 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
1950 * Undocumented EPLD version (doesn't match RTD driver results)
1952 /*DPRINTK ("rtd520: Reading epld from %p\n",
1954 epld_version = readl (devpriv->las0+0);
1955 if ((epld_version & 0xF0) >> 4 == 0x0F) {
1956 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
1958 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
1962 /* Show board configuration */
1963 printk(KERN_INFO "%s:", dev->board_name);
1965 ret = comedi_alloc_subdevices(dev, 4);
1969 s = dev->subdevices + 0;
1970 dev->read_subdev = s;
1971 /* analog input subdevice */
1972 s->type = COMEDI_SUBD_AI;
1974 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
1975 s->n_chan = thisboard->aiChans;
1976 s->maxdata = (1 << thisboard->aiBits) - 1;
1977 if (thisboard->aiMaxGain <= 32)
1978 s->range_table = &rtd_ai_7520_range;
1980 s->range_table = &rtd_ai_4520_range;
1982 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
1983 s->insn_read = rtd_ai_rinsn;
1984 s->do_cmd = rtd_ai_cmd;
1985 s->do_cmdtest = rtd_ai_cmdtest;
1986 s->cancel = rtd_ai_cancel;
1987 /* s->poll = rtd_ai_poll; *//* not ready yet */
1989 s = dev->subdevices + 1;
1990 /* analog output subdevice */
1991 s->type = COMEDI_SUBD_AO;
1992 s->subdev_flags = SDF_WRITABLE;
1994 s->maxdata = (1 << thisboard->aiBits) - 1;
1995 s->range_table = &rtd_ao_range;
1996 s->insn_write = rtd_ao_winsn;
1997 s->insn_read = rtd_ao_rinsn;
1999 s = dev->subdevices + 2;
2000 /* digital i/o subdevice */
2001 s->type = COMEDI_SUBD_DIO;
2002 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
2003 /* we only support port 0 right now. Ignoring port 1 and user IO */
2006 s->range_table = &range_digital;
2007 s->insn_bits = rtd_dio_insn_bits;
2008 s->insn_config = rtd_dio_insn_config;
2010 /* timer/counter subdevices (not currently supported) */
2011 s = dev->subdevices + 3;
2012 s->type = COMEDI_SUBD_COUNTER;
2013 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
2015 s->maxdata = 0xffff;
2017 /* initialize board, per RTD spec */
2018 /* also, initialize shadow registers */
2019 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
2020 udelay(100); /* needed? */
2021 RtdPlxInterruptWrite(dev, 0);
2022 RtdInterruptMask(dev, 0); /* and sets shadow */
2023 RtdInterruptClearMask(dev, ~0); /* and sets shadow */
2024 RtdInterruptClear(dev); /* clears bits set by mask */
2025 RtdInterruptOverrunClear(dev);
2026 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
2027 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
2028 RtdDacClearFifo(dev, 0);
2029 RtdDacClearFifo(dev, 1);
2030 /* clear digital IO fifo */
2031 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
2032 RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
2033 RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
2034 RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
2035 RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
2036 /* TODO: set user out source ??? */
2038 /* check if our interrupt is available and get it */
2039 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
2040 IRQF_SHARED, DRV_NAME, dev);
2043 printk("Could not get interrupt! (%u)\n",
2044 devpriv->pci_dev->irq);
2047 dev->irq = devpriv->pci_dev->irq;
2048 printk(KERN_INFO "( irq=%u )", dev->irq);
2050 ret = rtd520_probe_fifo_depth(dev);
2054 devpriv->fifoLen = ret;
2055 printk("( fifoLen=%d )", devpriv->fifoLen);
2059 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
2061 * The PLX9080 has 2 DMA controllers, but there could be
2062 * 4 sources: ADC, digital, DAC1, and DAC2. Since only the
2063 * ADC supports cmd mode right now, this isn't an issue (yet)
2065 devpriv->dma0Offset = 0;
2067 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2068 devpriv->dma0Buff[index] =
2069 pci_alloc_consistent(devpriv->pci_dev,
2071 devpriv->fifoLen / 2,
2073 dma0BuffPhysAddr[index]);
2074 if (devpriv->dma0Buff[index] == NULL) {
2076 goto rtd_attach_die_error;
2078 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
2080 devpriv->dma0Buff[index],
2081 devpriv->dma0BuffPhysAddr[index]); */
2085 * setup DMA descriptor ring (use cpu_to_le32 for byte
2088 devpriv->dma0Chain =
2089 pci_alloc_consistent(devpriv->pci_dev,
2090 sizeof(struct plx_dma_desc) *
2092 &devpriv->dma0ChainPhysAddr);
2093 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2094 devpriv->dma0Chain[index].pci_start_addr =
2095 devpriv->dma0BuffPhysAddr[index];
2096 devpriv->dma0Chain[index].local_start_addr =
2098 devpriv->dma0Chain[index].transfer_size =
2099 sizeof(u16) * devpriv->fifoLen / 2;
2100 devpriv->dma0Chain[index].next =
2101 (devpriv->dma0ChainPhysAddr + ((index +
2104 * sizeof(devpriv->dma0Chain[0]))
2105 | DMA_TRANSFER_BITS;
2106 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
2108 ((long)devpriv->dma0ChainPhysAddr
2109 + (index * sizeof(devpriv->dma0Chain[0]))),
2110 devpriv->dma0Chain[index].pci_start_addr,
2111 devpriv->dma0Chain[index].local_start_addr,
2112 devpriv->dma0Chain[index].transfer_size,
2113 devpriv->dma0Chain[index].next); */
2116 if (devpriv->dma0Chain == NULL) {
2118 goto rtd_attach_die_error;
2121 RtdDma0Mode(dev, DMA_MODE_BITS);
2122 /* set DMA trigger source */
2123 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
2125 printk(KERN_INFO "( no IRQ->no DMA )");
2127 #endif /* USE_DMA */
2129 if (dev->irq) { /* enable plx9080 interrupts */
2130 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2133 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
2138 /* hit an error, clean up memory and return ret */
2139 /* rtd_attach_die_error: */
2141 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2142 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
2143 pci_free_consistent(devpriv->pci_dev,
2144 sizeof(u16) * devpriv->fifoLen / 2,
2145 devpriv->dma0Buff[index],
2146 devpriv->dma0BuffPhysAddr[index]);
2147 devpriv->dma0Buff[index] = NULL;
2150 if (NULL != devpriv->dma0Chain) {
2151 pci_free_consistent(devpriv->pci_dev,
2152 sizeof(struct plx_dma_desc)
2155 devpriv->dma0ChainPhysAddr);
2156 devpriv->dma0Chain = NULL;
2158 #endif /* USE_DMA */
2159 /* subdevices and priv are freed by the core */
2161 /* disable interrupt controller */
2162 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2163 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
2164 free_irq(dev->irq, dev);
2167 /* release all regions that were allocated */
2169 iounmap(devpriv->las0);
2172 iounmap(devpriv->las1);
2175 iounmap(devpriv->lcfg);
2177 if (devpriv->pci_dev)
2178 pci_dev_put(devpriv->pci_dev);
2184 static void rtd_detach(struct comedi_device *dev)
2191 /* Shut down any board ops by resetting it */
2193 if (devpriv->lcfg) {
2194 RtdDma0Control(dev, 0); /* disable DMA */
2195 RtdDma1Control(dev, 0); /* disable DMA */
2196 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2198 #endif /* USE_DMA */
2199 if (devpriv->las0) {
2200 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
2201 RtdInterruptMask(dev, 0);
2202 RtdInterruptClearMask(dev, ~0);
2203 RtdInterruptClear(dev); /* clears bits set by mask */
2207 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2208 if (NULL != devpriv->dma0Buff[index]) {
2209 pci_free_consistent(devpriv->pci_dev,
2211 devpriv->fifoLen / 2,
2212 devpriv->dma0Buff[index],
2214 dma0BuffPhysAddr[index]);
2215 devpriv->dma0Buff[index] = NULL;
2218 if (NULL != devpriv->dma0Chain) {
2219 pci_free_consistent(devpriv->pci_dev,
2220 sizeof(struct plx_dma_desc) *
2221 DMA_CHAIN_COUNT, devpriv->dma0Chain,
2222 devpriv->dma0ChainPhysAddr);
2223 devpriv->dma0Chain = NULL;
2225 #endif /* USE_DMA */
2227 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2228 & ~(ICS_PLIE | ICS_DMA0_E |
2230 free_irq(dev->irq, dev);
2233 iounmap(devpriv->las0);
2235 iounmap(devpriv->las1);
2237 iounmap(devpriv->lcfg);
2238 if (devpriv->pci_dev) {
2239 if (devpriv->got_regions)
2240 comedi_pci_disable(devpriv->pci_dev);
2241 pci_dev_put(devpriv->pci_dev);
2246 static struct comedi_driver rtd520_driver = {
2247 .driver_name = "rtd520",
2248 .module = THIS_MODULE,
2249 .attach = rtd_attach,
2250 .detach = rtd_detach,
2253 static int __devinit rtd520_pci_probe(struct pci_dev *dev,
2254 const struct pci_device_id *ent)
2256 return comedi_pci_auto_config(dev, &rtd520_driver);
2259 static void __devexit rtd520_pci_remove(struct pci_dev *dev)
2261 comedi_pci_auto_unconfig(dev);
2264 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
2265 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
2266 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
2269 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
2271 static struct pci_driver rtd520_pci_driver = {
2273 .id_table = rtd520_pci_table,
2274 .probe = rtd520_pci_probe,
2275 .remove = __devexit_p(rtd520_pci_remove),
2277 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
2279 MODULE_AUTHOR("Comedi http://www.comedi.org");
2280 MODULE_DESCRIPTION("Comedi low-level driver");
2281 MODULE_LICENSE("GPL");