2 * comedi/drivers/rtd520.c
3 * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Real Time Devices PCI4520/DM7520
22 * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
23 * (Real Time Devices) DM7520HR-8 [DM7520]
24 * (Real Time Devices) PCI4520 [PCI4520]
25 * (Real Time Devices) PCI4520-8 [PCI4520]
26 * Author: Dan Christian
27 * Status: Works. Only tested on DM7520-8. Not SMP safe.
29 * Configuration options: not applicable, uses PCI auto config
33 * Created by Dan Christian, NASA Ames Research Center.
35 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
37 * 8/16 12 bit ADC with FIFO and channel gain table
38 * 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
39 * 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
40 * 2 12 bit DACs with FIFOs
44 * timers: ADC sample, pacer, burst, about, delay, DA1, DA2
46 * 3 user timer/counters (8254)
49 * The DM7520 has slightly fewer features (fewer gain steps).
51 * These boards can support external multiplexors and multi-board
52 * synchronization, but this driver doesn't support that.
54 * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
55 * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
56 * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
57 * Call them and ask for the register level manual.
58 * PCI chip: http://www.plxtech.com/products/io/pci9080
61 * This board is memory mapped. There is some IO stuff, but it isn't needed.
63 * I use a pretty loose naming style within the driver (rtd_blah).
64 * All externally visible names should be rtd520_blah.
65 * I use camelCase for structures (and inside them).
66 * I may also use upper CamelCase for function names (old habit).
68 * This board is somewhat related to the RTD PCI4400 board.
70 * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
71 * das1800, since they have the best documented code. Driver cb_pcidas64.c
72 * uses the same DMA controller.
74 * As far as I can tell, the About interrupt doesn't work if Sample is
75 * also enabled. It turns out that About really isn't needed, since
76 * we always count down samples read.
78 * There was some timer/counter code, but it didn't follow the right API.
84 * Analog-In supports instruction and command mode.
86 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
87 * (single channel, 64K read buffer). I get random system lockups when
88 * using DMA with ALI-15xx based systems. I haven't been able to test
89 * any other chipsets. The lockups happen soon after the start of an
90 * acquistion, not in the middle of a long run.
92 * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
93 * (with a 256K read buffer).
95 * Digital-IO and Analog-Out only support instruction mode.
98 #include <linux/module.h>
99 #include <linux/pci.h>
100 #include <linux/delay.h>
101 #include <linux/interrupt.h>
103 #include "../comedidev.h"
105 #include "comedi_fc.h"
109 * Local Address Space 0 Offsets
111 #define LAS0_USER_IO 0x0008 /* User I/O */
112 #define LAS0_ADC 0x0010 /* FIFO Status/Software A/D Start */
113 #define FS_DAC1_NOT_EMPTY (1 << 0) /* DAC1 FIFO not empty */
114 #define FS_DAC1_HEMPTY (1 << 1) /* DAC1 FIFO half empty */
115 #define FS_DAC1_NOT_FULL (1 << 2) /* DAC1 FIFO not full */
116 #define FS_DAC2_NOT_EMPTY (1 << 4) /* DAC2 FIFO not empty */
117 #define FS_DAC2_HEMPTY (1 << 5) /* DAC2 FIFO half empty */
118 #define FS_DAC2_NOT_FULL (1 << 6) /* DAC2 FIFO not full */
119 #define FS_ADC_NOT_EMPTY (1 << 8) /* ADC FIFO not empty */
120 #define FS_ADC_HEMPTY (1 << 9) /* ADC FIFO half empty */
121 #define FS_ADC_NOT_FULL (1 << 10) /* ADC FIFO not full */
122 #define FS_DIN_NOT_EMPTY (1 << 12) /* DIN FIFO not empty */
123 #define FS_DIN_HEMPTY (1 << 13) /* DIN FIFO half empty */
124 #define FS_DIN_NOT_FULL (1 << 14) /* DIN FIFO not full */
125 #define LAS0_DAC1 0x0014 /* Software D/A1 Update (w) */
126 #define LAS0_DAC2 0x0018 /* Software D/A2 Update (w) */
127 #define LAS0_DAC 0x0024 /* Software Simultaneous Update (w) */
128 #define LAS0_PACER 0x0028 /* Software Pacer Start/Stop */
129 #define LAS0_TIMER 0x002c /* Timer Status/HDIN Software Trig. */
130 #define LAS0_IT 0x0030 /* Interrupt Status/Enable */
131 #define IRQM_ADC_FIFO_WRITE (1 << 0) /* ADC FIFO Write */
132 #define IRQM_CGT_RESET (1 << 1) /* Reset CGT */
133 #define IRQM_CGT_PAUSE (1 << 3) /* Pause CGT */
134 #define IRQM_ADC_ABOUT_CNT (1 << 4) /* About Counter out */
135 #define IRQM_ADC_DELAY_CNT (1 << 5) /* Delay Counter out */
136 #define IRQM_ADC_SAMPLE_CNT (1 << 6) /* ADC Sample Counter */
137 #define IRQM_DAC1_UCNT (1 << 7) /* DAC1 Update Counter */
138 #define IRQM_DAC2_UCNT (1 << 8) /* DAC2 Update Counter */
139 #define IRQM_UTC1 (1 << 9) /* User TC1 out */
140 #define IRQM_UTC1_INV (1 << 10) /* User TC1 out, inverted */
141 #define IRQM_UTC2 (1 << 11) /* User TC2 out */
142 #define IRQM_DIGITAL_IT (1 << 12) /* Digital Interrupt */
143 #define IRQM_EXTERNAL_IT (1 << 13) /* External Interrupt */
144 #define IRQM_ETRIG_RISING (1 << 14) /* Ext Trigger rising-edge */
145 #define IRQM_ETRIG_FALLING (1 << 15) /* Ext Trigger falling-edge */
146 #define LAS0_CLEAR 0x0034 /* Clear/Set Interrupt Clear Mask */
147 #define LAS0_OVERRUN 0x0038 /* Pending interrupts/Clear Overrun */
148 #define LAS0_PCLK 0x0040 /* Pacer Clock (24bit) */
149 #define LAS0_BCLK 0x0044 /* Burst Clock (10bit) */
150 #define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter (10bit) */
151 #define LAS0_DAC1_UCNT 0x004c /* D/A1 Update counter (10 bit) */
152 #define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter (10 bit) */
153 #define LAS0_DCNT 0x0054 /* Delay counter (16 bit) */
154 #define LAS0_ACNT 0x0058 /* About counter (16 bit) */
155 #define LAS0_DAC_CLK 0x005c /* DAC clock (16bit) */
156 #define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 */
157 #define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 */
158 #define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 */
159 #define LAS0_UTC_CTRL 0x006c /* 8254 TC Control */
160 #define LAS0_DIO0 0x0070 /* Digital I/O Port 0 */
161 #define LAS0_DIO1 0x0074 /* Digital I/O Port 1 */
162 #define LAS0_DIO0_CTRL 0x0078 /* Digital I/O Control */
163 #define LAS0_DIO_STATUS 0x007c /* Digital I/O Status */
164 #define LAS0_BOARD_RESET 0x0100 /* Board reset */
165 #define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */
166 #define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */
167 #define LAS0_ADC_CONVERSION 0x010c /* A/D Conversion Signal select */
168 #define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */
169 #define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */
170 #define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */
171 #define LAS0_ACNT_STOP_ENABLE 0x011c /* About Counter Stop Enable */
172 #define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */
173 #define LAS0_DIN_START 0x0124 /* HiSpd DI Sampling Signal select */
174 #define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */
175 #define LAS0_ADC_FIFO_CLEAR 0x012c /* A/D FIFO Clear */
176 #define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */
177 #define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */
178 #define LAS0_CG_DATA 0x0138 /* Digital Table Write */
179 #define LAS0_CGT_ENABLE 0x013c /* Channel Gain Table Enable */
180 #define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */
181 #define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */
182 #define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */
183 #define LAS0_CGT_CLEAR 0x014c /* Clear Channel Gain Table */
184 #define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */
185 #define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */
186 #define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */
187 #define LAS0_DAC1_RESET 0x015c /* D/A1 FIFO reset */
188 #define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */
189 #define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */
190 #define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */
191 #define LAS0_DAC2_CYCLE 0x016c /* D/A2 cycle mode */
192 #define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */
193 #define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */
194 #define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */
195 #define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */
196 #define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */
197 #define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */
198 #define LAS0_SBUS1_SRC 0x018c /* SyncBus 1 Source select */
199 #define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */
200 #define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */
201 #define LAS0_SBUS2_ENABLE 0x019c /* SyncBus 2 enable */
202 #define LAS0_ETRG_POLARITY 0x01a4 /* Ext. Trigger polarity select */
203 #define LAS0_EINT_POLARITY 0x01a8 /* Ext. Interrupt polarity select */
204 #define LAS0_UTC0_CLOCK 0x01ac /* UTC0 Clock select */
205 #define LAS0_UTC0_GATE 0x01b0 /* UTC0 Gate select */
206 #define LAS0_UTC1_CLOCK 0x01b4 /* UTC1 Clock select */
207 #define LAS0_UTC1_GATE 0x01b8 /* UTC1 Gate select */
208 #define LAS0_UTC2_CLOCK 0x01bc /* UTC2 Clock select */
209 #define LAS0_UTC2_GATE 0x01c0 /* UTC2 Gate select */
210 #define LAS0_UOUT0_SELECT 0x01c4 /* User Output 0 source select */
211 #define LAS0_UOUT1_SELECT 0x01c8 /* User Output 1 source select */
212 #define LAS0_DMA0_RESET 0x01cc /* DMA0 Request state machine reset */
213 #define LAS0_DMA1_RESET 0x01d0 /* DMA1 Request state machine reset */
216 * Local Address Space 1 Offsets
218 #define LAS1_ADC_FIFO 0x0000 /* A/D FIFO (16bit) */
219 #define LAS1_HDIO_FIFO 0x0004 /* HiSpd DI FIFO (16bit) */
220 #define LAS1_DAC1_FIFO 0x0008 /* D/A1 FIFO (16bit) */
221 #define LAS1_DAC2_FIFO 0x000c /* D/A2 FIFO (16bit) */
223 /*======================================================================
224 Driver specific stuff (tunable)
225 ======================================================================*/
227 /* We really only need 2 buffers. More than that means being much
228 smarter about knowing which ones are full. */
229 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
231 /* Target period for periodic transfers. This sets the user read latency. */
232 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
233 /* If this is too low, efficiency is poor */
234 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
236 /* Set a practical limit on how long a list to support (affects memory use) */
237 /* The board support a channel list up to the FIFO length (1K or 8K) */
238 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
240 /* tuning for ai/ao instruction done polling */
242 #define WAIT_QUIETLY /* as nothing, spin on done bit */
243 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
244 #define RTD_DAC_TIMEOUT 66000
245 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
247 /* by delaying, power and electrical noise are reduced somewhat */
248 #define WAIT_QUIETLY udelay(1)
249 #define RTD_ADC_TIMEOUT 2000 /* in usec */
250 #define RTD_DAC_TIMEOUT 2000 /* in usec */
251 #define RTD_DMA_TIMEOUT 1000 /* in usec */
254 /*======================================================================
256 ======================================================================*/
258 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
259 #define RTD_CLOCK_BASE 125 /* clock period in ns */
261 /* Note: these speed are slower than the spec, but fit the counter resolution*/
262 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
263 /* max speed if we don't have to wait for settling */
264 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
266 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
267 /* min speed when only 1 channel (no burst counter) */
268 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
270 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
271 #define DMA_MODE_BITS (\
272 PLX_LOCAL_BUS_16_WIDE_BITS \
273 | PLX_DMA_EN_READYIN_BIT \
274 | PLX_DMA_LOCAL_BURST_EN_BIT \
276 | PLX_DMA_INTR_PCI_BIT \
277 | PLX_LOCAL_ADDR_CONST_BIT \
278 | PLX_DEMAND_MODE_BIT)
280 #define DMA_TRANSFER_BITS (\
281 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
282 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
283 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
285 /*======================================================================
286 Comedi specific stuff
287 ======================================================================*/
290 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
292 static const struct comedi_lrange rtd_ai_7520_range = {
294 /* +-5V input range gain steps */
301 /* +-10V input range gain steps */
306 BIP_RANGE(10.0 / 16),
307 BIP_RANGE(10.0 / 32),
308 /* +10V input range gain steps */
313 UNI_RANGE(10.0 / 16),
314 UNI_RANGE(10.0 / 32),
318 /* PCI4520 has two more gains (6 more entries) */
319 static const struct comedi_lrange rtd_ai_4520_range = {
321 /* +-5V input range gain steps */
329 BIP_RANGE(5.0 / 128),
330 /* +-10V input range gain steps */
335 BIP_RANGE(10.0 / 16),
336 BIP_RANGE(10.0 / 32),
337 BIP_RANGE(10.0 / 64),
338 BIP_RANGE(10.0 / 128),
339 /* +10V input range gain steps */
344 UNI_RANGE(10.0 / 16),
345 UNI_RANGE(10.0 / 32),
346 UNI_RANGE(10.0 / 64),
347 UNI_RANGE(10.0 / 128),
351 /* Table order matches range values */
352 static const struct comedi_lrange rtd_ao_range = {
366 struct rtd_boardinfo {
368 int range_bip10; /* start of +-10V range */
369 int range_uni10; /* start of +10V range */
370 const struct comedi_lrange *ai_range;
373 static const struct rtd_boardinfo rtd520Boards[] = {
378 .ai_range = &rtd_ai_7520_range,
384 .ai_range = &rtd_ai_4520_range,
389 /* memory mapped board structures */
394 long ai_count; /* total transfer size (samples) */
395 int xfer_count; /* # to transfer data. 0->1/2FIFO */
396 int flags; /* flag event modes */
397 DECLARE_BITMAP(chan_is_bipolar, RTD_MAX_CHANLIST);
398 unsigned int ao_readback[2];
402 /* bit defines for "flags" */
403 #define SEND_EOS 0x01 /* send End Of Scan events */
404 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
405 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
408 Given a desired period and the clock period (both in ns),
409 return the proper counter value (divider-1).
410 Sets the original period to be the true value.
411 Note: you have to check if the value is larger than the counter range!
413 static int rtd_ns_to_timer_base(unsigned int *nanosec,
414 int round_mode, int base)
418 switch (round_mode) {
419 case TRIG_ROUND_NEAREST:
421 divider = (*nanosec + base / 2) / base;
423 case TRIG_ROUND_DOWN:
424 divider = (*nanosec) / base;
427 divider = (*nanosec + base - 1) / base;
431 divider = 2; /* min is divide by 2 */
433 /* Note: we don't check for max, because different timers
434 have different ranges */
436 *nanosec = base * divider;
437 return divider - 1; /* countdown is divisor+1 */
441 Given a desired period (in ns),
442 return the proper counter value (divider-1) for the internal clock.
443 Sets the original period to be the true value.
445 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
447 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
451 Convert a single comedi channel-gain entry to a RTD520 table entry
453 static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
454 unsigned int chanspec, int index)
456 const struct rtd_boardinfo *board = comedi_board(dev);
457 struct rtd_private *devpriv = dev->private;
458 unsigned int chan = CR_CHAN(chanspec);
459 unsigned int range = CR_RANGE(chanspec);
460 unsigned int aref = CR_AREF(chanspec);
461 unsigned short r = 0;
465 /* Note: we also setup the channel list bipolar flag array */
466 if (range < board->range_bip10) {
469 r |= (range & 0x7) << 4;
470 __set_bit(index, devpriv->chan_is_bipolar);
471 } else if (range < board->range_uni10) {
474 r |= ((range - board->range_bip10) & 0x7) << 4;
475 __set_bit(index, devpriv->chan_is_bipolar);
479 r |= ((range - board->range_uni10) & 0x7) << 4;
480 __clear_bit(index, devpriv->chan_is_bipolar);
484 case AREF_GROUND: /* on-board ground */
488 r |= 0x80; /* ref external analog common */
492 r |= 0x400; /* differential inputs */
495 case AREF_OTHER: /* ??? */
498 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
499 chan, range, aref, r); */
504 Setup the channel-gain table from a comedi list
506 static void rtd_load_channelgain_list(struct comedi_device *dev,
507 unsigned int n_chan, unsigned int *list)
509 struct rtd_private *devpriv = dev->private;
511 if (n_chan > 1) { /* setup channel gain table */
514 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
515 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
516 for (ii = 0; ii < n_chan; ii++) {
517 writel(rtd_convert_chan_gain(dev, list[ii], ii),
518 devpriv->las0 + LAS0_CGT_WRITE);
520 } else { /* just use the channel gain latch */
521 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
522 writel(rtd_convert_chan_gain(dev, list[0], 0),
523 devpriv->las0 + LAS0_CGL_WRITE);
527 /* determine fifo size by doing adc conversions until the fifo half
528 empty status flag clears */
529 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
531 struct rtd_private *devpriv = dev->private;
532 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
534 static const unsigned limit = 0x2000;
535 unsigned fifo_size = 0;
537 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
538 rtd_load_channelgain_list(dev, 1, &chanspec);
539 /* ADC conversion trigger source: SOFTWARE */
540 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
541 /* convert samples */
542 for (i = 0; i < limit; ++i) {
543 unsigned fifo_status;
544 /* trigger conversion */
545 writew(0, devpriv->las0 + LAS0_ADC);
547 fifo_status = readl(devpriv->las0 + LAS0_ADC);
548 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
554 dev_info(dev->class_dev, "failed to probe fifo size.\n");
557 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
558 if (fifo_size != 0x400 && fifo_size != 0x2000) {
559 dev_info(dev->class_dev,
560 "unexpected fifo size of %i, expected 1024 or 8192.\n",
568 "instructions" read/write data in "one-shot" or "software-triggered"
569 mode (simplest case).
570 This doesn't use interrupts.
572 Note, we don't do any settling delays. Use a instruction list to
573 select, delay, then read.
575 static int rtd_ai_rinsn(struct comedi_device *dev,
576 struct comedi_subdevice *s, struct comedi_insn *insn,
579 struct rtd_private *devpriv = dev->private;
583 /* clear any old fifo data */
584 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
586 /* write channel to multiplexer and clear channel gain table */
587 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
589 /* ADC conversion trigger source: SOFTWARE */
590 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
592 /* convert n samples */
593 for (n = 0; n < insn->n; n++) {
595 /* trigger conversion */
596 writew(0, devpriv->las0 + LAS0_ADC);
598 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
599 stat = readl(devpriv->las0 + LAS0_ADC);
600 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
604 if (ii >= RTD_ADC_TIMEOUT)
608 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
609 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
610 d = d >> 3; /* low 3 bits are marker lines */
611 if (test_bit(0, devpriv->chan_is_bipolar))
612 /* convert to comedi unsigned data */
613 d = comedi_offset_munge(s, d);
614 data[n] = d & s->maxdata;
617 /* return the number of samples read/written */
622 Get what we know is there.... Fast!
623 This uses 1/2 the bus cycles of read_dregs (below).
625 The manual claims that we can do a lword read, but it doesn't work here.
627 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
630 struct rtd_private *devpriv = dev->private;
633 for (ii = 0; ii < count; ii++) {
636 if (0 == devpriv->ai_count) { /* done */
637 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
641 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
642 d = d >> 3; /* low 3 bits are marker lines */
643 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
644 /* convert to comedi unsigned data */
645 d = comedi_offset_munge(s, d);
648 if (!comedi_buf_put(s->async, d))
651 if (devpriv->ai_count > 0) /* < 0, means read forever */
658 unknown amout of data is waiting in fifo.
660 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
662 struct rtd_private *devpriv = dev->private;
664 while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
665 unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
667 if (0 == devpriv->ai_count) { /* done */
668 continue; /* read rest */
671 d = d >> 3; /* low 3 bits are marker lines */
672 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
673 /* convert to comedi unsigned data */
674 d = comedi_offset_munge(s, d);
677 if (!comedi_buf_put(s->async, d))
680 if (devpriv->ai_count > 0) /* < 0, means read forever */
687 Handle all rtd520 interrupts.
688 Runs atomically and is never re-entered.
689 This is a "slow handler"; other interrupts may be active.
690 The data conversion may someday happen in a "bottom half".
692 static irqreturn_t rtd_interrupt(int irq, void *d)
694 struct comedi_device *dev = d;
695 struct comedi_subdevice *s = &dev->subdevices[0];
696 struct rtd_private *devpriv = dev->private;
704 fifo_status = readl(devpriv->las0 + LAS0_ADC);
705 /* check for FIFO full, this automatically halts the ADC! */
706 if (!(fifo_status & FS_ADC_NOT_FULL)) /* 0 -> full */
709 status = readw(devpriv->las0 + LAS0_IT);
710 /* if interrupt was not caused by our board, or handled above */
714 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
716 * since the priority interrupt controller may have queued
717 * a sample counter interrupt, even though we have already
718 * finished, we must handle the possibility that there is
721 if (!(fifo_status & FS_ADC_HEMPTY)) {
723 if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
726 if (0 == devpriv->ai_count)
729 comedi_event(dev, s);
730 } else if (devpriv->xfer_count > 0) {
731 if (fifo_status & FS_ADC_NOT_EMPTY) {
733 if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
736 if (0 == devpriv->ai_count)
739 comedi_event(dev, s);
744 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
748 /* clear the interrupt */
749 writew(status, devpriv->las0 + LAS0_CLEAR);
750 readw(devpriv->las0 + LAS0_CLEAR);
754 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
755 s->async->events |= COMEDI_CB_ERROR;
756 devpriv->ai_count = 0; /* stop and don't transfer any more */
757 /* fall into xfer_done */
760 /* pacer stop source: SOFTWARE */
761 writel(0, devpriv->las0 + LAS0_PACER_STOP);
762 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
763 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
764 writew(0, devpriv->las0 + LAS0_IT);
766 if (devpriv->ai_count > 0) { /* there shouldn't be anything left */
767 fifo_status = readl(devpriv->las0 + LAS0_ADC);
768 ai_read_dregs(dev, s); /* read anything left in FIFO */
771 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
772 comedi_event(dev, s);
774 /* clear the interrupt */
775 status = readw(devpriv->las0 + LAS0_IT);
776 writew(status, devpriv->las0 + LAS0_CLEAR);
777 readw(devpriv->las0 + LAS0_CLEAR);
779 fifo_status = readl(devpriv->las0 + LAS0_ADC);
780 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
786 cmdtest tests a particular command to see if it is valid.
787 Using the cmdtest ioctl, a user can create a valid cmd
788 and then have it executed by the cmd ioctl (asynchronously).
790 cmdtest returns 1,2,3,4 or 0, depending on which tests
794 static int rtd_ai_cmdtest(struct comedi_device *dev,
795 struct comedi_subdevice *s, struct comedi_cmd *cmd)
800 /* Step 1 : check if triggers are trivially valid */
802 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
803 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
804 TRIG_TIMER | TRIG_EXT);
805 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
806 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
807 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
812 /* Step 2a : make sure trigger sources are unique */
814 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
815 err |= cfc_check_trigger_is_unique(cmd->convert_src);
816 err |= cfc_check_trigger_is_unique(cmd->stop_src);
818 /* Step 2b : and mutually compatible */
823 /* Step 3: check if arguments are trivially valid */
825 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
827 if (cmd->scan_begin_src == TRIG_TIMER) {
828 /* Note: these are time periods, not actual rates */
829 if (1 == cmd->chanlist_len) { /* no scanning */
830 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
832 rtd_ns_to_timer(&cmd->scan_begin_arg,
836 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
838 rtd_ns_to_timer(&cmd->scan_begin_arg,
843 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
845 rtd_ns_to_timer(&cmd->scan_begin_arg,
849 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
851 rtd_ns_to_timer(&cmd->scan_begin_arg,
857 /* external trigger */
858 /* should be level/edge, hi/lo specification here */
859 /* should specify multiple external triggers */
860 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
863 if (cmd->convert_src == TRIG_TIMER) {
864 if (1 == cmd->chanlist_len) { /* no scanning */
865 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
867 rtd_ns_to_timer(&cmd->convert_arg,
871 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
873 rtd_ns_to_timer(&cmd->convert_arg,
878 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
880 rtd_ns_to_timer(&cmd->convert_arg,
884 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
886 rtd_ns_to_timer(&cmd->convert_arg,
892 /* external trigger */
894 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
897 if (cmd->stop_src == TRIG_COUNT) {
898 /* TODO check for rounding error due to counter wrap */
901 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
908 /* step 4: fix up any arguments */
910 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
911 cmd->chanlist_len = RTD_MAX_CHANLIST;
914 if (cmd->scan_begin_src == TRIG_TIMER) {
915 tmp = cmd->scan_begin_arg;
916 rtd_ns_to_timer(&cmd->scan_begin_arg,
917 cmd->flags & TRIG_ROUND_MASK);
918 if (tmp != cmd->scan_begin_arg)
922 if (cmd->convert_src == TRIG_TIMER) {
923 tmp = cmd->convert_arg;
924 rtd_ns_to_timer(&cmd->convert_arg,
925 cmd->flags & TRIG_ROUND_MASK);
926 if (tmp != cmd->convert_arg)
929 if (cmd->scan_begin_src == TRIG_TIMER
930 && (cmd->scan_begin_arg
931 < (cmd->convert_arg * cmd->scan_end_arg))) {
932 cmd->scan_begin_arg =
933 cmd->convert_arg * cmd->scan_end_arg;
945 Execute a analog in command with many possible triggering options.
946 The data get stored in the async structure of the subdevice.
947 This is usually done by an interrupt handler.
948 Userland gets to the data using read calls.
950 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
952 struct rtd_private *devpriv = dev->private;
953 struct comedi_cmd *cmd = &s->async->cmd;
956 /* stop anything currently running */
957 /* pacer stop source: SOFTWARE */
958 writel(0, devpriv->las0 + LAS0_PACER_STOP);
959 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
960 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
961 writew(0, devpriv->las0 + LAS0_IT);
962 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
963 writel(0, devpriv->las0 + LAS0_OVERRUN);
965 /* start configuration */
966 /* load channel list and reset CGT */
967 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
969 /* setup the common case and override if needed */
970 if (cmd->chanlist_len > 1) {
971 /* pacer start source: SOFTWARE */
972 writel(0, devpriv->las0 + LAS0_PACER_START);
973 /* burst trigger source: PACER */
974 writel(1, devpriv->las0 + LAS0_BURST_START);
975 /* ADC conversion trigger source: BURST */
976 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
977 } else { /* single channel */
978 /* pacer start source: SOFTWARE */
979 writel(0, devpriv->las0 + LAS0_PACER_START);
980 /* ADC conversion trigger source: PACER */
981 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
983 writel((devpriv->fifosz / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
985 if (TRIG_TIMER == cmd->scan_begin_src) {
986 /* scan_begin_arg is in nanoseconds */
987 /* find out how many samples to wait before transferring */
988 if (cmd->flags & TRIG_WAKE_EOS) {
990 * this may generate un-sustainable interrupt rates
991 * the application is responsible for doing the
994 devpriv->xfer_count = cmd->chanlist_len;
995 devpriv->flags |= SEND_EOS;
997 /* arrange to transfer data periodically */
998 devpriv->xfer_count =
999 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1000 cmd->scan_begin_arg;
1001 if (devpriv->xfer_count < cmd->chanlist_len) {
1002 /* transfer after each scan (and avoid 0) */
1003 devpriv->xfer_count = cmd->chanlist_len;
1004 } else { /* make a multiple of scan length */
1005 devpriv->xfer_count =
1006 (devpriv->xfer_count +
1007 cmd->chanlist_len - 1)
1008 / cmd->chanlist_len;
1009 devpriv->xfer_count *= cmd->chanlist_len;
1011 devpriv->flags |= SEND_EOS;
1013 if (devpriv->xfer_count >= (devpriv->fifosz / 2)) {
1014 /* out of counter range, use 1/2 fifo instead */
1015 devpriv->xfer_count = 0;
1016 devpriv->flags &= ~SEND_EOS;
1018 /* interrupt for each transfer */
1019 writel((devpriv->xfer_count - 1) & 0xffff,
1020 devpriv->las0 + LAS0_ACNT);
1022 } else { /* unknown timing, just use 1/2 FIFO */
1023 devpriv->xfer_count = 0;
1024 devpriv->flags &= ~SEND_EOS;
1026 /* pacer clock source: INTERNAL 8MHz */
1027 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1028 /* just interrupt, don't stop */
1029 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1031 /* BUG??? these look like enumerated values, but they are bit fields */
1033 /* First, setup when to stop */
1034 switch (cmd->stop_src) {
1035 case TRIG_COUNT: /* stop after N scans */
1036 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
1037 if ((devpriv->xfer_count > 0)
1038 && (devpriv->xfer_count > devpriv->ai_count)) {
1039 devpriv->xfer_count = devpriv->ai_count;
1043 case TRIG_NONE: /* stop when cancel is called */
1044 devpriv->ai_count = -1; /* read forever */
1049 switch (cmd->scan_begin_src) {
1050 case TRIG_TIMER: /* periodic scanning */
1051 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1052 TRIG_ROUND_NEAREST);
1053 /* set PACER clock */
1054 writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
1059 /* pacer start source: EXTERNAL */
1060 writel(1, devpriv->las0 + LAS0_PACER_START);
1064 /* Sample timing within a scan */
1065 switch (cmd->convert_src) {
1066 case TRIG_TIMER: /* periodic */
1067 if (cmd->chanlist_len > 1) {
1068 /* only needed for multi-channel */
1069 timer = rtd_ns_to_timer(&cmd->convert_arg,
1070 TRIG_ROUND_NEAREST);
1071 /* setup BURST clock */
1072 writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
1077 case TRIG_EXT: /* external */
1078 /* burst trigger source: EXTERNAL */
1079 writel(2, devpriv->las0 + LAS0_BURST_START);
1082 /* end configuration */
1084 /* This doesn't seem to work. There is no way to clear an interrupt
1085 that the priority controller has queued! */
1086 writew(~0, devpriv->las0 + LAS0_CLEAR);
1087 readw(devpriv->las0 + LAS0_CLEAR);
1089 /* TODO: allow multiple interrupt sources */
1090 if (devpriv->xfer_count > 0) { /* transfer every N samples */
1091 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1092 } else { /* 1/2 FIFO transfers */
1093 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1096 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1097 /* BUG? it seems like things are running before the "start" */
1098 readl(devpriv->las0 + LAS0_PACER); /* start pacer */
1103 Stop a running data acquisition.
1105 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1107 struct rtd_private *devpriv = dev->private;
1111 /* pacer stop source: SOFTWARE */
1112 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1113 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
1114 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1115 writew(0, devpriv->las0 + LAS0_IT);
1116 devpriv->ai_count = 0; /* stop and don't transfer any more */
1117 status = readw(devpriv->las0 + LAS0_IT);
1118 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1123 Output one (or more) analog values to a single port as fast as possible.
1125 static int rtd_ao_winsn(struct comedi_device *dev,
1126 struct comedi_subdevice *s, struct comedi_insn *insn,
1129 struct rtd_private *devpriv = dev->private;
1131 int chan = CR_CHAN(insn->chanspec);
1132 int range = CR_RANGE(insn->chanspec);
1134 /* Configure the output range (table index matches the range values) */
1135 writew(range & 7, devpriv->las0 +
1136 ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1138 /* Writing a list of values to an AO channel is probably not
1139 * very useful, but that's how the interface is defined. */
1140 for (i = 0; i < insn->n; ++i) {
1141 int val = data[i] << 3;
1142 int stat = 0; /* initialize to avoid bogus warning */
1145 /* VERIFY: comedi range and offset conversions */
1147 if ((range > 1) /* bipolar */
1148 && (data[i] < 2048)) {
1149 /* offset and sign extend */
1150 val = (((int)data[i]) - 2048) << 3;
1151 } else { /* unipolor */
1155 /* a typical programming sequence */
1156 writew(val, devpriv->las1 +
1157 ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1158 writew(0, devpriv->las0 +
1159 ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1161 devpriv->ao_readback[chan] = data[i];
1163 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1164 stat = readl(devpriv->las0 + LAS0_ADC);
1165 /* 1 -> not empty */
1166 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1171 if (ii >= RTD_DAC_TIMEOUT)
1175 /* return the number of samples read/written */
1179 /* AO subdevices should have a read insn as well as a write insn.
1180 * Usually this means copying a value stored in devpriv. */
1181 static int rtd_ao_rinsn(struct comedi_device *dev,
1182 struct comedi_subdevice *s, struct comedi_insn *insn,
1185 struct rtd_private *devpriv = dev->private;
1187 int chan = CR_CHAN(insn->chanspec);
1189 for (i = 0; i < insn->n; i++)
1190 data[i] = devpriv->ao_readback[chan];
1196 static int rtd_dio_insn_bits(struct comedi_device *dev,
1197 struct comedi_subdevice *s,
1198 struct comedi_insn *insn,
1201 struct rtd_private *devpriv = dev->private;
1203 if (comedi_dio_update_state(s, data))
1204 writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
1206 data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
1211 static int rtd_dio_insn_config(struct comedi_device *dev,
1212 struct comedi_subdevice *s,
1213 struct comedi_insn *insn,
1216 struct rtd_private *devpriv = dev->private;
1219 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1223 /* TODO support digital match interrupts and strobes */
1226 writew(0x01, devpriv->las0 + LAS0_DIO_STATUS);
1227 writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
1229 /* clear interrupts */
1230 writew(0x00, devpriv->las0 + LAS0_DIO_STATUS);
1232 /* port1 can only be all input or all output */
1234 /* there are also 2 user input lines and 2 user output lines */
1239 static void rtd_reset(struct comedi_device *dev)
1241 struct rtd_private *devpriv = dev->private;
1243 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1244 udelay(100); /* needed? */
1245 writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1246 writew(0, devpriv->las0 + LAS0_IT);
1247 writew(~0, devpriv->las0 + LAS0_CLEAR);
1248 readw(devpriv->las0 + LAS0_CLEAR);
1252 * initialize board, per RTD spec
1253 * also, initialize shadow registers
1255 static void rtd_init_board(struct comedi_device *dev)
1257 struct rtd_private *devpriv = dev->private;
1261 writel(0, devpriv->las0 + LAS0_OVERRUN);
1262 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1263 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1264 writel(0, devpriv->las0 + LAS0_DAC1_RESET);
1265 writel(0, devpriv->las0 + LAS0_DAC2_RESET);
1266 /* clear digital IO fifo */
1267 writew(0, devpriv->las0 + LAS0_DIO_STATUS);
1268 writeb((0 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1269 writeb((1 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1270 writeb((2 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1271 writeb((3 << 6) | 0x00, devpriv->las0 + LAS0_UTC_CTRL);
1272 /* TODO: set user out source ??? */
1275 /* The RTD driver does this */
1276 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1277 struct pci_dev *pcidev)
1279 unsigned char pci_latency;
1281 pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1282 if (pci_latency < 32) {
1283 dev_info(dev->class_dev,
1284 "PCI latency changed from %d to %d\n",
1286 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1290 static int rtd_auto_attach(struct comedi_device *dev,
1291 unsigned long context)
1293 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1294 const struct rtd_boardinfo *board = NULL;
1295 struct rtd_private *devpriv;
1296 struct comedi_subdevice *s;
1299 if (context < ARRAY_SIZE(rtd520Boards))
1300 board = &rtd520Boards[context];
1303 dev->board_ptr = board;
1304 dev->board_name = board->name;
1306 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1310 ret = comedi_pci_enable(dev);
1314 devpriv->las0 = pci_ioremap_bar(pcidev, 2);
1315 devpriv->las1 = pci_ioremap_bar(pcidev, 3);
1316 devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
1317 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1320 rtd_pci_latency_quirk(dev, pcidev);
1323 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1324 dev->board_name, dev);
1326 dev->irq = pcidev->irq;
1329 ret = comedi_alloc_subdevices(dev, 4);
1333 s = &dev->subdevices[0];
1334 /* analog input subdevice */
1335 s->type = COMEDI_SUBD_AI;
1336 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1338 s->maxdata = 0x0fff;
1339 s->range_table = board->ai_range;
1340 s->len_chanlist = RTD_MAX_CHANLIST;
1341 s->insn_read = rtd_ai_rinsn;
1343 dev->read_subdev = s;
1344 s->subdev_flags |= SDF_CMD_READ;
1345 s->do_cmd = rtd_ai_cmd;
1346 s->do_cmdtest = rtd_ai_cmdtest;
1347 s->cancel = rtd_ai_cancel;
1350 s = &dev->subdevices[1];
1351 /* analog output subdevice */
1352 s->type = COMEDI_SUBD_AO;
1353 s->subdev_flags = SDF_WRITABLE;
1355 s->maxdata = 0x0fff;
1356 s->range_table = &rtd_ao_range;
1357 s->insn_write = rtd_ao_winsn;
1358 s->insn_read = rtd_ao_rinsn;
1360 s = &dev->subdevices[2];
1361 /* digital i/o subdevice */
1362 s->type = COMEDI_SUBD_DIO;
1363 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1364 /* we only support port 0 right now. Ignoring port 1 and user IO */
1367 s->range_table = &range_digital;
1368 s->insn_bits = rtd_dio_insn_bits;
1369 s->insn_config = rtd_dio_insn_config;
1371 /* timer/counter subdevices (not currently supported) */
1372 s = &dev->subdevices[3];
1373 s->type = COMEDI_SUBD_COUNTER;
1374 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1376 s->maxdata = 0xffff;
1378 rtd_init_board(dev);
1380 ret = rtd520_probe_fifo_depth(dev);
1383 devpriv->fifosz = ret;
1386 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1388 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
1393 static void rtd_detach(struct comedi_device *dev)
1395 struct rtd_private *devpriv = dev->private;
1398 /* Shut down any board ops by resetting it */
1399 if (devpriv->las0 && devpriv->lcfg)
1402 writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
1403 ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
1404 devpriv->lcfg + PLX_INTRCS_REG);
1405 free_irq(dev->irq, dev);
1408 iounmap(devpriv->las0);
1410 iounmap(devpriv->las1);
1412 iounmap(devpriv->lcfg);
1414 comedi_pci_disable(dev);
1417 static struct comedi_driver rtd520_driver = {
1418 .driver_name = "rtd520",
1419 .module = THIS_MODULE,
1420 .auto_attach = rtd_auto_attach,
1421 .detach = rtd_detach,
1424 static int rtd520_pci_probe(struct pci_dev *dev,
1425 const struct pci_device_id *id)
1427 return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1430 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
1431 { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1432 { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1435 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1437 static struct pci_driver rtd520_pci_driver = {
1439 .id_table = rtd520_pci_table,
1440 .probe = rtd520_pci_probe,
1441 .remove = comedi_pci_auto_unconfig,
1443 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1445 MODULE_AUTHOR("Comedi http://www.comedi.org");
1446 MODULE_DESCRIPTION("Comedi low-level driver");
1447 MODULE_LICENSE("GPL");